CN108735576A - Semiconductor structure and forming method thereof - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 238000000034 method Methods 0.000 title claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 114
- 238000005987 sulfurization reaction Methods 0.000 claims abstract description 6
- 229910052717 sulfur Inorganic materials 0.000 claims description 39
- 239000011593 sulfur Substances 0.000 claims description 39
- 239000010410 layer Substances 0.000 claims description 36
- 230000008569 process Effects 0.000 claims description 26
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 11
- 238000000137 annealing Methods 0.000 claims description 7
- UCKMPCXJQFINFW-UHFFFAOYSA-N Sulphide Chemical compound [S-2] UCKMPCXJQFINFW-UHFFFAOYSA-N 0.000 claims description 6
- 238000004073 vulcanization Methods 0.000 claims description 6
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 5
- 239000002356 single layer Substances 0.000 claims description 5
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 238000007740 vapor deposition Methods 0.000 claims description 3
- -1 sulfur ions Chemical class 0.000 description 22
- 230000007547 defect Effects 0.000 description 9
- 230000008439 repair process Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000002411 adverse Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 240000002329 Inga feuillei Species 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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Abstract
本发明提供一种半导体结构及其形成方法，所述形成方法包括：提供基底；对所述基底进行等离子体硫化处理；对所述基底进行等离子体硫化处理之后，在所述基底上形成高K介质层。本发明形成方法形成的半导体结构电学性能得到提高。
The present invention provides a semiconductor structure and its forming method. The forming method includes: providing a substrate; performing plasma sulfurization treatment on the substrate; and forming a high-K medium layer. The electrical performance of the semiconductor structure formed by the forming method of the invention is improved.
Description
技术领域technical field
本发明涉及半导体制造技术领域，特别涉及一种半导体结构及其形成方法。The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof.
背景技术Background technique
随着半导体技术的飞速发展，半导体结构的特征尺寸不断缩小，使得集成电路的集成度越来越高，这对器件的性能也提出了更高的要求。With the rapid development of semiconductor technology, the feature size of semiconductor structures is constantly shrinking, which makes the integration of integrated circuits higher and higher, which also puts forward higher requirements for the performance of devices.
目前，随着金属-氧化物半导体场效应晶体管(MOSFET)的尺寸不断变小。为了适应工艺节点的减小，只能不断缩短MOSFET场效应管的沟道长度。沟道长度的缩短具有增加芯片的管芯密度、增加MOSFET场效应管的开关速度等好处。Currently, as the size of Metal-Oxide Semiconductor Field Effect Transistors (MOSFETs) continues to decrease. In order to adapt to the reduction of process nodes, the channel length of MOSFET field effect transistors can only be continuously shortened. The shortening of the channel length has the advantages of increasing the die density of the chip and increasing the switching speed of the MOSFET field effect tube.
然而，随着器件沟道长度的缩短，器件源极与漏极间的距离也随之缩短，这样一来栅极对沟道的控制能力变差，栅极电压夹断(pinch off)沟道的难度也越来越大，使得亚阀值漏电现象，即短沟道效应(SCE：short-channel effects)成为一个至关重要的技术问题。However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control ability of the gate to the channel becomes worse, and the gate voltage pinches off the channel. The difficulty is also increasing, making the sub-threshold leakage phenomenon, that is, short-channel effects (SCE: short-channel effects) become a crucial technical issue.
因此，为了更好的适应器件尺寸按比例缩小的要求，半导体工艺逐渐开始从平面MOSFET晶体管向具有更高功效的三维立体式的晶体管过渡，如鳍式场效应管(FinFET)。FinFET具有很好的沟道控制能力。Therefore, in order to better meet the requirement of scaling down the device size, the semiconductor process gradually begins to transition from planar MOSFET transistors to three-dimensional transistors with higher efficiency, such as Fin Field Effect Transistors (FinFETs). FinFET has very good channel control ability.
然而，现有技术形成的半导体结构的电学性能有待提高。However, the electrical performance of the semiconductor structure formed by the prior art needs to be improved.
发明内容Contents of the invention
本发明解决的问题是提供一种半导体结构及其形成方法，提高半导体结构的电学性能。The problem to be solved by the present invention is to provide a semiconductor structure and its forming method to improve the electrical performance of the semiconductor structure.
为解决上述问题，本发明提供一种半导体结构的形成方法，包括：提供基底；对所述基底进行等离子体硫化处理；对所述基底进行等离子体硫化处理之后，在所述基底上形成高K介质层。In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; performing plasma sulfurization treatment on the substrate; after performing plasma sulfurization treatment on the substrate, forming a high-K medium layer.
可选的，所述等离子硫化处理的步骤包括：对所述基底进行掺硫处理；掺硫处理之后，对所述基底进行退火处理。Optionally, the step of the plasma vulcanization treatment includes: performing sulfur doping treatment on the substrate; after the sulfur doping treatment, performing annealing treatment on the substrate.
可选的，采用等离子体H2S气体对所述基底进行掺硫处理。Optionally, the substrate is treated with sulfur doping by using plasma H 2 S gas.
可选的，采用等离子体H2S气体对所述基底进行掺硫处理的工艺参数包括：通入H2S气体，所述H2S气体的气体流量为40sccm至120sccm，功率为500w至1200w，压力为0.5mtorr至20mtorr，温度为500℃至1050℃，时间为60s至150s。Optionally, the process parameters for sulfur-doping the substrate with plasma H 2 S gas include: feeding H 2 S gas, the gas flow rate of the H 2 S gas is 40 sccm to 120 sccm, and the power is 500w to 1200w , the pressure is 0.5mtorr to 20mtorr, the temperature is 500°C to 1050°C, and the time is 60s to 150s.
可选的，所述退火处理的工艺参数包括：温度为400℃至1100℃，时间为80s至120s。Optionally, the process parameters of the annealing treatment include: the temperature is 400°C to 1100°C, and the time is 80s to 120s.
可选的，所述基底为单层结构或者叠层结构。Optionally, the substrate is a single-layer structure or a laminated structure.
可选的，所述基底的材料为：InP、InxGa1-xAs或者GaN中的一种或者多种。Optionally, the material of the substrate is: one or more of InP, InxGa 1-x As or GaN.
可选的，提供所述基底的工艺为选择性外延生长或者金属有机气相沉积。Optionally, the process for providing the substrate is selective epitaxial growth or metal-organic vapor deposition.
可选的，所述高K介质层的材料为：Al2O3或者HfO2中的一种或者多种。Optionally, the material of the high-K dielectric layer is: one or more of Al 2 O 3 or Hf O 2 .
可选的，形成所述高K介质层的工艺为物理气相沉积、化学气相沉积或者原子层沉积。Optionally, the process for forming the high-K dielectric layer is physical vapor deposition, chemical vapor deposition or atomic layer deposition.
相应地，本发明还提供一种半导体结构，包括：基底，对所述基底采用等离子体硫化物进行处理；高K介质层，位于所述基底上。Correspondingly, the present invention also provides a semiconductor structure, comprising: a substrate, the substrate is treated with plasma sulfide; a high-K dielectric layer is located on the substrate.
可选的，所述基底为单层结构或者叠层结构。Optionally, the substrate is a single-layer structure or a laminated structure.
可选的，所述基底的材料为：InP、InxGa1-xAs或者GaN中的一种或者多种。Optionally, the material of the substrate is: one or more of InP, InxGa 1-x As or GaN.
可选的，所述高K介质层的材料为：Al2O3或者HfO2中的一种或者多种。Optionally, the material of the high-K dielectric layer is: one or more of Al 2 O 3 or Hf O 2 .
与现有技术相比，本发明的技术方案具有以下优点：Compared with the prior art, the technical solution of the present invention has the following advantages:
先提供基底，再对所述基底进行等离子体硫化处理，之后再在所述基底上形成高K介质层。采用等离子硫化物气体对所述基底进行掺硫处理，由于所述等离子硫化物气体掺入基底的深度和浓度便于控制，能够使得硫离子掺入所述基底的深度和浓度大，从而在后续半导体高温制程中，使得所述硫离子在所述基底中的稳定性好，不容易发生流失。所述硫离子掺入所述基底中，能够修复所述基底中的晶格缺陷，从而改善了所述基底的界面性能。后续再在所述基底上形成所述高K介质层的步骤中，由于所述基底的界面性能好，从而使得所述高K介质层的质量也得到提高，从而使得半导体结构的漏电率得到降低，因此改善了所述半导体结构的电学性能。A substrate is firstly provided, and then plasma sulfurization is performed on the substrate, and then a high-K dielectric layer is formed on the substrate. Using plasma sulfide gas to carry out sulfur doping treatment on the substrate, because the depth and concentration of the plasma sulfide gas doped into the substrate are easy to control, it can make the depth and concentration of sulfur ions doped into the substrate large, so that in the subsequent semiconductor In the high-temperature process, the stability of the sulfide ions in the substrate is good, and the loss is not easy to occur. The sulfide ions doped into the substrate can repair lattice defects in the substrate, thereby improving the interface properties of the substrate. In the subsequent step of forming the high-K dielectric layer on the substrate, due to the good interface performance of the substrate, the quality of the high-K dielectric layer is also improved, thereby reducing the leakage rate of the semiconductor structure , thus improving the electrical performance of the semiconductor structure.
可选方案中，采用等离子体H2S气体对所述基底进行掺硫处理，具体工艺参数包括：通入H2S气体，所述H2S气体的气体流量为40sccm至120sccm，功率为500w至1200w，压力为0.5mtorr至20mtorr，温度为500℃至1050℃，时间为60s至150s。由于所述H2S气体容易形成等离子体(DPS plasma)，通过调节掺硫处理的工艺参数，将所述工艺参数控制在适当的范围内，可以使得硫离子掺入基底的深度和浓度较大，后续再对所述基底进行退火处理后，所述硫离子在所述基底中被激活，并修复所述基底中的晶格缺陷，从而使得所述基底的界面性能得到改善。由于所述掺硫后基底的界面性能好，在所述基底上形成高K介质层时，相应地也提高了所述高K介质层的质量，因此降低了所述半导体结构的漏电率。In an optional solution, the substrate is treated with sulfur doping by using plasma H 2 S gas, and the specific process parameters include: feeding H 2 S gas, the gas flow rate of the H 2 S gas is 40 sccm to 120 sccm, and the power is 500w to 1200w, the pressure is 0.5mtorr to 20mtorr, the temperature is 500°C to 1050°C, and the time is 60s to 150s. Since the H 2 S gas is easy to form plasma (DPS plasma), by adjusting the process parameters of the sulfur doping treatment, the process parameters are controlled within an appropriate range, so that the depth and concentration of sulfur ions doped into the substrate can be greater After the substrate is subsequently annealed, the sulfide ions are activated in the substrate and repair lattice defects in the substrate, so that the interface performance of the substrate is improved. Since the interface performance of the sulfur-doped substrate is good, when the high-K dielectric layer is formed on the substrate, the quality of the high-K dielectric layer is correspondingly improved, thereby reducing the leakage rate of the semiconductor structure.
附图说明Description of drawings
图1至图2是半导体结构形成过程的结构示意图；1 to 2 are structural schematic diagrams of the process of forming a semiconductor structure;
图3至图5是本发明实施例半导体结构形成过程的结构示意图。3 to 5 are structural schematic diagrams of the formation process of the semiconductor structure according to the embodiment of the present invention.
具体实施方式Detailed ways
根据背景技术形成的半导体结构的电学性能有待提高。图1和图2示出了半导体结构形成过程的结构示意图，现结合图1和图2对半导体结构的电学性能有待提高的原因进行分析。The electrical performance of semiconductor structures formed according to the background art needs to be improved. FIG. 1 and FIG. 2 show schematic structural diagrams of the process of forming a semiconductor structure. The reasons why the electrical performance of the semiconductor structure needs to be improved are now analyzed in conjunction with FIG. 1 and FIG. 2 .
参考图1，提供基底100；采用(NH4)2S溶液对所述基底100进行掺硫处理。Referring to FIG. 1 , a substrate 100 is provided; the substrate 100 is treated with sulfur doping using (NH 4 ) 2 S solution.
参考图2，采用(NH4)2S溶液对所述基底100进行掺硫处理之后，在所述基底100上形成介电层110。Referring to FIG. 2 , after the substrate 100 is treated with sulfur doping using (NH 4 ) 2 S solution, a dielectric layer 110 is formed on the substrate 100 .
上述形成方法形成的半导体结构电学性能有待提高。The electrical performance of the semiconductor structure formed by the above forming method needs to be improved.
经分析发现，导致所述半导体结构电学性能有待提高的原因包括：由于所述(NH4)2S溶液具有较大的腐蚀性，采用(NH4)2S溶液对所述基底100进行掺硫处理之后，容易对所述基底100造成界面损伤，从而对所述基底100的界面性能产生不良影响。此外，由于采用(NH4)2S溶液处理之后，硫离子掺入所述基底100的深度和浓度较小，在后续半导体高温制程中容易造成流失，从而导致硫离子修复所述基底100晶格缺陷的效果差。After analysis, it was found that the reasons for the electrical performance of the semiconductor structure to be improved include: because the (NH 4 ) 2 S solution is highly corrosive, the substrate 100 was doped with sulfur by using the (NH 4 ) 2 S solution. After the treatment, it is easy to cause interface damage to the substrate 100 , thereby adversely affecting the interface properties of the substrate 100 . In addition, after the treatment with (NH 4 ) 2 S solution, the depth and concentration of sulfide ions doped into the substrate 100 are relatively small, which will easily cause loss in the subsequent high-temperature semiconductor manufacturing process, thus causing sulfide ions to repair the crystal lattice of the substrate 100 Defects are less effective.
采用(NH4)2S溶液对所述基底100进行掺硫处理之后，还在所述基底100上形成介电层110，相应地也会造成所述介电层110的质量差。结合上述两个方面，所述基底100与所述介电层110之间的界面性能差，且所述介电层110的质量差，从而导致所述半导体结构的漏电率增大，因此降低了所述半导体结构的电学性能。After the sulfur doping treatment is performed on the substrate 100 by using the (NH 4 ) 2 S solution, a dielectric layer 110 is also formed on the substrate 100 , which correspondingly causes poor quality of the dielectric layer 110 . Combining the above two aspects, the interface performance between the substrate 100 and the dielectric layer 110 is poor, and the quality of the dielectric layer 110 is poor, resulting in an increase in the leakage rate of the semiconductor structure, thereby reducing the Electrical properties of the semiconductor structure.
为了解决上述问题，本发明实施例中，采用等离子体硫化处理的方法对所述基底进行掺硫处理，能够使得所述硫离子在所述基底中稳定性好，不易流失，并能够修复所述基底的晶格缺陷，从而改善了所述基底的界面性能。相应地，由于所述基底的界面性能好，从而使得形成的所述高K介质层的质量也得到提高，从而所述半导体结构的漏电率得到降低，进而改善了所述半导体结构的电学性能。In order to solve the above problems, in the embodiment of the present invention, the method of plasma vulcanization treatment is used to do sulfur-doped treatment on the substrate, which can make the sulfur ions in the substrate stable and not easy to be lost, and can repair the lattice defects of the substrate, thereby improving the interfacial properties of the substrate. Correspondingly, due to the good interface performance of the substrate, the quality of the formed high-K dielectric layer is also improved, thereby reducing the leakage rate of the semiconductor structure, thereby improving the electrical performance of the semiconductor structure.
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.
图3至图5是本发明实施例半导体结构形成过程的结构示意图。3 to 5 are structural schematic diagrams of the formation process of the semiconductor structure according to the embodiment of the present invention.
参考图3，提供基底200。Referring to FIG. 3 , a substrate 200 is provided.
本实施例中，所述基底200为单层结构或者叠层结构。In this embodiment, the substrate 200 is a single-layer structure or a laminated structure.
本实施例中，所述基底200选用能够提高载流子迁移率的III-V族材料，具体为：InP、InxGa1-xAs或者GaN中的一种或者多种。在本发明其他实施例中，所述基底的材料还可以为：Si、Ge、SiGe、SiC、GaAs或者InGa中的一种或者多种。In this embodiment, the substrate 200 is selected from III-V group materials that can improve carrier mobility, specifically: one or more of InP, InxGa 1-x As or GaN. In other embodiments of the present invention, the material of the substrate may also be: one or more of Si, Ge, SiGe, SiC, GaAs or InGa.
本实施例中，提供所述基底200的工艺为选择性外延生长。采用选择性外延生长工艺能够改善所述基底200的晶格缺陷，提高所述基底200的质量。在本发明其他实施例中，形成所述基底的工艺还可以为金属有机气相沉积。In this embodiment, the process of providing the substrate 200 is selective epitaxial growth. Adopting the selective epitaxial growth process can improve the lattice defects of the substrate 200 and improve the quality of the substrate 200 . In other embodiments of the present invention, the process of forming the substrate may also be metal-organic vapor deposition.
参考图4，对所述基底200进行等离子体硫化处理。Referring to FIG. 4 , the substrate 200 is subjected to plasma vulcanization treatment.
本实施例中，采用等离子硫化物气体对所述基底200进行掺硫处理之后，使得硫离子掺入所述基底200的深度和浓度大，从而在后续半导体高温制程中，使得所述硫离子在所述基底200中的稳定性好，不容易发生流失。In this embodiment, after the sulfur doping treatment is performed on the substrate 200 by using plasma sulfide gas, the depth and concentration of sulfur ions doped into the substrate 200 are large, so that in the subsequent high-temperature semiconductor manufacturing process, the sulfur ions are The substrate 200 has good stability and is not easy to be lost.
掺入所述基底200的硫离子，用于修复所述基底200中的晶格缺陷，从而改善了所述基底200的界面性能。后续再在所述基底200上形成所述高K介质层210的步骤中，由于所述基底200的界面性能好，从而使得所述高K介质层210的质量也得到提高。The sulfide ions doped into the substrate 200 are used to repair lattice defects in the substrate 200 , thereby improving the interface properties of the substrate 200 . In the subsequent step of forming the high-K dielectric layer 210 on the substrate 200, the quality of the high-K dielectric layer 210 is also improved due to the good interface performance of the substrate 200.
结合上述两个方面，由于所述基底200与所述高K介质层210之间的界面性能好，且所述高K介质层210的质量高，从而使得半导体结构的漏电率得到降低，因此改善了所述半导体结构的电学性能。Combining the above two aspects, since the interface performance between the substrate 200 and the high-K dielectric layer 210 is good, and the quality of the high-K dielectric layer 210 is high, the leakage rate of the semiconductor structure is reduced, thus improving electrical properties of the semiconductor structure.
本实施例中，所述等离子体硫化处理的步骤包括：对所述基底200进行掺硫处理；掺硫处理之后，对所述基底200进行退火处理。In this embodiment, the step of the plasma vulcanization treatment includes: performing sulfur doping treatment on the substrate 200 ; and performing annealing treatment on the substrate 200 after the sulfur doping treatment.
具体地，在所述掺硫处理的步骤中，采用等离子体H2S气体对所述基底200进行掺硫处理。由于所述H2S气体很容易形成等离子体，通过调节所述等离子体H2S气体掺硫处理的工艺参数，可以使得硫离子掺入基底200的深度和浓度较大。进行所述掺硫处理之后，对所述基底200进行退火处理，使得所述硫离子在所述基底200中被激活，从而发挥修复所述基底200中晶格缺陷的作用，进而提高了所述基底200的界面性能。Specifically, in the step of sulfur doping treatment, sulfur doping treatment is performed on the substrate 200 by using plasma H 2 S gas. Since the H 2 S gas is easy to form plasma, by adjusting the process parameters of the sulfur doping treatment of the plasma H 2 S gas, the depth and concentration of sulfur ions doped into the substrate 200 can be increased. After the sulfur doping treatment, the substrate 200 is annealed, so that the sulfur ions are activated in the substrate 200, thereby playing a role in repairing lattice defects in the substrate 200, thereby improving the Interface properties of the substrate 200.
本实施例中，采用等离子体H2S气体对所述基底200进行掺硫处理的工艺参数包括：通入H2S气体，所述H2S气体的气体流量为40sccm至120sccm，功率为500w至1200w，压力为0.5mtorr至20mtorr，温度为500℃至1050℃，时间为60s至150s。In this embodiment, the process parameters for sulfur doping treatment of the substrate 200 using plasma H 2 S gas include: feeding H 2 S gas, the gas flow rate of the H 2 S gas is 40 sccm to 120 sccm, and the power is 500w to 1200w, the pressure is 0.5mtorr to 20mtorr, the temperature is 500°C to 1050°C, and the time is 60s to 150s.
所述H2S气体容易形成等离子体，将所述进行掺硫处理的工艺参数控制在适当的范围内，能够使得硫离子掺入所述基底200的深度和浓度满足半导体结构的需求。例如，本实施例中，所述等离子体H2S气体的气体流量在40sccm至120sccm范围内。若所述等离子体H2S气体的气体流量过小，则会导致硫离子掺入的浓度过小，从而影响所述基底200界面的修复性能；若所述等离子体H2S气体的气体流量过大，则又会对所述基底200的电学性能产生不良影响。本实施例中，所述掺硫处理的功率在40sccm至120sccm范围内。若所述掺硫处理的功率过小，则会导致硫离子掺入基底200的深度不够；若所述掺硫处理的功率过大，又会对所述基底200表面造成损伤。The H 2 S gas is easy to form plasma, and the process parameters of the sulfur doping treatment are controlled within an appropriate range, so that the depth and concentration of sulfur ions doped into the substrate 200 can meet the requirements of the semiconductor structure. For example, in this embodiment, the gas flow rate of the plasma H 2 S gas is in the range of 40 sccm to 120 sccm. If the gas flow rate of the plasma H 2 S gas is too small, the concentration of sulfur ion doping will be too small, thereby affecting the repair performance of the interface of the substrate 200; if the gas flow rate of the plasma H 2 S gas If it is too large, it will adversely affect the electrical performance of the substrate 200 . In this embodiment, the power of the sulfur doping treatment is in the range of 40 sccm to 120 sccm. If the power of the sulfur doping treatment is too low, the depth of sulfur ions doped into the substrate 200 will be insufficient; if the power of the sulfur doping treatment is too high, the surface of the substrate 200 will be damaged.
本实施例中，所述退火处理的工艺参数包括：温度为400℃至1100℃，时间为80s至120s。若所述退火处理的温度过低，时间过短，则使得位于所述基底200内的硫离子很难被激活发挥作用；若所述退火处理的温度过高，时间过长，又会导致所述硫离子容易扩散出去，使得硫离子修复基底200中晶格缺陷的效果差。In this embodiment, the process parameters of the annealing treatment include: the temperature is 400°C to 1100°C, and the time is 80s to 120s. If the temperature of the annealing treatment is too low and the time is too short, it will be difficult for the sulfide ions located in the substrate 200 to be activated to play a role; if the temperature of the annealing treatment is too high and the time is too long, it will cause the The sulfur ions are easy to diffuse out, so that the sulfur ions are less effective in repairing lattice defects in the substrate 200 .
参考图5，对所述基底200进行等离子体硫化处理之后，在所述基底200上形成高K介质层210。Referring to FIG. 5 , after performing plasma sulfurization on the substrate 200 , a high-K dielectric layer 210 is formed on the substrate 200 .
本实施例中，由于所述基底200中掺杂有硫离子，并具有良好的界面性能，使得在所述基底200上形成的高K介质层210的质量高。所述高K介质层210具有良好的绝缘性能，并可以减小所述半导体结构的漏电率。所述高K介质层210的材料为：Al2O3或者HfO2中的一种或者多种。In this embodiment, since the substrate 200 is doped with sulfur ions and has good interface properties, the quality of the high-K dielectric layer 210 formed on the substrate 200 is high. The high-K dielectric layer 210 has good insulation properties and can reduce the leakage rate of the semiconductor structure. The material of the high-K dielectric layer 210 is one or more of Al 2 O 3 or Hf O 2 .
本实施例中，形成所述高K介质层210的工艺为：物理气相沉积、化学气相沉积或者原子层沉积。In this embodiment, the process of forming the high-K dielectric layer 210 is: physical vapor deposition, chemical vapor deposition or atomic layer deposition.
相应地，本发明还提供一种半导体结构，参考图5，包括：基底200，对所述基底200采用等离子体硫化物进行处理；高K介质层210，位于所述基底200上。Correspondingly, the present invention also provides a semiconductor structure, referring to FIG. 5 , including: a substrate 200 , which is treated with plasma sulfide; and a high-K dielectric layer 210 located on the substrate 200 .
本实施例中，所述基底200掺杂硫离子的深度和浓度较大，从而在后续半导体高温制程中，具有较好的稳定性，不容易发生扩散。同时，位于所述基底200中的硫离子可以起到修复基底200晶格缺陷的作用，有利于改善所述基底200的界面性能。相应地，由于所述基底200具有良好地界面性能，在所述基底200上形成的高K介质层210的质量较好。结合上述两个方面，由于所述基底200与所述高K介质层210之间具有良好的界面性能，且所述高K介质层210的质量好，从而降低了所述半导体结构的漏电率，改善了所述半导体结构的电学性能。In this embodiment, the base 200 is doped with sulfur ions at a higher depth and concentration, so that it has better stability and is less prone to diffusion in the subsequent high-temperature semiconductor manufacturing process. At the same time, the sulfur ions in the substrate 200 can repair lattice defects of the substrate 200 , which is beneficial to improve the interface performance of the substrate 200 . Correspondingly, since the substrate 200 has good interface properties, the quality of the high-K dielectric layer 210 formed on the substrate 200 is better. Combining the above two aspects, since the substrate 200 and the high-K dielectric layer 210 have good interface performance, and the quality of the high-K dielectric layer 210 is good, thereby reducing the leakage rate of the semiconductor structure, The electrical performance of the semiconductor structure is improved.
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.
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