CN103632975B - PMOS transistor and preparation method thereof - Google Patents

Abstract

A method for manufacturing a PMOS transistor, comprising: providing a substrate, where a sigma-shaped groove is formed in a region where a source region and a drain region are to be formed in the substrate; filling the first silicon-germanium material layer into the sigma-shaped groove , the first silicon-germanium material layer does not fill the sigma-shaped groove; remove part of the thickness of the first silicon-germanium material layer at the bottom of the sigma-shaped groove; fill the second silicon into the sigma-shaped groove The germanium material layer stops filling up, and the germanium content of the second silicon germanium material layer is higher than the germanium content of the first silicon germanium material layer. In addition, the present invention also provides the PMOS transistor manufactured by the above manufacturing method. By adopting the technical scheme of the invention, the carrier mobility of the PMOS transistor can be improved.

Description

PMOS transistor and its manufacturing method

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a PMOS transistor and a manufacturing method thereof.

Background technique

In the existing manufacturing process of semiconductor devices, since stress can change the energy gap and carrier mobility of silicon materials, it has become an increasingly common means to improve the performance of MOS transistors through stress. Specifically, by properly controlling the stress, the mobility of carriers (electrons in NMOS transistors and holes in PMOS transistors) can be increased, thereby increasing the driving current, thereby greatly improving the performance of MOS transistors. For PMOS transistors, embedded silicon germanium technology (Embedded SiGe Technology) can be used to generate compressive stress in the channel region of the transistor, thereby improving carrier mobility. The so-called embedded silicon germanium technology refers to embedding silicon germanium materials in the regions where the source region and the drain region need to be formed on the semiconductor substrate, and using the lattice mismatch between silicon and silicon germanium (SiGe) to generate compressive stress on the channel region .

Fig. 1 is a cross-sectional view of a PMOS transistor using embedded silicon germanium technology, as shown in Fig. layer 11 and the side walls 13 on both sides of the gate 12, and the source 14 and the drain 15 respectively formed on both sides of the gate insulating layer 11 and the gate 12, wherein the source 14 and the drain 15 are filled in The sigma-shaped groove 16 is made of silicon germanium material. The sigma-shaped groove 16, whose shape is close to the symbol Σ, has a groove tip 161, and the compressive stress generated by the silicon germanium material on the channel region is realized by generating pressure on the upper surface 1611 and the lower surface 1612 forming the groove tip 161 of. In order to avoid the problem of poor growth of silicon germanium material in the groove 16 caused by the large lattice mismatch between silicon germanium and silicon, generally a buffer layer with a low germanium content is formed in the sigma-shaped groove 16 first, and then The buffer layer is filled with silicon germanium material with higher germanium content.

However, the present inventors found that the PMOS transistor formed by the above method is not effective in improving the carrier mobility when studying the PMOS transistor embedded with silicon germanium.

Contents of the invention

The purpose of the present invention is to provide a new PMOS transistor and its manufacturing method, so as to improve its carrier mobility.

In order to achieve the above object, the manufacturing method of the PMOS transistor provided by the present invention includes:

A single crystal silicon substrate is provided, and a sigma-shaped groove is formed in a region where a source region and a drain region are to be formed in the substrate;

filling the first silicon-germanium material layer into the sigma-shaped groove, and the first silicon-germanium material layer does not fill the sigma-shaped groove;

removing a partial thickness of the first silicon germanium material layer at the bottom of the sigma-shaped groove;

Filling the second silicon germanium material layer into the sigma-shaped groove until the filling stops, the germanium content of the second silicon germanium material layer is higher than the germanium content of the first silicon germanium material layer.

Optionally, removing part of the thickness of the first silicon germanium material layer at the bottom of the sigma-shaped groove is achieved by treating with an alkaline solution.

Optionally, the alkaline solution is TMAH solution or ammonia water.

Optionally, the treatment temperature is 20-100°C, and the treatment time is 5-100s.

Optionally, the atomic number of germanium in the first silicon-germanium material layer filled into the sigma-shaped groove is 5-30%.

Optionally, when filling the first silicon germanium material layer into the sigma-shaped groove, in-situ doping of P-type elements is performed.

Optionally, the doping element in the P-type element in-situ doping performed when filling the first silicon germanium material layer into the sigma-shaped groove is boron, and the doping dose is 0.1-5E20/cm ³ .

Optionally, the thickness of the first silicon germanium material layer filled into the sigma-shaped groove is 2-5 nm.

Optionally, the atomic number of germanium in the second silicon-germanium material layer filled into the sigma-shaped groove is 20-60%

Optionally, in-situ doping of P-type elements is performed when filling the second silicon germanium material layer into the sigma-shaped groove.

Optionally, the doping element in the P-type element in-situ doping performed when filling the second silicon germanium material layer into the sigma-shaped groove is boron, and the doping dose is 0.1-5E20/cm ³ .

Optionally, the thickness of the second silicon-germanium material layer filled into the sigma-shaped groove is 3-10 nm.

Optionally, after filling the second silicon-germanium material layer into the sigma-shaped groove until the filling stops, a third silicon-germanium material layer is formed at least on the second silicon-germanium material layer, and the third silicon-germanium material layer is The germanium content of the germanium material layer is lower than the germanium content of the second silicon germanium material layer.

Optionally, the atomic number of germanium in the formed third silicon-germanium material layer accounts for less than 30%

Optionally, in-situ doping of P-type elements is performed when forming the third silicon germanium material layer.

Optionally, the doping element in the P-type element in-situ doping performed when forming the third silicon germanium material layer is boron, and the doping dose is 0.1-5E20/cm ³ .

Optionally, the formed third silicon germanium material layer has a thickness less than 5 nm.

Optionally, the method for forming the sigma-shaped groove is: forming a gate structure on the substrate, forming sidewalls on both sides of the gate structure, and using the gate structure and the sidewalls as a mask A sigma-shaped groove is formed in a region of the substrate where the source region and the drain region are to be formed.

In addition, the present invention also provides a PMOS transistor manufactured according to any one of the above methods.

Compared with the prior art, the present invention has the following advantages:

1) The disadvantage of the existing solutions for forming embedded silicon-germanium PMOS transistors is that the buffer layer (silicon-germanium material layer with low germanium content, which is equivalent to the first layer of silicon-germanium material layer) is formed on the lower surface of the groove tip (corresponding to The 111 crystal system of silicon germanium material) deposition rate is slower than the deposition rate at the bottom of the groove (corresponding to the 100 crystal system of silicon germanium material), resulting in the first layer of silicon germanium material layer with low germanium concentration occupying the sigma-shaped groove More space limits the filling amount of the second silicon-germanium material layer with high germanium concentration, thus limiting the stress applied to the channel, in other words, the pressure applied to the channel is not enough. Different from the above solution, the present invention removes part of the buffer layer at the bottom of the sigma-shaped groove after forming the buffer layer, and then fills it with a filling layer (ie, the second layer of silicon germanium material). In this way, the volume of the silicon-germanium material layer with high germanium content in the groove is increased, and the stress on the channel is increased. This solution provides an embedded silicon-germanium PMOS transistor that applies uniform compressive stress to the channel, and applies enough pressure to the channel. The compressive stress can make the carrier mobility of the PMOS transistor better.

2) In the optional solution, the removal of the buffer layer is achieved by TMAH solution treatment. The corrosion rate of the 100 crystal system of silicon germanium material using the TMAH solution is higher than that of the 111 crystal system, and the TMAH solution is environmentally friendly. pollute.

3) In the alternative scheme, there are two schemes for forming the source and drain regions of the PMOS transistor: the first one: after forming the buffer layer and filling the groove with the filling layer, the material filled in the groove is doped with ion implantation. In the second type, in the process of forming the buffer layer and filling the groove with the filling layer, the P well is formed by in-situ doping. The in-situ doping means depositing silicon germanium material while doping to avoid The disadvantage of the first method is easy to generate defects in the formed source region and drain region.

4) In an optional solution, after filling the second silicon-germanium material layer into the sigma-shaped groove until the filling stops, a third silicon-germanium material layer (cap layer) is also formed on the second silicon-germanium material layer, and the third silicon-germanium material layer The germanium content of the germanium material layer is lower than the germanium content of the second silicon germanium material layer. The advantage is: filling the sigma-shaped groove with a thinner first silicon-germanium material layer and then filling the second silicon-germanium material layer until the filling stops. The purpose is to form a source region and a drain region. For the electrical connection of other devices, metal interconnection structures, such as conductive plugs, etc. will be formed later on. Due to the high silicon content of the third silicon germanium material layer, it is easy to form metal silicide to reduce the source region, drain region and conductivity. Contact resistance between plugs.

Description of drawings

FIG. 1 is a schematic cross-sectional view of an existing embedded silicon-germanium PMOS transistor;

Figure 2 shows the defects of the structure shown in Figure 1;

Fig. 3 is a schematic diagram of the growth rate of each crystal system of silicon germanium material;

4 is a flowchart of a method for manufacturing a PMOS transistor according to Embodiment 1 of the present invention;

5 to 7 are schematic diagrams of the intermediate structure of the PMOS transistor formed according to the process of FIG. 4;

FIG. 8 is a schematic diagram of the final structure of the PMOS transistor formed according to the process of FIG. 4;

FIG. 9 is a schematic cross-sectional structure diagram of the PMOS transistor in the third embodiment.

detailed description

In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. Since the emphasis is on explaining the principle of the present invention, the drawings are not drawn to scale.

As mentioned above, as shown in FIG. 2 , the existing solution for forming embedded silicon-germanium PMOS transistors is to first form a buffer layer 171 with a low germanium content in the sigma-shaped groove, and then use germanium on the buffer layer 171 The SiGe material 172 with higher content is filled. The lattice structure of silicon germanium material is diamond structure, with 100, 111, 110 and other crystal systems.

In order to show the deposition rate of the buffer layer 171 corresponding to each crystal system, based on its deposition rate on the crystal system 111, the deposition rates corresponding to the crystal systems 100, 110, etc. are shown in FIG. 3 . 2 and 3, the deposition rate formed on the upper and lower surfaces 1611, 1612 (corresponding to the 111 crystal system of silicon germanium material) of the groove tip 161 is slower than that at the bottom of the groove 16 (corresponding to the 100 crystal system of silicon germanium material). ) deposition rate, which will easily lead to deformation of the sigma-shaped groove 16 space filled with the silicon-germanium material 172 with higher germanium content after the buffer layer 171 is formed, thus resulting in insufficient compressive stress applied to the channel, especially when forming The compressive stress on the lower surface 1612 of the sigma-shaped groove tip 161 near the bottom of the groove 16 is too small.

In view of the above problems, three manufacturing methods of PMOS transistors are provided below to solve them.

Embodiment one

Combining the flow chart of FIG. 4 and the cross-sectional schematic diagram shown in FIG. 5 , step S11 is first performed to provide a single crystal silicon substrate 20 , where the source region 24 and the drain region 25 (refer to FIG. 8 ) are to be formed in the substrate 20 A sigma-shaped groove 26 is formed.

Specifically, referring to FIG. 5 , the method for forming the sigma-shaped groove 26 is: forming a gate structure on the substrate 20, forming sidewalls 23 on both sides of the gate structure, and using the gate structure and the sidewalls 23 as a mask. The mold is etched to form a sigma-shaped groove 26 in the region where the source region 24 and the drain region 25 are to be formed in the substrate. In this embodiment, the gate structure includes a gate oxide layer 21 formed on the substrate 20 , and a gate 22 formed on the gate oxide layer 21 . The method for forming the sigma-shaped groove 26 can also refer to other existing processes.

The sigma-shaped groove 26 is similar in shape to the existing sigma-shaped groove, and also has a groove tip 261 , and the groove tip 261 is composed of an upper surface 2611 and a lower surface 2612 .

Next, step S12 is executed to fill the first silicon germanium material layer 271 into the sigma-shaped groove 26 , and the first silicon-germanium material layer 271 does not fill the sigma-shaped groove 26 .

The germanium content of the first silicon germanium material layer 271 is relatively low, which can prevent the interface between the silicon germanium material with a relatively high germanium content and the silicon in the substrate 20 from causing a large lattice mismatch, and avoid causing the latter to grow. The effect is poor. It can be understood that the first silicon germanium material layer 271 acts as a buffer, so it is also called a buffer layer. Based on this, if the chemical formula Si _1-x Ge _x is used to represent the material of the first silicon-germanium material layer 271, the range of x is 5-30%. In other words, the percentage of germanium atoms in the buffer layer 271 is 5-30. %. The first silicon-germanium material layer 271 is based on the function of buffering. If its thickness is too thick, the effect of improving electron mobility is not good. If its thickness is too thin, it is difficult to avoid the problem of large lattice mismatch. The inventors found that the thickness of the buffer layer 271 When the range is 2~5nm, the above-mentioned problems caused by too thick and too thin can be avoided.

After this step is performed, a schematic cross-sectional view of the formed structure is shown in FIG. 6 .

Then, step S13 is executed, referring to FIG. 7 , removing part of the thickness of the first silicon germanium material layer 271 at the bottom of the sigma-shaped groove 26 .

Based on the defect analysis of the above-mentioned prior art, in this step, the best solution for the removal amount of part of the thickness at the bottom of the groove 26 is: after the buffer layer 271 is filled, the remaining space of the sigma-shaped groove 26 still maintains the original sigma shape The shape of the groove 26. But even so, removing part of the thickness of the buffer layer 271 at the bottom of the groove 26 can still improve the shape of the remaining space of the sigma-shaped groove 26 after the buffer layer 271 is filled, making it close to the shape of the original sigma-shaped groove 26 .

In this embodiment, in order to achieve the above purpose, part of the thickness of the buffer layer 271 at the bottom of the groove 26 is removed by alkaline solution treatment in this step. The alkaline solution has the property that the removal rate of the 100 crystal system of the silicon germanium material is greater than that of the 111 crystal system. The 100 crystal system corresponds to the plane of the bottom of the groove 26 , and the 111 crystal system corresponds to the respective planes forming the upper surface 2611 and the lower surface 2612 of the groove tip 261 .

During specific implementation, the alkaline solution can be selected from a variety of options, such as TMAH solution (tetramethylammonium hydroxide solution), KOH solution, ammonia water, etc., but based on the purpose of not introducing impurities, TMAH solution and ammonia water are preferably used.

No matter what kind of alkaline solution is used, the length of treatment time will cause the difference in the removal amount. The inventors found that 5-100 s can realize the excess thickness at the bottom of the groove 26 caused by the thickness of the buffer layer 271 in the range of 2-5 nm. In addition, the inventors also found that during the above-mentioned alkaline solution treatment process, the treatment temperature also has a slight influence on the removal amount, but it has a nonlinear relationship with the removal amount. To remove the over-thickness that appears at the bottom of the groove 26, the temperature range of 20-100°C can meet the requirements. For example, using a 70.9°C KOH solution with a mass percentage of 34%, within the same treatment time, the removal thickness for the 100 crystal system (corresponding to the bottom of the groove) is 0.629 μm, and for the 111 crystal system (corresponding to the upper and lower surfaces 2611, 2612) The removal thickness is 0.009μm, and the removal rate ratio between the two is approximately 151:1. Using 79.8°C TMAH solution with a mass percentage of 20%, within the same treatment time, the removal thickness of the 100 crystal system (corresponding to the bottom of the groove) is 0.603 μm, and the removal thickness of the 111 crystal system (corresponding to the upper and lower surfaces 2611, 2612) is 0.017μm, and the removal rate ratio between the two is approximately 68:1.

In this embodiment, after this step is performed, a schematic cross-sectional view of the formed structure is shown in FIG. 7 , and the formed new buffer layer is marked with 271'.

Afterwards, step S14 is executed, as shown in FIG. 8 , the second silicon-germanium material layer 272 is filled in the sigma-shaped groove 26 until the filling stops, and the germanium content of the second silicon-germanium material layer 272 is higher than that of the first silicon-germanium material layer. Germanium content of layer 271.

In this step, the purpose of the second silicon-germanium material layer 272 is to apply compressive stress to the boundaries between the groove 26 and the substrate 20. It can be understood that the second silicon-germanium material layer 272 mainly plays a role in applying compressive stress. Therefore, it is also called the filling layer. Based on this, if the chemical formula Si _1-y Ge _y is used to represent the material of the second silicon-germanium material layer 272, the range of y is 20-60%. In other words, the percentage of germanium atoms in the filling layer 272 is 20-60%. %; preferably, the range of y is 40-60%, that is, the percentage of germanium atoms in the filling layer 272 is 40-60%. The second silicon germanium material layer 272 mainly applies compressive stress, and its thickness range is preferably 3-10 nm.

After the above steps are completed, as shown in FIG. 8 , the sigma-shaped groove 26 has been filled. Next, according to the needs of the source region 24 and the drain region 25 , P-type ion implantation is performed in the SiGe material filled in the sigma-shaped groove 26 .

Embodiment two

The PMOS transistor provided in the second embodiment and its manufacturing method are substantially the same as those in the first embodiment. The difference is that the timing of P-type ion implantation in the source region 24 and the drain region 25 is different. It is mainly reflected in the following two points.

1) During the execution of step S12, the buffer layer 271 finally forms part of the structure of the source region 24 and the drain region 25. Therefore, in order to form a PMOS transistor, in-situ doping can also be used in the step of forming the buffer layer 271 in this step Forming a P well, the in-situ doping means depositing silicon germanium material while doping, avoiding ion implantation of P-type elements after the source region 24 and drain region 25 are formed. Defects are generated in the drain region 25 .

Specifically, the P-type element may be boron, and the inventors found that the performance of the PMOS transistor can be satisfied when the doping amount thereof is, for example, but not limited to 0.1-5E20/cm ³ .

2) During the execution of step S14, the filling layer 272 finally forms part of the structure of the source region 24 and the drain region 25. Therefore, in order to form a PMOS transistor, in this step, the filling layer 272 can also be formed in situ. Doping to form a P well, the in-situ doping means depositing silicon germanium material while doping, avoiding ion implantation of P-type elements after the source region 24 and drain region 25 are formed. 24 and drain region 25 have defects.

Specifically, the P-type element may be boron, and the inventors found that the performance of the PMOS transistor can be satisfied when the doping amount thereof is, for example, but not limited to 0.1-5E20/cm ³ .

Embodiment Three

The PMOS transistor provided in the third embodiment and its manufacturing method are substantially the same as those in the first embodiment. The difference is that, as shown in FIG. 9 , step S13 fills the sigma-shaped groove 26 with the second silicon-germanium material layer 272 until the filling stops, and then forms a silicon-germanium layer on the surface of the substrate 20 between adjacent sidewalls 23 . The third silicon germanium material layer 273 , the germanium content of the third silicon germanium material layer 273 is lower than the germanium content of the second silicon germanium material layer 272 . The third SiGe material layer 273 is intended to be formed on the source region 24 and the drain region 25 , but at least needs to cover the second SiGe material layer 272 .

In some cases, the PMOS transistors produced in the first and second embodiments will subsequently form metal interconnection structures (such as conductive plugs, etc.) on the source region 24 and the drain region 25 to realize electrical connection with other devices. To reduce the contact resistance between the source region 24 and the drain region 25 and the conductive plug of the metal interconnection structure, a metal silicide can be formed on the third silicon germanium material layer 273 by using a metal silicide process to reduce the contact resistance.

Based on the above-mentioned purpose, the third silicon-germanium material layer 273 is also called a cap layer. If the material of the third silicon-germanium material layer 273 is represented by the chemical formula Si _1-z Ge _z , the range of z is less than 30%. In other words, the cap layer The percentage of atomic number of germanium in 273 is less than 30%.

It should be noted that during the formation of the metal silicide, the third layer of silicon germanium material layer 273 may not be fully used in its entire thickness, and part of the thickness of the third layer of silicon germanium material layer 273 may be used to form the source region 24 and the drain region. Region 25 , therefore, the third silicon germanium material layer 273 is preferably doped with P-type ions, and the doping type and concentration are preferably the same as those of the buffer layer 271 and the filling layer 272 . In addition, the inventors found that doping is also beneficial to the stability of the metal silicide. The doping timing of the third silicon germanium material layer 273 may be the same as that in the first embodiment, or the doping while growing the third layer may be adopted in the second embodiment.

Each embodiment in this specification is described in a progressive manner, and the same and similar parts of each embodiment can be referred to each other, and each example focuses on the difference from other examples.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention, and any person skilled in the art can use the methods disclosed above and technical content to analyze the present invention without departing from the spirit and scope of the present invention. Possible changes and modifications are made in the technical solution. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention, which do not depart from the content of the technical solution of the present invention, all belong to the technical solution of the present invention. protected range.

Claims (19)

1. A manufacturing method of a PMOS transistor, characterized in that, comprising: A substrate is provided, and a sigma-shaped groove is formed in a region where a source region and a drain region are to be formed in the substrate; Filling the first silicon-germanium material layer into the sigma-shaped groove, the first silicon-germanium material layer is in direct contact with the substrate of the sidewall of the sigma-shaped groove, and does not fill the sigma-shaped groove; removing a partial thickness of the first silicon germanium material layer at the bottom of the sigma-shaped groove; Filling the second silicon germanium material layer into the sigma-shaped groove until the filling stops, the germanium content of the second silicon germanium material layer is higher than the germanium content of the first silicon germanium material layer. 2 . The method according to claim 1 , characterized in that, removing the partial thickness of the first silicon-germanium material layer at the bottom of the sigma-shaped groove is achieved by treating with an alkaline solution. 3 . 3. The method according to claim 2, characterized in that, the alkaline solution is TMAH solution or ammoniacal liquor. 4. The method according to claim 2, characterized in that the temperature of the treatment is 20-100°C, and the treatment time is 5-100s. 5 . The method according to claim 1 , characterized in that the percentage of germanium atoms in the first silicon germanium material layer filled into the sigma-shaped groove is 5-30%. 6 . 6 . The method according to claim 1 , characterized in that, when filling the first silicon germanium material layer into the sigma-shaped groove, in-situ doping of P-type elements is performed. 7 . 7 . The method according to claim 6 , wherein the P-type element is boron, and the doping dose is 0.1˜5E20/cm ³ . 8 . The method according to claim 1 , wherein the thickness of the first silicon-germanium material layer filled into the sigma-shaped groove is 2-5 nm. 9 . The method according to claim 1 , characterized in that the percentage of germanium atoms in the second silicon germanium material layer filled into the sigma-shaped groove is 20-60%. 10 . The method according to claim 1 , characterized in that, when filling the second silicon germanium material layer into the sigma-shaped groove, in-situ doping of P-type elements is performed. 11 . 11 . The method according to claim 10 , wherein the P-type element is boron, and the doping dose is 0.1˜5E20/cm ³ . 12 . The method according to claim 1 , wherein the thickness of the second silicon germanium material layer filled into the sigma-shaped groove is 3-10 nm. 13 . 13. The method according to claim 1, characterized in that, after filling the second silicon-germanium material layer into the sigma-shaped groove until the filling stops, a third silicon-germanium material layer is also formed on the second silicon-germanium material layer. For the silicon germanium material layer, the germanium content of the third silicon germanium material layer is lower than the germanium content of the second silicon germanium material layer. 14 . The method according to claim 13 , wherein the germanium atoms in the formed third silicon germanium material layer account for less than 30%. 15 . 15. The method according to claim 13, characterized in that, in-situ doping of P-type elements is performed when forming the third silicon germanium material layer. 16 . The method according to claim 15 , wherein the P-type element is boron, and the doping dose is 0.1˜5E20/cm ³ . 17. The method according to claim 13, characterized in that the thickness of the formed third silicon germanium material layer is less than 5 nm. 18. The method according to claim 1, wherein the method for forming the sigma-shaped groove is: forming a gate structure on the substrate, forming sidewalls on both sides of the gate structure, so as to The gate structure and the sidewall are masks, and a sigma-shaped groove is formed in the region where the source region and the drain region are to be formed in the substrate. 19. A PMOS transistor fabricated according to the method of any one of claims 1 to 18.