CN108389914A - A kind of passivation tunnel layer material preparation and its application in solar cell - Google Patents

Abstract

The present invention relates to the preparation of a passivated tunneling layer material and its application in solar cells. Specifically, the present invention discloses an application for preparing a carrier passivated tunneling film for solar cells. The film contains Tantalum pentoxide (Ta ₂ O ₅ ). The invention also provides a carrier transport structure for preparing solar cells and a preparation method thereof. The carrier passivation tunnel thin film provided by the invention overcomes the shortcomings of silicon oxide as a passivation tunnel layer in the application of passivation contact heterojunction cells.

Description

Preparation of a passivating tunneling layer material and its application in solar cells

technical field

The invention belongs to the field of inorganic materials. Specifically, the invention relates to the preparation of a passivation tunneling layer material and its application in solar cells.

Background technique

In recent years, the tunneling oxygen passivation contact crystalline silicon solar cell (also known as TOPCon or POLO cell in English) has become a hot spot in the international photovoltaic field. The battery device for current collection, the device structure is shown in Figure 1.

Compared with conventional crystalline silicon solar cells, the structure of tunneling oxygen passivated contact crystalline silicon solar cells mainly adds two characteristic functional layers, the silicon oxide passivation tunneling layer and the polysilicon carrier collection layer, to form electrons or holes Selective transport structure. Moreover, the two characteristic functional layers of the tunneling oxygen passivation contact crystalline silicon cell can adopt a high-temperature preparation process, which is compatible with the existing crystalline silicon cell manufacturing process. Therefore, the tunneling oxygen passivation contact crystalline silicon cell is very promising in terms of industrial application.

However, as a passivation tunneling layer, silicon oxide still has too large a band step with silicon, and the thickness needs to be less than 2nm, which is difficult to overcome, which affects the full potential of this structure battery.

Therefore, it is of great significance to develop a new type of passivation tunneling layer material with better performance to improve the performance of tunneling oxygen passivation contact crystalline silicon solar cells.

Contents of the invention

The object of the present invention is to provide a passivation tunneling layer material.

The object of the present invention is also to provide a preparation method and application of a passivation tunneling layer material.

The first aspect of the present invention provides the use of a carrier passivation tunneling film, the carrier passivation tunneling film contains tantalum pentoxide (Ta ₂ O ₅ ); the film is used for preparing solar cells .

In another preferred example, the solar cell is a crystalline silicon solar cell.

In another preferred example, the thickness of the carrier passivation tunneling film is 0.5-5 nm; preferably, 1-2.5 nm.

In another preferred example, the carriers are electrons or holes.

In another preferred example, the preparation method of the carrier passivation tunneling film includes: using magnetron sputtering (Sputter), plasma enhanced chemical vapor deposition (PECVD), thermal evaporation (Thermal Evaporator), electron beam Evaporation (E-beam Evaporator), low-pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD) methods, deposit tantalum pentoxide (Ta ₂ O ₅ ) on silicon wafers to form the carrier passivation tunneling film.

In another preferred embodiment, tantalum pentoxide (Ta ₂ O ₅ ) is deposited by atomic layer deposition (ALD).

In another preferred example, the preparation method adopts atomic layer deposition (ALD), comprising the steps of:

(a) in the vacuum cavity loaded with silicon wafers, the gas containing tantalum (Ta) precursor molecules is passed into;

(b) Passing inert gas;

(c) a gas containing oxygen (O) precursor molecules is introduced;

(d) Passing inert gas;

Thus forming the carrier passivation tunneling film.

In another preferred embodiment, the inert gas is selected from the group consisting of nitrogen, argon or combinations thereof.

In another preferred embodiment, the oxygen-containing (O) precursor molecule is selected from the group consisting of H ₂ O, O ₃ or combinations thereof.

In another preferred example, the silicon wafer is n-type or p-type.

In another preferred example, the silicon wafer is a single crystal silicon wafer with a resistivity of 0.5-10Ω·cm.

In another preferred example, in step (a), the pressure of the vacuum chamber is lower than 10 ^-2 Torr.

In another preferred example, in step (a), the passing time is 0.5-5 seconds; preferably, 1 second.

In another preferred example, in step (b), the time for passing in is 10-60 seconds; preferably, 20-35 seconds.

In another preferred embodiment, in step (b), the flow rate of the inert gas is 50-200 sccm; preferably, 80-120 sccm.

In another preferred example, in step (c), the time for passing through is 0.5-5 seconds; preferably, 1 second.

In another preferred example, in step (d), the time for passing in is 10-60 seconds; preferably, 20-35 seconds.

In another preferred embodiment, in step (d), the flow rate of the inert gas is 50-200 sccm; preferably, 80-120 sccm.

In another preferred example, the steps (a)-(d) are carried out at 50-500°C.

In another preferred example, the steps (a)-(d) are carried out at 150-250°C.

In another preferred example, steps (a)-(d) are repeated sequentially for 1-200 times.

In another preferred example, steps (a)-(d) are repeated sequentially for 1-100 times.

In another preferred example, the Ta-containing precursor molecule is selected from the group consisting of tantalum methoxide, tantalum ethoxide, tantalum propoxide, tantalum isopropoxide, tantalum butoxide, tantalum tetraethoxy acetylacetonate, tantalum trifluoroethoxide , tantalum chloride, tantalum iodide, or combinations thereof.

The second aspect of the present invention provides a carrier transport structure, the carrier transport structure includes or consists of the following: a carrier passivation tunneling layer and a doped polysilicon layer; wherein, the carrier passivation The tunneling layer contains tantalum pentoxide (Ta ₂ O ₅ ); the carrier passivation tunneling layer is coated on the surface of the silicon wafer; the doped polysilicon layer is coated on the carrier Passivate the surface of the tunneling layer.

In another preferred example, the thickness of the carrier passivation tunneling layer is 0.5-5 nm; preferably, 1-2.5 nm.

In another preferred example, the carriers are electrons or holes.

In another preferred embodiment, the doped polysilicon layer is a boron-doped polysilicon film or a phosphorus-doped polysilicon film.

In another preferred example, the doped polysilicon layer has a thickness of 20-100 nm; preferably, 30-50 nm.

In another preferred example, the doped polysilicon layer is a phosphorus-doped polysilicon film, and the carrier transport structure selectively transports electrons.

In another preferred example, the doped polysilicon layer is a boron-doped polysilicon film, and the carrier transport structure selectively transports holes.

The third aspect of the present invention provides a method for preparing the carrier transport structure described in the second aspect of the present invention, the method comprising the steps of:

(a1) Depositing a doped amorphous silicon layer on the surface of the carrier passivation tunneling layer by PECVD method, and then performing annealing treatment, so as to form the carrier transport structure.

In another preferred example, the preparation method of the carrier passivation tunneling layer is the same as that described above.

In another preferred example, the preparation method of the carrier transport structure includes the following steps: in the vacuum chamber carrying the carrier passivation tunneling layer, injecting silicon-containing precursor molecules and containing Doping the gas of the precursor molecule of the element, so as to form the amorphous silicon layer containing the doping element; annealing the amorphous silicon layer containing the doping element, so as to form the carrier transport structure.

In another preferred example, the silicon-containing precursor molecule is SiH ₄ .

In another preferred example, the precursor molecule containing doping elements is PH ₃ or B ₂ H ₆ .

In another preferred example, the temperature of the annealing treatment is 400-900°C.

In another preferred example, the time for the annealing treatment is 10-40 minutes.

The fourth aspect of the present invention provides the use of the carrier transport structure described in the second aspect of the present invention for preparing a solar cell.

In another preferred example, the solar cell is a crystalline silicon solar cell.

The fifth aspect of the present invention provides a solar cell, which includes the following parts: a carrier passivation tunneling layer, a doped polysilicon layer, and an electrode layer; wherein, the carrier passivation tunneling layer contains Tantalum pentoxide (Ta ₂ O ₅ ); the carrier passivation tunneling layer is coated on the surface of the silicon wafer; the doped polysilicon layer is coated on the carrier passivation tunneling layer Surface; the electrode layer covers the surface of the doped polysilicon layer.

In another preferred example, the electrode layer partially or fully covers the surface of the doped polysilicon layer.

A sixth aspect of the present invention provides a method for preparing a solar cell according to the fifth aspect of the present invention, the method comprising the steps of:

(a) depositing a doped amorphous silicon layer on the surface of the carrier passivation tunneling layer by PECVD method, and then performing annealing treatment, thereby forming the carrier transport structure; and

(b) Depositing an electrode layer on the surface of the carrier transport structure obtained in step (a), thereby forming the solar cell.

In another preferred example, the preparation method of the carrier passivation tunneling layer is the same as that described above.

In another preferred embodiment, the step (b), before depositing the electrode layer, further includes depositing a second passivation layer on the emitter on the front surface of the silicon wafer of the carrier transport structure obtained in the step (a).

In another preferred example, the front surface is another surface of the silicon wafer opposite to the passivation tunneling layer.

In another preferred example, the second passivation layer is selected from the group consisting of a silicon nitride layer, an aluminum oxide layer, or a combination thereof.

In another preferred example, when the emitter on the front surface of the silicon wafer is n ⁺ type, the second passivation layer is a silicon nitride layer.

In another preferred example, when the emitter on the front surface of the silicon wafer is p ⁺ type, the second passivation layer is a silicon nitride layer and an aluminum oxide layer.

The present invention also provides the use of the solar cell described in the present invention for photovoltaic power generation.

It should be understood that within the scope of the present invention, the above-mentioned technical features of the present invention and the technical features specifically described in the following (such as embodiments) can be combined with each other to form new or preferred technical solutions. Due to space limitations, we will not repeat them here.

Description of drawings

Figure 1 shows a schematic diagram of the TOPCon cell structure.

Detailed ways

Through extensive and in-depth research, the inventor unexpectedly found for the first time that the use of tantalum pentoxide material as a passivation tunneling layer can overcome the shortcomings of silicon oxide as a passivation tunneling layer in the application of passivation contact heterojunction cells . The present invention has been accomplished on this basis.

Carrier Passivation Tunneling Thin Film

The invention provides a carrier passivation tunneling film, the carrier passivation tunneling film contains tantalum pentoxide (Ta ₂ O ₅ ); stream transport structure.

The solar cell may be a crystalline silicon solar cell.

The thickness of the carrier passivation tunneling film may be 0.5-5 nm; preferably, 1-2.5 nm.

The carriers may be electrons or holes.

The preparation method of the carrier passivation tunneling film may include the steps of: using magnetron sputtering (Sputter), plasma enhanced chemical vapor deposition (PECVD), thermal evaporation (Thermal Evaporator), electron beam evaporation (E-beamEvaporator ), low-pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD), depositing tantalum pentoxide (Ta ₂ O ₅ ) on the silicon wafer, thereby forming the carrier passivation tunneling film.

The preparation method of the carrier passivation tunneling film may include the following steps:

(a) In the vacuum cavity loaded with the silicon wafer, the pressure of the vacuum cavity is lower than 10 ^-2 Torr, and the gas containing tantalum (Ta) precursor molecules is introduced; wherein, the input time is 0.5-5 seconds; Preferably, it is 1 second;

(b) feed an inert gas; wherein, the feed time is 10-60 seconds; preferably, 20-35 seconds; the flow rate of the inert gas is 50-200 sccm; preferably, 80-120 sccm;

(c) passing a gas containing oxygen (O) precursor molecules; wherein, the passing time is 0.5-5 seconds; preferably, 1 second;

(d) Passing inert gas; Wherein, passing time is 10-60 seconds; Preferably, is 20-35 seconds; The flow rate of inert gas is 50-200sccm; Preferably, is 80-120sccm;

Thus forming the carrier passivation tunneling film.

The inert gas may be selected from the group consisting of nitrogen, argon or combinations thereof.

The oxygen (O) precursor molecule may be selected from the group consisting of H ₂ O, O ₃ or a combination thereof.

The silicon chip is n-type or p-type.

The silicon wafer is a single crystal silicon wafer with a resistivity of 0.5-10Ω·cm.

The steps (a)-(d) are carried out at 50-500°C; preferably, at 150-250°C.

Steps (a)-(d) can be repeated sequentially for 1-200 times; steps (a)-(d) can be repeated sequentially for 1-100 times.

The Ta-containing precursor molecule can be selected from the following group: tantalum methoxide, tantalum ethoxide, tantalum propoxide, tantalum isopropoxide, tantalum butoxide, tantalum tetraethoxyacetylacetonate, tantalum trifluoroethoxide, tantalum chloride, iodine tantalum oxide, or combinations thereof.

carrier transport structure

The present invention provides a carrier transport structure, which comprises or consists of the following: a carrier passivation tunneling layer and a doped polysilicon layer; wherein, the carrier passivation tunneling The film contains tantalum pentoxide (Ta ₂ O ₅ ); the carrier passivation tunneling layer is coated on the surface of the silicon chip; the doped polysilicon layer is coated on the carrier passivation tunnel Wear surface.

The doped polysilicon layer can be a boron-doped polysilicon film or a phosphorus-doped polysilicon film.

The thickness of the doped polysilicon layer may be 20-100 nm; preferably, 30-50 nm.

When the doped polysilicon layer is a phosphorus-doped polysilicon film, the carrier transport structure selectively transports electrons.

When the doped polysilicon layer is a boron-doped polysilicon film, the carrier transport structure selectively transports holes.

The preparation method of the carrier transport structure comprises the steps of:

(a1) Depositing a doped amorphous silicon layer on the surface of the carrier passivation tunneling layer by PECVD method, and then performing annealing treatment, so as to form the carrier transport structure.

The preparation method of the carrier passivation tunneling layer is the same as that described above.

Specifically, the preparation method of the carrier transport structure may include the following steps: in the vacuum chamber carrying the carrier passivation tunneling layer, inject silicon-containing precursor molecules and dopant element-containing The gas of the precursor molecules, so as to form the amorphous silicon layer containing the doping element; annealing the amorphous silicon layer containing the doping element, so as to form the carrier transport structure.

The silicon-containing precursor molecule may be SiH ₄ .

The precursor molecules containing doping elements may be PH ₃ or B ₂ H ₆ .

The temperature of the annealing treatment may be 400-900°C.

The time for the annealing treatment may be 10-40 minutes.

The carrier transport structure of the present invention can be used to prepare solar cells, for example, the solar cells are crystalline silicon solar cells.

Solar battery

The invention provides a solar cell, which comprises the following parts: a carrier passivation tunneling layer, a doped polysilicon layer, and an electrode layer; wherein, the carrier passivation tunneling layer is coated on The surface of the silicon chip; the doped polysilicon layer is covered on the surface of the carrier passivation tunneling layer; the electrode layer is completely or partially covered on the surface of the doped polysilicon layer.

The preparation method of the solar cell of the present invention comprises steps:

(a) depositing a doped amorphous silicon layer on the surface of the carrier passivation tunneling layer by PECVD method, and then performing annealing treatment, thereby forming the carrier transport structure; and

(b) Depositing an electrode layer on the surface of the carrier transport structure obtained in step (a), thereby forming the solar cell.

In the step (b), before depositing the electrode layer, it also includes depositing a second passivation layer on the emitter on the front surface of the silicon wafer of the carrier transport structure obtained in the step (a).

The second passivation layer is selected from the group consisting of a silicon nitride layer, an aluminum oxide layer, or a combination thereof.

When the emitter on the front surface of the silicon wafer is n ⁺ type, the second passivation layer is a silicon nitride layer.

When the emitter on the front surface of the silicon chip is p ⁺ type, the second passivation layer is a silicon nitride layer and an aluminum oxide layer.

The use of the solar cell described in the present invention is for photovoltaic power generation.

The main advantages of the present invention are:

1. Tantalum pentoxide has excellent surface passivation performance as a passivation layer on the silicon surface;

2. The conduction band step between tantalum pentoxide and silicon is very small. When used as an electron tunneling material, the contact barrier with silicon is very low, and it has excellent electron tunneling effect.

3. The valence band step between tantalum pentoxide and silicon is small, and when used as a hole tunneling material, it has a relatively low contact barrier and can also achieve a good hole tunneling effect.

4. Tantalum pentoxide has excellent high-temperature stability, is compatible with the existing crystalline silicon manufacturing process, and can completely replace silicon oxide as a passivation tunneling material.

5. As a passivation tunneling layer, the tantalum pentoxide film can be thicker than the silicon oxide film, and the film is denser, and has a stronger blocking ability for impurities, especially doping atoms in polysilicon layers such as B and P, and can obtain better passivation effect.

6. The tantalum pentoxide thin film carries a fixed negative charge on the order of 10 ¹² cm ^-2 , which is very suitable as a passivation tunneling layer for p-type crystalline silicon.

Below in conjunction with specific embodiment, further illustrate the present invention. It should be understood that these examples are only used to illustrate the present invention and are not intended to limit the scope of the present invention. For the experimental methods without specific conditions indicated in the following examples, the conventional conditions or the conditions suggested by the manufacturer are usually followed. Percentages and parts are by weight unless otherwise indicated.

The experimental materials and reagents used in the following examples can be obtained from commercially available channels unless otherwise specified.

Example 1:

Step (1): Using a p-type single crystal silicon wafer with a resistivity of 2.0 Ω·cm as a substrate, a Ta ₂ O ₅ thin film is deposited on both sides of the silicon wafer by atomic layer deposition (ALD). Specific method: put the silicon wafer cleaned by RCA standard process into the ALD cavity, pump the cavity pressure below 10 ^-2 Torr, and heat the cavity to 200°C at the same time. Using tantalum ethoxide and water as precursors, first pass tantalum ethoxide vapor for 1 second, then pass nitrogen gas with a flow rate of 100 sccm for 30 seconds, then pass water vapor for 1 second, and finally pass nitrogen gas with a flow rate of 100 sccm for 30 seconds , which is a cycle. After 60 cycles of treatment, a 1.8±0.2nm Ta ₂ O ₅ film can be obtained on the surface of the silicon wafer.

Step (2): using aluminum particles as an evaporation source, an aluminum electrode is evaporated on the surface of the prepared Ta ₂ O ₅ film with a specific mask pattern, and the thickness of the aluminum electrode is 1 μm. An all-round aluminum electrode was evaporated on the surface of the sample without the Ta ₂ O ₅ film, and the thickness of the aluminum electrode was 1 μm.

The prepared samples were tested by CV with a semiconductor parameter analyzer. The results showed that the Ta ₂ O ₅ thin film carried fixed negative charges with a charge density of -1.2×10 ¹² cm ^-2 ; the interface state density between Ta ₂ O ₅ and silicon was 8.5 ×10 ⁹ cm ^-2 /eV.

Comparative example 1:

Step (1): Using a p-type monocrystalline silicon wafer with a resistivity of 2.0Ω·cm as a substrate, a SiO ₂ film is grown on both sides of the silicon wafer by thermal nitric acid oxidation (NAOS). Specific method: soak the silicon wafer cleaned by RCA standard process in boiling concentrated nitric acid (68wt.%), and after about 10 minutes, a _SiO2 film of about 1.8±0.2nm can be obtained on the surface of the silicon wafer.

Step (2): Remove one side of the SiO ₂ film with HF acid vapor. Using aluminum particles as the evaporation source, aluminum electrodes were evaporated with a specific mask pattern on the surface where the SiO ₂ film remained, and the thickness of the aluminum electrodes was 1 μm. A full-scale aluminum electrode was evaporated on the surface of the sample without the _SiO2 film, and the thickness of the aluminum electrode was 1 μm.

The prepared samples were tested by CV with a semiconductor parameter analyzer, and the results showed that the SiO ₂ thin film carried a small amount of fixed positive charges with a charge density of 5.4×10 ¹⁰ cm ^-2 ; the interface state density between SiO ₂ and silicon was 8.9×10 ¹⁰ cm ^-2 /eV.

Example 2:

Step (1): Using a p-type single crystal silicon wafer with a resistivity of 2.0 Ω·cm as a substrate, a Ta ₂ O ₅ thin film is deposited on both sides of the silicon wafer by atomic layer deposition (ALD). Concrete method is with embodiment 1 step (1)

Step (2): Subsequently, a boron-doped amorphous silicon film is deposited on both sides of the sample with a Ta ₂ O ₅ film deposited on both sides by PECVD method. The specific method is: transfer the sample of Ta ₂ O ₅ film deposited on both sides into the PECVD chamber, pump the chamber pressure below 10 ^{− 5} Torr, and heat the sample to 150° C. at the same time. 10sccm of high-purity silane (SiH ₄ ) and 10sccm of hydrogen-diluted diborane (3% B ₂ H ₆ ), radio frequency power of 10W, process pressure of 0.4Torr, and time of 10min, can obtain about 40nm doped particles on the surface of the sample. boron amorphous silicon thin film.

Step (3): Transfer the above-mentioned double-sided Ta ₂ O ₅ thin film and boron-doped amorphous silicon thin film laminated sample to an annealing furnace, and place it under N ₂ or N ₂ and H ₂ (content 5-30%) Under the atmosphere of mixed gas, anneal at 850°C for 30 minutes to crystallize the boron-doped amorphous silicon film to form a boron-doped polysilicon film with a doping concentration of 5×10 ¹⁹ cm ^-3 .

The prepared samples were tested by a Sinton WCT-120 quasi-steady-state photoconductive minority carrier lifetime tester, and the fitting results showed that the surface saturation current density J ₀ was 40-60 fA/cm ² .

Comparative example 2:

Step (1): Using a p-type monocrystalline silicon wafer with a resistivity of 2.0Ω·cm as a substrate, a SiO ₂ film is grown on both sides of the silicon wafer by thermal nitric acid oxidation (NAOS). The specific method is the same as the step (1) of Comparative Example 1.

Step (2): Then use the PECVD method to deposit a boron-doped amorphous silicon film on both sides of the sample with SiO ₂ film deposited on both sides. Concrete method is with embodiment 2 step (2).

Step (3): The double-sided SiO ₂ thin film and the boron-doped amorphous silicon thin film laminated sample are annealed at a high temperature to form a boron-doped polysilicon thin film. Concrete method is with embodiment 2 step (3).

The prepared samples were tested with a Sinton WCT-120 quasi-steady-state photoconductive minority carrier lifetime tester, and the fitting results showed that the surface saturation current density J ₀ was 60-90 fA/cm ² .

Compared with Comparative Example 2, the sample of Example 2 has a lower surface saturation current density, indicating that the Ta ₂ O ₅ thin film has a better surface passivation effect on p-type crystalline silicon.

Example 3:

Step (1): Using an n-type single crystal silicon wafer with a resistivity of 1.0 Ω·cm as a substrate, a Ta ₂ O ₅ thin film is deposited on both sides of the silicon wafer by atomic layer deposition (ALD). Concrete method is with embodiment 1 step (1).

Step (2): Subsequently, a phosphorus-doped amorphous silicon film is deposited on both sides of the sample with a Ta ₂ O ₅ film deposited on both sides by PECVD method. The specific method is: transfer the sample of Ta ₂ O ₅ film deposited on both sides into the PECVD chamber, pump the chamber pressure below 10 ^{− 5} Torr, and heat the sample to 150° C. at the same time. Pass 10sccm high-purity silane (SiH ₄ ) and 10sccm hydrogen diluted phosphine (5% PH ₃ ), radio frequency power 10W, process pressure 0.4Torr, time 10min, that is, about 40nm phosphorus-doped amorphous can be obtained on the sample surface silicon thin film.

Step (3): Transfer the above-mentioned double-sided Ta ₂ O ₅ thin film and phosphorus-doped amorphous silicon thin film laminated sample to an annealing furnace, and place it under N ₂ or N ₂ and H ₂ (content 5-30%) Under the atmosphere of mixed gas, anneal at 850°C for 30 minutes to crystallize the phosphorus-doped amorphous silicon film to form a phosphorus-doped polysilicon film with a doping concentration of 2.3×10 ²⁰ cm ^-3 .

The prepared samples were tested with a Sinton WCT-120 quasi-steady-state photoconductive minority carrier lifetime tester, and the fitting results showed that the surface saturation current density J ₀ was 10-30 fA/cm ² .

Comparative example 3:

Step (1): Using an n-type single crystal silicon wafer with a resistivity of 1.0 Ω·cm as a substrate, a SiO ₂ film is grown on both sides of the silicon wafer by thermal nitric acid oxidation (NAOS). The specific method is the same as the step (1) of Comparative Example 1.

Step (2): further deposit phosphorus-doped amorphous silicon on both sides of the sample, and anneal to form phosphorus-doped polysilicon. Concrete method is the same as embodiment 3 step (2) and step (3).

The prepared samples were tested by a Sinton WCT-120 quasi-steady-state photoconductive minority carrier lifetime tester, and the fitting results showed that the surface saturation current density J ₀ was 20-40 fA/cm ² .

Compared with Comparative Example 3, the sample of Example 3 has a lower surface saturation current density, indicating that the Ta ₂ O ₅ film has a better surface passivation effect on n-type crystalline silicon.

Example 4:

Step (1): Use a p-type solar-grade monocrystalline silicon wafer with a <100> crystal orientation and a resistivity of 2.0Ω·cm as the substrate, and corrode it with a 1-3% KOH solution at about 80°C for 15 minutes to remove surface damage layer, and form a random pyramid textured pile. The sample is transferred to a quartz furnace tube at about 800°C, and POCl ₃ liquid source steam is brought into the quartz furnace tube with 250 sccm N ₂ as the carrier gas, and 100 sccm O ₂ is introduced at the same time, after 20 minutes of high temperature treatment, a n ⁺ type emitter layer. The phosphosilicate glass layer on the surface was removed with 5% HF solution, and the n ⁺ type layer on the back surface was removed by etching with a mixed solution of HNO ₃ and HF acid.

Step (2): Deposit a Ta ₂ O ₅ film with a thickness of about 1.8 nm on the back surface of the sample by ALD method, and the specific method is the same as step (1) in Example 1.

Step (3): Then, a boron-doped amorphous silicon film is deposited on the back surface of the sample by PECVD, and a boron-doped polysilicon film is formed by high-temperature annealing. The specific method is the same as step (2) and step (3) of embodiment 2.

Step (4): Transfer the sample to the PECVD chamber, use silane (SiH ₄ ) and ammonia (NH ₃ ) as precursors, deposit a silicon nitride (SiN _x :H) film on the front surface of the sample, and the The thickness and refractive index are 80nm and 2.05, respectively.

Step (5): Using silver particles as an evaporation source, a silver electrode layer is evaporated on the back of the sample, and the thickness of the silver electrode layer is 300 nm. On the front surface of the sample, fine-grid silver electrodes and main-grid silver electrodes with widths of 35 μm and 1.0 mm were printed with electronic silver paste and a screen with a specific pattern. Subsequently, the sample was sintered in a chain-type sintering furnace at 300-900° C. for about 1.5 minutes to complete the preparation of the battery sample.

Finally, the battery sample passed the solar simulator I-V tester, and the electrical properties were tested as follows:

open circuit voltage Short circuit current density fill factor efficiency 660mV 38.9mA/ ^cm2 79.8% 20.5%

Comparative example 4:

Step (1): Using a p-type solar-grade monocrystalline silicon wafer with a <100> crystal orientation and a resistivity of 2.0Ω·cm as the substrate, perform pyramid texture and n ⁺ type Preparation of the emitter layer.

Step (2): grow a _SiO2 film of about 1.8 nm on the surface of the sample by hot nitric acid oxidation, and the specific method is the same as step (1) of Comparative Example 1.

Step (3): Then, a boron-doped amorphous silicon film is deposited on the back surface of the sample by PECVD, and a boron-doped polysilicon film is formed by high-temperature annealing. The specific method is the same as step (2) and step (3) of embodiment 2.

Step (4): Complete the battery sample preparation through subsequent steps, specifically the same as step (4) and step (5) in Example 4.

Finally, the battery sample passed the solar simulator I-V tester, and the electrical properties were tested as follows:

open circuit voltage Short circuit current density fill factor efficiency 636mV 38.6mA/ ^cm2 79.5% 19.5%

Example 5:

Step (1): Use an n-type solar-grade monocrystalline silicon wafer with a <100> crystal orientation and a resistivity of 1.0Ω·cm as the substrate, and corrode it with a 1-3% KOH solution at about 80°C for 15 minutes to remove surface damage layer, and form a random pyramid textured pile. The sample is transferred to a quartz furnace tube at about 900°C, and BBr ₃ liquid source steam is brought into the quartz furnace tube with 100 sccm of N ₂ as the carrier gas, and 50 sccm of O ₂ is introduced at the same time, and after 30 minutes of high temperature treatment, p ⁺ type emitter layer. The borosilicate glass layer on the surface was removed with 5% HF solution, and the p ⁺ type layer on the back surface was removed by etching with a mixed solution of HNO ₃ and HF acid.

Step (2): Deposit a Ta ₂ O ₅ film with a thickness of about 1.8 nm on the back surface of the sample by ALD method, and the specific method is the same as step (1) in Example 1.

Step (3): Then, a phosphorus-doped amorphous silicon film is deposited on the back surface of the sample by PECVD, and a phosphorus-doped polysilicon film is formed by high-temperature annealing. The specific method is the same as step (2) and step (3) of embodiment 3.

Step (4): After that, put the sample into the ALD chamber, use trimethylaluminum and water vapor as the precursor source, and deposit 10nm of aluminum oxide (Al ₂ O ₃ )film.

Step (5): Transfer the sample to the PECVD chamber, use silane (SiH ₄ ) and ammonia (NH ₃ ) as precursors, deposit a silicon nitride (SiN _x :H) film on the front surface of the sample, and the The thickness and refractive index are 70nm and 2.05, respectively.

Step (6): Complete the battery sample preparation through subsequent steps, specifically the same as Step (5) in Example 4.

Finally, the battery sample passed the solar simulator I-V tester, and the electrical properties were tested as follows:

open circuit voltage Short circuit current density fill factor efficiency 672mV 39.2mA/ ^cm2 80.7% 21.3%

Comparative example 5:

Step (1): Using an n-type solar-grade monocrystalline silicon wafer with a <100> crystal orientation and a resistivity of 1.0 Ω cm as the substrate, perform pyramid texture and p ⁺ type in the same manner as in step (1) of Example 5. Preparation of the emitter layer.

Step (2): grow a _SiO2 film of about 1.8 nm on the surface of the sample by hot nitric acid oxidation, and the specific method is the same as step (1) of Comparative Example 1.

Step (3): Then, a phosphorus-doped amorphous silicon film is deposited on the back surface of the sample by PECVD, and a phosphorus-doped polysilicon film is formed by high-temperature annealing. The specific method is the same as step (2) and step (3) of embodiment 3.

Step (4): Complete the battery sample preparation through subsequent steps, specifically the same as Step (4), Step (5) and Step (6) in Example 5.

Finally, the battery sample passed the solar simulator I-V tester, and the electrical properties were tested as follows:

open circuit voltage Short circuit current density fill factor efficiency 661mV 39.1mA/ ^cm2 80.3% 20.8%

It can be seen from the above experiments that:

1. The interface state density between tantalum pentoxide and silicon is lower than 10 ¹⁰ cm ^-2 /eV, while the interface state density between silicon oxide and silicon is close to 10 ¹¹ cm ^-2 /eV, indicating that the use of tantalum pentoxide Has more excellent surface passivation performance;

2. The conduction band step between tantalum pentoxide and silicon is 0.8eV, which means that when tantalum pentoxide is used as an electron tunneling material, the contact barrier with silicon is very low. According to calculations, the thickness of the tantalum pentoxide thin film only needs to be as thin as 5nm to achieve good electron tunneling effect.

3. The valence band step between tantalum pentoxide and silicon is 2.3eV, which is obviously lower than the 4.8eV valence band step between silicon oxide and silicon. When tantalum pentoxide is used as a hole tunneling material, it has a lower contact barrier. According to calculations, when the thickness of the tantalum pentoxide thin film is as low as 2nm, a good hole tunneling effect can be achieved.

4. Tantalum pentoxide has excellent high temperature stability and can completely replace silicon oxide as a passivation tunneling material.

5. As a passivation tunneling layer, the tantalum pentoxide film can be thicker than the silicon oxide film, and the film is denser, and has a stronger blocking ability for impurities, especially doping atoms in polysilicon layers such as B and P, and can obtain better passivation effect.

6. The tantalum pentoxide thin film carries a fixed negative charge on the order of 10 ¹² cm ^-2 , and can obtain more excellent passivation performance as a passivation tunneling layer of p-type crystalline silicon.

In summary, tantalum pentoxide has many characteristics and advantages, and is an ideal passivation tunneling material to further improve the efficiency of passivation contact heterojunction solar cells.

All documents mentioned in this application are incorporated by reference in this application as if each were individually incorporated by reference. In addition, it should be understood that after reading the above teaching content of the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms also fall within the scope defined by the appended claims of the present application.

Claims (10)

1. The use of a carrier passivation tunneling film, characterized in that the carrier passivation tunneling film contains tantalum pentoxide (Ta ₂ O ₅ ); the film is used to prepare solar cells. 2. purposes as claimed in claim 1, is characterized in that, the preparation method of described carrier passivation tunneling thin film comprises: adopt magnetron sputtering (Sputter), plasma enhanced chemical vapor deposition (PECVD), thermal Evaporation (Thermal Evaporator), electron beam evaporation (E-beam Evaporator), low-pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD) method, deposit tantalum pentoxide (Ta ₂ O ₅ ) on the silicon wafer to form the The above-mentioned carrier passivation tunneling film. 3. purposes as claimed in claim 2, is characterized in that, described preparation method adopts atomic layer deposition (ALD), comprises the steps: (a) in the vacuum cavity loaded with silicon wafers, the gas containing tantalum (Ta) precursor molecules is passed into; (b) Passing inert gas; (c) passing a gas containing oxygen (O) precursor molecules; (d) Passing inert gas; Thus forming the carrier passivation tunneling film. 4. The use according to claim 3, wherein the oxygen-containing (O) precursor molecule is selected from the group consisting of _H2O , _O3 or a combination thereof. 5. The use according to claim 3, wherein the Ta-containing precursor molecule is selected from the group consisting of tantalum methoxide, tantalum ethoxide, tantalum propoxide, tantalum isopropoxide, tantalum butoxide, tetraethoxy Tantalum acetylacetonate, tantalum trifluoroethanolate, tantalum chloride, tantalum iodide, or combinations thereof. 6. A carrier transport structure, characterized in that the carrier transport structure comprises or consists of the following: a carrier passivation tunneling layer and a doped polysilicon layer; wherein the carrier passivation The tunneling layer contains tantalum pentoxide (Ta ₂ O ₅ ); the carrier passivation tunneling layer is coated on the surface of the silicon wafer; the doped polysilicon layer is coated on the carrier passivation surface of the tunneling layer. 7. The preparation method of carrier transport structure as claimed in claim 6, is characterized in that, described method comprises the step: (a1) Depositing a doped amorphous silicon layer on the surface of the carrier passivation tunneling layer by PECVD method, and then performing annealing treatment, so as to form the carrier transport structure. 8. The use of the carrier transport structure according to claim 6, characterized in that it is used to prepare solar cells. 9. A solar cell, characterized in that the solar cell comprises the following parts: a carrier passivation tunneling layer, a doped polysilicon layer and an electrode layer; wherein the carrier passivation tunneling layer contains five Tantalum oxide (Ta ₂ O ₅ ); the carrier passivation tunneling layer is coated on the surface of the silicon wafer; the doped polysilicon layer is coated on the carrier passivation tunneling layer surface ; The electrode layer covers the surface of the doped polysilicon layer. 10. The preparation method of solar cell as claimed in claim 9, is characterized in that, described method comprises the step: (a) depositing a doped amorphous silicon layer on the surface of the carrier passivation tunneling layer by PECVD method, and then performing annealing treatment, thereby forming the carrier transport structure; and (b) Depositing an electrode layer on the surface of the carrier transport structure obtained in step (a), thereby forming the solar cell.