CN106784128A - The preparation method of preceding emitter junction back side tunnel oxidation passivation contact high-efficiency battery - Google Patents

Abstract

The invention relates to a method for making a high-efficiency battery with tunnel oxidation passivation contact on the back of the front emitter junction. After removing the damaged layer of the silicon wafer, the texture is made, and then a low surface concentration B-doped P ⁺ emitter junction is formed. After edge insulation and back polishing, the silicon An ultra-thin tunnel oxide layer SiO ₂ and a P-doped polysilicon layer are grown on the back of the wafer, an aluminum oxide layer is deposited on the surface of the P ⁺ emitter junction, and hydrogenated amorphous nitrogen is grown on the front of the wafer by PECVD or magnetron sputtering. Passivate the anti-reflection layer with silicon, and finally print Ag/Al paste on the front side of the silicon wafer, and form an all-aluminum back field Al-BSF structure on the back side, and dry it in a drying furnace. Compared with the prior art, the present invention adopts a layer of ultra-thin (<2nm) tunnel oxide _SiO2 and a layer of phosphorus P-doped silicon layer, which can greatly reduce the metal-semiconductor surface recombination on the back surface, which The most obvious advantage is that it can greatly improve the electrical performance parameters on the basis of compatibility with traditional battery manufacturing processes.

Description

Fabrication method of high-efficiency cell with front-emitter junction back tunnel oxidation passivation contact

technical field

The invention relates to a method for manufacturing a crystalline silicon cell, in particular to a method for manufacturing a high-efficiency cell with an oxidation passivation contact on the back side of a front emitter junction.

Background technique

The difference between front-emitter junction back tunnel oxidation passivation contact cell technology and conventional battery technology is the preparation of the composite structure of back tunnel oxidation passivation layer and doped polysilicon layer. The key point of this method is the ultra-thin tunnel Preparation control of the through-oxide layer and treatment of the interface state with the silicon substrate before preparation. Chinese patent CN102544198A discloses a method for preparing a selective emission crystalline silicon solar cell, including single-step high-concentration doping diffusion, and then printing anti-corrosion paste on the electrode area by printing process, and chemically etching the non-electrode area to achieve light doping The emitter junction, and then remove the anti-corrosion barrier layer, and finally use the conventional solar energy preparation method to make the selective emission crystalline silicon solar cell, but this patent application still uses the back point contact of the N-type crystalline silicon cell, so the electrical performance is not great. improvement.

Contents of the invention

The purpose of the present invention is to provide a high-efficiency cell manufacturing method with a front-emitter junction, back tunnel oxidation passivation contact, which can greatly improve electrical performance parameters in order to overcome the above-mentioned defects in the prior art.

The purpose of the present invention can be achieved through the following technical solutions:

A method for making a high-efficiency cell with an oxidation passivation contact on the back side of the front emitter junction adopts the following steps:

(1) Remove the damaged layer of the silicon wafer in KOH or NaOH alkali solution and H ₂ O ₂ solution, and then use tetramethylammonium hydroxide and isopropanol to form a mixed solution to make texture on the silicon wafer, forming a texture on both sides. 1-4μm pyramid suede;

(2) In the boron source high-temperature diffusion furnace tube, control the temperature at 850-1000°C to diffuse for 20-40 minutes, and then control the temperature at 800-900°C to feed oxygen into the junction to form a low surface concentration B-doped P ⁺ emitter junction;

(3) Use HF solution to remove the borosilicate glass BSG layer, and use a mixed solution of HNO ₃ and HF to perform edge insulation and back polishing;

(4) A layer of ultra-thin tunnel oxide layer SiO ₂ is grown on the back of the silicon wafer by wet chemical method, and its thickness is less than 2nm, and then a P-doped layer with a thickness of 15-20nm is grown on it by PECVD or other CVD methods. polysilicon layer;

(5) adopting atomic layer deposition or PECVD technology to form the surface deposition thickness of P ⁺ emitter junction on the silicon wafer is an aluminum oxide layer with a thickness of 20-30nm;

(6) growing a hydrogenated amorphous silicon nitride passivation anti-reflection layer on the front side of the silicon wafer by PECVD or magnetron sputtering, with a thickness of 75-85nm;

(7) Print Ag/Al paste on the front side of the silicon wafer by screen printing, and sinter it. The back side adopts evaporation or coating source method to form an all-aluminum back field Al-BSF structure, and dry it with a drying furnace. Just make sure that both sides of the cell are in good contact.

Step (4) Take fluorosilicate H ₂ SiO ₆ solution with a concentration of 1.3-1.7M, protect the front side of the silicon wafer with a mask and put it into the fluorosilicate solution, and accurately control the SiO ₂ film layer according to the deposition time Generally, the control time within 2nm thickness is 5-8 minutes. The P-doped polysilicon layer is prepared based on the PECVD method using high-purity SiH ₄ as a gas source at 500-600°C and then annealed at 900-1100°C.

The thickness of the P-doped polysilicon layer is 15-20nm, and the content of P atoms is 5×10 ¹⁸ -1×10 ¹⁹ cm ^-3 .

In step (5), when depositing the Al2O3 layer, control the deposition temperature to be 180-200°C.

When growing the hydrogenated amorphous silicon nitride passivation anti-reflection layer in step (6), the temperature is controlled to be 350-400°C.

The drying temperature in step (7) is 200-300°C.

Compared with the prior art, the present invention replaces the mechanism of the point contact on the back of the N-type crystalline silicon cell, and adopts a layer of ultra-thin (<2nm) tunnel oxide SiO ₂ and a layer of phosphorus P-doped silicon layer, such that The composite layer can greatly reduce the metal-semiconductor surface recombination on the back surface, and its most obvious advantage is that it can greatly improve the electrical performance parameters (Implied V _oc >710mV, Implied FF>82%, conversion Efficiency η > 23%). The fabricated battery structure (compared with IBC and HIT high-efficiency batteries) is simple, the process feasibility is relatively strong, and it is relatively easy to be compatible with existing production line equipment and processes. The most important thing is through the tunneling effect in quantum mechanics. It can greatly improve the open circuit voltage and conversion efficiency, and is a low-cost and high-efficiency monocrystalline silicon cell product.

Description of drawings

Fig. 1 is a structural schematic diagram of the fabricated crystalline silicon battery.

In the figure, 1-electrode, 2-hydrogenated amorphous silicon nitride passivation anti-reflection layer, 3-aluminum oxide layer, 4-B-doped P ⁺ emitter junction, 5-N-type silicon wafer, 6-tunnel oxidation SiO ₂ , 7-doped P polysilicon layer, 8-all aluminum back field.

detailed description

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

Example 1

A method for making a high-efficiency cell with an oxidation passivation contact on the back side of the front emitter junction adopts the following steps:

(1) Remove the damaged layer of the silicon wafer in KOH alkali solution and H ₂ O ₂ solution, and then use tetramethylammonium hydroxide and isopropanol to form a mixed solution to texture the silicon wafer, forming a 1 μm texture on both sides. pyramid suede;

(2) In the boron source high-temperature diffusion furnace tube, control the temperature at 850°C to diffuse for 40 minutes, and then control the temperature at 800°C to pass oxygen into the junction to form a low surface concentration B-doped P ⁺ emitter junction;

(3) Use HF solution to remove the borosilicate glass BSG layer, and use a mixed solution of HNO ₃ and HF to perform edge insulation and back polishing;

(4) A layer of ultra-thin tunnel oxide layer SiO ₂ is grown on the back side of the silicon wafer by wet chemical method, its thickness is less than 2nm, and then a P-doped polysilicon layer with a thickness of 15nm is grown on it by PECVD method. This implementation Take fluosilicic acid H ₂ SiO ₆ solution with a concentration of 1.3M, protect the front side of the silicon wafer with a mask and put it into the fluosilicic acid solution, and accurately control the thickness of the SiO ₂ film according to the deposition time, generally at The control time within 2nm thickness is 5 minutes. The P-doped polysilicon layer is prepared based on the PECVD method with high-purity SiH ₄ as the gas source at 500°C and then annealed at 900°C. The thickness of the P-doped polysilicon layer is 15nm, and the content of P atoms is 5×10 ¹⁸ cm ^-3 .

(5) Adopt atomic layer deposition technology, control the deposition temperature to be 180°C, and deposit a layer of aluminum oxide with a thickness of 20nm on the surface of the silicon chip to form a P ⁺ emitter junction;

(6) Control the temperature to 350°C, and grow a hydrogenated amorphous silicon nitride passivation anti-reflection layer on the front of the silicon wafer by PECVD method, with a thickness of 75nm;

(7) Use screen printing to print Ag/Al paste on the front side of the silicon wafer, sinter, and evaporate the back side to form an all-aluminum back field Al-BSF structure, and dry it in a drying oven. For 200°C, it is enough to ensure that both sides of the cell are in good contact.

Using this method to produce a battery, its structure is shown in Figure 1, on the front side of the silicon wafer 5 is provided with a B-doped P ⁺ emitter junction 4, a layer of aluminum oxide 3 and a hydrogenated amorphous silicon nitride passivation anti-reflection layer 2. An electrode 1 is provided on the upper part. An ultra-thin tunnel oxide layer SiO ₂ 6 is grown on the back of the silicon wafer, and a P-doped polysilicon layer 7 and an all-aluminum back field 8 are grown on the surface. The biggest advantage of the present invention is that the open circuit voltage of the battery can be greatly improved with a simple process. Compared with the open circuit voltage of the conventional battery of 650mV, the open circuit voltage of the battery can reach more than 690mV, and the conversion efficiency of the battery can be greatly improved. , can reach 22%-23%.

Example 2

A method for making a high-efficiency cell with an oxidation passivation contact on the back side of the front emitter junction adopts the following steps:

(1) Remove the damaged layer of the silicon wafer in NaOH alkali solution and H ₂ O ₂ solution, then use tetramethylammonium hydroxide and isopropanol to form a mixed solution to texture the silicon wafer, and form a 2 μm texture on both sides. pyramid suede;

(2) In the boron source high-temperature diffusion furnace tube, control the temperature at 900°C to diffuse for 30 minutes, and then control the temperature at 850°C to pass oxygen into the junction to form a low surface concentration B-doped P ⁺ emitter junction;

(3) Use HF solution to remove the borosilicate glass BSG layer, and use a mixed solution of HNO ₃ and HF to perform edge insulation and back polishing;

(4) Use wet chemical method to grow an ultra-thin tunnel oxide layer SiO ₂ on the back of the silicon wafer with a thickness of less than 2nm, and then grow a P-doped polysilicon layer with a thickness of 18nm on it by PECVD or other CVD methods In this example, a solution of fluorosilicate H ₂ SiO ₆ is used with a concentration of 1.5M. The front side of the silicon wafer is protected with a mask and placed in the fluorosilicate solution, and the thickness of the SiO ₂ film is precisely controlled according to the deposition time. , Generally, the control time within 2nm thickness is 6 minutes. The P-doped polysilicon layer is prepared based on the PECVD method with high-purity SiH ₄ as the gas source at 600°C and then annealed at 1000°C. The thickness of the P-doped polysilicon layer is 18nm, and the content of P atoms is 8×10 ¹⁸ - 1×10 ¹⁹ cm ^-3 .

(5) Adopting PECVD technology to deposit a layer of Al2O3 with a thickness of 25nm on the surface of the P ⁺ emitter junction on the silicon wafer, and control the deposition temperature to be 190°C when depositing the Al2O3 layer;

(6) A hydrogenated amorphous silicon nitride passivation antireflection layer is grown on the front side of the silicon wafer by magnetron sputtering, the temperature is controlled at 360°C, and the thickness is 80nm;

(7) Use screen printing to print Ag/Al paste on the front side of the silicon wafer and sinter it. The back side adopts evaporation method to form an all-aluminum back field Al-BSF structure, and dry it in a drying oven. The temperature is 260°C, just make sure that both sides of the cell are in good contact.

Example 3

A method for making a high-efficiency cell with an oxidation passivation contact on the back side of the front emitter junction adopts the following steps:

(1) Remove the damaged layer of the silicon wafer in NaOH alkali solution and H ₂ O ₂ solution, then use tetramethylammonium hydroxide and isopropanol to form a mixed solution to texture the silicon wafer, and form a 4 μm texture on both sides. pyramid suede;

(2) In the boron source high-temperature diffusion furnace tube, control the temperature at 1000°C to diffuse for 20 minutes, and then control the temperature at 900°C to pass oxygen into the junction to form a low surface concentration B-doped P ⁺ emitter junction;

(3) Use HF solution to remove the borosilicate glass BSG layer, and use a mixed solution of HNO ₃ and HF to perform edge insulation and back polishing;

(4) Use wet chemical method to grow an ultra-thin tunnel oxide layer SiO ₂ on the back of the silicon wafer, the thickness of which is less than 2nm, and then grow a P-doped polysilicon layer with a thickness of 20nm on it by PECVD or other CVD methods In this example, a solution of fluorosilicate H ₂ SiO ₆ with a concentration of 1.7M is used. The front side of the silicon wafer is protected with a mask and placed in the fluorosilicate solution, and the thickness of the SiO ₂ film is precisely controlled according to the deposition time. , Generally, the control time within 2nm thickness is 8 minutes. The P-doped polysilicon layer is prepared based on the PECVD method with high-purity SiH ₄ as the gas source at 600°C and then annealed at 1100°C. The thickness of the P-doped polysilicon layer is 20nm, and the content of P atoms is 1×10 ¹⁹ cm ^{- 3} .

(5) A layer of Al2O3 with a thickness of 30nm is deposited on the surface of the P ⁺ emitter junction on the silicon wafer by atomic layer deposition technology, and the deposition temperature is controlled to be 200°C when depositing the Al2O3 layer;

(6) Control the temperature to 400°C, and grow a hydrogenated amorphous silicon nitride passivation anti-reflection layer on the front of the silicon wafer by magnetron sputtering, with a thickness of 85nm;

(7) Use screen printing method to print Ag/Al paste on the front side of the silicon wafer and sinter it. The back side adopts the source coating method to form an all-aluminum back-field Al-BSF structure, and dry it in a drying furnace. The temperature is 300°C, just ensure that both sides of the cell are in good contact.

The main advantage of the present invention is that compared with other high-efficiency batteries, such as IBC, HIT, etc., the process is relatively simple, and compared with traditional crystalline silicon batteries, the process compatibility is strong, suitable for large-scale production, and has certain practicability . From the performance testing data of the battery prepared in Examples 1-3, it can be seen that the open circuit voltage V _oc of the battery is very high, about 30mV higher than that of a conventional battery (～650mV), and the fill factor is very high (>80%). Therefore, the conversion efficiency can reach more than 22%.

V _oc =680±2mV, J _sc =39.6±0.4mA/cm ² , FF=81.5±0.5%, Eff=22.5±0.5%.

Claims (9)

1. the preparation method of emitter junction back side tunnel oxidation passivation contact high-efficiency battery before, it is characterised in that the party Method uses following steps：

(1) utilize silicon chip in KOH or NaOH aqueous slkalis and H₂O₂Removed in solution and damage layer, then used TMAH and isopropanol constitute mixed solution and making herbs into wool are carried out to silicon chip, and two-sided formation has 1-4 μm Pyramid matte；

(2) in boron source high temperature diffusion furnace tube, it is 850-1000 DEG C of diffusion 20-40min to control temperature, is then controlled Temperature processed is passed through oxygen knot for 800-900 DEG C, forms low surface concentration B doping P⁺Emitter junction；

(3) using HF solution removal Pyrex bsg layer, HNO is used₃Mixed solution with HF carries out side Insulation and polished backside；

(4) one layer of ultra-thin tunnel oxidation layer SiO is grown at the back side of silicon chip using the method for wet chemistry₂, connect And grow phosphorus doped polysilicon layer thereon with PECVD or other CVDs；

(5) ald or PECVD technique is taken to form P to silicon chip⁺The surface deposit thickness of emitter junction is The alundum (Al2O3) layer of 20-30nm；

(6) in front side of silicon wafer using PECVD or magnetron sputtering method growth hydrogenated amorphous silicon nitride passivated reflection reducing Layer is penetrated, thickness is 75-85nm；

(7) Ag/Al slurries are printed in the front of silicon chip using the method for silk-screen printing, is sintered, the back side is adopted Take evaporation or apply source method and form full aluminium back surface field Al-BSF structures, dried with drying oven, it is ensured that cell piece it is double Face all forms good contact.

2. tunnel oxidation passivation in the preceding emitter junction back side according to claim 1 contacts the making side of high-efficiency battery Method, it is characterised in that be put into silicate fluoride solution after front side of silicon wafer mask protection is got up in step (4), Time according to deposition is come precise control SiO₂The thickness of film layer.

3. tunnel oxidation passivation in the preceding emitter junction back side according to claim 2 contacts the making side of high-efficiency battery Method, it is characterised in that the concentration of described silicate fluoride solution is 1.3-1.7M, and silicon chip is deposited on into silicate fluoride solution Middle 5-8min, controls SiO₂The thickness of film layer is within 2nm.

4. tunnel oxidation passivation in the preceding emitter junction back side according to claim 1 contacts the making side of high-efficiency battery Method, it is characterised in that phosphorus doped polysilicon layer is with high-purity Si H based on PECVD in step (4)₄It is source of the gas Formed by annealing at 900-1100 DEG C after being prepared at 500-600 DEG C.

5. tunnel oxidation passivation in the preceding emitter junction back side according to claim 1 contacts the making side of high-efficiency battery Method, it is characterised in that the thickness of phosphorus doped polysilicon layer is 15-20nm.

6. tunnel oxidation passivation in the preceding emitter junction back side according to claim 1 contacts the making side of high-efficiency battery Method, it is characterised in that P atom contents are 5 × 10 in phosphorus doped polysilicon layer¹⁸-1×10¹⁹cm^-3。

7. tunnel oxidation passivation in the preceding emitter junction back side according to claim 1 contacts the making side of high-efficiency battery Method, it is characterised in that it is 180-200 DEG C to control depositing temperature during step (5) deposition alundum (Al2O3) layer.

8. tunnel oxidation passivation in the preceding emitter junction back side according to claim 1 contacts the making side of high-efficiency battery Method, it is characterised in that control the temperature to be when growth hydrogenated amorphous silicon nitride passivated reflection reducing is penetrated layer in step (6) 350-400℃。

9. tunnel oxidation passivation in the preceding emitter junction back side according to claim 1 contacts the making side of high-efficiency battery Method, it is characterised in that the temperature of drying is 200-300 DEG C in step (7).