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AU2003298903A1 - Mechanism for processor power state aware distribution of lowest priority interrupts - Google Patents

Mechanism for processor power state aware distribution of lowest priority interrupts

Info

Publication number
AU2003298903A1
AU2003298903A1 AU2003298903A AU2003298903A AU2003298903A1 AU 2003298903 A1 AU2003298903 A1 AU 2003298903A1 AU 2003298903 A AU2003298903 A AU 2003298903A AU 2003298903 A AU2003298903 A AU 2003298903A AU 2003298903 A1 AU2003298903 A1 AU 2003298903A1
Authority
AU
Australia
Prior art keywords
power state
lowest priority
processor power
state aware
priority interrupts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003298903A
Other languages
English (en)
Inventor
James Crossland
John Horigan
Shivnandan Kaushik
Alon Naveh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU2003298903A1 publication Critical patent/AU2003298903A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3243—Power saving in microcontroller unit
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/329—Power saving characterised by the action undertaken by task scheduling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5094—Allocation of resources, e.g. of the central processing unit [CPU] where the allocation takes into account power or heat criteria
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Power Sources (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Pinball Game Machines (AREA)
  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
AU2003298903A 2002-12-26 2003-12-05 Mechanism for processor power state aware distribution of lowest priority interrupts Abandoned AU2003298903A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/330,622 US7191349B2 (en) 2002-12-26 2002-12-26 Mechanism for processor power state aware distribution of lowest priority interrupt
US10/330,622 2002-12-26
PCT/US2003/038612 WO2004061686A2 (fr) 2002-12-26 2003-12-05 Mecanisme pour la repartition compatible a l'etat de puissance de processeur d'interruptions de derniere priorite

Publications (1)

Publication Number Publication Date
AU2003298903A1 true AU2003298903A1 (en) 2004-07-29

Family

ID=32654547

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003298903A Abandoned AU2003298903A1 (en) 2002-12-26 2003-12-05 Mechanism for processor power state aware distribution of lowest priority interrupts

Country Status (7)

Country Link
US (2) US7191349B2 (fr)
CN (1) CN100349147C (fr)
AU (1) AU2003298903A1 (fr)
DE (1) DE10393969T5 (fr)
GB (1) GB2412457B (fr)
TW (1) TWI233545B (fr)
WO (1) WO2004061686A2 (fr)

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GB2412457B (en) 2006-01-25
US20040128563A1 (en) 2004-07-01
US7191349B2 (en) 2007-03-13
GB0505391D0 (en) 2005-04-20
DE10393969T5 (de) 2008-06-26
WO2004061686A2 (fr) 2004-07-22
HK1075314A1 (en) 2005-12-09
CN1732447A (zh) 2006-02-08
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US7761720B2 (en) 2010-07-20

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