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AU2001283374A1 - Method and apparatus for combining architectures with logic option - Google Patents

Method and apparatus for combining architectures with logic option

Info

Publication number
AU2001283374A1
AU2001283374A1 AU2001283374A AU8337401A AU2001283374A1 AU 2001283374 A1 AU2001283374 A1 AU 2001283374A1 AU 2001283374 A AU2001283374 A AU 2001283374A AU 8337401 A AU8337401 A AU 8337401A AU 2001283374 A1 AU2001283374 A1 AU 2001283374A1
Authority
AU
Australia
Prior art keywords
logic option
architectures
combining
combining architectures
option
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001283374A
Inventor
Dean D. Gans
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of AU2001283374A1 publication Critical patent/AU2001283374A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1678—Details of memory controller using bus width
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/104—Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
AU2001283374A 2000-08-18 2001-08-16 Method and apparatus for combining architectures with logic option Abandoned AU2001283374A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/640,740 US6725316B1 (en) 2000-08-18 2000-08-18 Method and apparatus for combining architectures with logic option
US09640740 2000-08-18
PCT/US2001/025499 WO2002017081A1 (en) 2000-08-18 2001-08-16 Method and apparatus for combining architectures with logic option

Publications (1)

Publication Number Publication Date
AU2001283374A1 true AU2001283374A1 (en) 2002-03-04

Family

ID=24569518

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001283374A Abandoned AU2001283374A1 (en) 2000-08-18 2001-08-16 Method and apparatus for combining architectures with logic option

Country Status (5)

Country Link
US (1) US6725316B1 (en)
JP (1) JP4226898B2 (en)
KR (1) KR100628550B1 (en)
AU (1) AU2001283374A1 (en)
WO (1) WO2002017081A1 (en)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6727533B2 (en) * 2000-11-29 2004-04-27 Fujitsu Limited Semiconductor apparatus having a large-size bus connection
US20030088799A1 (en) * 2001-11-05 2003-05-08 Bodas Devadatta V. Method and apparatus for regulation of electrical component temperature and power consumption rate through bus width reconfiguration
JP2003208399A (en) * 2002-01-15 2003-07-25 Hitachi Ltd Data processing device
PE20040015A1 (en) * 2002-03-26 2004-01-29 Derhsing Lai NEW CHIP OF INTEGRATED CIRCUITS FOR BIOLOGICAL TESTS
US6882590B2 (en) * 2003-01-29 2005-04-19 Micron Technology, Inc. Multiple configuration multiple chip memory device and method
US7280428B2 (en) 2004-09-30 2007-10-09 Rambus Inc. Multi-column addressing mode memory system including an integrated circuit memory device
US8595459B2 (en) 2004-11-29 2013-11-26 Rambus Inc. Micro-threaded memory
US20070094436A1 (en) * 2005-10-20 2007-04-26 Keown William F Jr System and method for thermal management in PCI express system
KR20070105779A (en) * 2006-04-27 2007-10-31 엠텍비젼 주식회사 Memory device having process function and process method thereof
US20070260841A1 (en) * 2006-05-02 2007-11-08 Hampel Craig E Memory module with reduced access granularity
KR100782594B1 (en) 2006-07-14 2007-12-06 엠텍비젼 주식회사 Memory device with data processing function
KR100805836B1 (en) * 2006-07-26 2008-02-21 삼성전자주식회사 Bus width setting device, display device and bus width setting method
US9268719B2 (en) 2011-08-05 2016-02-23 Rambus Inc. Memory signal buffers and modules supporting variable access granularity
US9037948B2 (en) 2013-03-13 2015-05-19 International Business Machines Corporation Error correction for memory systems
US20160092383A1 (en) * 2014-09-26 2016-03-31 Kuljit S. Bains Common die implementation for memory devices
JP6230588B2 (en) * 2015-12-25 2017-11-15 ルネサスエレクトロニクス株式会社 Semiconductor device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4667305A (en) * 1982-06-30 1987-05-19 International Business Machines Corporation Circuits for accessing a variable width data bus with a variable width data field
DE3884492T2 (en) 1987-07-15 1994-02-17 Hitachi Ltd Integrated semiconductor circuit arrangement.
US5165037A (en) * 1988-09-09 1992-11-17 Compaq Computer Corporation System for controlling the transferring of different widths of data using two different sets of address control signals
US5262990A (en) * 1991-07-12 1993-11-16 Intel Corporation Memory device having selectable number of output pins
JP2836321B2 (en) * 1991-11-05 1998-12-14 三菱電機株式会社 Data processing device
US5293381A (en) * 1992-03-27 1994-03-08 Advanced Micro Devices Byte tracking system and method
US5504875A (en) 1993-03-17 1996-04-02 Intel Corporation Nonvolatile memory with a programmable output of selectable width and a method for controlling the nonvolatile memory to switch between different output widths
US5991196A (en) 1997-12-16 1999-11-23 Microchip Technology Incorporated Reprogrammable memory device with variable page size
US6463031B1 (en) * 1998-12-03 2002-10-08 Nokia Mobile Phones Limited Rate determination technique that utilizes modified cumulative metrics to orthogonalize the rates
US6049501A (en) 1998-12-14 2000-04-11 Motorola, Inc. Memory data bus architecture and method of configuring multi-wide word memories

Also Published As

Publication number Publication date
JP2004517382A (en) 2004-06-10
KR20030024890A (en) 2003-03-26
WO2002017081A1 (en) 2002-02-28
US6725316B1 (en) 2004-04-20
KR100628550B1 (en) 2006-09-26
JP4226898B2 (en) 2009-02-18

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