KR20070105779A - Memory device having process function and process method thereof - Google Patents

Abstract

A memory device having a process function and a process method thereof are disclosed. A storage unit for recording one or more data and instruction information by a processor according to an embodiment of the present invention; And a processing unit that performs a process corresponding to the command information with respect to any data recorded in the storage unit. According to the present invention, a memory device having a processing unit and an instruction processing method thereof may independently execute a command received from a processor and enhance processing efficiency of a processor performing processing of data recorded in the memory device. have.

Description

Memory device having a process function and a process method thereof

1 is a block diagram illustrating a configuration of a memory device and a peripheral device according to an exemplary embodiment of the present invention.

2 is a flowchart illustrating a process of processing an instruction when the processor does not need to receive the instruction completion information again according to an exemplary embodiment of the present invention.

3 is a flowchart illustrating a process of processing an instruction when the processor needs to receive instruction completion information again according to an exemplary embodiment of the present invention.

4 is a flowchart illustrating a process of processing a command when the processor 120 directly delivers command completion information to an external output device according to an exemplary embodiment of the present invention.

5 is a view showing an example of a command to be processed in the processing unit 120 according to an embodiment of the present invention.

Fig. 6 is a diagram showing a dual port memory device showing an instruction processing relationship from a plurality of processors according to a preferred embodiment of the present invention.

The present invention relates to a memory device, and more particularly, to a memory device having a process function and a process method thereof.

The conventional memory control method uses an interrupt. This sends commands (e.g., data transfer commands to the receiving end, etc.) to an In / Output controller that has a processor (e.g., Central Processing Unit) internally or coupled to it. After the input / output controller executes the received command, a series of tasks are completed by transmitting an interrupt signal (for example, a processing completion signal) to the processor.

In the conventional memory control scheme, when the input / output controller is provided independently, the processor may perform other tasks while the input / output controller executes a received command. However, there has been a problem in that the processor must be directly involved in communication between an input / output device and a storage device such as a memory.

In order to improve this, a direct memory control (DMA) method has been conventionally proposed. This is a method of directly transferring data between memories or between a memory and a peripheral without intervening a processor. Therefore, the direct memory control controller (DMA Controller) does not use a processor, so the address of the input / output controller, an operation specifier (for example, information for interpreting processing instructions for performing read and / or write operations), memory It should be configured to know the information such as start address, transmission data, etc. of the storage area.

The direct memory control scheme described above has the advantage of reducing the burden on the processor to perform tasks and eliminating processor involvement. However, there is a problem in that a function such as direct memory control must be provided in the memory, and a corresponding interface must be separately provided in order for the direct memory control controller to communicate with the processor or the memory. In addition, since a corresponding interface must be provided in order to be directly interlocked with the memory control controller, there is a problem in that free replacement of the memory is limited.

Accordingly, an object of the present invention to solve the above problems is to provide a memory device having a process function and a process method implemented so that the memory device can independently execute instructions received from the processor.

It is another object of the present invention to provide a memory device having a processing unit 120 to increase the processing efficiency of a processor for processing data recorded in the memory device and a method of processing the same.

It is still another object of the present invention to provide a memory device having a process function capable of improving system processing efficiency and speed when displaying data recorded in the memory device through an external output device, and a process method thereof.

Other objects of the present invention will be readily understood through the description of the following examples.

In order to achieve the above object and solve the problems of the prior art, according to one aspect of the present invention, a memory device having a process function is provided.

A memory device having a process function according to an embodiment of the present invention includes a storage unit for recording arbitrary data and instruction information by a processor; And a processing unit that performs a process corresponding to the command information recorded in the storage unit on the data.

The process processed by the memory device may be any one of data copying, data operation, and data output through an external output device.

At this time, the command information includes command start information for instructing to start execution of the process; It may include command processing information for specifying the type and content of the process.

In addition, when the process is a data copy, the command processing information includes type information for designating a type of the process, address information in the storage unit where source data is recorded, and address information on which the source data is copied. It may include.

Further, when the process is a data operation, the instruction processing information includes type information for designating a type of the process, address information in the storage unit in which source data is recorded, and the memory in which data calculated from the source data is to be recorded. May contain address information within the department.

Further, when the process is a data output, the command processing information includes type information for designating a type of the process, address information in the storage unit in which source data to be output through the external output device is recorded, and the external output device. May include address information in the storage to be recorded.

According to an embodiment, when the instruction start information and the instruction processing information are divided and recorded in the storage unit from the processor, the storage unit may include: a storage area in which one or more data is recorded; A mailbox control register in which the command start information is recorded; And a mailbox in which the command processing information is recorded.

 The storage unit may further include a mail out box in which command completion information corresponding to a result of the process performed by the processing unit is recorded.

Further, the processing unit may include a command signal generation unit for determining whether the command start information is recorded and outputting the command start signal when recorded; It may include a command processing unit for performing the corresponding process by reading the command processing information corresponding to the command start signal.

The processor may output an interrupt signal to the processor when execution of a process corresponding to the command information is completed.

In addition, the memory device according to an embodiment of the present invention may be provided between the processor and the external output device.

A memory device shared by a plurality of processors according to an embodiment of the present invention includes a storage unit for storing arbitrary data and instruction information recorded by a processor; A processing unit may be configured to perform a process corresponding to the command information on any data recorded in the storage unit, and the processing unit may be provided for each of the coupled processors.

That is, the memory unit included in the memory device shared by the plurality of processors may be one or two or more. However, the processing unit may be provided separately for the plurality of processors.

In particular, when there are a plurality of storage units, the storage units may be individually allocated to each processor and provided in pairs with the plurality of processing units.

In addition, when the storage unit is one or more than one, any one of the storage unit is composed of a plurality of partitions logically divided in the storage unit to match the number of the combined processor, each partition area is assigned to each processor Individually allocated may be provided in pairs with the plurality of processing units.

In addition, when any one of the storage units is jointly allocated to a processing unit coupled to each of the plurality of processors regardless of the number of the plurality of processors, and the data is stored, the processing unit corresponds only to instruction information by the coupled processor. You can also run the process individually.

In other words, the storage unit may be physically provided in pairs with the plurality of processing units, or may be provided in pairs with the plurality of processing units using a logical partition area. Further, the same area allocated to the storage unit may share an area in which the plurality of processing units record the instruction information transmitted from the processor. However, in this case, each processor may record information in the same region that the processor connected to the processor processes the instruction so that each processor coupled to the processor may process an instruction corresponding to the instruction of the processor. to be.

In addition, the process processed in a memory device shared by a plurality of processors may be any one of data copying, data operation, and data output through an external output device.

In particular, for a memory device shared by a plurality of processors, the process may be data copying, data operation, data output through an external output device, or the like. Detailed description of each process for this is as described above.

The instruction information may include instruction start information for instructing to start execution of the process; Command processing information for specifying the type and content of the process may be further included.

In this case, when the instruction start information and the instruction processing information are divided and recorded in the storage unit from the processor, the storage unit includes: a storage area in which one or more data is recorded; A mailbox control register in which the instruction start information is recorded; It may include a mailbox in which the command processing information is recorded.

 The storage unit may further include a mail out box in which command completion information corresponding to a result of performing the process by the processing unit is recorded.

The processing unit may further include: a command start signal generation unit that determines whether the command start information is recorded and outputs a command start signal when the command start information is recorded; It may include a command processing unit for performing the corresponding process by reading the command processing information corresponding to the command start signal.

In addition, the processor may provide an interrupt signal to the processor when execution of a process corresponding to the command information is completed.

In order to achieve the above object, a method of performing a process of a memory device having a process function according to an embodiment of the present invention comprises the steps of: determining whether instruction start information has been recorded by an arbitrary processor; Reading the command processing information recorded corresponding to the command start information when the command start information is recorded; The method may include performing a process specified in advance to correspond to the read command processing information.

In addition, when the execution of the process is completed, the method may further include recording command completion information that is a result value corresponding to the execution of the process.

Furthermore, the process execution method may further include outputting command completion information, which is a result value corresponding to the process execution, to the external output device when the execution of the process is completed.

The method may further include outputting an interrupt signal to the processor when the process is completed.

In order to perform the process performing method according to an embodiment of the present invention, a program of instructions that can be executed in a memory device is tangibly implemented, and a recording medium in which a program that can be read by the memory device is recorded,

Determining whether instruction start information has been recorded by an arbitrary processor; Reading the command processing information recorded corresponding to the command start information when the command start information is recorded; A program for executing a process of performing a predetermined process corresponding to the read command processing information may be a recording medium.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements.

Terms such as first, second, A, and B may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. The term and / or includes a combination of a plurality of related items or any item of a plurality of related items.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. Hereinafter, the same reference numerals are used for the same components in the drawings, and duplicate descriptions of the same components are omitted. In addition, in describing the present invention, when it is determined that the detailed description of the related known technology may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted.

1 is a block diagram illustrating a configuration of a memory device and a peripheral device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a memory device 100 according to an embodiment of the present invention includes a memory 110 and a processor 120.

The storage unit 110 may include a mailbox control register 112, a mailbox 114, a mail outbox 116, and a storage area 118. The memory unit 110 may be, for example, an SDRAM.

The mailbox control register 112 is an area in which instruction start information is recorded by the processor 130. The instruction start information is information for indicating the start of the instruction processing information recorded in the mailbox 114 by the processor 130.

The processor 130 may access the mailbox control register 112 to record instruction start information (for example, '1' or '0', which is assumed to be '1'). The mailbox control register 112 may be any storage area designated to have a size of, for example, several tens of bytes, and the processor 130 may read a value written in the area or read any value. Can be written.

Specifically, the processing unit 120 may not perform any processing operation even if arbitrary command processing information is recorded in the mailbox 114 in the state where '0' is recorded in the mailbox control register 112. . Then, when '1' is recorded in the mailbox control register 112, processing operations corresponding to the command processing information recorded in the mailbox 114 (e.g., data copying, graphic data processing, arbitrary data). Output to the external output device 140). Of course, the command start information may be recorded as a value of n (arbitrary natural number), and it is obvious that various values may be set whether or not to recognize the command start information when the value is recorded.

The mailbox box 114 is an area where the instruction processing information is recorded by the processor 130. The command processing information is information indicating the content of a command to be processed by the processing unit 120.

The type of command processing information may be specified in advance so as to be recognized by the processing unit 120. For example, the command processing information may be an operation command for calculating (eg, adding or subtracting) values recorded at respective addresses in the storage area 118 and writing them to a new address. In addition, the operation command may include a case of performing an operation (for example, function processing of a log value, an exponent value, etc.) using one value recorded at the arbitrary address.

The mail out box 116 is an area in which command completion information, which is a processing result value processed by the processing unit 120, is recorded corresponding to the command processing information. In this case, the processor 120 may determine whether to record the command completion information in the mail out box 116 according to the type of the command processing information. This will be described in detail later with reference to FIGS. 2 to 4. Of course, since the address at which the processing result value is to be recorded is designated by the processor 130, the mail outbox 116 may be omitted if any address of the storage area 118 is previously designated as the address at which the processing result value is to be recorded. Could be However, in the present specification, a description will be given on the assumption that the mail out box 116 is separately allocated so that the processor 130 may receive the processing result value.

The storage area 118 is an area in which data to be processed by the processing unit 120 or to be used by each processor 130 is recorded. The mailbox control register 112, the mailbox 114, and the mail outbox 116 described above may be areas in which one areas of the storage area 118 are respectively allocated for a predetermined use.

The processor 120 may include a command signal generator 122 and a command processor 124. In FIG. 1, the command signal generator 122 and the command processor 124 are shown as independent components for convenience of description and understanding, but the functions of the command signal generator 122 to be described below are described as command processor. If 122) is performed together, it is obvious that both may be implemented in an integrated manner. It is apparent that the processor 120 may be implemented as a software program (or a combination of program codes).

When the command signal generator 122 recognizes that command start information is recorded in the mailbox control register 112, the command processor 122 performs a processing operation corresponding to the command processing information recorded in the mailbox 114. It provides a command start signal to the command processing unit 122 to do so. The command signal generator 122 may detect whether the command start information is recorded by continuously or periodically monitoring the mailbox control register 112.

The processing operation of the command signal generator 122 will be briefly described as follows.

If, for example, " 1 " is recorded in the mailbox control register 112 as the command start information, the command signal generator 122 may delay the toggle signal and each toggle signal to be sequentially outputted. Each delay signal may be used to generate a command start signal of a predetermined type.

When the command start signal is input from the command signal generator 122, the command processor 124 reads the command processing information recorded in the mailbox 114 and performs a predetermined processing operation corresponding to the command processing information (ie , Process the command). In this case, the command processing unit 122 may record the command completion information as a result value in the mail out box 116 according to the type of the command processing information, or may transmit data to be output to the external output device 140.

In addition, when the processing operation corresponding to the command processing information recorded by the processor 130 is completed, the processing unit 120 outputs an interrupt signal indicating that the execution of the command processing information is completed to the corresponding processor 130. .

As described above, the command processing information recorded by the processor 130 may read a value Data recorded at an arbitrary address of the storage area 118, or write it to another address (for example, For example, a copy command, arithmetic operations (e.g., one or more of the four operations or log, exponent, etc.) to write the resulting value to another address (e.g., (Operation Command, etc.), converting the read data into a form that can be output through the external output device 140 to provide to the external output device 140 (for example, an output command (Output Command), etc.) ) And the like. Of course, when the processor 130 is directly connected to the external output device 140 to perform a separate process (for example, outputting through the external output device directly after the processor processes the graphic data), the memory It is apparent that the external output device can be controlled regardless of the device, and the data processing and the input / output relationship of the data between the processor, the memory device and the external output device can be variously set.

In addition, the interrupt signal described above is a signal that the processor 120 transmits to the processor 130 to inform that the processing corresponding to the command processing information is completed. The interrupt signal may be previously specified in the form of a signal transition (eg, Low to High, High to Low) or an edge signal (eg, Rising Edge, Falling Edge, etc.).

 2 is a flowchart illustrating a process in which an instruction is processed when the processor does not need to receive instruction completion information, which is a result value of the instruction processing information processed by the processor 120, according to an exemplary embodiment of the present invention. . For example, the processor 130 may not be provided with command completion information corresponding to the command processing information. For example, the command processing information may be a copy command.

In step S200, the processor 130 records in the storage unit 110 command processing information to be processed by the processing unit 120 and command start information for instructing the start of the command processing. As described above, the areas in which the command processing information and the command start information are recorded may be different. In this case, the processor 130 may record the instruction processing information after completing the recording of the instruction start information.

In step S210, the processor 120 detects that instruction start information is recorded in the memory 110. As described above, whether the command start information is recorded may be detected by the command signal generator 122 or the command processor 124.

The command signal generator 122, which detects that the command start information has been recorded, generates a command start signal for instructing the start of the process corresponding to the command process information and outputs the command start signal to the command processor 124 (step S220). As described above, when the command signal generator 122 and the command processor 122 are integrally implemented, step S220 may be omitted.

The processing unit 120 reads the command processing information recorded in the storage unit 110 in step S230 and proceeds to step S240 to perform the corresponding processing operation. The type and processing method of the command to be performed by the processing unit 120 may be specified in advance by the command processing information, and it is obvious that the processing unit 120 may be implemented to perform a corresponding operation.

Therefore, it is obvious that the execution process and the processing result of the processor 120 vary according to the read command processing information. As described above, when the command processing information is a copy command for copying the data recorded at the first address of the storage area 118 to the second address of the storage area 118, the processing unit 120 at the first address. The recorded data will be read and copied to the second address.

In operation S250, the processor 120 outputs an interrupt signal, which is a signal indicating that the processing of the command processing information is completed, to the processor 130 that records the command processing information.

3 is a flowchart illustrating a process of processing an instruction when the processor 130 needs to receive the instruction completion information again according to another exemplary embodiment of the present invention.

However, with respect to FIG. 2, descriptions overlapping with those described in detail will be omitted. Steps S300 to S340 are the same as the command processing method described with reference to FIG. 2, and thus description thereof will be omitted.

In step S350, the processing unit 120 processes the command according to the command processing information, and then records the command completion information, which is a command processing result value corresponding to the command processing information, in the specific area of the storage unit 110. Of course, the area designated by the processor 130 may be a mail out box. In this case, the instruction completion information needs to be returned from the processor 130 by the instruction completion information. As an example of the command processing information, arithmetic processing (for example, using arithmetic operation) may be performed on information recorded in a specific area C of the storage area 118 in the storage unit 110 and information recorded in another specific area D. For example, an operation command to generate a new result value or to generate a result value using a logarithmic operation or an exponential operation) and write it to another specific area E may be an example.

Since step S360 is the same as step S260, description thereof will be omitted.

In step S370, when the command is processed by the processor 120, the processor 120 generates the interrupt signal and outputs the interrupt signal to the processor 130. The processor 130 records the command completion information. The command completion information is read from the specific area E. Of course, the processor 130 may not read the command completion information. For example, when a process corresponding to a wrong operation instruction is performed by the processing unit, the processor may delete the first instruction completion information in which the instruction completion information is recorded without reading.

4 is a flowchart illustrating a process in which a command is processed when the processor 120 directly outputs command completion information to an external output device according to another exemplary embodiment of the present invention. Of course, as described above, the processor 130 may directly output data with the external output device 140.

However, descriptions overlapping with the already described contents will be omitted. Steps S400 to S440 are the same as the command processing method described in FIG. 2, and thus description thereof will be omitted.

In operation S450, the processor 120 processes the command according to the command processing information, and then transfers the command completion information, which is a result value, to the external output device 140. As an example of the command processing information, the information recorded in the specific area G of the storage area 118 of the storage unit 110 and the information recorded in the other specific area G are processed to obtain command completion information as a result value. An example may be an output command output to the external output device 140.

Since step S460 is the same as step S260, description thereof will be omitted.

5 is a diagram illustrating a configuration of a copy command which is one of command processing information according to an exemplary embodiment of the present invention.

Referring to FIG. 5, a command processing apparatus corresponding to a copy command includes a first line specifying a type of a corresponding command, a second line indicating a recording address of source data, and an address to which copied data is to be recorded. a third row indicating an address) and a fourth row indicating a size of data to be recorded.

Specifically, '0x0001' (530-1, that is, a copy command) indicating the type of the command is recorded in the address '0xfff80' 510-1 of the mailbox 114, and the mailbox 114 In the address '0xfff84' 510-2, the address 530-2 in the storage area 118 where the source data is recorded is recorded. Although the address 530-2 is described as Notfixed in FIG. 5, it is obvious that a related address may be recorded in the corresponding field.

Similarly, the address 530-3 to which the copied data is to be recorded is recorded at the address '0xfff88' 510-3 of the mailbox 114, and at the address '0xfff8c' 510-4 of the mailbox 114. The size 530-4 of the data to be copied is recorded.

Of course, the configuration of the illustrated command processing information may be different according to the type of the command. For example, in the case of an operation instruction, a plurality of source data addresses that are subject to an operation may be included, and an address in which an operation result value is recorded may be included. In addition, in the case of an output command, an address to which a result value is to be recorded may be omitted, and when there are a plurality of external output devices 140, information specifying which external output device 140 is to be outputted may be further included.

FIG. 6 is a diagram illustrating a dual port memory device indicating an instruction processing relationship from a plurality of processors according to another embodiment of the present invention.

The technical spirit of the present invention can be applied without limitation to a multiport memory device. This will be described in detail as follows. In the following description, it is assumed that the memory device is a dual port memory device shared by two processors.

When the plurality of processors 640 and 650 share one memory device 600, the memory device 600 may include storage units 612 and 614 and processing units 620 and 630 corresponding to each processor. have.

That is, the first processor 640 will record the command processing information and the command start information in the designated area of the first storage unit 612, and the second processor 650 will store the command processing information and the command start information in the second memory. It will write to the designated area of section 614.

The first processor 620 performs a corresponding process using the command processing information and the command start information recorded in the first storage unit 612, and then outputs an interrupt signal to the first processor 640. The operation 630 may output the interrupt signal to the second processor 650 after performing a corresponding process using the command processing information and the command start information recorded in the second storage unit 614.

Configurations of the first and second storage units 612 and 614 may be the same as or similar to those of the storage unit 110 described above with reference to FIG. 1. That is, when the accessible storage area for each processor is logically divided and set, it may have the same configuration as the storage unit 110 of FIG. 1. However, when the storage area is set to be accessible in common, but the mailboxes 114 and the like are independently assigned to each other, the first and second storage units 612 and 614 may have the same configuration as the storage unit 110 of FIG. 1. It will be slightly different.

In the latter case, however, normal processing may not be completed if the address to which the result value of the processing indicated by each processor matches the address to be recorded. In order to prevent this, an address for recording the processed result value may be set differently for each processor, or the instruction processing information may be mutually checked between the processing units 620 and 630 (or between processors) before recording the result value. It might be possible to have the steps performed.

 In other words, the storage unit may be physically provided in pairs with the plurality of processing units, or may be provided in pairs with the plurality of processing units using a logical partition area. Further, the same area allocated to the storage unit may share an area in which the plurality of processing units record the instruction information transmitted from the processor. However, in this case, each processor may record information in the same region that the processor connected to the processor processes the instruction so that each processor coupled to the processor may process an instruction corresponding to the instruction of the processor. to be.

In addition, a dual port memory device connected to the plurality of processors according to an embodiment of the present invention may be provided between the plurality of processors and the external output device. In addition, the external output devices may be provided in pairs corresponding to the plurality of processors. In addition, the external output device may be provided jointly for the plurality of processors.

That is, the plurality of processing units may be provided in pairs to correspond to the plurality of processors and may be provided in pairs for the external output device. In addition, the plurality of processing units are provided in pairs to correspond to the plurality of processors, but for the external output device, a process corresponding to the command processing information recorded by the processor is jointly connected to the external output device (for example, For example, an external output command may be performed.

The present invention is not limited to the above embodiments, and many variations are possible by those skilled in the art within the spirit of the present invention.

As described above, the memory device having the processing unit 120 and the command processing method according to the present invention have an effect that the memory device can independently execute a command received from the processor.

In addition, the present invention also has an effect of improving the processing efficiency of the processor for processing the data recorded in the memory device.

In addition, the present invention also has the effect of improving the system processing efficiency and speed when displaying the data recorded in the memory device via the external output device.

In addition, the present invention does not need to provide a separate interface for the direct memory control method, it is also an effect that the replacement of the memory device is easy.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art to which the present invention pertains without departing from the spirit and scope of the present invention and equivalents thereof described in the claims below. It will be understood that various modifications and changes can be made.

Claims (30)

A storage unit for storing arbitrary data and instruction information recorded by the processor; And And a processing unit that performs a process corresponding to the command information stored in the storage unit on the data. The method of claim 1, Wherein said process is any one of data copying, data operation and data output via an external output device. The method of claim 2, The command information, Instruction start information for instructing to start execution of the process; And And instruction processing information for designating the type and content of the process. The method of claim 3, wherein When the process is a data copy, the command processing information includes type information for designating a type of the process, address information in the storage unit in which source data is recorded, and data in which the source data is copied. And memory address information. The method of claim 3, wherein When the process is a data operation, the instruction processing information includes type information for designating the type of the process, address information in the storage unit in which source data is recorded, and data in the storage unit in which data calculated from the source data is to be recorded. And memory address information. The method of claim 3, wherein When the process is a data output, the command processing information includes type information for designating a type of the process, address information in the storage unit in which source data to be output through the external output device is recorded, and the external output device. And address information in the storage unit in which data to be outputted is recorded. The method of claim 3, wherein The storage unit, A storage area in which data is recorded; A mailbox control register in which the command start information is recorded; And And a mailbox in which the command processing information is recorded. The method of claim 7, wherein And the storage unit further includes a mail out box in which command completion information corresponding to a result of the process performed by the processing unit is recorded. The method according to any one of claims 3 to 8, The processing unit, A command signal generator which determines whether the command start information is recorded and outputs a command start signal when the command start information is recorded; And And a command processor to read the command processing information in response to the command start signal and perform a corresponding process. The method of claim 1, And the processing unit outputs an interrupt signal to the processor when execution of a process corresponding to the command information is completed. The method of claim 2, The memory device is provided between the processor and the external output device. In a memory device shared by a plurality of processors, A storage unit for storing arbitrary data and instruction information recorded by the processor; And A plurality of processing units for performing the process corresponding to the command information recorded in the storage unit on the data; And the processor is provided for each of the coupled processors. The method of claim 12, The memory unit is a plurality, And the storage unit is allocated to each of the processors individually and provided in pairs with the processing unit. The method of claim 12, wherein the memory unit is divided into a plurality of partitions divided to match the number of processors, each partition is individually assigned to each of the processor is provided with a pair with the processing unit, characterized in that Memory device. The method of claim 12, The storage unit is jointly assigned to a processing unit respectively coupled to the processor, And the processing unit individually performs a process corresponding to the instruction information by the coupled processor. The method according to any one of claims 13 to 15, Wherein said process is any one of data copying, data operation, and data output via an external output device. The method of claim 16, The command information, Instruction start information for instructing to start execution of the process; And And instruction processing information for designating the type and content of the process. The method of claim 17, When the process is a data copy, the command processing information includes type information for designating a type of the process, address information in the storage area in which source data is recorded, and address information in which data in which the source data is copied is recorded. And a memory device. The method of claim 17, When the process is a data operation, the command processing information includes type information for designating a type of the process, a plurality of address information in the storage unit in which source data is recorded, and data in which the source data is calculated. A memory device comprising address information in a storage unit. The method of claim 17, When the process is a data output, the command processing information includes type information for designating a type of the process, address information in the storage unit in which one or more source data to be output through the external output device are written, and the external output device. And information on the address in the storage to which the data to be output is to be written. The method of claim 17, The storage unit, A storage area in which one or more data are recorded; A mailbox control register in which the command start information is recorded; And And a mailbox in which the command processing information is recorded. The method of claim 21, And a mail out box in which command completion information corresponding to a result of performing the process by the processing unit is recorded. The method of claim 17, The processing unit, A command signal generator which determines whether the command start information is recorded and outputs a command start signal when the command start information is recorded; And And a command processor to read the command processing information in response to the command start signal and perform a corresponding process. The method of claim 12, And the processing unit outputs an interrupt signal to the processor when execution of a process corresponding to the command information is completed. The method according to any one of claims 12 to 15, The memory device is provided between the processor and the external output device. A method in which a memory device performs a predetermined process, (a) determining whether instruction start information has been recorded by an arbitrary processor; (b) when the command start information is recorded, reading the command processing information recorded corresponding to the command start information; And (c) performing the predetermined process to correspond to the read command processing information. The method of claim 26, In step (c), And when the execution of the process is completed, recording command completion information that is a result value corresponding to the execution of the process. The method of claim 26, In step (c), And outputting command completion information that is a result value corresponding to the execution of the process to an external output device when the execution of the process is completed. The method according to any one of claims 26 to 28, Outputting an interrupt signal to the processor when the execution of the process is completed. In a recording medium in which a program of instructions that can be executed in a memory device is tangibly embodied to perform a method of performing a process, and in which a program that can be read by the memory device is recorded. Determining whether instruction start information has been recorded by an arbitrary processor; Reading the command processing information recorded corresponding to the command start information when the command start information is recorded; And And a program for executing a step of performing a predetermined process corresponding to the read command processing information.

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