AU2001273526A1 - Devices and methods for addressing optical edge effects in connection with etched trenches - Google Patents
Devices and methods for addressing optical edge effects in connection with etched trenchesInfo
- Publication number
- AU2001273526A1 AU2001273526A1 AU2001273526A AU7352601A AU2001273526A1 AU 2001273526 A1 AU2001273526 A1 AU 2001273526A1 AU 2001273526 A AU2001273526 A AU 2001273526A AU 7352601 A AU7352601 A AU 7352601A AU 2001273526 A1 AU2001273526 A1 AU 2001273526A1
- Authority
- AU
- Australia
- Prior art keywords
- methods
- devices
- connection
- edge effects
- etched trenches
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/617,356 US6555895B1 (en) | 2000-07-17 | 2000-07-17 | Devices and methods for addressing optical edge effects in connection with etched trenches |
| US09617356 | 2000-07-17 | ||
| PCT/US2001/022456 WO2002007201A2 (fr) | 2000-07-17 | 2001-07-17 | Dispositifs et procedes d'adressage d'effets optiques de bord en relation avec des tranchees gravees |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| AU2001273526A1 true AU2001273526A1 (en) | 2002-01-30 |
Family
ID=24473331
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AU2001273526A Abandoned AU2001273526A1 (en) | 2000-07-17 | 2001-07-17 | Devices and methods for addressing optical edge effects in connection with etched trenches |
Country Status (8)
| Country | Link |
|---|---|
| US (3) | US6555895B1 (fr) |
| EP (1) | EP1303871A2 (fr) |
| JP (1) | JP4122215B2 (fr) |
| KR (3) | KR100848850B1 (fr) |
| CN (1) | CN1193411C (fr) |
| AU (1) | AU2001273526A1 (fr) |
| TW (1) | TW508694B (fr) |
| WO (1) | WO2002007201A2 (fr) |
Families Citing this family (43)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6461918B1 (en) | 1999-12-20 | 2002-10-08 | Fairchild Semiconductor Corporation | Power MOS device with improved gate charge performance |
| US7745289B2 (en) | 2000-08-16 | 2010-06-29 | Fairchild Semiconductor Corporation | Method of forming a FET having ultra-low on-resistance and low gate charge |
| US6916745B2 (en) | 2003-05-20 | 2005-07-12 | Fairchild Semiconductor Corporation | Structure and method for forming a trench MOSFET having self-aligned features |
| US6803626B2 (en) | 2002-07-18 | 2004-10-12 | Fairchild Semiconductor Corporation | Vertical charge control semiconductor device |
| US7132712B2 (en) | 2002-11-05 | 2006-11-07 | Fairchild Semiconductor Corporation | Trench structure having one or more diodes embedded therein adjacent a PN junction |
| US7345342B2 (en) | 2001-01-30 | 2008-03-18 | Fairchild Semiconductor Corporation | Power semiconductor devices and methods of manufacture |
| US6677641B2 (en) | 2001-10-17 | 2004-01-13 | Fairchild Semiconductor Corporation | Semiconductor structure with improved smaller forward voltage loss and higher blocking capability |
| US6818513B2 (en) | 2001-01-30 | 2004-11-16 | Fairchild Semiconductor Corporation | Method of forming a field effect transistor having a lateral depletion structure |
| US7061066B2 (en) | 2001-10-17 | 2006-06-13 | Fairchild Semiconductor Corporation | Schottky diode using charge balance structure |
| JP3701227B2 (ja) * | 2001-10-30 | 2005-09-28 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
| KR100859701B1 (ko) | 2002-02-23 | 2008-09-23 | 페어차일드코리아반도체 주식회사 | 고전압 수평형 디모스 트랜지스터 및 그 제조 방법 |
| US7033891B2 (en) | 2002-10-03 | 2006-04-25 | Fairchild Semiconductor Corporation | Trench gate laterally diffused MOSFET devices and methods for making such devices |
| US7576388B1 (en) | 2002-10-03 | 2009-08-18 | Fairchild Semiconductor Corporation | Trench-gate LDMOS structures |
| US6710418B1 (en) | 2002-10-11 | 2004-03-23 | Fairchild Semiconductor Corporation | Schottky rectifier with insulation-filled trenches and method of forming the same |
| US6716709B1 (en) * | 2002-12-31 | 2004-04-06 | Texas Instruments Incorporated | Transistors formed with grid or island implantation masks to form reduced diffusion-depth regions without additional masks and process steps |
| US7022247B2 (en) * | 2003-03-26 | 2006-04-04 | Union Semiconductor Technology Corporation | Process to form fine features using photolithography and plasma etching |
| TWI223448B (en) * | 2003-04-29 | 2004-11-01 | Mosel Vitelic Inc | DMOS device having a trenched bus structure |
| US7652326B2 (en) | 2003-05-20 | 2010-01-26 | Fairchild Semiconductor Corporation | Power semiconductor devices and methods of manufacture |
| KR100511045B1 (ko) * | 2003-07-14 | 2005-08-30 | 삼성전자주식회사 | 리세스된 게이트 전극을 갖는 반도체 소자의 집적방법 |
| US7138638B2 (en) * | 2003-11-20 | 2006-11-21 | Juni Jack E | Edge effects treatment for crystals |
| KR100994719B1 (ko) | 2003-11-28 | 2010-11-16 | 페어차일드코리아반도체 주식회사 | 슈퍼정션 반도체장치 |
| US7368777B2 (en) | 2003-12-30 | 2008-05-06 | Fairchild Semiconductor Corporation | Accumulation device with charge balance structure and method of forming the same |
| US7352036B2 (en) | 2004-08-03 | 2008-04-01 | Fairchild Semiconductor Corporation | Semiconductor power device having a top-side drain using a sinker trench |
| US7265415B2 (en) | 2004-10-08 | 2007-09-04 | Fairchild Semiconductor Corporation | MOS-gated transistor with reduced miller capacitance |
| JP2006196545A (ja) * | 2005-01-11 | 2006-07-27 | Toshiba Corp | 半導体装置の製造方法 |
| US7504306B2 (en) | 2005-04-06 | 2009-03-17 | Fairchild Semiconductor Corporation | Method of forming trench gate field effect transistor with recessed mesas |
| CN103094348B (zh) | 2005-06-10 | 2016-08-10 | 飞兆半导体公司 | 场效应晶体管 |
| US7385248B2 (en) | 2005-08-09 | 2008-06-10 | Fairchild Semiconductor Corporation | Shielded gate field effect transistor with improved inter-poly dielectric |
| US20070157516A1 (en) * | 2006-01-09 | 2007-07-12 | Fischer Bernhard A | Staged modular hydrocarbon reformer with internal temperature management |
| US7446374B2 (en) | 2006-03-24 | 2008-11-04 | Fairchild Semiconductor Corporation | High density trench FET with integrated Schottky diode and method of manufacture |
| US7319256B1 (en) | 2006-06-19 | 2008-01-15 | Fairchild Semiconductor Corporation | Shielded gate trench FET with the shield and gate electrodes being connected together |
| US8928077B2 (en) | 2007-09-21 | 2015-01-06 | Fairchild Semiconductor Corporation | Superjunction structures for power devices |
| US7772668B2 (en) | 2007-12-26 | 2010-08-10 | Fairchild Semiconductor Corporation | Shielded gate trench FET with multiple channels |
| US20120273916A1 (en) | 2011-04-27 | 2012-11-01 | Yedinak Joseph A | Superjunction Structures for Power Devices and Methods of Manufacture |
| US8432000B2 (en) | 2010-06-18 | 2013-04-30 | Fairchild Semiconductor Corporation | Trench MOS barrier schottky rectifier with a planar surface using CMP techniques |
| JP5691259B2 (ja) * | 2010-06-22 | 2015-04-01 | 株式会社デンソー | 半導体装置 |
| CN102183265A (zh) * | 2011-02-10 | 2011-09-14 | 刘清惓 | 一种用于测量表面覆盖物的电容传感器及测量方法 |
| US8772868B2 (en) | 2011-04-27 | 2014-07-08 | Fairchild Semiconductor Corporation | Superjunction structures for power devices and methods of manufacture |
| US8836028B2 (en) | 2011-04-27 | 2014-09-16 | Fairchild Semiconductor Corporation | Superjunction structures for power devices and methods of manufacture |
| US8673700B2 (en) | 2011-04-27 | 2014-03-18 | Fairchild Semiconductor Corporation | Superjunction structures for power devices and methods of manufacture |
| US8786010B2 (en) | 2011-04-27 | 2014-07-22 | Fairchild Semiconductor Corporation | Superjunction structures for power devices and methods of manufacture |
| EP3496153B1 (fr) | 2017-12-05 | 2021-05-19 | STMicroelectronics S.r.l. | Procédé de fabrication d'un dispositif semi-conducteur ayant une structure de bord efficace |
| CN112864239B (zh) * | 2021-03-17 | 2022-04-26 | 长江存储科技有限责任公司 | 场效应晶体管及其制备方法 |
Family Cites Families (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0239438A (ja) * | 1988-07-28 | 1990-02-08 | Nec Corp | 半導体装置の製造方法 |
| US5072266A (en) | 1988-12-27 | 1991-12-10 | Siliconix Incorporated | Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry |
| US5057462A (en) | 1989-09-27 | 1991-10-15 | At&T Bell Laboratories | Compensation of lithographic and etch proximity effects |
| US5430324A (en) | 1992-07-23 | 1995-07-04 | Siliconix, Incorporated | High voltage transistor having edge termination utilizing trench technology |
| JP2655469B2 (ja) * | 1993-06-30 | 1997-09-17 | 日本電気株式会社 | 半導体集積回路装置の製造方法 |
| US5468982A (en) * | 1994-06-03 | 1995-11-21 | Siliconix Incorporated | Trenched DMOS transistor with channel block at cell trench corners |
| JP3307785B2 (ja) | 1994-12-13 | 2002-07-24 | 三菱電機株式会社 | 絶縁ゲート型半導体装置 |
| KR100215759B1 (ko) | 1994-12-19 | 1999-08-16 | 모리시타 요이치 | 반도체 장치 및 그 제조방법 |
| EP0726603B1 (fr) | 1995-02-10 | 1999-04-21 | SILICONIX Incorporated | Transistor à effet de champ avec tranchée à barrière de dépletion PN |
| EP0746042B1 (fr) * | 1995-06-02 | 2004-03-31 | SILICONIX Incorporated | MOSFET de puissance avec tranchée bloquant bidirectionnel |
| KR0172561B1 (ko) | 1995-06-23 | 1999-03-30 | 김주용 | 노강 마스크의 근접 효과 억제방법 |
| JP2751909B2 (ja) | 1996-02-26 | 1998-05-18 | 日本電気株式会社 | 半導体装置の製造方法 |
| JP3311244B2 (ja) | 1996-07-15 | 2002-08-05 | 株式会社東芝 | 基本セルライブラリ及びその形成方法 |
| JPH10199859A (ja) * | 1997-01-08 | 1998-07-31 | Hitachi Ltd | 半導体装置の製造方法 |
| US5877528A (en) | 1997-03-03 | 1999-03-02 | Megamos Corporation | Structure to provide effective channel-stop in termination areas for trenched power transistors |
| TW322619B (en) * | 1997-04-15 | 1997-12-11 | Winbond Electronics Corp | The method for forming trench isolation |
| US6031265A (en) | 1997-10-16 | 2000-02-29 | Magepower Semiconductor Corp. | Enhancing DMOS device ruggedness by reducing transistor parasitic resistance and by inducing breakdown near gate runners and termination area |
| US6005271A (en) * | 1997-11-05 | 1999-12-21 | Magepower Semiconductor Corp. | Semiconductor cell array with high packing density |
| US6228746B1 (en) * | 1997-12-18 | 2001-05-08 | Advanced Micro Devices, Inc. | Methodology for achieving dual field oxide thicknesses |
| US5981999A (en) | 1999-01-07 | 1999-11-09 | Industrial Technology Research Institute | Power trench DMOS with large active cell density |
| US6413822B2 (en) * | 1999-04-22 | 2002-07-02 | Advanced Analogic Technologies, Inc. | Super-self-aligned fabrication process of trench-gate DMOS with overlying device layer |
| JP2001345294A (ja) * | 2000-05-31 | 2001-12-14 | Toshiba Corp | 半導体装置の製造方法 |
| US6372605B1 (en) * | 2000-06-26 | 2002-04-16 | Agere Systems Guardian Corp. | Additional etching to decrease polishing time for shallow-trench isolation in semiconductor processing |
-
2000
- 2000-07-17 US US09/617,356 patent/US6555895B1/en not_active Expired - Fee Related
-
2001
- 2001-07-16 TW TW090117362A patent/TW508694B/zh not_active IP Right Cessation
- 2001-07-17 EP EP01952808A patent/EP1303871A2/fr not_active Withdrawn
- 2001-07-17 KR KR1020077024366A patent/KR100848850B1/ko not_active Expired - Fee Related
- 2001-07-17 JP JP2002513007A patent/JP4122215B2/ja not_active Expired - Fee Related
- 2001-07-17 WO PCT/US2001/022456 patent/WO2002007201A2/fr not_active Ceased
- 2001-07-17 AU AU2001273526A patent/AU2001273526A1/en not_active Abandoned
- 2001-07-17 KR KR1020037000609A patent/KR100829047B1/ko not_active Expired - Fee Related
- 2001-07-17 CN CNB018129587A patent/CN1193411C/zh not_active Expired - Fee Related
- 2001-07-17 KR KR1020077024364A patent/KR20070116909A/ko not_active Abandoned
- 2001-08-08 US US09/924,855 patent/US6475884B2/en not_active Expired - Lifetime
-
2002
- 2002-01-17 US US10/051,504 patent/US6576952B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US20020093048A1 (en) | 2002-07-18 |
| KR100848850B1 (ko) | 2008-07-29 |
| KR20070116909A (ko) | 2007-12-11 |
| US6555895B1 (en) | 2003-04-29 |
| KR100829047B1 (ko) | 2008-05-16 |
| KR20030018050A (ko) | 2003-03-04 |
| EP1303871A2 (fr) | 2003-04-23 |
| JP4122215B2 (ja) | 2008-07-23 |
| JP2004504719A (ja) | 2004-02-12 |
| WO2002007201A3 (fr) | 2002-04-18 |
| CN1193411C (zh) | 2005-03-16 |
| US6576952B2 (en) | 2003-06-10 |
| US20020008281A1 (en) | 2002-01-24 |
| WO2002007201A2 (fr) | 2002-01-24 |
| TW508694B (en) | 2002-11-01 |
| KR20070107188A (ko) | 2007-11-06 |
| US6475884B2 (en) | 2002-11-05 |
| CN1449573A (zh) | 2003-10-15 |
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