NL2018115B1 - Active semiconductor device with linearized depletion capacitance - Google Patents
Active semiconductor device with linearized depletion capacitance Download PDFInfo
- Publication number
- NL2018115B1 NL2018115B1 NL2018115A NL2018115A NL2018115B1 NL 2018115 B1 NL2018115 B1 NL 2018115B1 NL 2018115 A NL2018115 A NL 2018115A NL 2018115 A NL2018115 A NL 2018115A NL 2018115 B1 NL2018115 B1 NL 2018115B1
- Authority
- NL
- Netherlands
- Prior art keywords
- semiconductor device
- capacitance
- active semiconductor
- depleted region
- port active
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 133
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 15
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 9
- 239000003990 capacitor Substances 0.000 claims description 7
- 238000013461 design Methods 0.000 description 12
- 238000000034 method Methods 0.000 description 11
- 125000006850 spacer group Chemical group 0.000 description 4
- 230000006872 improvement Effects 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000796 flavoring agent Substances 0.000 description 1
- 235000019634 flavors Nutrition 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009022 nonlinear effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D10/00—Bipolar junction transistors [BJT]
- H10D10/80—Heterojunction BJTs
- H10D10/821—Vertical heterojunction BJTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D10/00—Bipolar junction transistors [BJT]
- H10D10/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D10/00—Bipolar junction transistors [BJT]
- H10D10/01—Manufacture or treatment
- H10D10/021—Manufacture or treatment of heterojunction BJTs [HBT]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D10/00—Bipolar junction transistors [BJT]
- H10D10/40—Vertical BJTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/137—Collector regions of BJTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/60—Impurity distributions or concentrations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
Landscapes
- Bipolar Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Three port active semiconductor device (1) comprising a depleted region. The depleted region has a depletion capacitance (Ci) which is non-linear as function of a voltage over the depleted region. The semiconductor device (1) further comprises a depleted region capacitance linearization component (Ce), which in combination with the depletion capacitance (Ci) provides a linear capacitance-voltage relationship over a load line trajectory associated with the three port active semiconductor device (1).
Description
Field of the invention
The present invention relates to a three port active semiconductor device comprising a depleted region. The depleted region has a depletion capacitance which in general is non-linear as function of a voltage over the depleted region.
Background art
The article by K. Buisman et al. Evaluation of HBT device linearity using advanced measurement techniques, in European Microwave Conference (EuMC), 2013, discloses linearity characteristics of HBT semiconductor devices, and discusses that in bipolar semiconductor devices, the base-collector capacitance is a cause for non-linearity at higher power levels. This articles discusses the achievable linearity of four different SiGe and GaAs devices to their biasdependent base-collector charge behaviour in terms of their Cbc variation, as can be obtained from pulsed l-V/ s-parameters data. Solutions are also disclosed to address this non-linearity, however, this can only be attained in a very limited part of the load line of such semiconductor devices.
Summary of the invention
The present invention seeks to provide a linearized relationship between the capacitance and the voltage in the depletion region of a three port active semiconductor device achieving an improvement of linearity and reduction in distortion.
In accordance with the present invention embodiments, a three port active semiconductor device is provided as defined above, wherein the depleted region further comprise of a depleted region capacitance linearization component, which in combination with the (originally already present) depletion capacitance provides a linear capacitance-voltage relationship over a load line trajectory associated with the three port active semiconductor device. The three port active semiconductor device is e.g. a transistor, wherein the depleted region exhibits a non-linear intrinsic capacitance behaviour. The load line trajectory is associated with a specific part of the voltage range across the output terminals of the three port active semiconductor device (e.g. base-collector voltage) when a load impedance is connected, and is (more or less) centred around a bias point of the semiconductor device.
The present invention embodiments provide a solution to the impact of nonlinear effects due to base-collector, source-drain or drain-bulk charge storage, on the signal transfer characteristics of active semiconductor devices. This will provide an improvement in linearity and a reduction of distortion, without significantly increasing the device complexity or associated circuit complexity. Further design considerations for applications of such a semiconductor device can be maintained, as these design techniques are not affected by the present invention embodiment features. The present invention embodiments may be advantageously applied in many semiconductor technologies, including SiGe, GaAs, GaN and Si based three port devices.
Short description of drawings
The present invention will be discussed in more detail below, with reference to the attached drawings, in which;
Fig. 1 shows a schematic circuit of a cascode configuration with a compensated basecollectorjunction capacitance in the common-base stage, being a HBT semiconductor device, as used in a simulator circuit set-up, in accordance with an embodiment of the present invention.
Fig. 2 shows a cross sectional view of an HBT semiconductor device according to a further embodiment of the present invention.
Fig. 3 shows a graphical representation of OIP3 performance as a function of the Emitter resistance (Re) for an exemplary embodiment of a present invention semiconductor device.
Fig. 4A shows a graphical representation of a doping profile for an intrinsic part of an exemplary embodiment of a present invention semiconductor device.
Fig. 4B shows a graphical representation of a doping profile for an extrinsic region of an exemplary embodiment of a present invention semiconductor device.
Fig. 5A shows a graphical representation of capacitance curves for intrinsic, extrinsic and total capacitance of an exemplary embodiment of the present invention semiconductor device.
Fig. 5B shows a graphical representation of capacitance curves for intrinsic, extrinsic and total capacitance of a further exemplary embodiment of the present invention semiconductor device.
Description of embodiments
In modern day RF amplifiers using three port active semiconductor devices, a high linearity is crucial to ensure good performance of the amplifier. The three port active semiconductor device discussed is e.g. a Heterojunction Bipolar Transistor (HBT) or a Bipolar Junction Transistor (BJT), and may be provided in any of, as such, known techniques, such as Si, SiGe, GaAs or combinations of semiconductor materials. However the method described can also be used to linearize the junction capacitances of FET in various technology flavours.
One of the sources of nonlinearity in these types of devices is the nonlinear space charge modulation. The depleted region of such a semiconductor device has a depletion capacitance which is in general non-linear as function of a voltage over and possibly also non-linear as a function of current through the depleted region. In practical applications there are several ways in which the nonlinearity of these devices is addressed.
In bipolar devices, the limiting cause for the linearity at higher power levels is the basecollector capacitance. In e.g. SiGe HBT devices, this problem can only be minimized by careful device and/or circuit design (e.g. by using a high power back-off operation), or by using analog or digital pre-distortion. Analog pre-distortion is not precise in cancelling these kind of nonlinearities while digital pre-distortion needs a lot of digital computational power, resulting in a significant drop of overall power added /system efficiency.
The second option is to use lll-V semiconductor devices, such as GaAs devices, who have a higher electron drift velocity (including an velocity overshoot vs. electric field), allowing for a better trade-off in the collector design. By optimizing the collector design and the load line trajectory, the capacitance in these latter devices can be made relatively constant with respect to this load line trajectory, resulting in a significant improvement in the Output Third Order Intercept Point (OIP3), which is an important characteristic allowing to quantify third order intermodulation distortion (IM3D). However, this method is limited as the capacitance can only be optimized for a limited part of the load line. This means that for large signal excitation and class AB, B or F operation, the base-collector charge storage related distortion is still limiting the OIP3 significantly.
Laterally Diffused Metal Oxide Semiconductor (LDMOS) devices also have a nonlinear output capacitance in view of the drain-source/bulk substrate. Currently Field-Effect Transistor (FET) / LDMOS device are being linearized using a technique called Derivative Superposition (DS) which linearizes their transconductance. However, the DS technique does not tackle the problem of the nonlinear Cds capacitance.
Existing methods used for the linearization of the depletion capacitance either minimize the base-collector capacitance or make the base-collector capacitance as constant as possible for a give voltage range. Hence these methods do not provide a real solution for these distortion phenomena.
The present invention embodiments provide a linear relation of the capacitance in three port active semiconductor devices with respect to the voltage across the junction. In a first generic embodiment, the present invention relates to a three port active semiconductor device (transistor) comprising a depleted region, the depleted region having a depletion capacitance which is nonlinear as function of a voltage over the depleted region. The three port active semiconductor device further comprises a depleted region capacitance linearization component, which in combination with the depletion capacitance provides a linear capacitance-voltage relationship over a load line trajectory associated with the three port active semiconductor device 1. The implementation of the depleted region capacitance linearization component may be accomplished by changing the design of the device or by adding an additional linearization component in the device design, or external to the device. Thus according to the present invention embodiments, an addition of a component with a particular shaped C-V relation is used in order to reach an overall capacitance-voltage relation for the three port semiconductor device that is linear with the applied voltage in a predetermined range. The load line trajectory is associated with a specific part of the voltage range across the output terminals of the three port active semiconductor device (e.g. base-collector voltage) when a load impedance is connected, and is more or less centred around a bias point of the semiconductor device.
Fig. 1 shows a schematic circuit of a cascode configuration with a compensated basecollectorjunction capacitance in the common-base stage, being a HBT semiconductor device, as used in a simulator circuit set-up, in accordance with an embodiment of the present invention.
A simulator circuit set-up, which as such is known to the skilled person, is shown with a first transistor Q1 (with emitter lead resistor Re) and a second transistor Q2 in common-base configuration, of which the second transistor Q2 is linearized according to the present invention embodiments. The simulator circuit set-up arrangement further includes an input source Vin, with a source input impedance Zs and DC block capacitor Cs, in combination with a bias source Vbias in series with a DC feed inductor Li. At the load side, a further DC block capacitor Cl is shown in series with a load impedance Zl. Furthermore, voltage sources Vb.ce and Vce and DC feed inductor l_2 are provided as shown.
In this circuit diagram, the three port semiconductor device 1 is shown as comprising a (normal) transistor Q2, with a non-linear intrinsic capacitance Ci being present between the base and collector terminals of the device 1 (formed by a depletion capacitance of a depletion region of the device 1). Furthermore, as indicated, an extrinsic capacitance Ce is shown which is connected in parallel to the intrinsic capacitance Ci. The extrinsic capacitance Ce is an exemplary embodiment of the depleted region capacitance linearization component of the present invention embodiments.
In a three port active semiconductor device 1, a depletion capacitance Ci varies due to modulation of the space charge width of the depletion region in the semiconductor device 1. This modulation leads to a voltage and sometimes current dependent depletion capacitance C. When focusing on only the voltage dependency, the nonlinearity can be described by a nonlinear current source giving the following third order current;
i-NLCs(.Sl’S2’S3) = (S1 + S2 + S3) ' (^1)^1(^2)^1(¾) + 3 ^2c(^l (¾)¾ (S2< S3) + ^1(^2)^2(^11¾) + Hi(s3)H2(S1i S2)}j
Two components contribute to the non-linearity, a direct mixing component (influenced by the third Taylor derivative foe) and an indirect mixing component (influenced by the second Taylor derivative K2c). the indirect mixing component can be cancelled by shorting the currents at the baseband and second harmonic frequency (i.e. by proper circuit design around the semiconductor device 1), leaving the direct mixing component as source of the non-linear behavior. The direct mixing component cannot be canceled in a similar way and needs to be linearized, which means that the following equation should be complied with:
Since a depletion capacitance needs to be positive and always decreasing with the voltage, that leads to the following capacitance formula;
In the above equation, the first order exponent Ci needs to be large enough to ensure that the capacitance always decreases as voltage increases, as expected in a depletion capacitance. The zero order exponent Co needs to ensure that the capacitance stays positive in the desired voltage range. This capacitance formula gives a capacitor with a completely linear capacitance - voltage relation, i.e. a linear capacitance-voltage relationship over a load line trajectory associated with the three port active semiconductor device 1. (Note that the term ‘linear capacitance voltage relationship’ as used in the present application should not be confused with a constant capacitance, which is often also called linear.)
In any amplifier circuit with a second harmonic short and optionally a baseband short (e.g. implemented as the load impedance Zl in the Fig. 1 circuit arrangement), a capacitance in accordance with this capacitance formula would result in no nonlinearity due to the depletion capacitance. Using the constants Co and Ci, the capacitance can be made linear with respect to the voltage in a physical semiconductor device 1 within a defined voltage range. This means that such a semiconductor device 1 can be used in Low Noise Amplifiers (LNAs) and Power Amplifiers (PAs) used in class A, AB, B and F operation, or in other circuits that allow the use of a second harmonic short and optionally a baseband short.
Fig. 2 shows a cross sectional view of an example of a SiGe HBT device 1, in which the present invention embodiments may be applied. The SiGe HBT device 1 has a base terminal 2, an emitter terminal 3 and a collector terminal 4 (thus an example of a three port active semiconductor device 1). The structure of such a HBT device 1 as such is known to the person skilled in the art, and comprises as main functional regions a poly emitter region 5, a SiGe base region 6, a selectively implanted collector (SIC) region 7, a buried sub-collector region 8, an n-epilayer 9, and (only shown on one side, a deep trench (or channel stop) region 10. When looking at the base-collector capacitance, two regions play a possible role, i.e. the intrinsic capacitance region 11 and an extrinsic capacitance region 12. The extrinsic capacitance region 12represent a possible implementation for addition of the depleted region capacitance linearization component . The intrinsic capacitance region 11 is usually fully optimized for RF performance.
In accordance with the present invention, there are three possible groups of embodiments which implement the depleted region capacitance linearization component.
In a first group of embodiments, the depleted region capacitance linearization component is implemented as an adapted doping profile of the depleted region itself (e.g. intrinsic capacitance region 11 of the HBT device 1 shown in Fig. 2) which results in a linear capacitance voltage relationship over the load line trajectory. In this group of embodiments the doping profile of the junction of interest will be changed. E.g. the base-collector junction of a BJT device 1or a drain-source junction of an LDMOS device 1 are optimized for linearity behavior (but note that the design should also take into account other performance characteristics, such as ft, fmax, breakdown etc.).
In one embodiment of the first group of embodiment, the depleted region can be approximated by a one-sided junction having a doping profile which is function of the distance x from the one-sided junction according to the equation given below, wherein es is the permittivity of the active semiconductor device, q is the electronic charge, Ci is the linear voltage dependency of the capacitance and x is the distance from the one-sided junction. At V=0, the distance x should correspond to; x = — ; where Co is the zero voltage co capacitance. In order to prevent a singularity at x=0 according to the above equation, in a further embodiment of the present invention, the one-sided junction includes a spacer region. Thus the doping and thickness of this spacer region ultimately determines the value of Co per unit length of the active device The spacer region does not have to be abrupt, but only the distance at V=0 needs to be the same. If the operation is optimized for V>0, the rest of the design of the semiconductor device 1 is free to be determined.
In the second and third group of embodiments, it is recognized that the design of the transistor device 1 is constrained by various performance considerations and not only driven by linearity considerations. Especially since the intrinsic region 11 of the transistor (see exemplary embodiment of Fig. 2) is optimized for many different characteristics and/or specifications, an “external” compensation implementation has design advantages.
In the second and third group of embodiments, an external additional component is used, located outside the semiconductor device 1 in parallel to the nonlinear junction. In a further embodiment the present invention thus relates to a three port active semiconductor device wherein the depleted region capacitance linearization component is an additional component Ce connected in parallel to the depletion capacitance Ci of the depleted region.
There are two main implementation possibilities to implement the “external” compensation.
In the second group of embodiments, the extrinsic base-collector capacitance or extrinsic capacitance region 12 (see exemplary embodiment of Fig. 2) is used, located inside the semiconductor device 1 as a parallel parasitic capacitance to the intrinsic capacitance region 11. Thus, a further embodiment of the present invention relates to a three port active semiconductor device wherein an extrinsic capacitance is provided in parallel to the depletion region, having a capacitance-voltage relationship over the load line trajectory, which in combination with the intrinsic capacitance-voltage relationship of the depletion region, provides a linear capacitancevoltage relationship over the load line trajectory. Fig. 4A shows a graphical representation of the doping profile for the intrinsic capacitance region 11of an exemplary semiconductor device 1 according to this group of embodiments, whereas Fig. 4B shows a graphical representation of the doping profile for the extrinsic capacitance region 12 of that exemplary semiconductor device 1.
In the third group of embodiments the present invention relates to a three port active semiconductor device wherein a (discrete) capacitor component is connected externally to the active semiconductor device 1 parallel to the depletion region, having a capacitance-voltage relationship over the load line trajectory which, in combination with the intrinsic capacitancevoltage relationship of the depletion region, provides a linear capacitance-voltage relationship over the load line trajectory.
An additional embodiment for the second and third group of embodiments according to the present invention relates to a three port active semiconductor device wherein the depleted region capacitance linearization component has a capacitance-voltage relationship over the load line trajectory, wherein a capacitance value as function of the voltage over the depleted region capacitance linearization component has a second derivative which is opposite to a second derivative of the intrinsic capacitance-voltage relationship of the depletion capacitance Ci of the depletion region 11. In other words, two of the three possible alternatives of implementing a capacitance linear with respect to the voltage are to compensate the nonlinear part of the transistor externally, or in the extrinsic part of the transistor. When one of these alternatives is used, the second derivative of the compensation capacitor needs to be opposite of the second derivative of the intrinsic capacitance;
_ 1 d2 _ 1 d2 _ β dV2 β dV2
If this is done correctly, the total adds to zero;
K^r = K^r. + K^r = 0
Since in ordinary semiconductor devices 1, the capacitance-voltage curve shows a convex behaviour, the second derivative of these semiconductor devices 1 is positive. This means that the linearization component needs to have a negative second derivative, resulting in a concave curve. This can also be seen from the two examples presented in figure 5A and figure 5B. Fig. 5A shows a graphical representation of capacitance curves for intrinsic, extrinsic and total capacitance of an exemplary embodiment of the present invention semiconductor device. 1, which has an operational voltage range of about 0 to 2.5 V in its the load line trajectory. This is applicable to a general three port active semiconductor device such as a BJT or HBT device 1. Fig. 5B shows a graphical representation of capacitance curves for intrinsic, extrinsic and total capacitance of a further exemplary embodiment of the present invention semiconductor device. In this case, the operational voltage range is.in the 0 to 12 V region of the load line trajectory, i.e. for a high voltage device. It can be seen that the desired linearity is achieved in both cases.
In an another exemplary embodiment, the present invention relates to a three port active semiconductor device 1 comprising a compensation inductance which is used to correct for increased total capacitance. The extra capacitance due to the depleted region capacitance linearization component (in any of the embodiments described above) can be resonated out using this compensating inductor. A further embodiment of the present invention relates to a three port active semiconductor device wherein the three port active semiconductor device is a three terminal active semiconductor device as part of an electronic circuit, such as an amplifier, providing second harmonic shorts (Zl) for the three port active semiconductor device 1. An example of this relates to an amplifier with second harmonic shorts (and possibly also baseband shorts), e.g. implemented as the load impedance Zl (see Fig. 2). In an exemplary HBT device 1 based amplifier circuit, the collector-emitter (CE) stage can be linearized using two techniques. One of the methods is out-of-band matching using emitter tuning and the second method is by a derivative superposition. By using a collector base (CB) stage (cascoding), the voltage swing on the collector of the CE-stage is kept low, reducing feedback and nonlinearity due to the Cbc capacitance of the CE-stage. The CB-stage has no exponential distortion, since it is currentdriven. The expected limiting factor on linearity is the Cbc distortion in the CB-stage. To demonstrate this, two simulations have been done, one without and one with Cbc in the CB-stage as shown in the graphical representation of Fig. 3. The reference curve (without Cbc) strongly peaks in OIP3 when the optimum emitter resistance is offered for the chosen collector quiescent current, this result is represented by a dashed line. When the non-linear Cbc is included (without compensation) the OIP3 in the peak is decreased by 17dB. By inclusion of the Cbc compensation (making the total Cbc linear with respect to the applied junction voltage), the OIP3 is matching closely the achieved linearity performance of that of the reference curve (without Cbc).
As described above, the three port active semiconductor device 1 is e.g. a SiGe based semiconductor device. SiGe based devices are more cost-efficient and have integration advantages in the manufacturing process when compared to other semiconductor devices (such as GaAs based devices 1). Examples include but are not limited to a SiGe HBT or a SiGe BJT device 1. In SiGe bipolar HBT based amplifier circuits, the main sources of nonlinearity are originating from the exponential distortion created by the nonlinear Vbe-lc relation and the Cbc distortion created by the modulation of the space-charge region in the base-collector junction. Exponential distortion can be cancelled using out-of-band matching or derivative superposition. Further, Cbc distortion ultimately limits the linearity in SiGe HBT based amplifier circuits. According to the present invention embodiments as described above, it is shown that the Cbc distortion can be compensated by using the extrinsic region 12 of the collector part of the device to compensate the intrinsic region 11 of the collector part.
In yet a further embodiment the three port active semiconductor device 1 is a GaAs based semiconductor device. GaAs based semiconductor devices 1 can be very useful in specific applications, where manufacturing cost is less of an issue.
Furthermore, in a further embodiment, the three port active semiconductor device 1 is a silicon (Si) based semiconductor device. An example is a LDMOS type of device. In even further embodiments the three port active semiconductor device 1 is a GaN based semiconductor device, e.g. a high electron mobility transistor (HEMT) device.
The present invention embodiments as described above can be summarized by the following numbered and mutually referenced embodiments.
Embodiment 1. Three port active semiconductor device comprising a depleted region, the depleted region having a depletion capacitance which is non-linear as function of a voltage over the depleted region, further comprising a depleted region capacitance linearization component, which in combination with the depletion capacitance provides a linear capacitance-voltage relationship over a load line trajectory associated with the three port active semiconductor device (1).
Embodiment 2. Three port active semiconductor device according to embodiment 1, wherein the depleted region capacitance linearization component comprises a doping profile of the depleted region resulting in a linear capacitance voltage relationship over the load line trajectory.
Embodiment 3. Three port active semiconductor device according to embodiment 2, wherein the depleted region is a one-sided junction having a doping profile as function of the distance x from the one-sided junction according to:
N(x) = —---7 [cm-3] q · C! Xs wherein es is the permittivity of the active semiconductor device, q is the electronic charge, Ci is the linear voltage dependency of the capacitance and x is the distance from the one-sided junction.
Embodiment 4. Three port active semiconductor device according to embodiment 3, wherein the one-sided junction includes a spacer region.
Embodiment 5. Three port active semiconductor device according to embodiment 1, wherein the depleted region capacitance linearization component is an additional component (Ce) connected in parallel to the depletion capacitance (Ci) of the depleted region.
Embodiment 6. Three port active semiconductor device according to embodiment 5, wherein an extrinsic capacitance (Ce; 12) is provided in parallel to the depletion capacitance (Ci) of the depleted region (11), having a capacitance-voltage relationship over the load line trajectory, which in combination with the intrinsic capacitance-voltage relationship of the depleted region (11), provides a linear capacitance-voltage relationship over the load line trajectory.
Embodiment 7. Three port active semiconductor device according to embodiment 5, wherein a capacitor component (Ce) is connected externally to the active semiconductor device (1) parallel to the depleted region (11), having a capacitance-voltage relationship over the load line trajectory which, in combination with the intrinsic capacitance-voltage relationship of the depleted region (11), provides a linear capacitance-voltage relationship over the load line trajectory.
Embodiment 8. Three port active semiconductor device according to any one of embodiments 5-
7, wherein the depleted region capacitance linearization component (Ce) has a capacitancevoltage relationship over the load line trajectory, wherein a capacitance value as function of the voltage over the depleted region capacitance linearization component (Ce) has a second derivative which is opposite to a second derivative of the intrinsic capacitance-voltage relationship of the depletion capacitance (Ci) of the depleted region (11).
Embodiment 9. Three port active semiconductor device according to any one of embodiments 1-
8, wherein the three port active semiconductor device (1) is a three terminal active semiconductor device as part of an electronic circuit providing second harmonic shorts (Zl) for the three port active semiconductor device (1).
Embodiment 10. Three port active semiconductor device according to any one of embodiments 1-9, further comprising a compensation inductance.
Embodiment 11. Three port active semiconductor device according to any one of embodiments 1-10, wherein the three port active semiconductor device (1) is a Si or SiGe based semiconductor device.
Embodiment 12. Three port active semiconductor device according to any one of embodiments 1-10, wherein the three port active semiconductor device (1) is a GaAs based semiconductor device.
Embodiment 13. Three port active semiconductor device according to any one of embodiments 1-10, wherein the three port active semiconductor device (1) is a Si based semiconductor device.
Embodiment 14. Three port active semiconductor device according to any one of embodiments 1-10, wherein the three port active semiconductor device (1) is a GaN based semiconductor device.
The present invention has been described above with reference to a number of exemplary embodiments as shown in the drawings. Modifications and alternative implementations of some parts or elements are possible, and are included in the scope of protection as defined in the appended claims.
Claims (14)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| NL2018115A NL2018115B1 (en) | 2017-01-03 | 2017-01-03 | Active semiconductor device with linearized depletion capacitance |
| PCT/EP2018/050136 WO2018127514A1 (en) | 2017-01-03 | 2018-01-03 | Active semiconductor device with linearized junction capacitance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| NL2018115A NL2018115B1 (en) | 2017-01-03 | 2017-01-03 | Active semiconductor device with linearized depletion capacitance |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| NL2018115B1 true NL2018115B1 (en) | 2018-07-25 |
Family
ID=57906957
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| NL2018115A NL2018115B1 (en) | 2017-01-03 | 2017-01-03 | Active semiconductor device with linearized depletion capacitance |
Country Status (2)
| Country | Link |
|---|---|
| NL (1) | NL2018115B1 (en) |
| WO (1) | WO2018127514A1 (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0949665A2 (en) * | 1998-04-07 | 1999-10-13 | Nec Corporation | High speed and low parasitic capacitance bipolar transistor and method for fabricating it |
| EP1168452A2 (en) * | 2000-06-30 | 2002-01-02 | Kabushiki Kaisha Toshiba | Semiconductor device having vertical bipolar transistor |
| US20050001233A1 (en) * | 2003-05-28 | 2005-01-06 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US20050184359A1 (en) * | 2004-02-25 | 2005-08-25 | International Business Machines Corporation | Structure and method of self-aligned bipolar transistor having tapered collector |
| US20130134483A1 (en) * | 2011-11-30 | 2013-05-30 | International Business Machines Corporation | Bipolar transistor with a raised collector pedastal for reduced capacitance and a method of forming the transistor |
| US20160133732A1 (en) * | 2013-07-10 | 2016-05-12 | Murata Manufacturing Co., Ltd. | Semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6468878B1 (en) * | 2001-02-27 | 2002-10-22 | Koninklijke Philips Electronics N.V. | SOI LDMOS structure with improved switching characteristics |
| US9432038B1 (en) * | 2015-02-27 | 2016-08-30 | Broadcom Corporation | Digital-to-analog converter using nonlinear capacitance compensation |
-
2017
- 2017-01-03 NL NL2018115A patent/NL2018115B1/en not_active IP Right Cessation
-
2018
- 2018-01-03 WO PCT/EP2018/050136 patent/WO2018127514A1/en not_active Ceased
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0949665A2 (en) * | 1998-04-07 | 1999-10-13 | Nec Corporation | High speed and low parasitic capacitance bipolar transistor and method for fabricating it |
| EP1168452A2 (en) * | 2000-06-30 | 2002-01-02 | Kabushiki Kaisha Toshiba | Semiconductor device having vertical bipolar transistor |
| US20050001233A1 (en) * | 2003-05-28 | 2005-01-06 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US20050184359A1 (en) * | 2004-02-25 | 2005-08-25 | International Business Machines Corporation | Structure and method of self-aligned bipolar transistor having tapered collector |
| US20130134483A1 (en) * | 2011-11-30 | 2013-05-30 | International Business Machines Corporation | Bipolar transistor with a raised collector pedastal for reduced capacitance and a method of forming the transistor |
| US20160133732A1 (en) * | 2013-07-10 | 2016-05-12 | Murata Manufacturing Co., Ltd. | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2018127514A1 (en) | 2018-07-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112543005B (en) | Amplitude modulation to phase modulation compensation circuit, radio frequency power amplifier and equipment | |
| JP4206589B2 (en) | Distributed amplifier | |
| CN101919158B (en) | microwave power amplifier | |
| US20130257545A1 (en) | Power amplifier including variable capacitor circuit | |
| US8493154B1 (en) | Linearity enhancement on cascode gain block amplifier | |
| KR20050084630A (en) | Improved rf transistor amplifier linearity using suppressed third order transconductance | |
| US20140225672A1 (en) | Input match network with rf bypass path | |
| US9276529B1 (en) | High performance GaN operational amplifier with wide bandwidth and high dynamic range | |
| Park et al. | A quad-band CMOS linear power amplifier for EDGE applications using an anti-phase method to enhance its linearity | |
| US10516370B2 (en) | Predistorter for compensating linearity of an amplifier | |
| CN111262534A (en) | Self-adaptive bias circuit for power amplifier chip | |
| KR20200038181A (en) | Power amplifier circuit | |
| WO2024141091A1 (en) | Power amplifier and electronic device | |
| US11070176B2 (en) | Amplifier linearization and related apparatus thereof | |
| Quay et al. | Dual-gate GaN MMICs for MM-wave operation | |
| CN109818580B (en) | Power amplifier and compound semiconductor device | |
| NL2018115B1 (en) | Active semiconductor device with linearized depletion capacitance | |
| CN112214061B (en) | Bias circuit | |
| US9356564B1 (en) | Broadband linear amplifier architecture by combining two distributed amplifiers | |
| JP2021090168A (en) | Power amplifier circuit | |
| KR101891619B1 (en) | Linearizing Bias Circuit for GaN MMIC Amplifier | |
| Kim et al. | A low-power highly linear cascoded multiple-gated transistor CMOS RF amplifier with 10 dB IP3 improvement (Revised) | |
| CN213243931U (en) | Broadband amplifier | |
| JP2001077637A (en) | Pre-distortion circuit | |
| Uchida et al. | 5-GHz band linear CMOS power amplifier IC with a novel integrated linearizer for WLAN applications |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM | Lapsed because of non-payment of the annual fee |
Effective date: 20200201 |