WO2024141091A1 - Power amplifier and electronic device - Google Patents

Abstract

Provided in the present application are a power amplifier and an electronic device. The power amplifier at least comprises: an amplification circuit, a bias circuit, a first resistor and a bypass circuit, wherein the amplification circuit is used for amplifying an input first radio frequency signal and outputting a second radio frequency signal after amplification; the bias circuit is used for providing a bias current for the amplification circuit; a first end of the first resistor is connected to an output end of the bias circuit, and a second end of the first resistor is connected to an input end of the amplification circuit; and the bypass circuit is connected between the bias circuit and the amplification circuit and is used for bypassing the first resistor, such that the input first radio frequency signal is input into the bias circuit through the bypass circuit and/or is input into the ground through the bypass circuit.

Description

Power amplifiers and electronic equipment

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to the Chinese patent application filed with the China Patent Office on December 31, 2022, with application number 202211737604.5 and application name “Power Amplifier and Electronic Device”, the entire contents of which are incorporated by reference in this application.

Technical Field

The present application relates to the field of electronic technology, and more particularly to a power amplifier and an electronic device.

Background technique

In existing power amplifiers, amplitude modulation-amplitude modulation (AM-AM) distortion and amplitude modulation-phase modulation (AM-PM) distortion can be used to characterize the output power after amplification of the front-end power amplifier and the adjacent channel leakage ratio (ACLR) performance. The resistance of the feedback resistor in the existing power amplifier is a fixed resistance. Therefore, when the input power increases, the gain of the power amplifier, such as AM-AM and AM-PM, will decrease and be compressed. The unstable gain leads to the nonlinear distortion of the power amplifier.

Summary of the invention

The present application provides a power amplifier and an electronic device.

According to a first aspect of the present application, a power amplifier is provided, the power amplifier comprising at least: an amplification circuit, a bias circuit, a first resistor and a bypass circuit;

The amplifier circuit is used to amplify the input first radio frequency signal and output the amplified second radio frequency signal;

The bias circuit is used to provide a bias current to the amplifier circuit;

The first end of the first resistor is connected to the output end of the bias circuit, and the second end is connected to the input end of the amplifier circuit;

The bypass circuit is connected between the bias circuit and the amplifier circuit, and is used to bypass the first resistor, so that the input first RF signal is input to the bias circuit through the bypass circuit and/or input to the ground through the bypass circuit.

In some embodiments, the bypass circuit includes: a first capacitor and/or a second capacitor; wherein,

The first end of the first capacitor is connected to the first end of the first resistor, and the second end of the first capacitor is connected to the input end of the amplifier circuit; wherein the first capacitor is used to allow the input first RF signal to be input to the bias circuit through the first capacitor;

and / or,

The first end of the second capacitor is connected to the first end of the first resistor. The two ends are grounded; wherein the second capacitor is used to allow the input first RF signal to be input to the ground through the second capacitor.

In some embodiments, the amplifier circuit includes: a first transistor;

The first end of the first transistor is connected to the second end of the first resistor; and/or the first end of the first transistor is connected to the second end of the first capacitor;

The second terminal of the first transistor is grounded;

The first transistor is used for amplifying the first radio frequency signal input to the first terminal based on the bias current input to the first terminal to obtain the second radio frequency signal to be outputted via the third terminal.

In some embodiments, the first resistor is used to adjust the bias current within a predetermined range when the temperature of the first transistor increases or decreases.

In some embodiments, the capacitance of the first capacitor and/or the second capacitor is adjustable, and is used to adjust the capacitance thereof to match the first RF signal of different frequency bands of the amplifying circuit.

In some embodiments, the power amplifier is a multi-stage power amplifier, and the power amplifier includes the 1st to nth amplifying circuits; wherein n is a positive integer, and the bypass circuit is connected to at least the last stage amplifying circuit.

In some embodiments, there are multiple bypass circuits, and the bypass circuits are used to connect the corresponding bias circuits and amplifier circuits respectively.

In some embodiments, both ends of the bypass circuit have switching devices; wherein the switching device is used to switch to one of the first-stage amplifier circuits and a bias circuit corresponding to the one of the first-stage amplifier circuits.

In some embodiments, the first transistor is an N-type Metal-Oxide-Semiconductor Field Effect Transistor (MOS); the first end of the first transistor is a gate; the second end of the first transistor is a source; the third end of the first transistor is a drain;

or,

The first transistor is a P-type MOS tube; the first end of the first transistor is a gate; the second end of the first transistor is a drain; and the third end of the first transistor is a source;

or,

The first transistor is a bipolar junction transistor (BJT); the first end of the first transistor is a base; the second end of the first transistor is an emitter; and the third end of the first transistor is a collector;

or,

The first transistor is an insulated gate bipolar transistor (IGBT); the first end of the first transistor is a gate; the second end of the first transistor is an emitter; and the third end of the first transistor is a collector.

According to a second aspect of the present application, an electronic device is provided, comprising: any power amplifier provided by the aforementioned first party.

The technical solution provided by the embodiment of the present application may have the following beneficial effects: the power amplifier at least includes: an amplifier circuit, a bias circuit, a first resistor and a bypass circuit; the amplifier circuit is used to amplify the input first radio frequency signal and output the amplified second radio frequency signal; the bias circuit is used to provide a bias current to the amplifier circuit; the first end of the first resistor is connected to the bias current The first end is connected to the output end of the circuit, and the second end is connected to the input end of the amplifier circuit; the bypass circuit is connected between the bias circuit and the amplifier circuit, and is used to bypass the first resistor, so that the input first radio frequency signal is input to the bias circuit through the bypass circuit and/or input to the ground through the bypass circuit.

In this way, the bypass circuit is connected between the bias circuit and the amplifier circuit. If the bypass circuit is used to input the input first RF signal to the bias circuit through the bypass circuit, the first resistor can be bypassed to reduce the loss caused by the first RF signal being input to the bias circuit through the first resistor, thereby improving the linearity of the amplifier circuit; if the bypass circuit is used to input the input first RF signal to the ground through the bypass circuit, the linearity of the amplifier circuit can be reversely adjusted according to the predetermined scenario requirements to meet the needs of different scenarios and enhance the user experience.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a circuit diagram of a conventional power amplifier;

FIG2 is a schematic diagram of a structure of a power amplifier according to an exemplary embodiment of the present application;

FIG3 is a second structural schematic diagram of a power amplifier shown in an exemplary embodiment of the present application;

FIG4 is a structural schematic diagram 1 of a bias circuit according to an exemplary embodiment of the present application;

FIG. 5 is a second structural schematic diagram of a bias circuit according to an exemplary embodiment of the present application.

Detailed ways

Here, exemplary embodiments will be described in detail, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the embodiments of the present application. Instead, they are only examples of devices and methods consistent with some aspects of the embodiments of the present application as detailed in the attached application documents.

The circuit structure of the existing power amplifier is shown in Figure 1, including transistor E1, capacitor C1, feedback resistor R1, transistor E3 and transistor E4 and current source Vbat, RF signal input terminal Rfin, RF signal output terminal Rfout, etc. The bias circuit composed of transistor E1, capacitor C1, transistor E3 and transistor E4 and current source provides DC bias current to power tube E2; transistor E3 and transistor E4 are used to provide a stable bias voltage for E1; transistor E2 is used to amplify the input RF signal. When the input RF signal increases, the RF signal input to transistor E1 through R1 also increases, but when the RF signal is input to transistor E1 through feedback resistor R1, unnecessary loss will be generated, thereby reducing the effect of adjusting the linearity of power tube E2, and the gain will decrease.

The embodiment of the present application provides a power amplifier 10, as shown in FIG2, the power amplifier 10 at least includes: an amplifying circuit 200, a bias circuit 100, a first resistor 301 and a bypass circuit 300;

The amplifier circuit 200 is used to amplify the input first radio frequency signal and output the amplified second radio frequency signal; the amplifier circuit 200 includes a first transistor 201;

The bias circuit 100 is used to provide a bias current to the amplifier circuit 200;

The first end of the first resistor 301 is connected to the output end of the bias circuit 100 , and the second end is connected to the input end of the amplifier circuit 200 ;

The bypass circuit 300 is connected between the bias circuit 100 and the amplifier circuit 200 and is used to bypass the first resistor 301 so that the input first RF signal is input to the bias circuit 100 through the bypass circuit 300 and/or input to the ground through the bypass circuit 300.

Here, the bias circuit 100 may be any circuit for providing a bias current and a bias signal to the amplifier circuit 200 .

Here, the amplifier circuit 200 may be any circuit for amplifying an input radio frequency signal.

The first transistor 201 , the second transistor, the third transistor and the fourth transistor mentioned in the embodiment of the present application may be a triode BJT, a MOS transistor or an IGBT transistor.

Here, the BJT tube includes three pins: emitter, collector and base.

Here, MOS tubes are divided into P-type MOS tubes and N-type MOS tubes, namely PMOS tubes and NMOS tubes. MOS tubes include three pins: G pole (gate) - gate, S pole (source) - source and D pole (drain) - drain.

Here, the IGBT tube includes three pins: gate, collector and emitter.

In some embodiments, the first transistor 201, the second transistor, the third transistor and the fourth transistor are all N-type MOS transistors; the first end of the first transistor 201, the first end of the second transistor, the first end of the third transistor and the first end of the fourth transistor are gates; the second end of the first transistor 201, the second end of the second transistor, the second end of the third transistor and the second end of the fourth transistor are sources; the third end of the first transistor 201, the third end of the second transistor, the third end of the third transistor and the third end of the fourth transistor are drains;

or,

The first transistor 201, the second transistor, the third transistor and the fourth transistor are all P-type MOS transistors; the first end of the first transistor 201, the first end of the second transistor, the first end of the third transistor and the first end of the fourth transistor are gates; the second end of the first transistor 201, the second end of the second transistor, the second end of the third transistor and the second end of the fourth transistor are drains; the third end of the first transistor 201, the third end of the second transistor, the third end of the third transistor and the third end of the fourth transistor are sources;

or,

The first transistor 201, the second transistor, the third transistor and the fourth transistor are all BJT transistors; the first end of the first transistor 201, the first end of the second transistor, the first end of the third transistor and the first end of the fourth transistor are bases; the second end of the first transistor 201, the second end of the second transistor, the second end of the third transistor and the second end of the fourth transistor are emitters; the third end of the first transistor 201, the third end of the second transistor, the third end of the third transistor and the third end of the fourth transistor are collectors;

or,

The first transistor 201, the second transistor, the third transistor and the fourth transistor are all IGBT tubes; the first end of the first transistor 201, the first end of the second transistor, the first end of the third transistor and the first end of the fourth transistor are gates; the second end of the first transistor 201, the second end of the second transistor, the second end of the third transistor and the second end of the fourth transistor are emitters; the third end of the first transistor 201, the second end of the second transistor, the second end of the third transistor and the second end of the fourth transistor are emitters; The third end of the third transistor, the third end of the fourth transistor and the third end of the fourth transistor are collectors.

Here, the first resistor 301 may be a fixed resistor or a variable resistor.

In one embodiment, the first resistor 301 may be one or more. At least one involved in the embodiments of the present application may be one or more; and a plurality may be two or more.

Exemplarily, the first resistor 301 may be a plurality of fixed resistors connected in parallel, and each resistor is connected in series with at least one switching device.

In the embodiment of the present application, the structure of the first resistor 301 is not limited to the above embodiment, and any series or parallel structure that implements the first resistor 301 is within the scope of the present application.

In one embodiment, as shown in FIG. 3 , the first resistor 301 is R1 , the first transistor 201 is E1 , and the fourth transistor is E4 ; the output end of the bias circuit 100 is the emitter of the fourth transistor E4 , and the input end of the amplifier circuit 200 is the base of E1 .

The first end of the first resistor 301 is connected to the output end of the bias circuit 100, and the second end is connected to the input end of the amplifier circuit 200, including:

A first end of the first resistor 301 is connected to the emitter of the second transistor, and a second end of the first resistor 301 is connected to the base of the first transistor 201 .

In some embodiments, the first resistor 301 is used to adjust the bias current within a predetermined range when the temperature of the first transistor 201 increases or decreases.

In some embodiments, the first resistor 301 is used to adjust the bias current within a predetermined range when the temperature of the first transistor 201 increases or decreases, including:

The first resistor 301 is used to adjust the current at the first end of the second transistor to be within a first predetermined range when the temperature of the first transistor 201 and/or the second transistor increases or decreases.

Here, the first predetermined range may be determined by a user or a designer based on personal experience, or may be determined based on a predetermined algorithm and/or model, or may be determined based on historical data.

Exemplarily, if the power amplifier in the above embodiment is applied to a mobile phone, the first terminal current of the first transistor 201 can be less than or equal to 3 milliamperes (mA) within the first predetermined range.

In one embodiment, as shown in FIG. 3 , the first resistor 301 is R1 , the first transistor 201 is E1 , and the fourth transistor is E4 .

The temperature of the first transistor E1 increases, thereby increasing the base current of the first transistor E1. Thus, the first resistor R1 reduces the influence of temperature on the bias current, maintains the stability of the bias current, and forms temperature compensation.

In this way, when the temperature of the first transistor 201 and/or the fourth transistor changes, the first terminal current (i.e., bias current) input to the first transistor 201 can be kept stable through the first resistor 301, reducing the influence of temperature on the bias current, thereby improving the performance of the first transistor 201 (i.e., power amplifier) in amplifying RF signals.

In some embodiments, the bypass circuit 200 is connected between the bias circuit 100 and the amplifying circuit 200 to input the input first RF signal to the bias circuit 100 through the bypass circuit 200 and/or to the ground through the bypass circuit 200 .

Thus, the bypass circuit 200 is connected between the bias circuit 100 and the amplifier circuit 200. If the bypass circuit 200 is used to input the input first RF signal to the bias circuit 100 through the bypass circuit 200, the first resistor 301 can be bypassed to reduce the first RF signal input to the bias circuit 100 through the first resistor 301. The loss caused by this can improve the linearity of the amplifier circuit 200; if the bypass circuit 200 is used to input the input first RF signal to the ground through the bypass circuit 200, the linearity of the amplifier circuit 200 can be reversely adjusted according to the requirements of the predetermined scene to meet the needs of different scenes and enhance the user experience.

In some embodiments, the bypass circuit 200 includes: a first capacitor and/or a second capacitor; wherein,

The first end of the first capacitor is connected to the first end of the first resistor 301, and the second end of the first capacitor is connected to the input end of the amplifier circuit 200; wherein the first capacitor is used to allow the input first RF signal to be input to the bias circuit 100 through the first capacitor;

and / or,

The first end of the second capacitor is connected to the first end of the first resistor 301, and the second end of the second capacitor is grounded; wherein the second capacitor is used to allow the input first RF signal to be input to the ground through the second capacitor.

In one embodiment, as shown in FIG3 , the first capacitor is C1, the second capacitor is C2, the first resistor is R1, the first transistor 201 is E1, the second transistor is E2, the input end of the amplifier circuit 200 is the base of the first transistor E1, and the output end of the bias circuit 100 is the emitter of the fourth transistor E4. The first capacitor C1 is used to allow the input first RF signal to be input to the second transistor E2 via the first capacitor C1; and/or, the second capacitor C2 is used to allow the input first RF signal to be input to the ground via the second capacitor C2.

In some embodiments, the capacitance of the first capacitor and/or the second capacitor is adjustable, and is used to adjust the capacitance thereof to match the first RF signal of different frequency bands of the amplifying circuit 200 .

Exemplarily, the predetermined frequency bands include: frequency band A, frequency band B, frequency band C, and frequency band D; wherein frequency band D is greater than frequency band C, frequency band C is greater than frequency band B, and frequency band B is greater than frequency band A. When the first capacitor adjusts its capacitance to a first threshold value, it matches the first RF signal of frequency band A of the amplifier circuit 200; when the first capacitor adjusts its capacitance to a second threshold value and the second capacitor adjusts its capacitance to a third threshold value, it matches the first RF signal of frequency band B of the amplifier circuit 200; when the first capacitor adjusts its capacitance to a second threshold value and the second capacitor adjusts its capacitance to a fourth threshold value, it matches the first RF signal of frequency band C of the amplifier circuit 200; when the second capacitor adjusts its capacitance to a fifth threshold value, it matches the first RF signal of frequency band D of the amplifier circuit 200.

In this way, the first capacitor is used to input the first RF signal to the bias circuit 100 through the first capacitor instead of the first resistor 301, thereby reducing the loss of the first RF signal input to the second transistor due to the first RF signal input through the first resistor 301, thereby increasing the first RF signal input to the bias circuit 100, ensuring the gain of the amplifier circuit 200 and thus improving the linearity of the amplifier circuit 200. The second capacitor is used to input the first RF signal to the ground through the second capacitor, reducing the first RF signal input to the bias circuit 100 and thus reversely adjusting the gain of the amplifier circuit 200. According to the combination of the first capacitor and the second capacitor, the gain and linearity of the amplifier circuit 200 can be adjusted to a predetermined value, ensuring the accuracy of the gain and linearity of the amplifier circuit 200 to meet the needs of different scenarios; and the input and output of the power amplifier tube of the power amplifier are in a linear range, reducing the nonlinear distortion of the power amplifier.

In some embodiments, the amplifier circuit 200 includes: a first transistor 201;

The first end of the first transistor 201 is connected to the second end of the first resistor 301; and/or the first end of the first transistor 201 is connected to the second end of the first capacitor;

The second terminal of the first transistor 201 is grounded;

The first transistor 201 is used for amplifying the first radio frequency signal input to the first end based on the bias current input to the first end to obtain the second radio frequency signal to be outputted through the third end.

In some embodiments, the first transistor 201 is a power amplifier tube, which is used to amplify a first radio frequency signal input to the first terminal based on a bias current input to the first terminal to obtain a second radio frequency signal to be outputted via a third terminal.

In one embodiment, as shown in FIG3 , the first transistor E1 is a power amplifier tube, and the first transistor E1 is used to amplify the first RF signal input to the base based on the base current of the input base to obtain a second RF signal output through the collector. The base current input to the base of the first transistor E1 is a bias current, and the bias current is used to provide a DC operating point for each level of amplifiers, so that the positive and negative half-waves of the RF signal input to the first transistor E1 are uniformly amplified to prevent distortion.

In some embodiments, the amplifier circuit 200 further includes: a radio frequency signal input terminal, a third capacitor, and a radio frequency signal output terminal; wherein,

The first end of the third capacitor is connected to the RF signal input end and the second end of the first capacitor respectively, and the second end is connected to the first end of the first transistor 201 and the second end of the first resistor 301 respectively; the RF signal output end is connected to the third end of the first transistor 201;

The radio frequency signal input terminal is used to obtain a first radio frequency signal;

The second capacitor is used to feed in and out the first RF signal and isolate the DC current flowing out of the bias circuit 100;

The RF signal output terminal is used to output the second RF signal amplified by the first transistor 201 .

In one embodiment, as shown in FIG3 , the RF signal input terminal is Rfin, the RF signal output terminal is Rfout, and the third capacitor is a DC blocking capacitor C3; wherein the first end of the third capacitor C3 is respectively connected to the RF signal input terminal Rfin and the second end of the first capacitor C1, and the second end is respectively connected to the base of the first transistor E1 and the second end of the first resistor R1; the RF signal output terminal Rfout is connected to the collector of the first transistor E1;

The radio frequency signal input terminal Rfin is used to obtain a first radio frequency signal;

A second capacitor C2, used for feeding in and out the first RF signal and the DC current flowing out of the isolation bias circuit 100;

The radio frequency signal output terminal Rfout is used to output the second radio frequency signal amplified by the first transistor E1.

In some embodiments, the amplifier circuit 200 further includes: a fourth capacitor; wherein,

The first end of the fourth capacitor is used to be connected to the first power supply, and the second end of the fourth capacitor is grounded; the fourth capacitor is used to output the leaked second RF signal to the ground.

In one embodiment, as shown in FIG3 , the fourth capacitor is C4, and the first power source is Vcc. The first end of the fourth capacitor C4 is respectively used to connect to the collector of the first transistor E1 and the first power source Vcc, and the second end of the fourth capacitor C4 is grounded. The fourth capacitor C4 is used to output the leaked second RF signal to the ground.

In some embodiments, the amplifier circuit 200 further includes: an inductor; wherein,

One end of the inductor is connected to the collector of the first transistor 201, and the other end is connected to the first power source and the first end of the fourth capacitor respectively;

The inductor is used to block the second radio frequency signal.

In some embodiments, the power amplifier is a multi-stage power amplifier, and the power amplifier includes the first to nth amplifying circuits 200; wherein n is a positive integer, and the bypass circuit 200 is connected to at least the last stage of the amplifying circuit 200.

In some embodiments, there are multiple bypass circuits 200, and the bypass circuits 200 are used to connect the corresponding bias circuits 100 and the amplifier circuits 200 respectively.

Exemplarily, n is 3, and the third bypass circuit 200 is used to connect the corresponding third bias circuit 100 and the third amplifier circuit 200 respectively.

In some embodiments, both ends of the bypass circuit 200 have switch devices; wherein the switch device is used to switch to one of the first-stage amplifier circuits 200 and the bias circuit 100 corresponding to one of the first-stage amplifier circuits 200.

In this way, the amplifier circuit 200 can amplify the RF signal input to the amplifier circuit 200 to a predetermined multiple of power and output it; and when the power amplifier is a multi-stage power amplifier, the RF signal input to the power amplifier can be further amplified.

It should be noted that the first power supply and the second power supply in the embodiment of the present application may be the same power supply or different power supplies.

In some embodiments, the bias circuit 100 includes: a second transistor and a current mirror circuit; wherein,

The current mirror circuit has a first output terminal and a second output terminal, the first output terminal is connected to the first terminal of the second transistor, and the second output terminal is used to connect the first terminal of the first transistor 201 in the amplifier circuit 200, so that the first current of the first transistor 201 and the second current of the second transistor are in a first preset ratio;

A second terminal of the first transistor 201 is grounded, and a third terminal of the first transistor 201 is connected to a second power source.

In some embodiments, the current mirror circuit includes: a third transistor and a fourth transistor; wherein,

The first end of the third transistor is connected to the first end of the fourth transistor, the second end of the third transistor is connected to the first output end of the current mirror circuit, the third end of the third transistor is connected to the first end of the third transistor, and is connected to the second power supply;

The second end of the fourth transistor is connected to the second output end of the current mirror circuit, and the third end of the fourth transistor is connected to the second power supply.

In one embodiment, the first output terminal of the current mirror circuit may be the second terminal of the third transistor; and the second output terminal of the current mirror circuit may be the second terminal of the fourth transistor.

In one embodiment, as shown in FIG4 , the first transistor E1, the second transistor E2, the third transistor E3 and the fourth transistor E4 are all BJT tubes. Among them, the base of the second transistor E2 is connected to the emitter of the third transistor E3, the collector of the second transistor E2 is respectively connected to the base of the third transistor E3, the collector of the third transistor E3, the base of the fourth transistor E4 and the second power supply Vbat, and the emitter of the second transistor E2 is grounded; the emitter of the third transistor E3 is the first output end of the current mirror circuit, the collector of the third transistor E3 is connected to the second power supply Vbat, and the base of the third transistor E3 is connected to the base of the fourth transistor E4; the emitter of the fourth transistor E4 is the second output end of the current mirror circuit, the collector of the fourth transistor E4 is connected to the second power supply Vbat, and the emitter of the fourth transistor E4 is connected to the base of the first transistor E1 of the amplifier circuit 200.

In one embodiment, the first current of the first transistor 201 and the second current of the second transistor are in a first preset ratio, including:

The ratio of the first current of the first transistor 201 to the second current of the second transistor satisfies a first preset ratio.

In some embodiments, the first transistor 201 and the second transistor are both BJT transistors. The first current of the first transistor 201 is the collector current of the first transistor 201, which is equal to the static current of the first transistor 201; the second current of the second transistor is the collector current of the second transistor, which is approximately equal to the reference current.

In one embodiment, if the reference current remains unchanged, the larger the size of the fourth transistor and the smaller the size of the third transistor, the larger the static current of the first transistor 201; if the size of the third transistor and the size of the fourth transistor remain unchanged, the static current of the first transistor 201 is positively correlated with the reference current.

In some embodiments, the first-end current of the input second transistor and the first-end current of the input third transistor are in a second preset ratio; the first-end current of the input first transistor 201 and the first-end current of the input fourth transistor are in a second preset ratio; wherein, the first-end current of the input second transistor is the output current of the first output terminal of the current mirror circuit, and the first-end current of the input first transistor 201 is the output current of the second output terminal of the current mirror circuit.

In one embodiment, the first terminal current of the input second transistor and the first terminal current of the input third transistor are in a second preset ratio, including:

A ratio of a first-end current input to the second transistor to a first-segment current input to the third transistor satisfies a second preset ratio.

In one embodiment, as shown in FIG4 , the emitter current of the third transistor E3 is input to the base of the second transistor E2 ; the emitter current of the third transistor E3 is the output current of the first output terminal of the current mirror circuit;

The ratio of the first terminal current input to the second transistor to the first segment current input to the third transistor satisfies a second preset ratio, including:

A ratio of a base current input to the second transistor to a base current input to the third transistor satisfies a second preset ratio.

In one embodiment, the first terminal current of the input first transistor 201 and the first terminal current of the input fourth transistor are in a second preset ratio, including:

The ratio of the current input to the first terminal of the first transistor 201 to the current input to the first terminal of the fourth transistor satisfies the second preset ratio.

In one embodiment, as shown in FIG4 , the emitter current of the fourth transistor E4 is input to the base of the first transistor E1; the emitter current of the fourth transistor E4 is the output current and bias current of the second output terminal of the current mirror circuit; the collector current of the first transistor E1 is the static current of the first transistor E1;

The ratio of the current at the first end of the input first transistor to the current at the first end of the input fourth transistor satisfies a second preset ratio, including:

A ratio of a base current input to the first transistor to a base current input to the fourth transistor satisfies a second preset ratio.

In some embodiments, the current at the first terminal of the third transistor is changed by changing the size of the third transistor; and/or the current at the first terminal of the fourth transistor is changed by changing the size of the fourth transistor.

Exemplarily, the base current of the base of the first transistor 201 is changed by changing the area of the collector region and/or the base region of the third transistor; and/or, the base current of the base of the third transistor is changed by changing the area of the collector region and/or the base region of the third transistor.

In this way, the current mirror circuit makes the first current of the first transistor 201 and the second current of the second transistor to be in a first preset ratio, so that the ratio of the first current to the second current is not affected by the amplification factor β; and the change in temperature has a greater impact on the transistor amplification factor β, so the first current of the first transistor 201 is not affected by the temperature. In addition, the first current of the first transistor 201 can be adjusted and controlled by the second current, the size of the third transistor in the current mirror circuit, and/or the size of the fourth transistor.

In some embodiments, the bias circuit 100 further includes: a second resistor, one end of the second resistor is connected to the first output end of the current mirror current, and the other end of the second resistor is connected to the first end of the second transistor.

In some embodiments, as shown in FIG5 , the second resistor is R2. One end of the second resistor is connected to the first output end of the current mirror circuit, and the other end is connected to the first end of the second transistor, including:

One end of the second resistor is connected to the second end of the third transistor, and the other end of the second resistor is connected to the first end of the second transistor.

Here, the second resistor is used to adjust the current at the first end of the second transistor to be within a second predetermined range when the temperature of the second transistor and/or the third transistor increases or decreases.

Here, the second predetermined range may be determined by a user or a designer based on personal experience, or may be determined based on a predetermined algorithm and/or model, or may be determined based on historical data.

In one embodiment, as shown in FIG. 5 , the second resistor is R2 , the second transistor is E2 , and the third transistor is E3 .

When the temperature of the second transistor E2 increases, the base current of the second transistor E2 increases, that is, the emitter current of the third transistor E3 increases, and the voltage of the second resistor R2 through which the emitter current of the third transistor E3 flows increases, thereby reducing the base voltage of the second transistor E2, thereby reducing the base current of the second transistor E2; or, when the temperature of the second transistor E2 decreases, the base current of the second transistor E2 decreases, that is, the emitter current of the third transistor E3 decreases, and the voltage of the second resistor R2 through which the emitter current of the third transistor E3 flows decreases, thereby increasing the base voltage of the second transistor E2, thereby increasing the base current of the second transistor E2. In this way, the second resistor R2 reduces the influence of temperature on the base current of the second transistor E2, forming temperature compensation.

Furthermore, the temperature of the third transistor E3 increases, thereby increasing the emitter current of the third transistor E3, and the voltage of the second resistor R2 through which the emitter current of the third transistor E3 flows increases, thereby reducing the emitter voltage of the third transistor E3, thereby reducing the emitter current of the third transistor E3; or, the temperature of the third transistor E3 decreases, thereby reducing the emitter current of the third transistor E3, and the voltage of the second resistor R2 through which the emitter current of the third transistor E3 flows decreases, thereby increasing the emitter voltage of the third transistor E3, thereby increasing the emitter current of the third transistor E3. In this way, the second resistor R2 reduces the influence of temperature on the emitter current of the third transistor E3, thereby forming temperature compensation.

Thus, when the temperature of the second transistor and/or the third transistor changes, the current at the first terminal of the second transistor can be kept stable by the second resistor, reducing the influence of temperature on the current, thereby improving the working performance of the bias circuit 100. By changing the current at the third terminal of the second transistor (reference current), and changing the resistance of the second resistor, the current at the second terminal of the third transistor can be changed, thereby changing the current at the first terminal of the third transistor. In this way, the current at the third terminal of the second transistor can be changed by changing the resistance of the second resistor.

In some embodiments, the output current of the first output terminal of the current mirror circuit is a third current, the output current of the second output terminal is a fourth current, and the third current and the fourth current are in a third preset ratio;

The first resistor 301 and the second resistor are in a fourth preset ratio, and the third preset ratio is inversely proportional to the fourth preset ratio.

In this way, by changing the impedance of the first resistor 301 and the second resistor, the output current of the first output terminal and the output current of the second output terminal of the current mirror circuit can be adjusted, and the operation is simple and convenient.

In some embodiments, the bias circuit 100 further includes: a constant current source;

One end of the constant current source is connected to the second power supply and the third end of the fourth transistor respectively, and the other end is connected to the third end of the second transistor and the first end of the third transistor respectively;

The constant current source is used to provide the second current.

In some embodiments, the current mirror circuit includes: a fifth capacitor;

A first end of the fifth capacitor is connected to the first end of the fourth transistor, and a second end of the fifth capacitor is grounded.

In one embodiment, as shown in FIG3 , the fifth capacitor is C5, the first end of the fifth capacitor C5 is respectively connected to the base of the third transistor E3, the collector of the third transistor E3, and the base of the fourth transistor E4, and the second end of the fifth capacitor C5 is grounded. The fifth capacitor C5 is used to ground the first RF signal input to the fourth transistor E4, to ensure the stability of the voltage Vbe4 of the fourth transistor E4, and thus to improve the linearity of the first transistor E1 of the amplifier circuit 200.

Here, the fourth transistor E4 voltage Vbe4 indicates a voltage between a base and an emitter of the fourth transistor E4.

Exemplarily, when the RF signal input to the fourth transistor E4 increases, the voltage Vbe4 of the fourth transistor E4 decreases; while the fifth capacitor C5 maintains Vbe4 unchanged, the voltage Vbe1 of the first transistor E1 increases, thereby increasing the bias voltage of the first transistor E1, thereby improving the linearity of the first transistor E1.

In this way, the fifth capacitor can ensure the stability of the fourth transistor voltage Vbe4, thereby improving the linearity of the first transistor 201 (power amplifier) in the amplifier circuit 200; and the fifth capacitor cooperates with the first capacitor and/or the second capacitor to adjust the linearity of the first transistor 201 in the amplifier circuit 200 to a predetermined appropriate size to meet the needs of different scenarios, enhance the user experience, and reduce the nonlinear distortion of the power amplifier.

In combination with the above embodiments, the following examples are provided:

As shown in FIG3 , a power amplifier is provided, which includes: a bias circuit 100, an amplifier circuit 200, a first resistor R1 and a bypass circuit 300; wherein the bias circuit 100 includes: a second transistor E2, a second resistor R2, a current mirror circuit, a constant current source Iref and a second power supply Vbat; the current mirror circuit includes: a third transistor E3, a fourth transistor E4, and a fifth capacitor C5; the bypass circuit 300 includes: a first capacitor C1 and a second capacitor C2; the amplifier circuit 200 includes: a first transistor E1, a radio frequency signal input terminal Rfin, a third capacitor C3, a radio frequency signal output terminal Rfout, a fourth capacitor C4, an inductor L1 and a first power supply Vcc.

The base of the first transistor E1 is connected to one end of the first resistor R1 and the second end of the third capacitor C3. The collector is connected to the RF signal output terminal Rfout and the first end of the inductor L1 respectively, and the emitter is grounded.

The base of the second transistor E2 is connected to one end of the second resistor R2, the collector is connected to one end of the constant current source Iref, and the emitter is grounded.

The base of the third transistor E3 is respectively connected to the collector of the third transistor E3, the first end of the fifth capacitor C5, the base of the fourth transistor E4, and one end of the constant current source Iref, and the emitter is connected to the other end of the second resistor R2.

The collector of the fourth transistor E4 is respectively connected to the other end of the constant current source Iref and the first power source Vbat, and the emitter is respectively connected to the other end of the first resistor R1 and the first end of the first capacitor C1.

The first end of the first capacitor C1 is respectively connected to the emitter of the fourth transistor E4, one end of the first resistor R1, and the first end of the second capacitor C2. The second end of the first capacitor C1 is respectively connected to the RF signal input terminal Rfin and the first end of the third capacitor C3.

A second terminal of the second capacitor C2 is grounded.

The second end of the third capacitor C3 is connected to the other end of the first resistor R1 and the base of the first transistor E1 respectively.

A first end of the fourth capacitor C4 is respectively connected to the second end of the inductor L1 and the first power source Vcc, and a second end thereof is grounded.

A second terminal of the fifth capacitor C5 is grounded.

The first capacitor C1 is used to allow the input first RF signal to be input into the bias circuit 100 via the first capacitor C1 to improve the linearity of the first transistor E1 in the amplifier circuit 200 .

The second capacitor C2 is used for inputting the first RF signal to the ground via the second capacitor C2 to reduce the first RF signal input to the bias circuit 100 .

The third capacitor C3 is used for feeding in and out the first radio frequency signal and isolating the direct current flowing out of the first resistor R1.

The fourth capacitor C4 is used to output the leaked second RF signal to ground.

The fifth capacitor C5 is used to allow the first RF signal input to the fourth transistor E4 to be input to the ground, thereby ensuring the stability of the voltage Vbe4 of the fourth transistor E4 and thus improving the linearity of the first transistor E1 of the amplifier circuit 200 .

The first resistor R1 is used for adjusting the base current of the first transistor E1 within a first predetermined range when the temperature of the first transistor E1 and/or the fourth transistor E4 increases or decreases.

The second resistor R2 is used for adjusting the base current of the second transistor E2 within a second predetermined range when the temperature of the second transistor E2 and/or the third transistor E3 increases or decreases.

The inductor L1 is used to block the second radio frequency signal.

In this way, the first capacitor is used to allow the input first RF signal to be input to the bias circuit 200 through the first capacitor instead of through the first resistor 301, thereby reducing the loss of the first RF signal input to the second transistor due to the first RF signal being input through the first resistor 301, thereby increasing the first RF signal input to the bias circuit 200, ensuring the gain of the amplifier circuit 200 and thus improving the linearity of the amplifier circuit 200. The second capacitor is used to allow the input first RF signal to be input to the ground through the second capacitor, reducing the first RF signal input to the bias circuit 200 and thus reversely adjusting the gain of the amplifier circuit 200. According to the combination of the first capacitor and the second capacitor, the gain and linearity of the amplifier circuit 200 can be adjusted to a predetermined size, ensuring that the accuracy of the gain and linearity of the amplifier circuit 200 is improved to meet the needs of different scenarios; and, The input and output of the power amplifier tube of the power amplifier are in the linear range, reducing the nonlinear distortion of the power amplifier.

Furthermore, the connection relationship between the third transistor and the fourth transistor in the current mirror circuit is such that the base current of the first transistor 201 and the base current of the third transistor are in a fourth preset ratio, and the base current of the second transistor and the base current of the fourth transistor are in a fourth preset ratio; thereby making the first current of the first transistor 201 and the second current of the second transistor in the first preset ratio, and further making the ratio of the second current of the second transistor to the first current not affected by the amplification factor β; and the change in temperature has a greater impact on the transistor amplification factor β, so the second current of the second transistor can be made unaffected by the temperature. Furthermore, the second current of the second transistor can be adjusted and controlled by the first current, the first resistor 301, the second resistor, the size of the third transistor in the current mirror circuit, and/or the size of the fourth transistor.

In some embodiments, an electronic device is provided, the electronic device comprising: any bias circuit provided by any of the foregoing embodiments or the power amplifier provided by any of the foregoing embodiments.

In some embodiments, the electronic device may be any mobile terminal or fixed terminal. For example, the electronic device may be a mobile phone, a computer, a server, etc.

It should be noted that, in the embodiments of the present application, "first", "second", "third", "fourth", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

In addition, the technical solutions described in the embodiments of the present application can be combined arbitrarily without conflict.

Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the claims above.

It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims (10)

A power amplifier, the power amplifier comprising at least: an amplification circuit, a bias circuit, a first resistor and a bypass circuit; The amplifier circuit is used to amplify the input first radio frequency signal and output the amplified second radio frequency signal; The bias circuit is used to provide a bias current to the amplifier circuit; The first end of the first resistor is connected to the output end of the bias circuit, and the second end is connected to the input end of the amplifier circuit; The bypass circuit is connected between the bias circuit and the amplifier circuit, and is used to bypass the first resistor, so that the input first RF signal is input to the bias circuit through the bypass circuit and/or input to the ground through the bypass circuit. The power amplifier according to claim 1, wherein the bypass circuit comprises: a first capacitor and/or a second capacitor; wherein: The first end of the first capacitor is connected to the first end of the first resistor, and the second end of the first capacitor is connected to the input end of the amplifier circuit; wherein the first capacitor is used to allow the input first RF signal to be input to the bias circuit through the first capacitor; and / or, The first end of the second capacitor is connected to the first end of the first resistor, and the second end of the second capacitor is grounded; wherein the second capacitor is used to allow the input first RF signal to be input to the ground through the second capacitor. The power amplifier according to claim 1, wherein the amplification circuit comprises: a first transistor; The first end of the first transistor is connected to the second end of the first resistor; and/or the first end of the first transistor is connected to the second end of the first capacitor; The second terminal of the first transistor is grounded; The first transistor is used for amplifying the first radio frequency signal input to the first terminal based on the bias current input to the first terminal to obtain the second radio frequency signal to be outputted via the third terminal. The power amplifier according to claim 3, wherein the first resistor is used to adjust the bias current within a predetermined range when the temperature of the first transistor increases or decreases. The power amplifier according to claim 2, wherein the capacitance of the first capacitor and/or the second capacitor is adjustable, and is used to adjust the capacitance thereof to match the first RF signal of different frequency bands of the amplifying circuit. The power amplifier according to any one of claims 1 to 5, wherein the power amplifier is a multi-stage power amplifier, and the power amplifier comprises the first to nth amplifying circuits; wherein n is a positive integer, and the bypass circuit is connected to at least the last-stage amplifying circuit. The power amplifier according to claim 6, wherein there are multiple bypass circuits, and the bypass circuits are used to connect the corresponding bias circuits and amplifier circuits respectively. The power amplifier according to claim 7, wherein both ends of the bypass circuit have a switch device; wherein the switch device is used to switch to one of the first-stage amplification circuits and one of the first-stage amplification circuits. The bias circuit corresponding to the first stage amplifier circuit. The power amplifier according to claim 3 or 4, wherein: The first transistor is an N-type MOS tube; the first end of the first transistor is a gate; the second end of the first transistor is a source; and the third end of the first transistor is a drain; or, The first transistor is a P-type MOS tube; the first end of the first transistor is a gate; the second end of the first transistor is a drain; and the third end of the first transistor is a source; or, The first transistor is a BJT tube; the first end of the first transistor is a base; the second end of the first transistor is an emitter; and the third end of the first transistor is a collector; or, The first transistor is an IGBT tube; the first end of the first transistor is a gate; the second end of the first transistor is an emitter; and the third end of the first transistor is a collector. An electronic device, comprising: the power amplifier according to any one of claims 1 to 9.