Goodman et al., 2002 - Google Patents
An energy/security scalable encryption processor using an embedded variable voltage DC/DC converterGoodman et al., 2002
View PDF- Document ID
- 16235158252865367199
- Author
- Goodman J
- Dancy A
- Chandrakasan A
- Publication year
- Publication venue
- IEEE Journal of Solid-State Circuits
External Links
Snippet
Security concerns for battery-operated wireless systems require the development of energy- efficient data-encryption techniques that can adapt to the time-varying data rates and quality- of-service requirements inherent in a wireless application. This work describes the design …
- 238000000034 method 0 abstract description 19
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
- G06F7/724—Finite field arithmetic
- G06F7/726—Inversion; Reciprocal calculation; Division of elements of a finite field
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/4806—Computations with complex numbers
- G06F7/4818—Computations with complex numbers using coordinate rotation digital computer [CORDIC]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/68—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using pulse rate multipliers or dividers pulse rate multipliers or dividers per se
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power Management, i.e. event-based initiation of power-saving mode
- G06F1/3234—Action, measure or step performed to reduce power consumption
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/16—Constructional details or arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/02—Digital function generators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication
- H04L9/30—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy
- H04L9/3006—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy underlying computational problems or public-key parameters
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Goodman et al. | An energy/security scalable encryption processor using an embedded variable voltage DC/DC converter | |
| Goodman et al. | An energy-efficient reconfigurable public-key cryptography processor | |
| Wolkerstorfer | Dual-field arithmetic unit for GF (p) and GF (2m) | |
| Chren | One-hot residue coding for low delay-power product CMOS design | |
| Khan et al. | High speed ECC implementation on FPGA over GF (2 m) | |
| Goodman et al. | Low power scalable encryption for wireless systems | |
| Namin et al. | Low-power design for a digit-serial polynomial basis finite field multiplier using factoring technique | |
| Zeghid et al. | Speed/area-efficient ECC processor implementation over GF (2 m) on FPGA via novel algorithm-architecture co-design | |
| Schroeppel et al. | A low-power design for an elliptic curve digital signature chip | |
| Lai et al. | Energy-adaptive dual-field processor for high-performance elliptic curve cryptographic applications | |
| Rebeiro et al. | Revisiting the Itoh-Tsujii inversion algorithm for FPGA platforms | |
| Trichina et al. | Supplemental cryptographic hardware for smart cards | |
| Tian et al. | Efficient software implementation of the SIKE protocol using a new data representation | |
| Muralidharan et al. | Radix-8 booth encoded modulo $2^{n}-1$ multipliers with adaptive delay for high dynamic range residue number system | |
| Meher et al. | A high bit rate serial-serial multiplier with on-the-fly accumulation by asynchronous counters | |
| Wajih et al. | Low power elliptic curve digital signature design for constrained devices | |
| Mathe et al. | Low‐power and low‐hardware bit‐parallel polynomial basis systolic multiplier over GF (2m) for irreducible polynomials | |
| Jung et al. | A reconfigurable coprocessor for finite field multiplication in GF (2n) | |
| Thampi et al. | Montgomery multiplier for faster cryptosystems | |
| Goodman et al. | Design and implementation of a scalable encryption processor with embedded variable DC/DC converter | |
| Renardy et al. | Hardware implementation of montgomery modular multiplication algorithm using iterative architecture | |
| Keller et al. | Elliptic curve cryptography on fpga for low-power applications | |
| Hu et al. | NTRU‐based sensor network security: a low‐power hardware implementation perspective | |
| Jiang et al. | Low-Latency and Area-Efficient Elliptic Curve Point Multiplication Architectures Over Koblitz Curves | |
| Desale et al. | Design of Power Efficient Bit Serial Finite Field GF (2 m) Multiplier |