[go: up one dir, main page]

Kim et al., 2022 - Google Patents

A charge domain p-8t sram compute-in-memory with low-cost dac/adc operation for 4-bit input processing

Kim et al., 2022

View PDF
Document ID
9236797105299475109
Author
Kim J
Lee K
Park J
Publication year
Publication venue
Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design

External Links

Snippet

This paper presents a low cost PMOS-based 8T (P-8T) SRAM Compute-In-Memory (CIM) architecture that efficiently per-forms the multiply-accumulate (MAC) operations between 4- bit input activations and 8-bit weights. First, bit-line (BL) charge-sharing technique is …
Continue reading at arxiv.org (PDF) (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit

Similar Documents

Publication Publication Date Title
Chen et al. CAP-RAM: A charge-domain in-memory computing 6T-SRAM for accurate and precision-programmable CNN inference
Zhang et al. A 177 TOPS/W, capacitor-based in-memory computing SRAM macro with stepwise-charging/discharging DACs and sparsity-optimized bitcells for 4-bit deep convolutional neural networks
Lee et al. A charge-sharing based 8T SRAM in-memory computing for edge DNN acceleration
Ha et al. A 36.2 dB high SNR and PVT/leakage-robust eDRAM computing-in-memory macro with segmented BL and reference cell array
Song et al. A 28 nm 16 kb bit-scalable charge-domain transpose 6T SRAM in-memory computing macro
Cheon et al. A 2941-TOPS/W charge-domain 10T SRAM compute-in-memory for ternary neural network
Choi et al. SRAM-based computing-in-memory macro with fully parallel one-step multibit computation
Chen et al. A 1.87-mm 2 56.9-GOPS accelerator for solving partial differential equations
Lee et al. A 17.5-fJ/bit energy-efficient analog SRAM for mixed-signal processing
Zhang et al. Ssm-cim: An efficient cim macro featuring single-step multi-bit mac computation for cnn edge inference
Xiao et al. A 28nm 32Kb SRAM computing-in-memory macro with hierarchical capacity attenuator and input sparsity-optimized ADC for 4b MAC operation
Zhan et al. A 28-nm 18.7 TOPS/mm² 89.4-to-234.6 TOPS/W 8b Single-Finger eDRAM Compute-in-Memory Macro With Bit-Wise Sparsity Aware and Kernel-Wise Weight Update/Refresh
Chen et al. DCT-RAM: A driver-free process-in-memory 8T SRAM macro with multi-bit charge-domain computation and time-domain quantization
Kim et al. A charge domain p-8t sram compute-in-memory with low-cost dac/adc operation for 4-bit input processing
Chen et al. PICO-RAM: A PVT-insensitive analog compute-in-memory SRAM macro with in situ multi-bit charge computing and 6T thin-cell-compatible layout
Lee et al. Low-cost 7t-sram compute-in-memory design based on bit-line charge-sharing based analog-to-digital conversion
Kushwaha et al. Multi-bit compute-in memory architecture using a C-2C ladder network
Chen et al. MC 2-RAM: An in-8T-SRAM computing macro featuring multi-bit charge-domain computing and ADC-reduction weight encoding
Qiao et al. A 16.38 TOPS and 4.55 POPS/W SRAM computing-in-memory macro for signed operands computation and batch normalization implementation
Zang et al. 282-to-607 TOPS/W, 7T-SRAM based CiM with reconfigurable column SAR ADC for neural network processing
Zhang et al. A charge-domain compute-in-memory macro with cell-embedded DA conversion and two-stage AD conversion for bit-scalable MAC operation
Zhang et al. In-memory multibit multiplication based on bitline shifting
Kim et al. A charge-domain 10T SRAM based in-memory-computing macro for low energy and highly accurate DNN inference
Lim et al. AA-ResNet: Energy efficient all-analog ResNet accelerator
Xiao et al. A 28nm 8Kb Reconfigurable SRAM Computing-In-Memory Macro With Input-Sparsity Optimized DTC for Multi-Mode MAC Operations