Cheon et al., 2023 - Google Patents
A 2941-TOPS/W charge-domain 10T SRAM compute-in-memory for ternary neural networkCheon et al., 2023
- Document ID
- 8573873773740605424
- Author
- Cheon S
- Lee K
- Park J
- Publication year
- Publication venue
- IEEE Transactions on Circuits and Systems I: Regular Papers
External Links
Snippet
In this paper, we present a 10T SRAM compute-in memory (CiM) macro to process the multiplication-accumulation (MAC) operations between ternary-inputs and binary-weights. In the proposed 10T SRAM bitcell, the charge-domain analog computations are employed to …
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computer systems based on biological models
- G06N3/02—Computer systems based on biological models using neural network models
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
- G06N3/0635—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means using analogue means
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/565—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using capacitive charge storage elements
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Yu et al. | A 65-nm 8T SRAM compute-in-memory macro with column ADCs for processing neural networks | |
| Guo et al. | A 28-nm 64-kb 31.6-TFLOPS/W digital-domain floating-point-computing-unit and double-bit 6T-SRAM computing-in-memory macro for floating-point CNNs | |
| Jiang et al. | C3SRAM: An in-memory-computing SRAM macro based on robust capacitive coupling computing mechanism | |
| Yu et al. | A logic-compatible eDRAM compute-in-memory with embedded ADCs for processing neural networks | |
| Kang et al. | A multi-functional in-memory inference processor using a standard 6T SRAM array | |
| Cheon et al. | A 2941-TOPS/W charge-domain 10T SRAM compute-in-memory for ternary neural network | |
| Lee et al. | A charge-domain scalable-weight in-memory computing macro with dual-SRAM architecture for precision-scalable DNN accelerators | |
| Valavi et al. | A 64-tile 2.4-Mb in-memory-computing CNN accelerator employing charge-domain compute | |
| Giacomin et al. | A robust digital RRAM-based convolutional block for low-power image processing and learning applications | |
| Su et al. | Two-way transpose multibit 6T SRAM computing-in-memory macro for inference-training AI edge chips | |
| Kang et al. | An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks | |
| Ha et al. | A 36.2 dB high SNR and PVT/leakage-robust eDRAM computing-in-memory macro with segmented BL and reference cell array | |
| Mu et al. | SRAM-based in-memory computing macro featuring voltage-mode accumulator and row-by-row ADC for processing neural networks | |
| Song et al. | A 28 nm 16 kb bit-scalable charge-domain transpose 6T SRAM in-memory computing macro | |
| Sharma et al. | A reconfigurable 16Kb AND8T SRAM macro with improved linearity for multibit compute-in memory of artificial intelligence edge devices | |
| Lee et al. | A charge-sharing based 8T SRAM in-memory computing for edge DNN acceleration | |
| Wu et al. | An 8b-precision 6T SRAM computing-in-memory macro using time-domain incremental accumulation for AI edge chips | |
| Song et al. | A 4-bit calibration-free computing-in-memory macro with 3T1C current-programed dynamic-cascode multi-level-cell eDRAM | |
| Nguyen et al. | STT-BSNN: An in-memory deep binary spiking neural network based on STT-MRAM | |
| Agrawal et al. | CASH-RAM: Enabling in-memory computations for edge inference using charge accumulation and sharing in standard 8T-SRAM arrays | |
| Zhang et al. | Ssm-cim: An efficient cim macro featuring single-step multi-bit mac computation for cnn edge inference | |
| Lee et al. | A 28-nm 50.1-TOPS/W P-8T SRAM compute-in-memory macro design with BL charge-sharing-based in-SRAM DAC/ADC operations | |
| Sehgal et al. | A bit-serial, compute-in-SRAM design featuring hybrid-integrating ADCs and input dependent binary scaled precharge eliminating DACs for energy-efficient DNN inference | |
| Chen et al. | PICO-RAM: A PVT-insensitive analog compute-in-memory SRAM macro with in situ multi-bit charge computing and 6T thin-cell-compatible layout | |
| Liu et al. | An energy-efficient mixed-bit CNN accelerator with column parallel readout for ReRAM-based in-memory computing |