OpenROAD's unified application implementing an RTL-to-GDS Flow

ABC: System for Sequential Logic Synthesis and Formal Verification

Yosys Open SYnthesis Suite

OpenSTA engine

Plugins for Yosys developed as part of the SymbiFlow project.

Create a pull request review based on clang-tidy warnings

KLayout Main Sources

https://caravel-user-project.readthedocs.io

Random Numbers

PDK installer for open-source EDA tools and toolchains. Distributed with a setup for the Google/SkyWater 130nm process.

7 track standard cells for GF180MCU provided by GlobalFoundries.

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format …

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

ANTLR (ANother Tool for Language Recognition) is a powerful parser generator for reading, processing, executing, or translating structured text or binary files.

Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)

bazel build rules to use boost in bazel projects

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

SWIG is a software development tool that connects programs written in C and C++ with a variety of high-level programming languages.

XLS: Accelerated HW Synthesis

This is the XDM netlist converter, used to convert PSPICE and HSPICE netists into Xyce format.

Constraint values for specifying platforms and toolchains