| A customized graph neural network model for guiding analog IC placement Y Li, Y Lin, M Madhusudan, A Sharma, W Xu, SS Sapatnekar, R Harjani, ... Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020 | 104 | 2020 |
| ALIGN: A system for automating analog layout T Dhar, K Kunal, Y Li, M Madhusudan, J Poojary, AK Sharma, W Xu, ... IEEE Design & Test 38 (2), 8-18, 2020 | 84 | 2020 |
| Exploring a machine learning approach to performance driven analog IC placement Y Li, Y Lin, M Madhusudan, A Sharma, W Xu, S Sapatnekar, R Harjani, ... 2020 IEEE computer society annual symposium on VLSI (ISVLSI), 24-29, 2020 | 42 | 2020 |
| A circuit attention network-based actor-critic learning approach to robust analog transistor sizing Y Li, Y Lin, M Madhusudan, A Sharma, S Sapatnekar, R Harjani, J Hu 2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD), 1-6, 2021 | 29 | 2021 |
| From specification to silicon: Towards analog/mixed-signal design automation using surrogate NN models with transfer learning J Liu, S Su, M Madhusudan, M Hassanpourghadi, S Saunders, Q Zhang, ... 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2021 | 25 | 2021 |
| Are analytical techniques worthwhile for analog IC placement? Y Lin, Y Li, D Fang, M Madhusudan, SS Sapatnekar, R Harjani, J Hu 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 154-159, 2022 | 18 | 2022 |
| NVCell 2: Routability-driven standard cell layout in advanced nodes with lattice graph routability model CT Ho, A Ho, M Fojtik, M Kim, S Wei, Y Li, B Khailany, H Ren Proceedings of the 2023 International Symposium on Physical Design, 44-52, 2023 | 15 | 2023 |
| DRC-Coder: Automated drc checker code generation using LLM autonomous agent CC Chang, CT Ho, Y Li, Y Chen, H Ren Proceedings of the 2025 International Symposium on Physical Design, 143-151, 2025 | 12 | 2025 |
| Novel transformer model based clustering method for standard cell design automation CT Ho, A Chandna, D Guan, A Ho, M Kim, Y Li, H Ren Proceedings of the 2024 International Symposium on Physical Design, 195-203, 2024 | 12 | 2024 |
| The ALIGN open-source analog layout generator: V1. 0 and beyond T Dhar, K Kunal, Y Li, Y Lin, M Madhusudan, J Poojary, AK Sharma, ... Proceedings of the 39th International Conference on Computer-Aided Design, 1-2, 2020 | 12 | 2020 |
| Fully automated machine learning model development for analog placement quality prediction CC Chang, J Pan, Z Xie, Y Li, Y Lin, J Hu, Y Chen Proceedings of the 28th Asia and South Pacific Design Automation Conference …, 2023 | 10 | 2023 |
| Fast and efficient constraint evaluation of analog layout using machine learning models T Dhar, J Poojary, Y Li, K Kunal, M Madhusudan, AK Sharma, SD Manasi, ... Proceedings of the 26th Asia and South Pacific design automation conference …, 2021 | 8 | 2021 |
| MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs Y Lin, Y Li, M Madhusudan, SS Sapatnekar, R Harjani, J Hu IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024 | 7 | 2024 |
| Analog layout generation using optimized primitives M Madhusudan, AK Sharma, Y Li, J Hu, SS Sapatnekar, R Hajiani 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021 | 7 | 2021 |
| Machine Learning for Analog Layout SM Burns, H Chen, T Dhar, R Harjani, J Hu, N Karmokar, K Kunal, Y Li, ... Machine Learning Applications in Electronic Design Automation, 505-544, 2022 | 6 | 2022 |
| A transferable GNN-based multi-corner performance variability modeling for analog ICs H Zhou, Y Li, X Xiong, P Zhou 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 411-416, 2024 | 5 | 2024 |
| Performance-driven wire sizing for analog integrated circuits Y Li, Y Lin, M Madhusudan, A Sharma, S Sapatnekar, R Harjani, J Hu ACM Transactions on Design Automation of Electronic Systems 28 (2), 1-23, 2022 | 4 | 2022 |
| Mapping large scale finite element computing on to wafer-scale engines Y Lin, R Liang, Y Li, H Hu, J Hu 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), 147-153, 2022 | 4 | 2022 |
| An outlier detection method and its application to multicore-chip power estimation Y Li, P Zhou 2017 IEEE 12th International Conference on ASIC (ASICON), 460-463, 2017 | 4 | 2017 |
| A cross-layer framework for temporal power and supply noise prediction Y Li, C Zhuo, P Zhou IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 3 | 2018 |
Jiang HuProfessor of Electrical and Computer Engineering, Texas A&M UniversityVerified email at tamu.edu
