| OASYS: A framework for analog circuit synthesis R Harjani, RA Rutenbar, LR Carley IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1989 | 622 | 1989 |
| A high-efficiency DC–DC converter using 2 nH integrated inductors J Wibben, R Harjani IEEE Journal of Solid-State Circuits 43 (4), 844-854, 2008 | 421 | 2008 |
| A low-power CMOS VGA for 50 Mb/s disk drive read channels R Harjani IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2002 | 290 | 2002 |
| Design of low-phase-noise CMOS ring oscillators L Dai, R Harjani IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2002 | 177 | 2002 |
| Fully-integrated on-chip DC-DC converter with a 450X output range SS Kudva, R Harjani IEEE Journal of Solid-State Circuits 46 (8), 1940-1951, 2011 | 161 | 2011 |
| A prototype framework for knowledge-based analog circuit synthesis R Harjani, RA Rutenbar, LR Carley Proceedings of the 24th ACM/IEEE Design Automation Conference, 42-49, 1987 | 159 | 1987 |
| CMOS switched-op-amp-based sample-and-hold circuit L Dai, R Harjani IEEE journal of solid-state circuits 35 (1), 109-113, 2000 | 146 | 2000 |
| Partial positive feedback for gain enhancement of low-power CMOS OTAs R Wang, R Harjani Analog Integrated Circuits and Signal Processing 8 (1), 21-35, 1995 | 144 | 1995 |
| ALIGN: Open-source analog layout automation from the ground up K Kunal, M Madhusudan, AK Sharma, W Xu, SM Burns, R Harjani, J Hu, ... Proceedings of the 56th Annual Design Automation Conference 2019, 1-4, 2019 | 139 | 2019 |
| A+ 18 dBm IIP3 LNA in 0.35/spl mu/m CMOS Y Ding, R Harjani 2001 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2001 | 121 | 2001 |
| A linearized, low phase noise VCO based 25 GHz PLL with automatic biasing B Sadhu, MA Ferriss, AS Natarajan, S Yaldiz, J Plouchart, AV Rylyakov, ... IEEE Journal of Solid-State Circuits 48 (5), 1138-1150, 2013 | 114 | 2013 |
| GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. K Kunal, T Dhar, M Madhusudan, J Poojary, AK Sharma, W Xu, SM Burns, ... DATE, 55-60, 2020 | 106 | 2020 |
| Design of high-performance CMOS voltage-controlled oscillators L Dai, R Harjani Springer Science & Business Media, 2003 | 105 | 2003 |
| A customized graph neural network model for guiding analog IC placement Y Li, Y Lin, M Madhusudan, A Sharma, W Xu, SS Sapatnekar, R Harjani, ... Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020 | 104 | 2020 |
| High-frequency LC VCO design using capacitive degeneration B Jung, R Harjani IEEE Journal of Solid-State Circuits 39 (12), 2359-2370, 2004 | 89 | 2004 |
| A high-efficiency CMOS +22-dBm linear power amplifier Y Ding, R Harjani Solid-State Circuits, IEEE Journal of 40 (9), 1895-1900, 2005 | 87 | 2005 |
| ALIGN: A system for automating analog layout T Dhar, K Kunal, Y Li, M Madhusudan, J Poojary, AK Sharma, W Xu, ... IEEE Design & Test 38 (2), 8-18, 2020 | 84 | 2020 |
| Time-encoded values for highly efficient stochastic circuits MH Najafi, S Jamali-Zavareh, DJ Lilja, MD Riedel, K Bazargan, R Harjani IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (5 …, 2017 | 82 | 2017 |
| An integrated low-voltage class AB CMOS OTA R Harjani, R Heineke, F Wang IEEE Journal of Solid-State Circuits 34 (2), 134-142, 1999 | 79 | 1999 |
| Feasibility and performance region modeling of analog and digital circuits R Harjani, J Shao Analog Integrated Circuits and Signal Processing 10 (1), 23-43, 1996 | 79 | 1996 |
Sachin SapatnekarUniversity of MinnesotaVerified email at umn.edu
