| Characterizing and comparing prevailing simulation techniques JJ Yi, SV Kodakara, R Sendag, DJ Lilja, DM Hawkins 11th International Symposium on High-Performance Computer Architecture, 266-277, 2005 | 145 | 2005 |
| Take it to the Limit: Peak Prediction-driven Resource Overcommitment in Datacenters N Bashir, N Deng, KM Rządca, D Irwin, S Kodakara, R Jnagal Eurosys 2021, 2021 | 87 | 2021 |
| Thunderbolt:{Throughput-Optimized},{Quality-of-Service-Aware} power capping at scale S Li, X Wang, X Zhang, V Kontorinis, S Kodakara, D Lo, P Ranganathan 14th USENIX Symposium on Operating Systems Design and Implementation (OSDI …, 2020 | 63 | 2020 |
| Extracting Effective Functional Tests from Commercial Programs SV Kodakara, MV Sagar, JT Yuen IEEE VLSI Test Symposium, 2015 | 21 | 2015 |
| Dynamic code region (DCR) based program phase tracking and prediction for dynamic optimizations J Kim, SV Kodakara, WC Hsu, DJ Lilja, PC Yew International Conference on High-Performance Embedded Architectures and …, 2005 | 21 | 2005 |
| Design fault directed test generation for microprocessor validation DA Mathaikutty, SK Shukla, SV Kodakara, D Lilja, A Dingankar 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007 | 20 | 2007 |
| Robust analytical gate delay modeling for low voltage circuits A Ramalingam, SV Kodakara, A Devgan, DZ Pan Proceedings of the 2006 Asia and South Pacific Design Automation Conference …, 2006 | 20 | 2006 |
| Model based test generation for microprocessor architecture validation SV Kodakara, DA Mathaikutty, A Dingankar, S Shukla, D Lilja 20th International Conference on VLSI Design held jointly with 6th …, 2007 | 10 | 2007 |
| CIM: A reliable metric for evaluating program phase classifications SV Kodakara, J Kim, DJ Lilja, D Hawkins, WC Hsu, PC Yew Computer Architecture Letters 6 (1), 9-12, 2007 | 8 | 2007 |
| MMV: A metamodeling based microprocessor validation environment DA Mathaikutty, SV Kodakara, A Dingankar, SK Shukla, DJ Lilja Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 16 (4 …, 2008 | 6 | 2008 |
| A Probabilistic Analysis For Fault Detectability of Code Coverage Metrics SV Kodakara, DA Mathaikutty, A Dingankar, S Shukla, D Lilja IEEE Micro. Test Verifi.(MTV) Work-shop, 2006 | 6 | 2006 |
| MMV: Metamodeling Based Microprocessor Valiation Environment A Dingankar, DA Mathaikutty, SV Kodakara, S Shukla, D Lilja 2006 IEEE International High Level Design Validation and Test Workshop, 143-148, 2006 | 5 | 2006 |
| Analysis of statistical sampling in microarchitecture simulation: metric, methodology and program characterization SV Kodakara, J Kim, DJ Lilja, WC Hsu, PC Yew 2007 IEEE 10th International Symposium on Workload Characterization, 139-148, 2007 | 4 | 2007 |
| Fault-tolerant image processing using stochastic logic Z Asgar, S Kodakara, D Lilja Technical Report, http://www. zasgar. net/zain/publications/publications. php, 2005 | 4 | 2005 |
| Throughput-optimized, quality-of-service aware power capping system V Kontorinis, S Li, X Zhang, SV Kodakara, K Ye US Patent 11,599,184, 2023 | 3 | 2023 |
| PASS: Program Structure Aware Stratified Sampling for Statistically selecting instruction traces and simulation points SV Kodakara, J Kim, W Hsu, DJ Lilja, PC Yew | 3 | 2005 |
| Throughput-optimized, quality-of-service aware power capping system V Kontorinis, S Li, X Zhang, SV Kodakara, K Ye US Patent 11,966,273, 2024 | 1 | 2024 |
| Dynamic Code Region-based Program Phase Classification and Transition Prediction J Kim, SV Kodakara, WC Hsu, DJ Lilja, PC Yew Uinversity of Minnesota, Computer Science & Engineering Technical Report, 05-021, 2005 | 1 | 2005 |
| Dedicated Telemetry Subsystem For Telemetry Data S Gal-On, O Isachar, VW Lee, S Eranian, SV Kodakara, Y Jiang, G Costi US Patent App. 18/116,042, 2024 | | 2024 |
| Take it to the limit: peak prediction-driven resource overcommitment in datacenters RJ Noman Bashir, Nan Deng , Krzysztof Rzadca , David Irwin , Sree Kodakara EuroSys '21: Proceedings of the Sixteenth European Conference on Computer …, 2021 | | 2021 |
David J. LiljaProfessor Emeritus of Electrical and Computer Engineering, University of MinnesotaVerified email at umn.edu
