| A survey on high-throughput non-binary LDPC decoders: ASIC, FPGA, and GPU architectures O Ferraz, S Subramaniyan, R Chinthala, J Andrade, JR Cavallaro, ... IEEE Communications Surveys & Tutorials 24 (1), 524-556, 2021 | 81 | 2021 |
| Low cost flex powered gesture detection system and its applications P Telluri, S Manam, S Somarouthu, JM Oli, C Ramesh 2020 Second International Conference on Inventive Research in Computing …, 2020 | 26 | 2020 |
| An efficient design methodology to speed up the FPGA implementation of artificial neural networks KV Vineetha, MMSK Reddy, C Ramesh, DG Kurup Engineering Science and Technology, an International Journal 47, 101542, 2023 | 18 | 2023 |
| Area Efficient Architecture for high speed wide data adders in Xilinx FPGAs R Chinthala, NS Murty 2019 International Conference on Computer Communication and Informatics …, 2019 | 7 | 2019 |
| Implementation of an area efficient high throughput architecture for sparse matrix LU factorization GP Kumar, C Ramesh 2019 3rd International Conference on Electronics, Materials Engineering …, 2019 | 6 | 2019 |
| Implementation of direct demodulator based on ANN using FPGA KV Vineetha, C Ramesh, DG Kurup Alexandria Engineering Journal 108, 730-753, 2024 | 5 | 2024 |
| An Efficient Automatic Car Parking Slot Allocation System N Srivani, A Prasanth, K Srija, C Ramesh, JM Oli 2025 10th International Conference on Signal Processing and Communication …, 2025 | 3 | 2025 |
| Complex Binary Number System-based Co-Processor Design for Signal Processing Applications SS Santosh, TS Swaroop, T Kavya, R Chinthala 2021 5th International Conference on Electronics, Materials Engineering …, 2021 | 3 | 2021 |
| An Enhanced Two-Speed, Radix-4 Multiplier using Spurious Power Suppression Technique N Soni, R Chinthala 2020 International Conference on Smart Electronics and Communication (ICOSEC …, 2020 | 3 | 2020 |
| High Throughput Basic-Set Trellis Min–Max Non-Binary LDPC Code Decoder Architecture over GF (4) CC Kumar, R Chinthala 2020 4th International Conference on Electronics, Materials Engineering …, 2020 | 2 | 2020 |
| Design and Implementation of Power Efficient Hardware Accelerator for Bidirectional Long Short-Term Memory (Bi-LSTM) KN Apoorva, V Venugopal, C Ramesh 2024 IEEE 21st India Council International Conference (INDICON), 1-6, 2024 | 1 | 2024 |
| Design and Implementation of an Efficient 32-Bit Fixed-Point Newton-Raphson Division-Based Reciprocal Computing Unit CS Aragula, B Preethi, C Ramesh 2024 IEEE 4th International Conference on VLSI Systems, Architecture …, 2024 | 1 | 2024 |
| Implementation of Neural Network Based Digital Pre-distorter for Power Amplifier Linearisation MA Bharadwaj, C Ramesh, RVS Devi 2024 Second International Conference on Emerging Trends in Information …, 2024 | 1 | 2024 |
| Implementation of Memristive Hodgkin-Huxley Neuron Model in Verilog HDL GH Kumar, R Sunitha, R Chinthala 2025 IEEE 5th International Conference on VLSI Systems, Architecture …, 2025 | | 2025 |
| Comparative Analysis of 6T, 8T, and 10T SRAM Architectures: A Study on Power, Noise Margin, and Leakage Current KS Sailaja, M Nithima, NSH Savitha, S Rajula, C Ramesh 2025 IEEE 5th International Conference on VLSI Systems, Architecture …, 2025 | | 2025 |
| Approximate Parallel Prefix Adders for Image Processing Applications BS Mithil, C Ramesh 2025 IEEE 5th International Conference on VLSI Systems, Architecture …, 2025 | | 2025 |
| Enhancing BER Performance in Phase Noise using KNN-based Symbol Detection S Krishnamurthy, M Panda, R Chinthala 2024 15th International Conference on Computing Communication and Networking …, 2024 | | 2024 |
| Cost Efficient Location Tracking and Health Monitoring System for Soldier Safety R Jayaramu, GSK Reddy, R Chinthala, P TL, N Yamanakkanavar, S HR 2023 Global Conference on Information Technologies and Communications (GCITC …, 2023 | | 2023 |
| FPGA Implementation of UaL Decomposition, an alternative to the LU factorization S Ruchitha, R Chinthala Mathematical Statistician and Engineering Applications 71 (4), 1081-1094, 2022 | | 2022 |
| Sensor Data Acquisition and De-noising using FPGA K Harikrishnan, HN Vishwas, KV Vineetha, R Chinthala International Journal of Scientific & Engineering Research 11 (8), 1673 - 1680, 2020 | | 2020 |
Joseph R. CavallaroProfessor of Electrical and Computer Engineering, Rice UniversityVerified email at rice.edu
