| Recurrent neural networks: An embedded computing perspective NM Rezk, M Purnaprajna, T Nordström, Z Ul-Abdin IEEE Access 8, 57967-57996, 2020 | 183 | 2020 |
| A survey on high-throughput non-binary LDPC decoders: ASIC, FPGA, and GPU architectures O Ferraz, S Subramaniyan, R Chinthala, J Andrade, JR Cavallaro, ... IEEE Communications Surveys & Tutorials 24 (1), 524-556, 2021 | 81 | 2021 |
| Genetic algorithms for hardware–software partitioning and optimal resource allocation M Purnaprajna, M Reformat, W Pedrycz Journal of Systems Architecture 53 (7), 339-354, 2007 | 75 | 2007 |
| Shortening design time through multiplatform simulations with a portable OpenCL golden-model: the LDPC decoder case G Falcao, M Owaida, D Novo, M Purnaprajna, N Bellas, CD Antonopoulos, ... 2012 IEEE 20th International Symposium on Field-Programmable Custom …, 2012 | 29 | 2012 |
| ASIC implementation of a high speed WGNG for communication channel emulation [white Gaussian noise generator] E Fung, K Leung, N Parimi, M Purnaprajna, VC Gaudet IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004., 304-309, 2004 | 25 | 2004 |
| Review of electrostatic force calculation methods and their acceleration in molecular dynamics packages using graphics processors A George, S Mondal, M Purnaprajna, P Athri ACS omega 7 (37), 32877-32896, 2022 | 24 | 2022 |
| Making wide-issue VLIW processors viable on FPGAs M Purnaprajna, P Ienne ACM Transactions on Architecture and Code Optimization (TACO) 8 (4), 1-16, 2012 | 21 | 2012 |
| Enabling seamless execution on hybrid CPU/FPGA systems: Challenges & directions M Belwal, M Purnaprajna 2015 25th International Conference on Field Programmable Logic and …, 2015 | 20 | 2015 |
| Enhancing design space exploration by extending CPU/GPU specifications onto FPGAs M Owaida, G Falcao, J Andrade, C Antonopoulos, N Bellas, ... ACM Transactions on Embedded Computing Systems (TECS) 14 (2), 1-23, 2015 | 18 | 2015 |
| Self-optimization of mpsocs targeting resource efficiency and fault tolerance M Porrmann, M Purnaprajna, C Puttmann 2009 NASA/ESA Conference on Adaptive Hardware and Systems, 467-473, 2009 | 18 | 2009 |
| Power aware reconfigurable multiprocessor for elliptic curve cryptography M Purnaprajna, C Puttmann, M Porrmann Proceedings of the conference on Design, automation and test in Europe, 1462 …, 2008 | 18 | 2008 |
| Shadow and-inverter cones H Parandeh-Afshar, G Zgheib, D Novo, M Purnaprajna, P Ienne 2013 23rd International Conference on Field programmable Logic and …, 2013 | 17 | 2013 |
| Compiler-driven reconfiguration of multiprocessors M Hußmann, M Thies, U Kastens, M Purnaprajna, M Porrmann, U Rückert Proceedings of the Workshop on Application Specific Processors (WASP), 3-10, 2007 | 11 | 2007 |
| Demystifying Compression Techniques in CNNs: CPU, GPU and FPGA cross-platform analysis R Ramakrishnan, AKV Dev, AS Darshik, R Chinchwadkar, M Purnaprajna 2021 34th International Conference on VLSI Design and 2021 20th …, 2021 | 10 | 2021 |
| CoIn: Accelerated CNN co-inference through data partitioning on heterogeneous devices K Vanishree, A George, S Gunisetty, S Subramanian, S Kashyap, ... 2020 6th International Conference on Advanced Computing and Communication …, 2020 | 9 | 2020 |
| A case for heterogeneous technology-mapping: Soft versus hard multiplexers M Purnaprajna, P Ienne 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom …, 2013 | 8 | 2013 |
| Run-time reconfigurable multiprocessors M Purnaprajna University of Paderborn, 2010 | 7 | 2010 |
| k-core: Hardware Accelerator for k-mer Generation and Counting used in Computational Genomics SM Bose, VS Lalapura, S Saravanan, M Purnaprajna 2019 32nd International Conference on VLSI Design and 2019 18th …, 2019 | 6 | 2019 |
| Runtime Reconfiguration of Multiprocessors Based on Compile-Time Analysis M Purnaprajna, M Porrmann, U Rueckert, M Hussmann, M Thies, ... ACM Transactions on Reconfigurable Technology and Systems (TRETS) 3 (3), 1-25, 2010 | 6 | 2010 |
| Pushing the limits of energy efficiency for non-binary LDPC decoders on GPUs and FPGAs S Subramaniyan, O Ferraz, MR Ashuthosh, S Krishna, G Wang, ... 2020 IEEE Workshop on Signal Processing Systems (SiPS), 1-6, 2020 | 4 | 2020 |
Paolo IenneProfessor, EPFLVerified email at epfl.ch
