| Monolithic piezoresistive CMOS magnetic field sensors V Beroulle, Y Bertrand, L Latorre, P Nouet Sensors and Actuators A: Physical 103 (1-2), 23-32, 2003 | 109 | 2003 |
| Laser fault injection at the CMOS 28 nm technology node: an analysis of the fault model JM Dutertre, V Beroulle, P Candelier, S De Castro, LB Faber, ML Flottes, ... 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), 1-6, 2018 | 89 | 2018 |
| Functional verification of rtl designs driven by mutation testing metrics Y Serrestou, V Beroulle, C Robach 10th Euromicro Conference on Digital System Design Architectures, Methods …, 2007 | 49 | 2007 |
| Antennas for RFID tags S Tedjini, TP Vuong, V Beroulle Proceedings of the 2005 joint conference on Smart objects and ambient …, 2005 | 44 | 2005 |
| Novel ECC-based RFID mutual authentication protocol for emerging IoT applications S Gabsi, Y Kortli, V Beroulle, Y Kieffer, A Alasiry, B Hamdi IEEE access 9, 130895-130913, 2021 | 42 | 2021 |
| Hardware security evaluation platform for MCU-based connected devices: application to healthcare IoT Z Kazemi, A Papadimitriou, D Hely, M Fazcli, V Beroulle 2018 IEEE 3rd International Verification and Security Workshop (IVSW), 87-92, 2018 | 40 | 2018 |
| Voltage glitch attacks on mixed-signal systems N Beringuier-Boher, K Gomina, D Hély, JB Rigaud, V Beroulle, A Tria, ... 2014 17th Euromicro Conference on Digital System Design, 379-386, 2014 | 40 | 2014 |
| A comprehensive survey of attacks without physical access targeting hardware vulnerabilities in IoT/IIoT devices, and their detection mechanisms NF Polychronou, PH Thevenon, M Puys, V Beroulle ACM Transactions on Design Automation of Electronic Systems (TODAES) 27 (1 …, 2021 | 39 | 2021 |
| A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks A Papadimitriou, D Hély, V Beroulle, P Maistri, R Leveugle 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-4, 2014 | 39 | 2014 |
| Fault injection on hidden registers in a risc-v rocket processor and software countermeasures J Laurent, V Beroulle, C Deleuze, F Pebay-Peyroula 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 252-255, 2019 | 35 | 2019 |
| On a low cost fault injection framework for security assessment of cyber-physical systems: Clock glitch attacks Z Kazemi, A Papadimitriou, I Souvatzoglou, E Aerabi, MM Ahmed, D Hely, ... 2019 IEEE 4th International Verification and Security Workshop (IVSW), 7-12, 2019 | 34 | 2019 |
| Machine learning and hardware security: Challenges and opportunities F Regazzoni, S Bhasin, AA Pour, I Alshaer, F Aydin, A Aysu, V Beroulle, ... Proceedings of the 39th International Conference on Computer-Aided Design, 1-6, 2020 | 33 | 2020 |
| Cross-layer analysis of software fault models and countermeasures against hardware fault attacks in a RISC-V processor J Laurent, V Beroulle, C Deleuze, F Pebay-Peyroula, A Papadimitriou Microprocessors and Microsystems 71, 102862, 2019 | 32 | 2019 |
| On the performance of non-profiled differential deep learning attacks against an AES encryption algorithm protected using a correlated noise generation based hiding countermeasure A Alipour, A Papadimitriou, V Beroulle, E Aerabi, D Hély 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 614-617, 2020 | 29 | 2020 |
| A DFT architecture for asynchronous networks-on-chip XT Tran, J Durupt, F Bertrand, V Beroulle, C Robach Eleventh IEEE European Test Symposium (ETS'06), 219-224, 2006 | 29 | 2006 |
| Evaluation of the oscillation-based test methodology for micro-electro-mechanical systems V Beroulle, Y Bertrand, L Latorre, P Nouet Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 439-444, 2002 | 29 | 2002 |
| Survey: Vulnerability analysis of low-cost ECC-based RFID protocols against wireless and side-channel attacks S Gabsi, V Beroulle, Y Kieffer, HM Dao, Y Kortli, B Hamdi Sensors 21 (17), 5824, 2021 | 28 | 2021 |
| Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application XT Tran, Y Thonnart, J Durupt, V Beroulle, C Robach IET computers & digital techniques 3 (5), 487-500, 2009 | 28 | 2009 |
| A design-for-test implementation of an asynchronous network-on-chip architecture and its associated test pattern generation and application XT Tran, Y Thonnart, J Durupt, V Beroulle, C Robach Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 149-158, 2008 | 27 | 2008 |
| Laser-induced fault effects in security-dedicated circuits R Leveugle, P Maistri, P Vanhauwaert, F Lu, G Di Natale, ML Flottes, ... 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC …, 2014 | 26 | 2014 |
David HélyUniv. Grenoble Alpes, Grenoble INP, LCISVerified email at lcis.grenoble-inp.fr
