| Low complexity design of ripple carry and Brent–Kung adders in QCA V Pudi, K Sridharan IEEE Transactions on nanotechnology 11 (1), 105-119, 2011 | 271 | 2011 |
| Security vulnerabilities of unmanned aerial vehicles and countermeasures: An experimental study V Dey, V Pudi, A Chattopadhyay, Y Elovici 2018 31st international conference on VLSI design and 2018 17th …, 2018 | 134 | 2018 |
| Efficient design of a hybrid adder in quantum-dot cellular automata V Pudi, K Sridharan IEEE transactions on very large scale integration (VLSI) systems 19 (9 …, 2010 | 129 | 2010 |
| New decomposition theorems on majority logic for low-delay adder designs in quantum dot cellular automata V Pudi, K Sridharan IEEE Transactions on Circuits and Systems II: Express Briefs 59 (10), 678-682, 2012 | 85 | 2012 |
| Efficient multiternary digit adder design in CNTFET technology K Sridharan, S Gurindagunta, V Pudi IEEE transactions on Nanotechnology 12 (3), 283-287, 2013 | 72 | 2013 |
| Design of arithmetic circuits in quantum dot cellular automata nanotechnology K Sridharan, V Pudi Springer International Publishing 599, 1-71, 2015 | 65 | 2015 |
| Lightweight secure-boot architecture for risc-v system-on-chip J Haj-Yahya, MM Wong, V Pudi, S Bhasin, A Chattopadhyay 20th International Symposium on Quality Electronic Design (ISQED), 216-223, 2019 | 52 | 2019 |
| A novel in-memory wallace tree multiplier architecture using majority logic V Lakshmi, J Reuben, V Pudi IEEE Transactions on Circuits and Systems I: Regular Papers 69 (3), 1148-1158, 2021 | 49 | 2021 |
| A bit-serial pipelined architecture for high-performance DHT computation in quantum-dot cellular automata V Pudi, K Sridharan IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (10 …, 2014 | 46 | 2014 |
| Majority logic formulations for parallel adder designs at reduced delay and circuit complexity V Pudi, K Sridharan, F Lombardi IEEE transactions on computers 66 (10), 1824-1830, 2017 | 45 | 2017 |
| New majority gate-based parallel BCD adder designs for quantum-dot cellular automata T Zhang, V Pudi, W Liu IEEE Transactions on Circuits and Systems II: Express Briefs 66 (7), 1232-1236, 2018 | 34 | 2018 |
| Secure and lightweight compressive sensing using stream cipher V Pudi, A Chattopadhyay, KY Lam IEEE Transactions on Circuits and Systems II: Express Briefs 65 (3), 371-375, 2017 | 32 | 2017 |
| CoLPUF: a novel configurable LFSR-based PUF B Srinivasu, P Vikramkumar, A Chattopadhyay, KY Lam 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 358-361, 2018 | 28 | 2018 |
| An FPGA-based brain computer interfacing using compressive sensing and machine learning RR Shrivastwa, V Pudi, A Chattopadhyay 2018 IEEE computer society annual symposium on VLSI (ISVLSI), 726-731, 2018 | 27 | 2018 |
| CORDIC-based azimuth calculation and obstacle tracing via optimal sensor placement on a mobile robot P Vyas, L Vachhani, K Sridharan, V Pudi IEEE/ASME Transactions on Mechatronics 21 (5), 2317-2329, 2015 | 22 | 2015 |
| Efficient design of Baugh-Wooley multiplier in quantum-dot cellular automata V Pudi, K Sridharan 2013 13th IEEE International conference on nanotechnology (IEEE-NANO 2013 …, 2013 | 22 | 2013 |
| A brain–computer interface framework based on compressive sensing and deep learning RR Shrivastwa, V Pudi, C Duo, R So, A Chattopadhyay, G Cuntai IEEE Consumer Electronics Magazine 9 (3), 90-96, 2020 | 21 | 2020 |
| Lightweight and high performance SHA-256 using architectural folding and 4-2 adder compressor MM Wong, V Pudi, A Chattopadhyay 2018 IFIP/IEEE International Conference on Very Large Scale Integration …, 2018 | 14 | 2018 |
| SHA-3 implementation using ReRAM based in-memory computing architecture D Bhattacharjee, V Pudi, A Chattopadhyay 2017 18th International Symposium on Quality Electronic Design (ISQED), 325-330, 2017 | 14 | 2017 |
| Efficient QCA design of single-bit and multi-bit subtractors V Pudi, K Sridharan 2013 13th IEEE International Conference on Nanotechnology (IEEE-NANO 2013 …, 2013 | 14 | 2013 |
Anupam ChattopadhyayAssociate Professor, CCDS, NTU, SingaporeVerified email at ntu.edu.sg
