| Precomputation-based sequential logic optimization for low power M Alidina, J Monteiro, S Devadas, A Ghosh, M Papaefthymiou IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2 (4), 426-436, 1994 | 488* | 1994 |
| Retiming sequential circuits for low power J Monteiro, S Devadas, A Ghosh International journal of high speed electronics and systems 7 (02), 323-340, 1996 | 276 | 1996 |
| Power estimation methods for sequential logic circuits CY Tsui, J Monteiro, M Pedram, S Devadas, AM Despain, B Lin IEEE Transactions on Very Large Scale Integration (VLSI) Systems 3 (3), 404-416, 1995 | 209 | 1995 |
| A methodology for efficient estimation of switching activity in sequential logic circuits J Monteiro, S Devadas, B Lin Proceedings of the 31st annual Design Automation Conference, 12-17, 1994 | 181 | 1994 |
| Exact and approximate algorithms for the optimization of area and delay in multiple constant multiplications L Aksoy, E Da Costa, P Flores, J Monteiro IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008 | 169 | 2008 |
| Scheduling techniques to enable power management J Monteiro, S Devadas, P Ashar, A Mauskar Proceedings of the 33rd annual Design Automation Conference, 349-352, 1996 | 159 | 1996 |
| Estimation of average switching activity in combinational logic circuits using symbolic simulation J Monteiro, S Devadas, A Ghosh, K Keutzer, J White IEEE transactions on computer-aided design of integrated circuits and …, 2002 | 121 | 2002 |
| Finite state machine decomposition for low power JC Monteiro, AL Oliveira Proceedings of the 35th annual Design Automation Conference, 758-763, 1998 | 120 | 1998 |
| A review of synthetic-aperture radar image formation algorithms and implementations: A computational perspective H Cruz, M Véstias, J Monteiro, H Neto, RP Duarte Remote Sensing 14 (5), 1258, 2022 | 96 | 2022 |
| Switching activity estimation using limited depth reconvergent path analysis JC Costa, JC Monteiro, S Devadas Proceedings of the 1997 international symposium on Low power electronics and …, 1997 | 83 | 1997 |
| An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications P Flores, J Monteiro, E Costa ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005 | 80 | 2005 |
| Assignment and reordering of incompletely specified pattern sequences targetting minimum power dissipation P Flores, J Costa, H Neto, J Monteiro, J Marques-Silva Proceedings Twelfth International Conference on VLSI Design.(Cat. No …, 1999 | 70 | 1999 |
| Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation: 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11 … J Monteiro, R Van Leuken Springer Science & Business Media, 2010 | 65 | 2010 |
| Mobile localization techniques for wireless sensor networks: Survey and recommendations LL Oliveira, GH Eisenkraemer, EA Carara, JB Martins, J Monteiro ACM Transactions on Sensor Networks 19 (2), 1-39, 2023 | 57 | 2023 |
| Optimization of area in digital FIR filters using gate-level metrics L Aksov, E Costa, P Flores, J Monteiro Proceedings of the 44th annual Design Automation Conference, 420-423, 2007 | 57 | 2007 |
| Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs J Monteiro, S Devadas Proceedings of the 1995 international symposium on Low power design, 33-38, 1995 | 57 | 1995 |
| Computer-Aided Design Techniques for Low Power Sequential Logic Circuits J Monteiro, S Devadas Springer Science & Business Media, 2012 | 56 | 2012 |
| A tutorial on multiplierless design of FIR filters: Algorithms and architectures L Aksoy, P Flores, J Monteiro Circuits, Systems, and Signal Processing 33 (6), 1689-1719, 2014 | 51 | 2014 |
| Design of digit-serial FIR filters: Algorithms, architectures, and a CAD tool L Aksoy, C Lazzari, E Costa, P Flores, J Monteiro IEEE transactions on very large Scale integration (VLSI) systems 21 (3), 498-511, 2012 | 51 | 2012 |
| Optimization of combinational and sequential logic circuits for low power using precomputation J Monteiro, J Rinderknecht, S Devadas, A Ghosh Proceedings Sixteenth Conference on Advanced Research in VLSI, 430-444, 1995 | 47 | 1995 |
Paulo FloresINESC-ID, Instituto Superior Técnico (IST), Universidade de Lisboa (ULisboa)Verified email at inesc-id.pt
