| A full featured configurable accelerator for object detection with YOLO D Pestana, PR Miranda, JD Lopes, RP Duarte, MP Véstias, HC Neto, ... IEEE Access 9, 75864-75877, 2021 | 102 | 2021 |
| A review of synthetic-aperture radar image formation algorithms and implementations: A computational perspective H Cruz, M Véstias, J Monteiro, H Neto, RP Duarte Remote Sensing 14 (5), 1258, 2022 | 97 | 2022 |
| Moving deep learning to the edge MP Véstias, RP Duarte, JT de Sousa, HC Neto Algorithms 13 (5), 125, 2020 | 90 | 2020 |
| CardioWheel: ECG biometrics on the steering wheel A Lourenço, AP Alves, C Carreiras, RP Duarte, A Fred Joint European conference on machine learning and knowledge discovery in …, 2015 | 58 | 2015 |
| kNN-STUFF: kNN STreaming Unit for Fpgas J Vieira, RP Duarte, HC Neto IEEE-Access, 2019 | 48 | 2019 |
| Parallel dot-products for deep learning on FPGA M Véstias, RP Duarte, JT De Sousa, H Neto 2017 27th international conference on field programmable logic and …, 2017 | 41 | 2017 |
| A fast and scalable architecture to run convolutional neural networks in low density FPGAs MP Véstias, RP Duarte, JT de Sousa, HC Neto Microprocessors and Microsystems 77, 103136, 2020 | 33 | 2020 |
| Double-precision gauss-jordan algorithm with partial pivoting on fpgas R Duarte, H Neto, M Véstias 2009 12th Euromicro Conference on Digital System Design, Architectures …, 2009 | 29 | 2009 |
| Fast convolutional neural networks in low density FPGAs using zero-skipping and weight pruning MP Véstias, RP Duarte, JT de Sousa, HC Neto Electronics 8 (11), 1321, 2019 | 24 | 2019 |
| Lite-CNN: A high-performance architecture to execute CNNs in low density FPGAs M Véstias, RP Duarte, JT De Sousa, H Neto 2018 28th International Conference on Field Programmable Logic and …, 2018 | 24 | 2018 |
| Onboard processing of synthetic aperture radar backprojection algorithm in FPGA D Mota, H Cruz, PR Miranda, RP Duarte, JT De Sousa, HC Neto, ... IEEE Journal of Selected Topics in Applied Earth Observations and Remote …, 2022 | 19 | 2022 |
| A configurable architecture for running hybrid convolutional neural networks in low-density FPGAs MP Véstias, RP Duarte, JT De Sousa, HC Neto IEEE Access 8, 107229-107243, 2020 | 18 | 2020 |
| Hybrid dot-product calculation for convolutional neural networks in FPGA MP Véstias, RP Duarte, JT De Sousa, H Neto 2019 29th International Conference on Field Programmable Logic and …, 2019 | 15 | 2019 |
| Configurable hardware core for IoT object detection PR Miranda, D Pestana, JD Lopes, RP Duarte, MP Véstias, HC Neto, ... Future Internet 13 (11), 280, 2021 | 12 | 2021 |
| Synthesis of Bayesian Machines On FPGAs Using Stochastic Arithmetic RP Duarte, J Lobo, JF Ferreira, J Dias 2nd International Workshop on Neuromorphic and Brain-Based Computing Systems …, 2015 | 12 | 2015 |
| Coarse-grained reconfigurable computing with the versat architecture JD Lopes, MP Vestias, RP Duarte, HC Neto, JT de Sousa Electronics 10 (6), 669, 2021 | 11 | 2021 |
| Low energy heterogeneous computing with multiple RISC-V and CGRA cores L Fiolhais, F Gonçalves, RP Duarte, M Véstias, JT De Sousa 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019 | 11 | 2019 |
| Technological Innovation for Cyber-Physical Systems: 7th IFIP WG 5.5/SOCOLNET Advanced Doctoral Conference on Computing, Electrical and Industrial Systems, DoCEIS 2016, Costa … LM Camarinha-Matos, AJ Falcão, N Vafaei, S Najdi Springer, 2016 | 11 | 2016 |
| A unified framework for over-clocking linear projections on FPGAs under PVT variation RP Duarte, CS Bouganis International Symposium on Applied Reconfigurable Computing, 49-60, 2014 | 10 | 2014 |
| High-level linear projection circuit design optimization framework for FPGAs under over-clocking RP Duarte, CS Bouganis 22nd International Conference on Field Programmable Logic and Applications …, 2012 | 10 | 2012 |
Horacio NetoINESC / IST, University of LisbonVerified email at inesc-id.pt
