WO2025234291A1 - Semiconductor memory device - Google Patents

Abstract

Active regions (P1-P4) having configured therein drive transistors (PU1, PU2) and access transistors (PG1-PG4), which are P-type transistors, are formed in a lower part of a cell. Active regions (P1-P4) having configured therein load transistors (PD1, PD2), which are N-type transistors, are formed in an upper part of the cell. Power supply wiring (11) for supplying a first power supply voltage is formed in a back wiring layer.

Description

semiconductor memory device

This disclosure relates to the layout structure of an SRAM (Static Random Access Memory) cell (hereinafter simply referred to as a cell, where appropriate) that uses a CFET (Complementary FET).

SRAM is widely used in semiconductor integrated circuits. There is also a type of SRAM called dual-port SRAM, which has two ports for reading and writing data.

Furthermore, transistors, which are the basic components of LSIs, have achieved increased integration density, lower operating voltages, and faster operating speeds through the reduction of gate length (scaling). However, in recent years, excessive scaling has caused problems with off-state current and the resulting significant increase in power consumption. To solve this problem, there has been active research into three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional one. Nanosheet FETs are one type of three-dimensional transistor that has attracted attention.

Patent Document 1 discloses the layout of a two-port SRAM cell using a CFET in which a P-type nanosheet transistor and an N-type nanosheet transistor are stacked on a substrate.

International Publication No. 2020/246344

In the technology disclosed in Patent Document 1, the bit lines and power supply wiring are separated into a buried wiring layer and an upper wiring layer, thereby increasing the wiring width of the wiring in the upper wiring layer. However, the wiring in the buried wiring layer cannot be arranged to overlap with the transistor (nanosheet). As a result, the wiring width of the wiring formed in the buried wiring layer cannot be increased, which increases the wiring resistance of the wiring and reduces the operating speed of the semiconductor memory device.

Furthermore, P-type nanosheet transistors and N-type nanosheet transistors are mixed in at least one of the layers below and above the cell. This complicates the manufacturing process for the semiconductor memory device, increasing manufacturing costs. Furthermore, since the P-type nanosheet transistors and N-type nanosheet transistors must be spaced apart, the area of the semiconductor memory device increases.

The purpose of this disclosure is to improve the operating speed of semiconductor memory devices, reduce manufacturing costs, and reduce the area of semiconductor memory devices in a layout structure of SRAM cells using CFETs.

A first aspect of the present disclosure is a semiconductor memory device including an SRAM cell, wherein the SRAM cell comprises a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a first word line; a fourth transistor having a source connected to a second bit line that forms a first complementary bit line pair with the first bit line, a drain connected to the second node, and a gate connected to the first word line; a fifth transistor having a source connected to a fourth bit line that forms a second complementary bit line pair with the third bit line, a drain connected to the second node, and a gate connected to the second word line; a sixth transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a seventh transistor having a drain connected to the first node and a gate connected to the second node; and an eighth transistor having a source connected to the second power supply, a drain connected to the second node and a gate connected to the first node, wherein the first to sixth transistors are transistors of a first conductivity type, and the seventh and eighth transistors are transistors of a second conductivity type different from the first conductivity type; and the SRAM cell includes a first active region including a third nanosheet extending in a first direction as the channel, and a fifth nanosheet extending in the first direction as the channel, and a fifth active region including a fifth nanosheet extending in the first direction as the channel, and a sixth transistor having a drain connected to the first node and a gate connected to the second node; a third active region constituting the channel, source, and drain of the second transistor and including the second nanosheet extending in the first direction as the channel; a fourth active region constituting the channel, source, and drain of the fourth transistor and including the fourth nanosheet extending in the first direction as the channel; and a fourth active region constituting the channel, source, and drain of the sixth transistor and including the sixth nanosheet extending in the first direction as the channel; a fifth active region formed higher than the first to fourth active regions in the depth direction and constituting the channel, source, and drain of the seventh transistor and including the seventh nanosheet extending in the first direction as the channel; and a fifth active region formed higher than the first to fourth active regions in the depth direction and constituting the channel, source, and drain of the eighth transistor. The channel comprises a sixth active region including an eighth nanosheet extending in the first direction; a first power supply wiring formed in a back wiring layer that is a wiring layer on the back side of the first to eighth transistors, extending in the first direction and overlapping with the second and third active regions in a planar view, and connected to the first power supply; a first via formed in a region where a region in the second active region that serves as the source of the first transistor and the first power supply wiring overlap, connecting the source of the first transistor in the second active region to the first power supply wiring; and a second via formed in a region where a region in the third active region that serves as the source of the second transistor and the first power supply wiring overlap, connecting the source of the second transistor in the third active region to the first power supply wiring, wherein the first and seventh nanosheets overlap in a planar view, and the second and eighth nanosheets overlap in a planar view.

According to the present disclosure, a first power supply wiring that supplies a first power supply voltage is formed in a back wiring layer, which is the wiring layer on the back side of the first to eighth transistors. The power supply wiring overlaps the second and third active regions in a planar view and is connected to each other through vias provided in the overlapping regions. Therefore, the active regions (transistors) and the power supply wiring can be arranged to overlap, which allows the wiring width of the first power supply wiring that supplies the first power supply voltage to be increased and the wiring resistance of the power supply wiring to be reduced. This improves the operating speed and operational stability of the semiconductor memory device. Furthermore, the fifth and sixth active regions are formed higher in the depth direction than the first to fourth active regions. This allows a first conductivity type transistor to be formed in the lower part of the cell and a second conductivity type transistor to be formed in the upper part of the cell, thereby reducing the complexity of the semiconductor memory device's manufacturing process and reducing manufacturing costs. Furthermore, since it is not necessary to space the first conductivity type transistor and the second conductivity type transistor apart, the semiconductor memory device's area can be reduced.

A second aspect of the present disclosure is a semiconductor memory device including an SRAM cell, wherein the SRAM cell comprises a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a first word line; a fourth transistor having a source connected to a second bit line that forms a first complementary bit line pair with the first bit line, a drain connected to the second node, and a gate connected to the first word line; a fifth transistor having a source connected to the third bit line, a drain connected to the first node, and a gate connected to the second word line; a sixth transistor having a source connected to a fourth bit line that forms a second complementary bit line pair with the third bit line, a drain connected to the second node, and a gate connected to the second word line; a seventh transistor having a drain connected to the first node and a gate connected to the second node, and an eighth transistor having a source connected to the second power supply, a drain connected to the second node, and a gate connected to the first node, the seventh transistor being connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage; and an eighth transistor having a source connected to the second power supply, a drain connected to the second node, and a gate connected to the first node, the first and second transistors being transistors of a first conductivity type, and the fifth to eighth transistors being transistors of a second conductivity type different from the first conductivity type. The SRAM cell includes a first active region that constitutes the channel, source, and drain of the first transistor, the channel including a first nanosheet extending in a first direction; a second active region that constitutes the channel, source, and drain of the second transistor, the channel including a second nanosheet extending in the first direction; and a second active region that is formed above the first and second active regions in a depth direction and constitutes the channel, source, and drain of the third transistor. a third active region including the fifth nanosheet extending in the first direction as the channel, and constituting the channel, source, and drain of the fifth transistor; a fourth active region formed higher than the first and second active regions in the depth direction and constituting the channel, source, and drain of the seventh transistor and including the seventh nanosheet extending in the first direction as the channel; a fifth active region formed higher than the first and second active regions in the depth direction and constituting the channel, source, and drain of the eighth transistor and including the eighth nanosheet extending in the first direction as the channel; and a fifth active region formed higher than the first and second active regions in the depth direction and constituting the channel, source, and drain of the fourth transistor and including the eighth nanosheet extending in the first direction as the channel. a fourth nanosheet extending in the first direction; a sixth active region including the sixth nanosheet extending in the first direction as the channel, which constitutes the channel, source, and drain of the sixth transistor; a first power supply wiring formed in a back wiring layer that is a wiring layer on the back side of the first to eighth transistors, extending in the first direction, overlapping with the first and second active regions in a planar view, and connected to the first power supply; a first via formed in a region in the first active region where the region that serves as the source of the first transistor overlaps with the first power supply wiring, connecting the source of the first transistor in the first active region to the first power supply wiring; and a second via formed in a region in the second active region where the region that serves as the source of the second transistor overlaps with the first power supply wiring, connecting the source of the second transistor in the second active region to the first power supply wiring, wherein the first and seventh nanosheets overlap in a planar view.

According to the present disclosure, a first power supply wiring that supplies a first power supply voltage is formed in a back wiring layer, which is the wiring layer on the back side of the first to eighth transistors. The power supply wiring overlaps the second and third active regions in a planar view and is connected to each other through vias provided in the overlapping regions. Therefore, the active regions (transistors) and the power supply wiring can be arranged to overlap, which allows the wiring width of the first power supply wiring that supplies the first power supply voltage to be increased and the wiring resistance of the power supply wiring to be reduced. This improves the operating speed and operational stability of the semiconductor memory device. Furthermore, the third to sixth active regions are formed higher in the depth direction than the first and second active regions. This allows first conductivity type transistors to be formed in the lower part of the cell and second conductivity type transistors to be formed in the upper part of the cell, thereby reducing the complexity of the semiconductor memory device's manufacturing process and reducing manufacturing costs. Furthermore, because there is no need to space the first conductivity type transistors and the second conductivity type transistors apart, the semiconductor memory device's area can be reduced.

A third aspect of the present disclosure is a semiconductor memory device including an SRAM cell, wherein the SRAM cell comprises a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node; a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node; a third transistor having a source connected to a first bit line, a drain connected to the first node, and a gate connected to a first word line; a fourth transistor having a source connected to a second bit line that forms a first complementary bit line pair with the first bit line, a drain connected to the second node, and a gate connected to the first word line; a fifth transistor having a source connected to the third bit line, a drain connected to the first node, and a gate connected to the second word line; and a sixth transistor having a source connected to a fourth bit line that forms a second complementary bit line pair with the third bit line, a drain connected to the second node, and a gate connected to the second word line. a seventh transistor having a source connected to a second power supply supplying a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node; and an eighth transistor having a source connected to the second power supply, a drain connected to the second node, and a gate connected to the first node, wherein the first transistor includes ninth and tenth transistors, the second transistor includes eleventh and twelfth transistors, the third to sixth and ninth to twelfth transistors are transistors of a first conductivity type, and the seventh and eighth transistors are transistors of a second conductivity type different from the first conductivity type; and the SRAM cell includes a first active region including a third nanosheet constituting a channel, a source, and a drain of the third transistor, the channel extending in a first direction, and a ninth nanosheet constituting a channel, a source, and a drain of the ninth transistor, the channel extending in the first direction. a second active region constituting the channel, source, and drain of the fifth transistor, the channel of which is a fifth nanosheet extending in the first direction, and the channel, source, and drain of the tenth transistor, the channel of which is a tenth nanosheet extending in the first direction; a third active region constituting the channel, source, and drain of the fourth transistor, the channel of which is a fourth nanosheet extending in the first direction, and the channel, source, and drain of the eleventh transistor, the channel of which is a eleventh nanosheet extending in the first direction; a fourth active region constituting the channel, source, and drain of the sixth transistor, the channel of which is a sixth nanosheet extending in the first direction, and the channel, source, and drain of the twelfth transistor, the channel of which is a twelfth nanosheet extending in the first direction; an active region; a fifth active region formed higher in the depth direction than the first to fourth active regions and constituting the channel, source, and drain of the seventh transistor, the channel including a seventh nanosheet extending in the first direction; and a sixth active region formed higher in the depth direction than the first to fourth active regions and constituting the channel, source, and drain of the eighth transistor, the channel including an eighth nanosheet extending in the first direction, wherein the third and ninth nanosheets are arranged side by side in the first direction, the fifth and tenth nanosheets are arranged side by side in the first direction, the fourth and eleventh nanosheets are arranged side by side in the first direction, the sixth and twelfth nanosheets are arranged side by side in the first direction, the seventh and tenth nanosheets overlap in a planar view, and the sixth and eleventh nanosheets overlap in a planar view.

According to the present disclosure, the fifth and sixth active regions are formed higher in the depth direction than the first to fourth active regions. This allows a first conductivity type transistor to be formed in the lower part of the cell and a second conductivity type transistor to be formed in the upper part of the cell, thereby reducing the complexity of the semiconductor memory device manufacturing process and reducing manufacturing costs. Furthermore, since there is no need to space the first conductivity type transistor and the second conductivity type transistor apart, the area of the semiconductor memory device can be reduced.

According to this disclosure, a layout structure of an SRAM cell using a CFET can improve the operating speed of a semiconductor memory device, reduce manufacturing costs, and reduce the area of the semiconductor memory device.

FIG. 2 is a plan view showing an example of a layout structure of an SRAM cell according to the first embodiment. 1 is a cross-sectional view showing an example of a layout structure of an SRAM cell according to the first embodiment; 1 is a cross-sectional view showing an example of a layout structure of an SRAM cell according to the first embodiment; FIG. 2 is a circuit diagram showing the configuration of an SRAM cell according to the first embodiment. 10 shows another example of the configuration of the semiconductor integrated circuit device according to the first embodiment. FIG. 10 is a plan view showing another example of the layout structure of the SRAM cell according to the first embodiment. FIG. 10 is a plan view showing another example of the layout structure of the SRAM cell according to the first embodiment. 3A to 3C are diagrams for explaining a method for manufacturing a semiconductor memory device according to the first embodiment. FIG. 10 is a plan view showing another example of the layout structure of the SRAM cell according to the first embodiment. FIG. 10 is a plan view showing another example of the layout structure of the SRAM cell according to the first embodiment. FIG. 10 is a circuit diagram showing another configuration of the SRAM cell according to the first embodiment. FIG. 10 is a plan view showing another example of the layout structure of the SRAM cell according to the first embodiment. FIG. 10 is a plan view showing an example of a layout structure of an SRAM cell according to a second embodiment.

Embodiments will be described below with reference to the drawings. In the following embodiments, a semiconductor memory device includes a plurality of SRAM cells. At least some of these SRAM cells include nanosheet FETs, and further include a CFET structure in which transistors of different conductivity types (in the embodiment, the lower part of the cell is P conductivity type and the upper part of the cell is N conductivity type) are stacked.

Furthermore, in this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. Furthermore, in this specification, expressions such as "same wiring width" that mean that the width, etc., is the same are considered to include the range of manufacturing variation.

(First embodiment)
(Configuration of SRAM cell)
1 to 3 show examples of the layout structure of an SRAM cell according to the first embodiment, with FIGS. 1(a) and 1(b) being plan views, and FIGS. 2(a) to 2(c) and 3(a) and 3(b) being cross-sectional views in the horizontal direction in a plan view. Specifically, FIG. 1(a) shows the upper part of the cell, i.e., the part including the nanosheet transistor formed on the side farther from the substrate, and FIG. 1(b) shows the lower part of the cell, i.e., the part including the nanosheet transistor formed on the side closer to the substrate. FIG. 2(a) shows the cross section along line X1-X1', FIG. 2(b) shows the cross section along line X2-X2', FIG. 2(c) shows the cross section along line X3-X3', FIG. 3(a) shows the cross section along line X4-X4', and FIG. 3(b) shows the cross section along line X5-X5'.

In the following description, in plan views such as Figure 1, the vertical direction of the drawing is the Y direction (first direction), the horizontal direction of the drawing is the X direction (second direction), and the direction perpendicular to the substrate surface is the Z direction (depth direction).

FIG. 4 is a circuit diagram showing the configuration of an SRAM cell according to the first embodiment. As shown in FIG. 4, the SRAM cell according to this embodiment has a two-port SRAM cell circuit made up of drive transistors PU1 and PU2, load transistors PD1 and PD2, and access transistors PG1 to PG4. The drive transistors PU1 and PU2 and the access transistors PG1 to PG4 are P-type FETs, and the load transistors PD1 and PD2 are N-type FETs.

The drive transistor PU1 is provided between the power supply VDD and the first node NA, and the load transistor PD1 is provided between the first node NA and the power supply VSS. The gates of the drive transistor PU1 and the load transistor PD1 are connected to the second node NB, and they form an inverter INV1. The drive transistor PU2 is provided between the power supply VDD and the second node NB, and the load transistor PD2 is provided between the second node NB and the power supply VSS. The gates of the drive transistor PU2 and the load transistor PD2 are connected to the first node NA, and they form an inverter INV2. In other words, the output of one inverter is connected to the input of the other inverter, thereby forming a latch.

The access transistor PG1 is provided between the first bit line BLA and the first node NA, and its gate is connected to the first word line WLA. The access transistor PG2 is provided between the second bit line BLAX and the second node NB, and its gate is connected to the first word line WLA. The access transistor PG3 is provided between the third bit line BLB and the first node NA, and its gate is connected to the second word line WLB. The access transistor PG4 is provided between the fourth bit line BLBX and the second node NB, and its gate is connected to the second word line WLB. The first and second bit lines BLA and BLAX form a first complementary bit line pair, and the third and fourth bit lines BLB and BLBX form a second complementary bit line pair.

In a two-port SRAM cell circuit, when the first and second bit lines BLA, BLAX constituting the first complementary bit line pair are driven to high and low levels, respectively, and the first word line WLA is driven to low level, a high level is written to the first node NA and a low level is written to the second node NB. On the other hand, when the first and second bit lines BLA, BLAX are driven to low and high levels, respectively, and the first word line WLA is driven to low level, a low level is written to the first node NA and a high level is written to the second node NB. Then, when the first word line WLA is driven to high level while data is written to the first and second nodes NA, NB, the latch state is established and the data written to the first and second nodes NA, NB is retained.

Furthermore, if the first and second bit lines BLA, BLAX are discharged to a low level beforehand and the first word line WLA is driven to a low level, the states of the first and second bit lines BLA, BLAX are determined according to the data written to the first and second nodes NA, NB, making it possible to read data from the SRAM cell. Specifically, if the first node NA is at a high level and the second node NB is at a low level, the first bit line BLA is charged to a high level and the second bit line BLAX is held at a low level. On the other hand, if the first node NA is at a low level and the second node NB is at a high level, the first bit line BLA is held at a low level and the second bit line BLAX is charged to a high level.

Furthermore, when the third and fourth bit lines BLB, BLBX constituting the second complementary bit line pair are driven to high and low levels, respectively, and the second word line WLB is driven to low level, a high level is written to the first node NA and a low level is written to the second node NB. On the other hand, when the third and fourth bit lines BLB, BLBX are driven to low and high levels, respectively, and the second word line WLB is driven to low level, a low level is written to the first node NA and a high level is written to the second node NB. Then, when the second word line WLB is driven to high level while data is written to the first and second nodes NA, NB, the latch state is established and the data written to the first and second nodes NA, NB is retained.

Furthermore, if the third and fourth bit lines BLB, BLBX are discharged to a low level in advance and the second word line WLB is driven to a low level, the states of the third and fourth bit lines BLB, BLBX are determined according to the data written to the first and second nodes NA, NB, allowing data to be read from the SRAM cell. Specifically, if the first node NA is at a high level and the second node NB is at a low level, the third bit line BLB is charged to a high level and the fourth bit line BLBX is held at a low level. On the other hand, if the first node NA is at a low level and the second node NB is at a high level, the third bit line BLB is held at a low level and the fourth bit line BLBX is charged to a high level.

As explained above, the two-port SRAM cell has the functions of writing data to the SRAM cell, retaining data, and reading data from the SRAM cell by controlling the first and second bit lines BLA, BLAX, and the first word line WLA. Furthermore, the two-port SRAM cell has the functions of writing data to the SRAM cell, retaining data, and reading data from the SRAM cell by controlling the third and fourth bit lines BLB, BLBX, and the second word line WLB.

In the following description, the dashed lines running vertically and horizontally in plan views such as Figure 1, and the dashed lines running vertically in cross-sectional views such as Figure 2, indicate grids used for component placement during design. The grids are arranged at equal intervals in the X direction and at equal intervals in the Y direction. The grid spacing may be the same or different in the X and Y directions. The grid spacing may also be different for each layer. Furthermore, each component does not necessarily have to be placed on a grid.

Furthermore, the dotted lines surrounding the cells in plan views such as Figure 1 indicate the cell frame (outer edge of the SRAM cell) of the SRAM cell. SRAM cells are arranged so that the cell frame is in contact with the cell frame of an adjacent cell in the X or Y direction.

Furthermore, in plan views such as Figure 1, on both sides of the SRAM cell in the X direction, SRAM cells inverted in the X direction are arranged. On both sides of the SRAM cell in the Y direction, SRAM cells inverted in the Y direction are arranged.

As shown in Figure 1(b), the backside of the semiconductor chip on which the transistors are formed has a wiring layer called BM0 (Backside Metal 0). The BM0 wiring layer corresponds to the backside wiring layer.

The BM0 wiring layer is formed with power supply wiring 11 that extends in the Y direction from both the top and bottom of the cell in the drawing. The power supply wiring 11 supplies the power supply voltage VDD.

In a P-type transistor region on an N-type well (NWell) (not shown), multiple active regions that form the channel, source, and drain of the P-type transistor are formed. Specifically, active regions P1 to P4 are formed in the P-type transistor region. Active regions P2 and P3 overlap with power supply wiring 11 in a plan view.

In the P-type transistor region, access transistors PG1 to PG4 and drive transistors PU1 and PU2 are formed. Access transistors PG1 and PG3, drive transistors PU1 and PU2, and access transistors PG2 and PG4 each have a channel structure consisting of two overlapping sheets in a plan view, with nanosheets 21 to 26 extending in the Y direction.

In active region P2, the source portion of drive transistor PU1 is connected to power supply wiring 11 via via 91, which is located at a position overlapping power supply wiring 11 in a planar view. In active region P3, the source portion of load transistor PU2 is connected to power supply wiring 11 via via 92, which is located at a position overlapping power supply wiring 11 in a planar view.

As shown in Figure 1(a), multiple active regions that form the channel, source, and drain of the N-type transistor are formed in the N-type transistor region. Specifically, active regions N1 to N4 are formed in the N-type transistor region. Active regions N1 to N4 are each located higher in the Z direction than active regions P1 to P4. Active regions N1 to N4 overlap with active regions P1 to P4, respectively, in a planar view.

In the N-type transistor region, load transistors PD1 and PD2 and dummy transistors DN1 to DN4 are formed. Load transistors PD1 and PD2 and dummy transistors DN1 to DN4 each have a channel consisting of two overlapping sheet structures in a plan view, with nanosheets 27, 28, and 30a to 30d extending in the Y direction. Note that dummy transistors DN1 to DN4 are transistors that do not have a logic function.

The width in the X direction of nanosheets 23, 24, 27, and 28 is twice the width in the X direction of nanosheets 21, 22, 25, 26, and 30a to 30d.

In the active region, the source and drain portions on both sides of the nanosheet are formed, for example, by epitaxial growth from the nanosheet.

Gate wiring (Gate) 31-36 are formed extending in the X direction. Gate wiring 31 surrounds the outer peripheries of nanosheets 21 and 30a in the X and Z directions. Gate wiring 32 surrounds the outer peripheries of nanosheets 24 and 28 in the X and Z directions. Gate wiring 33 surrounds the outer peripheries of nanosheets 25 and 30b in the X and Z directions. Gate wiring 34 surrounds the outer peripheries of nanosheets 22 and 30c in the X and Z directions. Gate wiring 35 surrounds the outer peripheries of nanosheets 23 and 27 in the X and Z directions. Gate wiring 36 surrounds the outer peripheries of nanosheets 26 and 30d in the X and Z directions. Gate wiring 31 corresponds to the gates of access transistor PG1 and dummy transistor DN1. Gate wiring 32 corresponds to the gates of drive transistor PU2 and load transistor PD2. Gate wiring 33 corresponds to the gates of access transistor PG2 and dummy transistor DN2. Gate wiring 34 corresponds to the gates of access transistor PG3 and dummy transistor DN3. Gate wiring 35 corresponds to the gates of drive transistor PU1 and load transistor PD1. Gate wiring 36 corresponds to the gates of access transistor PG4 and dummy transistor DN4.

As shown in Figure 1(b), local interconnects (LI) 41-46 extending in the X direction are formed at the bottom of the cell. Local interconnect 41 is connected to the source of access transistor PG1 in active region P1. Local interconnect 42 is connected to the source of access transistor PG2 in active region P4. Local interconnect 43 is connected to the drain of access transistor PG1 in active region P1, the drain of access transistor PG3 in active region P1, and the drain of drive transistor PU1 in active region P2. Local interconnect 44 is connected to the drain of drive transistor PU2 in active region P3, the drain of access transistor PG2 in active region P4, and the drain of access transistor PG4 in active region P4. Local interconnect 45 is connected to the source of access transistor PG3 in active region P1. Local interconnect 46 is connected to the source of access transistor PG4 in active region P4.

As shown in Figure 1(a), local wiring 47-50 extending in the X direction are formed above the cell. Local wiring 47 is connected to the portion that will become the source of load transistor PD2 in active region N3. Local wiring 48 is connected to the portion that will become the drain of load transistor PD1 in active region N2. Local wiring 49 is connected to the portion that will become the drain of load transistor PD2 in active region N3. Local wiring 50 is connected to the portion that will become the source of load transistor PD1 in active region N2.

Local wiring 48 is connected to gate wiring 32 via shared contact 51. Local wiring 48 is connected to local wiring 43 via via 52. Local wiring 49 is connected to gate wiring 35 via shared contact 53. Local wiring 49 is connected to local wiring 44 via via 54. Note that gate wiring 32, local wirings 43 and 48, shared contact 51, and via 52 correspond to the first node NA. Gate wiring 35, local wirings 44 and 49, shared contact 53, and via 54 correspond to the second node NB.

Power supply wiring 61 and wiring 62-65 extending in the Y direction from the top to the bottom of the cell in the drawing are formed in the M1 wiring layer, which is a metal wiring layer above the active regions N1-N4. Wiring 66-69 are also formed. Power supply wiring 61 supplies power supply voltage VSS. Wiring 62-65 correspond to the first bit line BLA, third bit line BLB, second bit line BLAX, and fourth bit line BLBX, respectively.

In a planar view, power supply wiring 61 overlaps with active regions P2, P3, N2, and N3 and power supply wiring 11. Power supply wiring 61 is connected to local wiring 47 through via 55 and to local wiring 50 through via 56. Via 55 is formed in the area where power supply wiring 61 and active region N3 overlap in a planar view. Via 56 is formed in the area where power supply wiring 61 and active region N2 overlap in a planar view.

Wire 62 is connected to local wire 41 via via 57. Wire 63 is connected to local wire 45 via via 58. Wire 64 is connected to local wire 42 via via 59. Wire 65 is connected to local wire 46 via via 60.

Wiring 71 and 72 extending in the X direction from the left and right ends of the cell in the drawing are formed in the M2 wiring layer, which is the layer above the M1 wiring layer. Wiring 71 and 72 correspond to the first word line WLA and the second word line WLB, respectively. Wiring 71 is connected to gate wiring 31 via via 81, wiring 66, and via 60a. Wiring 71 is connected to gate wiring 33 via via 82, wiring 67, and via 60b. Wiring 72 is connected to gate wiring 34 via via 83, wiring 68, and via 60c. Wiring 72 is connected to gate wiring 36 via via 84, wiring 69, and via 60d.

With the above configuration, power supply wiring 11 that supplies power supply voltage VDD is formed in the BM0 wiring layer, which is the wiring layer on the back side of the transistor. Power supply wiring 11 overlaps active areas P2 and P3 in a planar view, and is connected to each other by vias 91 and 92 provided in the overlapping areas. Therefore, because the active area (transistor) and power supply wiring can be arranged to overlap, the wiring width of power supply wiring 11 that supplies power supply voltage VDD can be increased, and the wiring resistance of the power supply wiring can be reduced. This can improve the operating speed and operational stability of the semiconductor memory device.

Furthermore, P-type active regions P1 to P4 are formed in the lower part of the cell. N-type active regions N1 to N4 are formed in the upper part of the cell. As a result, only P-type nanosheet transistors are formed in the lower part of the cell, and only N-type nanosheet transistors are formed in the upper part of the cell, which reduces the complexity of the semiconductor memory device manufacturing process and reduces manufacturing costs. Furthermore, because there is no need to space the P-type nanosheet transistors and the N-type nanosheet transistors apart, the area of the semiconductor memory device can be reduced.

Furthermore, the X-direction width of nanosheets 23, 24, 27, and 28 is twice the X-direction width of nanosheets 21, 22, 25, and 26. That is, the ratio of the width of the nanosheets in load transistors PD1 and PD2 to the width of the nanosheets in drive transistors PU1 and PU2 to the width of the nanosheets in access transistors PG1 to PG4 is 4:4:2. Here, the drive capability of load transistors PD1 and PD2 is kept lower than that of drive transistors PU1 and PU2 by adjusting the concentration of N-type impurities contained in active regions N2 and N3. For example, the concentration of N-type impurities contained in active regions N2 and N3 is adjusted so that the drive capability of load transistors PD1 and PD2 is 1/4 of the drive capability of drive transistors PU1 and PU2. As a result, the ratio of the drive capabilities of the load transistors PD1 and PD2, the drive transistors PU1 and PU2, and the access transistors PG1 to PG4 is 1:4:2. This ensures stable operation of the SRAM cells (static noise margin) when the word lines are driven.

(Other configuration examples)
Fig. 5(a) shows another example of the configuration of the semiconductor integrated circuit device according to the first embodiment. The semiconductor integrated circuit device 100 shown in Fig. 5(a) is configured by stacking a first semiconductor chip 101 (chip A) and a second semiconductor chip 102 (chip B). Chip A has the SRAM cells and the like arranged therein. Chip B has power wiring formed in a wiring layer provided on its surface. Chip B is attached to the back side of chip A using bumps and the like.

Figure 5(b) shows a cross section of the SRAM cell of Figure 1 taken along line X1-X1' in this configuration example. As shown in Figure 5(b), power supply wiring 11 that supplies VDD is formed in a wiring layer provided on the surface of chip B. Power supply wiring 11 is connected to active region P3 of chip A via via 92. Although not shown in the figure, power supply wiring 11 is also connected to active region P2 of chip A via via 91.

(Variation 1)
6A and 6B are plan views showing another example of the layout structure of the SRAM cell according to the first embodiment, in which Fig. 6A shows the upper part of the cell and Fig. 6B shows the lower part of the cell.

In Figure 6, compared to Figure 1, wires 63 and 65 in the M1 wiring layer are omitted, and wires 12 and 13 are formed in the BM0 wiring layer, extending in the Y direction from the top to the bottom of the cell in the drawing.

Wiring 12 and 13 correspond to the third bit line BLB and the fourth bit line BLBX, respectively. Wiring 12 overlaps with active regions N1 and P1 and wiring 62 in a planar view. Wiring 13 overlaps with active regions N4 and P4 and wiring 64 in a planar view. Wiring 12 is connected to the source of access transistor PG3 in active region P1 via via 93, which is located at the overlapping position in a planar view. Wiring 13 is connected to the source of access transistor PG4 in active region P4 via via 94, which is located at the overlapping position in a planar view.

In the configuration of FIG. 6, wiring 12 and 13 corresponding to the third bit line BLB and the fourth bit line BLBX, respectively, are formed in the BM0 wiring layer. Wiring 62 and 64 corresponding to the first bit line BLA and the second bit line BLAX, respectively, are formed in the M1 wiring layer. As a result, the wiring corresponding to the third bit line BLB and the fourth bit line BLBX and the wiring corresponding to the first bit line BLA and the second bit line BLAX are formed in different wiring layers, thereby suppressing crosstalk noise between the third bit line BLB and the fourth bit line BLBX and the first bit line BLA and the second bit line BLAX. This can improve the operational stability of the semiconductor memory device.

Furthermore, because the wiring corresponding to the third bit line BLB and the fourth bit line BLBX and the wiring corresponding to the first bit line BLA and the second bit line BLAX are formed in different wiring layers, the wiring width of the wirings 12, 13, 62, and 64 can be increased, thereby improving the operating speed of the semiconductor memory device.

Otherwise, the same effects as in Figure 1 can be achieved.

(Variation 2)
7A and 7B are plan views showing another example of the layout structure of the SRAM cell according to the first embodiment, in which Fig. 7A shows the upper part of the cell and Fig. 7B shows the lower part of the cell.

In Figure 7, compared to Figure 1, nanosheets 27a and 28a are arranged instead of nanosheets 27 and 28.

Nanosheets 27a and 28a correspond to the channels of load transistors PD1 and PD2, respectively. The X-direction width of nanosheets 27a and 28a is half the X-direction width of nanosheets 23 and 24 (27 and 28). In other words, the drive capability of load transistors PD1 and PD2 in FIG. 7 is lower than the drive capability of load transistors PD1 and PD2 in FIG. 1. This reduces the drive capability of load transistors PD1 and PD2. The X-direction width of nanosheets 27a and 28a may be determined according to the drive capability of load transistors PD1 and PD2, and may be larger or smaller than the X-direction width of nanosheets 21, 22, 25, and 26, for example.

FIG. 8 is a diagram illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Specifically, FIGS. 8(a) to 8(c) are cross-sectional views taken along line X6-X6' in FIG. 7.

In Figure 7, nanosheet 23 (24) of drive transistor PU1 (PU2) and nanosheet 27a (28a) of load transistor PD1 (PD2) are stacked in the Z direction. As described above, the X-direction width of nanosheet 27a (28a) is half the X-direction width of nanosheet 23 (24). In other words, in Figure 7, nanosheets with different X-direction widths are stacked in the Z direction. In the following explanation, Figures 8(a) to (c) will be used to explain a method for manufacturing a semiconductor memory device in which nanosheets with different X-direction widths are stacked in the Z direction.

First, as shown in FIG. 8(a), a laminated semiconductor 210 is formed on a semiconductor substrate 200. The laminated semiconductor 210 is formed by alternately stacking semiconductor layers 220 and 230. Here, silicon (Si) is used as the material for the semiconductor layer 220, and a silicon germanium alloy (SiGe) is used as the material for the semiconductor layer 230.

In Figure 8, the laminated semiconductor 210 includes four semiconductor layers 220. Of the four semiconductor layers 220, the two semiconductor layers 220 (220a) at the top of the drawing correspond to the nanosheet 27a at the top of the cell, and the two semiconductor layers 220 (220b) at the bottom of the drawing correspond to the nanosheet 23 at the bottom of the cell.

After forming the laminated semiconductor 210 on the semiconductor substrate 200, a mask 241 is formed above the laminated semiconductor 210 in the figure. The width and position of the mask 241 in the X and Y directions are formed to match the width and position of the nanosheet 23 in the X and Y directions. Then, anisotropic etching is performed to remove the laminated semiconductor 210 on both the left and right sides of the mask 241 in the X direction in the figure. Thereafter, the mask 241 is removed.

Next, as shown in FIG. 8(b), a mask 242 is formed in the upper right portion of the laminated semiconductor 210. The width and position of the mask 242 in the X and Y directions are formed to match the width and position of the nanosheet 27a in the X and Y directions. The laminated semiconductor 210 on the left side of the mask 242 in the drawing is then removed by anisotropic etching. Specifically, the upper portion of the laminated semiconductor 210 located on the left side of the mask 242 in the drawing, i.e., the semiconductor layer 220a and the semiconductor layer 230, are removed. After the mask 242 is removed, the load transistor PD1 and the drive transistor PU1 are formed.

The manufacturing method described above makes it possible to manufacture a semiconductor memory device in which nanosheets with different widths in the X direction are stacked in the Z direction, as shown in Figure 8(c).

In FIG. 8(b), if mask 242 is not formed on the upper part of laminated semiconductor 210, the upper part of laminated semiconductor 210, i.e., semiconductor layer 220a and semiconductor layer 230, will be completely removed. This allows nanosheets (transistors) to be formed only on the lower part of the cell, without forming nanosheets (transistors) on the upper part of the cell.

(Variation 3)
9A and 9B are plan views showing another example of the layout structure of the SRAM cell according to the first embodiment, in which Fig. 9A shows the upper part of the cell and Fig. 9B shows the lower part of the cell.

In Figure 9, compared to Figure 1, drive transistors PU1 and PU2 are each composed of two nanosheet FETs. Specifically, drive transistor PU1 is composed of transistors PU11 and PU12. Drive transistor PU2 is composed of transistors PU21 and PU22. Also, nanosheets 27b and 28b are arranged in place of nanosheets 27 and 28.

As shown in Figure 9(b), active regions P5 to P8 are formed in the P-type transistor region. Active regions P5 to P8 overlap with power supply wiring 11 in plan view.

Transistors PU11, PU12, PU21, and PU22 are formed in the P-type transistor region. Transistors PU11, PU12, PU21, and PU22 each have nanosheets 23a, 23b, 24a, and 24b extending in the Y direction.

In active region P5, the source of transistor PU11 is connected to power supply wiring 11 via via 95, which is located at a position overlapping power supply wiring 11 in a planar view. In active region P6, the source of transistor PU12 is connected to power supply wiring 11 via via 96, which is located at a position overlapping power supply wiring 11 in a planar view. In active region P7, the source of transistor PU21 is connected to power supply wiring 11 via via 97, which is located at a position overlapping power supply wiring 11 in a planar view. In active region P8, the source of transistor PU22 is connected to power supply wiring 11 via via 98, which is located at a position overlapping power supply wiring 11 in a planar view.

As shown in Figure 9(a), active regions N5 to N8 are formed in the N-type transistor region. Active regions N5 to N8 are respectively arranged above active regions P5 to P8 in the Z direction. Active regions N5 to N8 overlap with active regions P5 to P8, respectively, in a plan view.

In the N-type transistor region, load transistors PD1 and PD2 and dummy transistors DN5 and DN6 are formed. Load transistors PD1 and PD2 and dummy transistors DN5 and DN6 have nanosheets 27b, 28b, 30e, and 30f, respectively, extending in the Y direction. Note that dummy transistors DN5 and DN6 are transistors that do not have a logic function.

Nanosheets 21, 22, 23a, 23b, 24a, 24b, 25, 26, 27b, 28b, and 30a-30f all have the same width in the X direction.

Gate wiring 32 surrounds the outer peripheries of nanosheets 24a, 24b, 28b, and 30f in the X and Z directions. Gate wiring 35 surrounds the outer peripheries of nanosheets 23a, 23b, 27b, and 30e in the X and Z directions. Gate wiring 32 corresponds to the gates of transistors PU21, PU22, load transistor PD2, and dummy transistor DN6. Gate wiring 35 corresponds to the gates of transistors PU11, PU12, load transistor PD1, and dummy transistor DN5.

The portion that becomes the drain of transistor PU11 in active region P5 and the portion that becomes the drain of transistor PU12 in active region P6 are connected to the portion that becomes the drain of access transistors PG1 and PG3 in active region P1, the portion that becomes the drain of load transistor PD1 in active region N5, and gate wiring 32 via local wiring 43, via 52, local wiring 48, and shared contact 51. The portion that becomes the drain of transistor PU21 in active region P7 and the portion that becomes the drain of transistor PU22 in active region P8 are connected to the portion that becomes the drain of access transistors PG2 and PG4 in active region P4, the portion that becomes the drain of load transistor PD2 in active region N8, and gate wiring 35 via local wiring 44, via 54, local wiring 49, and shared contact 53.

The source of load transistor PD1 in active region N5 is connected to power supply wiring 61 via local wiring 50 and via 56. The source of load transistor PD2 in active region N8 is connected to power supply wiring 61 via local wiring 47 and via 55.

In the configuration of FIG. 9, transistors PU11 and PU12 that make up drive transistor PU1 have nanosheets 23a and 23b, respectively. Transistors PU21 and PU22 that make up drive transistor PU2 have nanosheets 24a and 24b, respectively. Load transistors PD1 and PD2 have nanosheets 27b and 28b, respectively. Nanosheets 23a, 23b, 24a, 24b, 27b, 30e, 30f, and 28b have the same width in the X direction. This allows the drive capability of drive transistors PU1 and PU2 to be greater than the drive capability of load transistors PD1 and PD2.

Furthermore, nanosheets 23a, 23b, 24a, and 24b overlap nanosheets 27b, 30e, 30f, and 28b, respectively, in a planar view. This ensures that the widths in the X direction of the nanosheets stacked in the Z direction are the same in the upper and lower cell sections, which helps prevent the manufacturing process from becoming too complicated and the manufacturing costs from increasing.

Note that although the widths of nanosheets 23a, 23b, 24a, and 24b in the X direction are the same, they do not have to be the same.

Alternatively, as in the configuration of Figure 7, the wiring 63 and 65 in the M1 wiring layer may be omitted, and wiring 12 and 13 corresponding to the third bit line BLB and the fourth bit line BLBX, respectively, may be formed in the BM0 wiring layer.

(Variation 4)
10A and 10B are plan views showing another example of the layout structure of the SRAM cell according to the first embodiment, in which Fig. 10A shows the upper part of the cell and Fig. 10B shows the lower part of the cell.

In Figure 10, the circuitry configured in the SRAM cell is different from that in Figure 1.

FIG. 11 is a circuit diagram showing another configuration of the SRAM cell according to the first embodiment. As shown in FIG. 11, the SRAM cell according to this modification has a two-port SRAM cell circuit made up of load transistors PU1 and PU2, drive transistors PD1 and PD2, and access transistors PG1 to PG4. The load transistors PU1 and PU2 are P-type FETs, and the drive transistors PD1 and PD2 and access transistors PG1 to PG4 are N-type FETs.

The load transistor PU1 is provided between the power supply VDD and the first node NA, and the drive transistor PD1 is provided between the first node NA and the power supply VSS. The gates of the load transistor PU1 and the drive transistor PD1 are connected to the second node NB, and they form an inverter INV1. The load transistor PU2 is provided between the power supply VDD and the second node NB, and the drive transistor PD2 is provided between the second node NB and the power supply VSS. The gates of the load transistor PU2 and the drive transistor PD2 are connected to the first node NA, and they form an inverter INV2. In other words, the output of one inverter is connected to the input of the other inverter, thereby forming a latch.

The access transistor PG1 is provided between the first bit line BLA and the first node NA, and its gate is connected to the first word line WLA. The access transistor PG2 is provided between the second bit line BLAX and the second node NB, and its gate is connected to the first word line WLA. The access transistor PG3 is provided between the third bit line BLB and the first node NA, and its gate is connected to the second word line WLB. The access transistor PG4 is provided between the fourth bit line BLBX and the second node NB, and its gate is connected to the second word line WLB. The first and second bit lines BLA and BLAX form a first complementary bit line pair, and the third and fourth bit lines BLB and BLBX form a second complementary bit line pair.

In a two-port SRAM cell circuit, when the first and second bit lines BLA, BLAX constituting the first complementary bit line pair are driven to high and low levels, respectively, and the first word line WLA is driven to high level, a high level is written to the first node NA and a low level is written to the second node NB. On the other hand, when the first and second bit lines BLA, BLAX are driven to low and high levels, respectively, and the first word line WLA is driven to high level, a low level is written to the first node NA and a high level is written to the second node NB. Then, when the first word line WLA is driven to low level while data is written to the first and second nodes NA, NB, the latch state is established and the data written to the first and second nodes NA, NB is retained.

Furthermore, when the first and second bit lines BLA, BLAX are precharged to a high level and the first word line WLA is driven to a high level, the states of the first and second bit lines BLA, BLAX are determined according to the data written to the first and second nodes NA, NB, allowing data to be read from the SRAM cell. Specifically, if the first node NA is at a high level and the second node NB is at a low level, the first bit line BLA remains at a high level and the second bit line BLAX is discharged to a low level. On the other hand, if the first node NA is at a low level and the second node NB is at a high level, the first bit line BLA is discharged to a low level and the second bit line BLAX remains at a high level.

Furthermore, when the third and fourth bit lines BLB, BLBX constituting the second complementary bit line pair are driven to high and low levels, respectively, and the second word line WLB is driven to high level, a high level is written to the first node NA and a low level is written to the second node NB. On the other hand, when the third and fourth bit lines BLB, BLBX are driven to low and high levels, respectively, and the second word line WLB is driven to high level, a low level is written to the first node NA and a high level is written to the second node NB. Then, when the second word line WLB is driven to low level while data is written to the first and second nodes NA, NB, the latch state is established and the data written to the first and second nodes NA, NB is retained.

Furthermore, when the third and fourth bit lines BLB, BLBX are precharged to a high level and the second word line WLB is driven to a high level, the states of the third and fourth bit lines BLB, BLBX are determined according to the data written to the first and second nodes NA, NB, allowing data to be read from the SRAM cell. Specifically, when the first node NA is at a high level and the second node NB is at a low level, the third bit line BLB remains at a high level and the fourth bit line BLBX is discharged to a low level. On the other hand, when the first node NA is at a low level and the second node NB is at a high level, the third bit line BLB is discharged to a low level and the fourth bit line BLBX remains at a high level.

As explained above, the two-port SRAM cell has the functions of writing data to the SRAM cell, retaining data, and reading data from the SRAM cell by controlling the first and second bit lines BLA, BLAX, and the first word line WLA. Furthermore, the two-port SRAM cell has the functions of writing data to the SRAM cell, retaining data, and reading data from the SRAM cell by controlling the third and fourth bit lines BLB, BLBX, and the second word line WLB.

As shown in Figure 10(b), power supply wiring 11 is formed in the BM0 wiring layer, extending in the Y direction from the top to the bottom of the cell in the drawing. Power supply wiring 11 supplies the power supply voltage VDD.

Active regions P1 to P4 are formed in the P-type transistor region. Active regions P2 and P3 overlap with power supply wiring 11 in plan view.

In the P-type transistor region, load transistors PU1 and PU2 and dummy transistors DP1 to DP4 are formed. Dummy transistors DP1 and DP3, load transistors PU1 and PU2, and dummy transistors DP2 and DP4 each have nanosheets 21 to 26 extending in the Y direction as their channels. Note that dummy transistors DP1 to DP4 are transistors that do not have a logic function.

As shown in Figure 10(a), active regions N1 to N4 are formed in the N-type transistor region. Active regions N1 to N4 are respectively arranged above active regions P1 to P4 in the Z direction. Active regions N1 to N4 overlap with active regions P1 to P4, respectively, in a plan view.

Drive transistors PD1 and PD2 and access transistors PG1 to PG4 are formed in the N-type transistor region. Drive transistors PD1 and PD2 and access transistors PG1 to PG4 each have nanosheets 27, 28, and 30a to 30d extending in the Y direction as their channels.

The width in the X direction of nanosheets 23, 24, 27, and 28 is twice the width in the X direction of nanosheets 21, 22, 25, 26, and 30a to 30d.

Gate wiring 31 to 36 are formed extending in the X direction. Gate wiring 31 surrounds the outer peripheries of nanosheets 21 and 30a in the X and Z directions. Gate wiring 32 surrounds the outer peripheries of nanosheets 24 and 28 in the X and Z directions. Gate wiring 33 surrounds the outer peripheries of nanosheets 25 and 30b in the X and Z directions. Gate wiring 34 surrounds the outer peripheries of nanosheets 22 and 30c in the X and Z directions. Gate wiring 35 surrounds the outer peripheries of nanosheets 23 and 27 in the X and Z directions. Gate wiring 36 surrounds the outer peripheries of nanosheets 26 and 30d in the X and Z directions. Gate wiring 31 corresponds to the gates of access transistor PG1 and dummy transistor DP1. Gate wiring 32 corresponds to the gates of load transistor PU2 and drive transistor PD2. Gate wiring 33 corresponds to the gates of access transistor PG2 and dummy transistor DP2. Gate wiring 34 corresponds to the gates of access transistor PG3 and dummy transistor DP3. Gate wiring 35 corresponds to the gates of load transistor PU1 and drive transistor PD1. Gate wiring 36 corresponds to the gates of access transistor PG4 and dummy transistor DP4.

As shown in Figure 10(b), local wiring 43 and 44 extending in the X direction are formed below the cell. Local wiring 43 is connected to the portion of active region P2 that will become the drain of load transistor PU1. Local wiring 44 is connected to the portion of active region P3 that will become the drain of load transistor PU2.

As shown in Figure 10(a), local interconnections 47-50 and 50a-50d extending in the X direction are formed above the cell. Local interconnection 47 is connected to the source of drive transistor PD2 in active region N3. Local interconnection 48 is connected to the drain of access transistor PG1 in active region N1, the drain of access transistor PG3 in active region N1, and the drain of drive transistor PD1 in active region N2. Local interconnection 49 is connected to the drain of drive transistor PD2 in active region N3, the drain of access transistor PG2 in active region N4, and the drain of access transistor PG4 in active region N4. Local interconnection 50 is connected to the source of drive transistor PD1 in active region N2. Local interconnection 50a is connected to the source of access transistor PG1 in active region N1. Local interconnection 50b is connected to the source of access transistor PG2 in active region N4. Local wiring 50c is connected to the source of access transistor PG3 in active region N1. Local wiring 50d is connected to the source of access transistor PG4 in active region N4.

Local wiring 48 is connected to gate wiring 32 via shared contact 51. Local wiring 48 is connected to local wiring 43 via via 52. Local wiring 49 is connected to gate wiring 35 via shared contact 53. Local wiring 49 is connected to local wiring 44 via via 54. Note that gate wiring 32, local wirings 43 and 48, shared contact 51, and via 52 correspond to the first node NA. Gate wiring 35, local wirings 44 and 49, shared contact 53, and via 54 correspond to the second node NB.

The M1 wiring layer is formed with power supply wiring 61 and wiring 62-65, which extend in the Y direction from the top to the bottom of the cell in the drawing. Wiring 66-69 is also formed. Power supply wiring 61 supplies power supply voltage VSS. Wiring 62-65 correspond to the first bit line BLA, third bit line BLB, second bit line BLAX, and fourth bit line BLBX, respectively.

In a planar view, power supply wiring 61 overlaps with active regions N2, N3, P2, and P3, and power supply wiring 11. Power supply wiring 61 is connected to local wiring 47 through via 55, and to local wiring 50 through via 56. Via 55 is formed in the area where power supply wiring 61 and active region N3 overlap in a planar view. Via 56 is formed in the area where power supply wiring 61 and active region N2 overlap in a planar view.

Wire 62 is connected to local wire 50a via via 60e. Wire 63 is connected to local wire 50c via via 60f. Wire 64 is connected to local wire 50b via via 60g. Wire 65 is connected to local wire 50d via via 60h.

In the M2 wiring layer, wiring 71 and 72 are formed, extending in the X direction from the left and right ends of the cell in the drawing. Wiring 71 and 72 correspond to the first word line WLA and the second word line WLB, respectively. Wiring 71 is connected to gate wiring 31 via via 81, wiring 66, and via 60a. Wiring 71 is connected to gate wiring 33 via via 82, wiring 67, and via 60b. Wiring 72 is connected to gate wiring 34 via via 83, wiring 68, and via 60c. Wiring 72 is connected to gate wiring 36 via via 84, wiring 69, and via 60d.

In the configuration of Figure 10, power supply wiring 11 that supplies power supply voltage VDD is formed in the BM0 wiring layer, which is the wiring layer on the back side of the transistor. Power supply wiring 11 overlaps active areas P2 and P3 in a planar view, and is connected to each other by vias 91 and 92 provided in the overlapping areas. Therefore, because the active area (transistor) and power supply wiring can be arranged to overlap, the wiring width of power supply wiring 11 that supplies power supply voltage VDD can be increased, and the wiring resistance of the power supply wiring can be reduced. This can improve the operating speed and stability of the semiconductor memory device.

Furthermore, P-type active regions P1 to P4 are formed in the lower part of the cell. N-type active regions N1 to N4 are formed in the upper part of the cell. As a result, only P-type nanosheet transistors are formed in the lower part of the cell, and only N-type nanosheet transistors are formed in the upper part of the cell, which reduces the complexity of the semiconductor memory device manufacturing process and reduces manufacturing costs. Furthermore, because there is no need to space the P-type nanosheet transistors and the N-type nanosheet transistors apart, the area of the semiconductor memory device can be reduced.

Furthermore, the X-direction width of nanosheets 23, 24, 27, and 28 is twice the X-direction width of nanosheets 21, 22, 25, and 26. That is, the ratio of the width of the nanosheets in load transistors PU1 and PU2 to the width of the nanosheets in drive transistors PD1 and PD2 to the width of the nanosheets in access transistors PG1 to PG4 is 4:4:2. Here, the drive capability of load transistors PU1 and PU2 is kept lower than that of drive transistors PD1 and PD2 by adjusting the concentration of P-type impurities contained in active regions P2 and P3. For example, the concentration of P-type impurities contained in active regions P2 and P3 is adjusted so that the drive capability of load transistors PU1 and PU2 is 1/4 of the drive capability of drive transistors PD1 and PD2. As a result, the ratio of the drive capabilities of the load transistors PU1 and PU2, the drive transistors PD1 and PD2, and the access transistors PG1 to PG4 is 1:4:2. This ensures stable operation of the SRAM cells (static noise margin) when the word lines are driven.

(Variation 5)
12A and 12B are plan views showing another example of the layout structure of the SRAM cell according to the first embodiment, in which Fig. 12A shows the upper part of the cell and Fig. 12B shows the lower part of the cell.

In Figure 12, compared to Figure 10, drive transistors PD1 and PD2 are each composed of two nanosheet FETs. Specifically, drive transistor PD1 is composed of transistors PD11 and PD12. Drive transistor PD2 is composed of transistors PD21 and PD22. Furthermore, nanosheets 23c and 24c are arranged in place of nanosheets 23 and 24.

As shown in Figure 12(b), active regions P5 to P8 are formed in the P-type transistor region. Active regions P5 to P8 overlap with power supply wiring 11 in plan view.

In the P-type transistor region, load transistors PU1 and PU2 and dummy transistors DP5 and DP6 are formed. Load transistors PU1 and PU2 and dummy transistors DP5 and DP6 have nanosheets 23c, 24c, 30g, and 30h extending in the Y direction, respectively. Note that dummy transistors DP5 and DP6 are transistors that do not have a logic function.

In active region P5, the source of load transistor PU1 is connected to power supply wiring 11 via via 91, which is located at a position overlapping power supply wiring 11 in a planar view. In active region P8, the source of load transistor PU2 is connected to power supply wiring 11 via via 92, which is located at a position overlapping power supply wiring 11 in a planar view.

As shown in Figure 12(a), active regions N5 to N8 are formed in the N-type transistor region. Active regions N5 to N8 are respectively arranged above active regions P5 to P8 in the Z direction. Active regions N5 to N8 overlap with active regions P5 to P8, respectively, in a plan view.

Transistors PD11, PD12, PD21, and PD22 are formed in the N-type transistor region. Transistors PD11, PD12, PD21, and PD22 have nanosheets 27c, 27d, 28c, and 28d, respectively, extending in the Y direction.

Nanosheets 21, 22, 23c, 24c, 25, 26, 27c, 27d, 28c, 28d, 30a-30d, 30g, and 30h have the same width in the X direction.

Gate wiring 32 surrounds the outer peripheries of nanosheets 24c, 28c, 28d, and 30h in the X and Z directions. Gate wiring 35 surrounds the outer peripheries of nanosheets 23c, 27c, 27d, and 30g in the X and Z directions. Gate wiring 32 corresponds to the gates of transistors PD21, PD22, load transistor PU2, and dummy transistor DP6. Gate wiring 35 corresponds to the gates of transistors PD11, PD12, load transistor PU1, and dummy transistor DP5.

The drain of load transistor PU1 in active region P5 is connected via local wiring 43, via 52, local wiring 48, and shared contact 51 to the drains of access transistors PG1 and PG3 in active region N1, the drain of transistor PD11 in active region N5, the drain of transistor PD12 in active region N6, and gate wiring 32. The drain of load transistor PU2 in active region P8 is connected via local wiring 44, via 54, local wiring 49, and shared contact 53 to the drains of access transistors PG2 and PG4 in active region N4, the drain of transistor PD21 in active region N7, the drain of transistor PD22 in active region N8, and gate wiring 35.

In the configuration of FIG. 12, transistors PD11 and PD12 that constitute drive transistor PD1 have nanosheets 27c and 27d, respectively. Transistors PD21 and PD22 that constitute drive transistor PD2 have nanosheets 28c and 28d, respectively. Load transistors PU1 and PU2 have nanosheets 23c and 24c, respectively. Nanosheets 23c, 24c, 27c, 27d, 28c, 28d, 30g, and 30h have the same width in the X direction. This allows the drive capability of drive transistors PD1 and PD2 to be greater than the drive capability of load transistors PU1 and PU2.

Furthermore, nanosheets 23c, 30g, 30h, and 24c overlap nanosheets 27c, 27d, 28c, and 28d in a planar view. This ensures that the widths of the stacked nanosheets in the X direction are the same in the upper and lower parts of the cell, which helps to prevent the manufacturing process from becoming too complicated and the manufacturing costs from increasing.

Note that although the widths of nanosheets 27c, 27d, 28c, and 28d in the X direction are the same, they do not have to be the same.

Alternatively, as in the configuration of Figure 7, the wiring 63 and 65 in the M1 wiring layer may be omitted, and wiring 12 and 13 corresponding to the third bit line BLB and the fourth bit line BLBX, respectively, may be formed in the BM0 wiring layer.

Second Embodiment
13A and 13B are plan views showing an example of the layout structure of an SRAM cell according to the second embodiment. Specifically, FIG. 13A shows the upper part of the cell, and FIG. 13B shows the lower part of the cell. In FIG. 13, the circuit of FIG. 4 is configured in the SRAM cell.

In Figure 13, compared to Figure 1, drive transistors PU1 and PU2 are each composed of two nanosheet FETs. Specifically, drive transistor PU1 is composed of transistors PU11 and PU12. Drive transistor PU2 is composed of transistors PU21 and PU22. Also, the arrangement of access transistors PG1 to PG4 is different.

As shown in Figure 13(b), the BM0 wiring layer is formed with power supply wiring 111 and wiring 112-115, which extend in the Y direction from the top to the bottom of the cell in the drawing. Power supply wiring 111 supplies power supply voltage VDD. Wiring 112-115 correspond to the first bit line BLA, third bit line BLB, second bit line BLAX, and fourth bit line BLBX, respectively.

Active regions P11 to P14 are formed in the P-type transistor region. In plan view, active regions P11 to P14 overlap with wiring 112 to 115, respectively.

In the P-type transistor region, access transistors PG1 to PG4 and transistors PU11, PU12, PU21, and PU22 are formed. Access transistor PG1, transistor PU11, access transistor PG3, transistors PU12 and PU21, access transistor PG2, transistor PU22, and access transistor PG4 each have nanosheets 121 to 128 extending in the Y direction as their channels.

In active region P11, the source portion of access transistor PG1 is connected to wiring 112 via via 191 located at a position overlapping wiring 112 in a planar view. In active region P12, the source portion of access transistor PG3 is connected to wiring 113 via via 192 located at a position overlapping wiring 113 in a planar view. In active region P13, the source portion of access transistor PG2 is connected to wiring 114 via via 193 located at a position overlapping wiring 114 in a planar view. In active region P14, the source portion of access transistor PG4 is connected to wiring 115 via via 194 located at a position overlapping wiring 115 in a planar view.

As shown in Figure 13(a), active regions N11 to N14 are formed in the N-type transistor region. Active regions N11 to N14 are respectively arranged above active regions P11 to P14 in the Z direction. Active regions N11 to N14 overlap with active regions P11 to P14, respectively, in a plan view.

In the N-type transistor region, load transistors PD1 and PD2 and dummy transistors DN11 to DN14 are formed. Load transistors PD1 and PD2 and dummy transistors DN11 to DN14 each have nanosheets 129, 130, and 130a to 130d extending in the Y direction. Note that dummy transistors DN11 to DN14 are transistors that do not have a logic function.

The X-direction width of nanosheets 129 and 130 is smaller than the X-direction width of nanosheets 121-128 and 130a-130d. Note that the X-direction width of nanosheets 129 and 130 may be the same as the X-direction width of nanosheets 121-128 and 130a-130d.

Gate wiring 131-136 are formed extending in the X direction. Gate wiring 131 surrounds the outer peripheries of nanosheets 121 and 130a in the X and Z directions. Gate wiring 132 surrounds the outer peripheries of nanosheet 123 in the X and Z directions. Gate wiring 133 surrounds the outer peripheries of nanosheets 125, 127, 130, and 130b in the X and Z directions. Gate wiring 134 surrounds the outer peripheries of nanosheets 122, 124, 129, and 130c in the X and Z directions. Gate wiring 135 surrounds the outer peripheries of nanosheet 126 in the X and Z directions. Gate wiring 136 surrounds the outer peripheries of nanosheets 128 and 130d in the X and Z directions. Gate wiring 131 corresponds to the gates of access transistor PG1 and dummy transistor DN11. Gate wiring 32 corresponds to the gate of access transistor PG3. Gate wiring 133 corresponds to the gates of load transistor PD2, transistors PU21 and PU22, and dummy transistor DN12. Gate wiring 134 corresponds to the gates of load transistor PD1, transistors PU11 and PU12, and dummy transistor DN13. Gate wiring 135 corresponds to the gate of access transistor PG2. Gate wiring 136 corresponds to the gates of access transistor PG4 and dummy transistor DN14.

As shown in Figure 13(b), local wiring 141-144 extending in the X direction are formed at the bottom of the cell. Local wiring 141 is connected to power supply wiring 111 via via 195. Local wiring 141 is connected to the portion that becomes the source of transistor PU21 in active region P13 and the portion that becomes the source of transistor PU22 in active region P14. Local wiring 142 is connected to the portion that becomes the drain of access transistor PG1 in active region P11, the portion that becomes the drain of transistor PU11 in active region P11, the portion that becomes the drain of access transistor PG3 in active region P12, and the portion that becomes the drain of transistor PU12 in active region P12. Local wiring 143 is connected to the portion that will become the drain of transistor PU21 in active region P13, the portion that will become the drain of access transistor PG2 in active region P13, the portion that will become the drain of transistor PU22 in active region P14, and the portion that will become the drain of access transistor PG4 in active region P14. Local wiring 144 is connected to power supply wiring 111 via via 196. Local wiring 144 is connected to the portion that will become the source of transistor PU11 in active region P11 and the portion that will become the source of transistor PU12 in active region P12.

As shown in Figure 13(a), local wiring 145-148 extending in the X direction are formed above the cell. Local wiring 145 is connected to the portion that will become the source of load transistor PD2 in active region N13. Local wiring 146 is connected to the portion that will become the drain of load transistor PD1 in active region N12. Local wiring 147 is connected to the portion that will become the drain of load transistor PD2 in active region N13. Local wiring 148 is connected to the portion that will become the source of load transistor PD1 in active region N12.

Local wiring 146 is connected to gate wiring 133 via shared contact 151. Local wiring 146 is connected to local wiring 142 via via 152. Local wiring 147 is connected to gate wiring 134 via shared contact 153. Local wiring 147 is connected to local wiring 143 via via 154. Gate wiring 133, local wirings 142 and 146, shared contact 151, and via 152 correspond to the first node NA. Gate wiring 134, local wirings 143 and 147, shared contact 153, and via 154 correspond to the second node NB.

Power supply wiring 161 is formed in the M1 wiring layer, extending in the Y direction from the top to the bottom of the cell in the drawing. Wiring 162 to 165 are also formed. Power supply wiring 161 supplies power supply voltage VSS. Power supply wiring 161 is connected to local wiring 145 via via 155, and to local wiring 148 via via 156.

In the M2 wiring layer, wiring 171 and 172 are formed, extending in the X direction from the left and right ends of the cell in the drawing. Wiring 171 and 172 correspond to the first word line WLA and the second word line WLB, respectively. Wiring 171 is connected to gate wiring 131 via via 181, wiring 162, and via 157. Wiring 171 is connected to gate wiring 135 via via 182, wiring 163, and via 158. Wiring 172 is connected to gate wiring 132 via via 183, wiring 164, and via 159. Wiring 172 is connected to gate wiring 136 via via 184, wiring 165, and via 160.

With the above configuration, wirings 112-115 corresponding to the first bit line BLA, third bit line BLB, second bit line BLAX, and fourth bit line BLBX are formed in the BM0 wiring layer, which is the wiring layer on the back side of the transistors. Wiring 112 overlaps with active region P11 in a planar view and is connected to each other through via 191 provided in the overlapping region. Wiring 113 overlaps with active region P12 in a planar view and is connected to each other through via 192 provided in the overlapping region. Wiring 114 overlaps with active region P13 in a planar view and is connected to each other through via 193 provided in the overlapping region. Wiring 115 overlaps with active region P14 in a planar view and is connected to each other through via 194 provided in the overlapping region. Therefore, since the active regions (transistors) and bit lines can be arranged to overlap, the wiring width of the bit lines can be increased and the wiring resistance of the bit lines can be reduced. This improves the operating speed of the semiconductor memory device.

Furthermore, P-type active regions P11 to P14 are formed in the lower part of the cell. N-type active regions N11 to N14 are formed in the upper part of the cell. As a result, only P-type nanosheet transistors are formed in the lower part of the cell, and only N-type nanosheet transistors are formed in the upper part of the cell, which reduces the complexity of the semiconductor memory device manufacturing process and reduces manufacturing costs. Furthermore, because there is no need to space the P-type nanosheet transistors and the N-type nanosheet transistors apart, the area of the semiconductor memory device can be reduced.

In this embodiment, the X-direction width of nanosheets 129 and 130 is smaller than the X-direction width of nanosheets 121-128 and 130a-130d. Nanosheets 129 and 130 are arranged overlapping nanosheets 124 and 125 in the Z direction. In other words, in this embodiment, nanosheets with different X-direction widths are stacked in the Z direction. Nanosheets with different X-direction widths can be stacked in the Z direction using the semiconductor memory device manufacturing method of Figure 8.

Furthermore, no nanosheets are formed above the nanosheets 123 and 126 in the Z direction. That is, in this embodiment, nanosheets are not formed above the cells, but only below the cells. In this case, in the method for manufacturing the semiconductor memory device shown in FIG. 8, by not forming mask 242 above the stacked semiconductor 210 in FIG. 8(b), nanosheets can be created only below the cells.

In the above-described embodiments and variations, each transistor is provided with two nanosheets, but some or all of the transistors may be provided with one nanosheet or three or more nanosheets.

Furthermore, in each of the above-described embodiments and variations, the cross-sectional shape of the nanosheet is rectangular, but this is not limited to this. For example, it may be square, circular, elliptical, etc.

Furthermore, in each of the above-described embodiments and variations, the shared contacts 51, 53, 151, and 153 may be manufactured in the same process as the contacts (gate contacts) and local wiring, or may be manufactured in a separate process.

Furthermore, in each of the above-described embodiments and modifications, the power supply that supplies the power supply voltage VDD to the sources of the drive transistors PU1 and PU2 is not limited to a power supply supplied from outside the semiconductor integrated circuit, but may be a power supply generated inside the semiconductor integrated circuit or a power supply generated inside the semiconductor memory device.

This disclosure provides a layout structure for an SRAM cell using a CFET that can improve the operating speed of a semiconductor memory device, reduce manufacturing costs, and reduce the area of the semiconductor memory device.

11, 61, 111, 161 Power supply wiring 91 to 98, 191 to 194 Vias 21 to 28, 23a to 23c, 24a to 24c, 27a to 27d, 28a to 28d, 30a to 30h, 121 to 130, 130a to 130d Nanosheets 31 to 36, 131 to 136 Gate wiring 12, 13, 62 to 65 Wiring PU1, PU2 Drive transistor (load transistor)
PD1, PD2: Load transistor (drive transistor)
PU11, PU12, PU21, PU22, PD11, PD12, PD21, PD22: transistors PG1 to PG4: access transistors DP1 to DP6, DN1 to DN6, DN11 to DN14: dummy transistors BLA: first bit line BLAX: second bit line BLB: third bit line BLBX: fourth bit line WLA: first word line WLB: second word line

Claims (18)

A semiconductor memory device including an SRAM cell,
The SRAM cell comprises:
a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node;
a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node;
a third transistor having a source connected to the first bit line, a drain connected to the first node, and a gate connected to the first word line;
a fourth transistor having a source connected to a second bit line that forms a first complementary bit line pair with the first bit line, a drain connected to the second node, and a gate connected to the first word line;
a fifth transistor having a source connected to a third bit line, a drain connected to the first node, and a gate connected to a second word line;
a sixth transistor having a source connected to a fourth bit line forming a second complementary bit line pair with the third bit line, a drain connected to the second node, and a gate connected to the second word line;
a seventh transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node;
an eighth transistor having a source connected to the second power supply, a drain connected to the second node, and a gate connected to the first node;
the first to sixth transistors are transistors of a first conductivity type,
the seventh and eighth transistors are transistors of a second conductivity type different from the first conductivity type,
The SRAM cell comprises:
a first active region including a third nanosheet that forms a channel, a source, and a drain of the third transistor and extends in a first direction as the channel, and a fifth nanosheet that forms a channel, a source, and a drain of the fifth transistor and extends in the first direction as the channel;
a second active region that constitutes a channel, a source, and a drain of the first transistor, the second active region including a first nanosheet extending in the first direction as the channel;
a third active region that constitutes a channel, a source, and a drain of the second transistor, the third active region including a second nanosheet extending in the first direction as the channel;
a fourth active region including a fourth nanosheet that forms a channel, a source, and a drain of the fourth transistor and extends in the first direction as the channel, and a sixth nanosheet that forms a channel, a source, and a drain of the sixth transistor and extends in the first direction as the channel;
a fifth active region formed above the first to fourth active regions in the depth direction, constituting a channel, a source, and a drain of the seventh transistor, the fifth active region including a seventh nanosheet extending in the first direction as the channel;
a sixth active region formed above the first to fourth active regions in the depth direction, constituting a channel, a source, and a drain of the eighth transistor, the channel including an eighth nanosheet extending in the first direction;
a first power supply wiring formed in a back wiring layer that is a wiring layer on the back side of the first to eighth transistors, extending in the first direction, overlapping the second and third active regions in a plan view, and connected to the first power supply;
a first via formed in a region where a region serving as a source of the first transistor in the second active region and the first power supply wiring overlap, the first via connecting the source of the first transistor in the second active region and the first power supply wiring;
a second via formed in a region where a region serving as a source of the second transistor in the third active region and the first power supply wiring overlap, the second via connecting the source of the second transistor in the third active region and the first power supply wiring;
the first and seventh nanosheets overlap in plan view,
A semiconductor memory device, wherein the second and eighth nanosheets overlap in a planar view. 2. The semiconductor memory device according to claim 1,
The first and seventh nanosheets have the same width in the first direction and a second direction perpendicular to the depth direction,
A semiconductor memory device, wherein the second and eighth nanosheets have the same width in the second direction. 2. The semiconductor memory device according to claim 1,
The seventh nanosheet has a smaller width in a second direction perpendicular to the first direction and the depth direction than the first nanosheet,
A semiconductor memory device, wherein the eighth nanosheet has a width in the second direction smaller than that of the second nanosheet. 2. The semiconductor memory device according to claim 1,
the first bit line is formed in a metal wiring layer above the first to eighth transistors and includes a first wiring extending in the first direction;
the second bit line is formed in the metal wiring layer and includes a second wiring extending in the first direction;
the third bit line is formed in the metal wiring layer and includes a third wiring extending in the first direction;
the fourth bit line is formed in the metal wiring layer and includes a fourth wiring extending in the first direction. 2. The semiconductor memory device according to claim 1,
the first bit line is formed in a metal wiring layer above the first to eighth transistors and includes a first wiring extending in the first direction;
the second bit line is formed in the metal wiring layer and includes a second wiring extending in the first direction;
the third bit line is formed in the backside wiring layer and includes a third wiring extending in the first direction;
the fourth bit line is formed in the backside wiring layer and includes a fourth wiring extending in the first direction;
The SRAM cell comprises:
a third via formed in a region where a region serving as a source of the fifth transistor in the first active region and the third wiring overlap, and connecting the source of the fifth transistor in the first active region and the third wiring;
a fourth via formed in a region where a region serving as a source of the sixth transistor in the fourth active region overlaps with the fourth wiring, and connecting the source of the sixth transistor in the fourth active region with the fourth wiring. 2. The semiconductor memory device according to claim 1,
the first transistor further includes a ninth transistor of the first conductivity type;
the second transistor further includes a tenth transistor of the first conductivity type;
The SRAM cell comprises:
a seventh active region formed in the same layer as the first to fourth active regions, constituting a channel, a source, and a drain of the ninth transistor, the channel including a ninth nanosheet extending in the first direction;
an eighth active region formed in the same layer as the first to fourth active regions, constituting a channel, a source, and a drain of the tenth transistor, the channel including a tenth nanosheet extending in the first direction;
a ninth active region formed in the same layer as the fifth and sixth active regions, constituting a channel, a source, and a drain of the first dummy transistor of the second conductivity type, the ninth active region including an eleventh nanosheet extending in the first direction as the channel;
a tenth active region formed in the same layer as the fifth and sixth active regions, constituting a channel, a source, and a drain of the second dummy transistor of the second conductivity type, the tenth active region including a twelfth nanosheet extending in the first direction as the channel;
a fifth via formed in a region where a region serving as a source of the ninth transistor in the seventh active region and the first power supply wiring overlap, the fifth via connecting the source of the ninth transistor in the seventh active region and the first power supply wiring;
a sixth via formed in a region where a region serving as a source of the tenth transistor in the eighth active region and the first power supply wiring overlap, the sixth via connecting the source of the tenth transistor in the eighth active region and the first power supply wiring;
The first and seventh nanosheets have the same width in the first direction and a second direction perpendicular to the depth direction,
the second and eighth nanosheets have the same width in the second direction;
A semiconductor memory device, wherein the ninth and eleventh nanosheets overlap in a planar view and have the same width in the second direction, and the tenth and twelfth nanosheets overlap in a planar view and have the same width in the second direction. 2. The semiconductor memory device according to claim 1,
The SRAM cell comprises:
an eleventh active region formed in the same layer as the fifth and sixth active regions, the eleventh active region including a thirteenth nanosheet that forms a channel, a source, and a drain of the third dummy transistor of the second conductivity type, the channel extending in the first direction; and a fourteenth nanosheet that forms a channel, a source, and a drain of the fourth dummy transistor of the second conductivity type, the channel extending in the first direction;
a twelfth active region that is formed in the same layer as the fifth and sixth active regions, that constitutes a channel, a source, and a drain of the fifth dummy transistor of the second conductivity type, the channel including a fifteenth nanosheet extending in the first direction; and that constitutes a channel, a source, and a drain of the sixth dummy transistor of the second conductivity type, the channel including a sixteenth nanosheet extending in the first direction;
the third and thirteenth nanosheets overlap in a planar view and have the same width in a second direction perpendicular to the first direction and the depth direction; the fifth and fourteenth nanosheets overlap in a planar view and have the same width in the second direction;
A semiconductor memory device, wherein the fourth and fifteenth nanosheets overlap in a planar view and have the same width in the second direction, and the sixth and sixteenth nanosheets overlap in a planar view and have the same width in the second direction. A semiconductor memory device including an SRAM cell,
The SRAM cell comprises:
a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node;
a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node;
a third transistor having a source connected to the first bit line, a drain connected to the first node, and a gate connected to the first word line;
a fourth transistor having a source connected to a second bit line that forms a first complementary bit line pair with the first bit line, a drain connected to the second node, and a gate connected to the first word line;
a fifth transistor having a source connected to a third bit line, a drain connected to the first node, and a gate connected to a second word line;
a sixth transistor having a source connected to a fourth bit line forming a second complementary bit line pair with the third bit line, a drain connected to the second node, and a gate connected to the second word line;
a seventh transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node;
an eighth transistor having a source connected to the second power supply, a drain connected to the second node, and a gate connected to the first node;
the first and second transistors are transistors of a first conductivity type;
the third to eighth transistors are transistors of a second conductivity type different from the first conductivity type,
The SRAM cell comprises:
a first active region that constitutes a channel, a source, and a drain of the first transistor, the first active region including a first nanosheet extending in a first direction as the channel;
a second active region that constitutes a channel, a source, and a drain of the second transistor, the second active region including a second nanosheet extending in the first direction as the channel;
a third active region formed above the first and second active regions in the depth direction, the third active region constituting a channel, a source, and a drain of the third transistor, the channel of the third nanosheet extending in the first direction, and a fifth active region constituting a channel, a source, and a drain of the fifth transistor, the channel of the fifth nanosheet extending in the first direction;
a fourth active region formed above the first and second active regions in the depth direction, constituting a channel, a source, and a drain of the seventh transistor, the channel including a seventh nanosheet extending in the first direction;
a fifth active region formed above the first and second active regions in the depth direction, constituting a channel, a source, and a drain of the eighth transistor, the fifth active region including an eighth nanosheet extending in the first direction as the channel;
a sixth active region formed above the first and second active regions in the depth direction, the sixth active region including a fourth nanosheet that constitutes a channel, a source, and a drain of the fourth transistor and extends in the first direction as the channel, and a sixth nanosheet that constitutes a channel, a source, and a drain of the sixth transistor and extends in the first direction as the channel;
a first power supply wiring formed in a back wiring layer that is a wiring layer on the back side of the first to eighth transistors, extending in the first direction, overlapping with the first and second active regions in a plan view, and connected to the first power supply;
a first via formed in a region where a region serving as a source of the first transistor in the first active region and the first power supply wiring overlap, the first via connecting the source of the first transistor in the first active region and the first power supply wiring;
a second via formed in a region where a region serving as a source of the second transistor in the second active region and the first power supply wiring overlap, the second via connecting the source of the second transistor in the second active region and the first power supply wiring;
the first and seventh nanosheets overlap in plan view,
A semiconductor memory device, wherein the second and eighth nanosheets overlap in a planar view. 9. The semiconductor memory device according to claim 8,
The first and seventh nanosheets have the same width in the first direction and a second direction perpendicular to the depth direction,
A semiconductor memory device, wherein the second and eighth nanosheets have the same width in the second direction. 9. The semiconductor memory device according to claim 8,
the first bit line is formed in a metal wiring layer above the first to eighth transistors and includes a first wiring extending in the first direction;
the second bit line is formed in the metal wiring layer and includes a second wiring extending in the first direction;
the third bit line is formed in the metal wiring layer and includes a third wiring extending in the first direction;
the fourth bit line is formed in the metal wiring layer and includes a fourth wiring extending in the first direction. 9. The semiconductor memory device according to claim 8,
the first bit line is formed in a metal wiring layer above the first to eighth transistors and includes a first wiring extending in the first direction;
the second bit line is formed in the metal wiring layer and includes a second wiring extending in the first direction;
the third bit line is formed in the backside wiring layer and includes a third wiring extending in the first direction;
the fourth bit line is formed in the backside wiring layer and includes a fourth wiring extending in the first direction. 9. The semiconductor memory device according to claim 8,
the seventh transistor further includes a ninth transistor of the second conductivity type;
the eighth transistor further includes a tenth transistor of the second conductivity type;
The SRAM cell comprises:
a seventh active region formed in the same layer as the third to sixth active regions, constituting a channel, a source, and a drain of the ninth transistor, the channel including a ninth nanosheet extending in the first direction;
an eighth active region formed in the same layer as the third to sixth active regions, constituting a channel, a source, and a drain of the tenth transistor, the channel including a tenth nanosheet extending in the first direction;
a ninth active region formed in the same layer as the first and second active regions, constituting a channel, a source, and a drain of the first conductivity type first dummy transistor, the channel including an eleventh nanosheet extending in the first direction;
a tenth active region formed in the same layer as the first and second active regions, constituting a channel, a source, and a drain of a second dummy transistor of the first conductivity type, the tenth active region including a twelfth nanosheet extending in the first direction as the channel;
The first and seventh nanosheets have the same width in the first direction and a second direction perpendicular to the depth direction,
the second and eighth nanosheets have the same width in the second direction;
A semiconductor memory device, wherein the ninth and eleventh nanosheets overlap in a planar view and have the same width in the second direction, and the tenth and twelfth nanosheets overlap in a planar view and have the same width in the second direction. 9. The semiconductor memory device according to claim 8,
The SRAM cell comprises:
an eleventh active region formed in the same layer as the first and second active regions, the eleventh active region including a thirteenth nanosheet that forms a channel, a source, and a drain of a third dummy transistor of the first conductivity type, the channel extending in the first direction; and a fourteenth nanosheet that forms a channel, a source, and a drain of a fourth dummy transistor of the first conductivity type, the channel extending in the first direction;
a twelfth active region formed in the same layer as the first and second active regions, constituting a channel, a source, and a drain of the fifth dummy transistor of the first conductivity type, the channel including a fifteenth nanosheet extending in the first direction; and a twelfth active region constituting a channel, a source, and a drain of the sixth dummy transistor of the first conductivity type, the channel including a sixteenth nanosheet extending in the first direction;
the third and thirteenth nanosheets overlap in a planar view and have the same width in a second direction perpendicular to the first direction and the depth direction; the fifth and fourteenth nanosheets overlap in a planar view and have the same width in the second direction;
A semiconductor memory device, wherein the fourth and fifteenth nanosheets overlap in a planar view and have the same width in the second direction, and the sixth and sixteenth nanosheets overlap in a planar view and have the same width in the second direction. A semiconductor memory device including an SRAM cell,
The SRAM cell comprises:
a first transistor having a source connected to a first power supply that supplies a first power supply voltage, a drain connected to a first node, and a gate connected to a second node;
a second transistor having a source connected to the first power supply, a drain connected to the second node, and a gate connected to the first node;
a third transistor having a source connected to the first bit line, a drain connected to the first node, and a gate connected to the first word line;
a fourth transistor having a source connected to a second bit line that forms a first complementary bit line pair with the first bit line, a drain connected to the second node, and a gate connected to the first word line;
a fifth transistor having a source connected to a third bit line, a drain connected to the first node, and a gate connected to a second word line;
a sixth transistor having a source connected to a fourth bit line forming a second complementary bit line pair with the third bit line, a drain connected to the second node, and a gate connected to the second word line;
a seventh transistor having a source connected to a second power supply that supplies a second power supply voltage different from the first power supply voltage, a drain connected to the first node, and a gate connected to the second node;
an eighth transistor having a source connected to the second power supply, a drain connected to the second node, and a gate connected to the first node;
the first transistors include ninth and tenth transistors;
the second transistors include eleventh and twelfth transistors;
the third to sixth and ninth to twelfth transistors are transistors of a first conductivity type,
the seventh and eighth transistors are transistors of a second conductivity type different from the first conductivity type,
The SRAM cell comprises:
a first active region including a third nanosheet that forms a channel, a source, and a drain of the third transistor and extends in a first direction as the channel, and a ninth nanosheet that forms a channel, a source, and a drain of the ninth transistor and extends in the first direction as the channel;
a second active region including a fifth nanosheet that forms a channel, a source, and a drain of the fifth transistor and extends in the first direction as the channel, and a tenth nanosheet that forms a channel, a source, and a drain of the tenth transistor and extends in the first direction as the channel;
a third active region including a fourth nanosheet that forms a channel, a source, and a drain of the fourth transistor and extends in the first direction as the channel, and an eleventh nanosheet that forms a channel, a source, and a drain of the eleventh transistor and extends in the first direction as the channel;
a fourth active region including a sixth nanosheet that forms a channel, a source, and a drain of the sixth transistor and extends in the first direction as the channel, and a twelfth nanosheet that forms a channel, a source, and a drain of the twelfth transistor and extends in the first direction as the channel;
a fifth active region formed above the first to fourth active regions in the depth direction, constituting a channel, a source, and a drain of the seventh transistor, the fifth active region including a seventh nanosheet extending in the first direction as the channel;
a sixth active region that is formed above the first to fourth active regions in the depth direction, that constitutes a channel, a source, and a drain of the eighth transistor, and that includes an eighth nanosheet extending in the first direction as the channel;
the third and ninth nanosheets are arranged side by side in the first direction,
the fifth and tenth nanosheets are arranged side by side in the first direction,
the fourth and eleventh nanosheets are arranged side by side in the first direction,
the sixth and twelfth nanosheets are arranged side by side in the first direction,
The seventh and tenth nanosheets overlap in a planar view. 15. The semiconductor memory device according to claim 14,
The SRAM cell includes a first power supply wiring formed in a back wiring layer that is a wiring layer on the back side of the third to sixth and ninth to twelfth transistors. 15. The semiconductor memory device according to claim 14,
the first bit line is formed in a back wiring layer that is a wiring layer on the back side of the third to sixth and ninth to twelfth transistors, and includes a first wiring extending in the first direction;
the second bit line is formed in the backside wiring layer and includes a second wiring extending in the first direction;
the third bit line is formed in the backside wiring layer and includes a third wiring extending in the first direction;
the fourth bit line is formed in the backside wiring layer and includes a fourth wiring extending in the first direction;
The SRAM cell comprises:
a first via formed in a region in the first active region where a region serving as a source of the third transistor and the first wiring overlap, the first via connecting the source of the third transistor in the first active region and the first wiring;
a second via formed in a region where a region serving as a source of the fifth transistor in the second active region and the third wiring overlap, the second via connecting the source of the fifth transistor in the second active region and the third wiring;
a third via formed in a region where a region serving as a source of the fourth transistor in the third active region and the second wiring overlap, the third via connecting the source of the fourth transistor in the third active region and the second wiring;
a fourth via formed in a region where a region serving as a source of the sixth transistor in the fourth active region overlaps with the fourth wiring, and connecting the source of the sixth transistor in the fourth active region with the fourth wiring. 15. The semiconductor memory device according to claim 14,
The tenth nanosheet has a larger width in a second direction perpendicular to the first direction and the depth direction than the seventh nanosheet,
The semiconductor memory device, wherein the 11th nanosheet has a width in the second direction greater than that of the 8th nanosheet. 15. The semiconductor memory device according to claim 14,
The SRAM cell comprises:
a seventh active region formed in the same layer as the fifth and sixth active regions, the seventh active region including a thirteenth nanosheet that constitutes a channel, a source, and a drain of the first dummy transistor of the second conductivity type, the channel extending in the first direction, and a fourteenth nanosheet that constitutes a channel, a source, and a drain of the second dummy transistor of the second conductivity type, the channel extending in the first direction;
an eighth active region that is formed in the same layer as the fifth and sixth active regions, that constitutes a channel, a source, and a drain of the third dummy transistor of the second conductivity type, the channel including a fifteenth nanosheet extending in the first direction; and that constitutes a channel, a source, and a drain of the fourth dummy transistor of the second conductivity type, the channel including a sixteenth nanosheet extending in the first direction;
The third and thirteenth nanosheets overlap in a planar view and have the same width in a second direction perpendicular to the first direction and the depth direction, and the ninth and fourteenth nanosheets overlap in a planar view and have the same width in the second direction.