WO2025232322A1 - Instruction processing method, instruction processing system and system-on-chip - Google Patents

Abstract

The present disclosure relates to the fields of instruction set architectures and data security. Provided are an instruction processing method, an instruction processing system and a system-on-chip. The method comprises: monitoring a processing flow of processing a source instruction file of a first language by means of a tool chain, so as to determine whether an instruction to be processed in the source instruction file is a preset instruction; in case of said instruction to be processed being the preset instruction, invoking an interpretation component in the tool chain to process instruction description information of said instruction to be processed, so as to obtain a plurality of instruction elements of a second language; and executing the plurality of instruction elements of the second language by means of the tool chain, so as to obtain a processing result of said instruction undergoing processing. The present disclosure solves the technical problem of low accuracy in instruction processing in the prior art.

Description

Instruction processing methods, instruction processing systems, and on-chip systems Technical Field

This disclosure relates to the field of processors, and more specifically, to an instruction processing method, an instruction processing system, and a system-on-a-chip.

Background Technology

In toolchain software development, tools within different toolchains abstract and interpret the semantics of instruction sets. Taking a single instruction as an example, a simulator interprets it as simulated execution, a compiler interprets it as matching the corresponding operator sequence in the upper-level language, and an assembler interprets it as matching a specific assembly string sequence. The core content revolving around these processes is the semantic description of the instruction set. Generally, the semantic description of the instruction set is described in a specification document using natural or mathematical language. Implementers of different tools use the same document for unified understanding and implementation. However, in this process, discrepancies in understanding or implementation can easily arise, leading to toolchain errors and lower accuracy in instruction processing.

There is currently no effective solution to the above problems.

Summary of the Invention

This disclosure provides an instruction processing method, an instruction processing system, and a system-on-a-chip to at least address the technical problem of low accuracy in instruction processing in related technologies.

According to one aspect of the present disclosure, an instruction processing method is provided, comprising: monitoring the processing flow of a source instruction file of a first language processed by a toolchain, and determining whether the instruction to be processed in the source instruction file is a preset instruction; if the instruction to be processed is a preset instruction, calling an interpretation component in the toolchain to process the instruction description information of the instruction to be processed to obtain multiple instruction elements of a second language; and executing the multiple instruction elements of the second language through the toolchain to obtain the processing result of the instruction to be processed.

According to another aspect of the embodiments of this disclosure, an instruction processing system is also provided, including: a toolchain, comprising at least an execution component and an interpretation component; wherein, the execution component is used to process the processing flow of a source instruction file in a first language and determine whether the instruction to be processed in the source instruction file is a preset instruction; the interpretation component is used to process the instruction description information of the instruction to be processed to obtain multiple instruction elements in a second language; the execution component is also used to execute the multiple instruction elements in the second language to obtain the processing result of the instruction to be processed.

According to another aspect of the embodiments of this disclosure, a system-on-a-chip is also provided, including: an instruction processing system of any one of the above embodiments.

According to another aspect of the embodiments of this disclosure, a computer terminal is also provided, including: a memory storing an executable program; and a processor for running the program, wherein the program executes the methods in the various embodiments of this disclosure when it runs.

According to another aspect of the embodiments of the present disclosure, a computer-readable storage medium is also provided, the computer-readable storage medium including a stored executable program, wherein, when the executable program is executed, it controls the device where the computer-readable storage medium is located to perform the methods of the various embodiments of the present disclosure.

According to another aspect of the embodiments of this disclosure, a computer program product is also provided, including a computer program that, when executed by a processor, implements the methods of various embodiments of this disclosure.

According to another aspect of the embodiments of this disclosure, a computer program product is also provided, including a non-volatile computer-readable storage medium storing a computer program that, when executed by a processor, implements the methods in various embodiments of this disclosure.

According to another aspect of the embodiments of this disclosure, a computer program is also provided, which, when executed by a processor, implements the methods in the various embodiments of this disclosure. In the embodiments of this disclosure, the processing flow of a source instruction file in a first language processed by a toolchain is monitored to determine whether the instruction to be processed in the source instruction file is a preset instruction; if the instruction to be processed is a preset instruction, an interpretation component in the toolchain is invoked to process the instruction description information of the instruction to be processed, obtaining multiple instruction elements in a second language; the multiple instruction elements in the second language are executed by the toolchain to obtain the processing result of the instruction to be processed, thereby improving the accuracy of instruction processing. It is noteworthy that when processing a source instruction file in a first language through a toolchain, if there is an instruction to be processed that is a preset instruction, the interpretation component in the toolchain can be invoked to interpret the instruction description information of the instruction to be processed, so as to obtain multiple instruction elements in the second language that the toolchain can execute. This allows the toolchain to efficiently and accurately process and execute the source instruction file without introducing additional language learning costs, thereby improving the accuracy of instruction processing and solving the technical problem of low accuracy in instruction processing in related technologies.

It is worth noting that the above general description and the following detailed description are merely for illustrative and explanatory purposes and do not constitute a limitation thereof.

Attached Figure Description

The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

Figure 1 is a hardware structure block diagram of a RISC-V system for implementing an instruction processing method according to an embodiment of the present disclosure;

Figure 2 is a schematic diagram of a system-on-a-chip according to an embodiment of the present disclosure;

Figure 3 is a flowchart of the instruction processing method according to Embodiment 1 of this disclosure;

Figure 4 is a schematic diagram of a directed acyclic graph according to an embodiment of the present disclosure;

Figure 5 is a schematic diagram of a character representation matching relationship according to an embodiment of the present disclosure;

Figure 6 is a schematic diagram of a simulator scene according to an embodiment of the present disclosure;

Figure 7 is a schematic diagram of an instruction processing apparatus according to an embodiment of the present disclosure;

Figure 8 is a schematic diagram of an instruction processing system according to an embodiment of the present disclosure;

Figure 9 is a structural block diagram of an electronic device according to an embodiment of the present disclosure.

Detailed Implementation

To enable those skilled in the art to better understand the present disclosure, the technical solutions of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present disclosure, and not all embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present disclosure.

It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

First, some nouns or terms that appear in the description of the embodiments of this disclosure shall be interpreted as follows:

Instruction Set Architecture (ISA): A set of hardware architecture standards that defines the core interfaces of a computer, such as instructions, registers, and data types.

Domain-Specific Accelerator (DSA): A dedicated hardware computing device designed to improve the performance and efficiency of a specific application domain;

Domain-Specific Language (DSL): A computer programming language that focuses on a specific problem domain, purpose, or task, and is designed to simplify programming tasks related to that domain.

Toolchain: A set of software tools that work together, typically used for compiling, debugging, and building software for programming languages.

Python: A widely used high-level programming language known for its readability and concise syntax, suitable for a wide range of programming tasks, from web development to data science.

Abstract Interpretation: A method of analyzing a program by using simplified (or "abstract") data to represent the actual data in the program, in order to simplify the understanding or prediction of the program's behavior.

Embedded Domain-Specific Language (EDSL): A DSL built on another (host) programming language, which uses the syntax and features of the host language to express domain-specific logic and operations.

Currently, different toolchains cannot reuse implementations, leading to some degree of duplication of work. In toolchain use cases, processor core design (CPU IP core) customers often have needs for customized domain-specific accelerators. The instruction set of this accelerator is defined by the customer, but the toolchain is provided by the CPU IP core vendor because the generated DSA instructions are integrated into the normal CPU instruction sequence. Furthermore, due to the confidentiality of customer instructions and the need to prevent toolchain fragmentation, CPU vendors cannot support customers' DSA instruction customization needs during the toolchain development phase; they can only deliver general toolchain binary distribution packages. Therefore, after receiving the general toolchain, customers need to perform secondary development or configuration of the toolchain in their own environment. At this point, customers need to describe the semantics of their designed DSA instructions so that the toolchain can read and support them.

Related technologies can provide instruction description languages and parsing tools to automatically generate support code for toolchains, but users need to learn new syntax, and the generator pattern introduces an intermediate layer, making debugging and building complex and difficult to trace. This disclosure uses Python libraries, which offers lower language learning costs and better dynamic loading and flexibility.

Based on the aforementioned problems and needs, this disclosure provides a method for using Python as a host language to express instruction semantics, and defines the interface for how to use this library during toolchain development. This facilitates unified instruction implementation for toolchain developers and allows DSA customers to dynamically perform secondary development and configuration of the toolchain.

Example 1

According to embodiments of this disclosure, an instruction processing method is provided. It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowcharts, in some cases, the steps shown or described may be executed in a different order than that shown here.

The method embodiment provided in Embodiment 1 of this disclosure can be executed in a RISC-V system, a RISC-V chip, or a similar device. Figure 1 is a hardware structure block diagram of a RISC-V system for implementing an instruction processing method according to an embodiment of this disclosure. As shown in Figure 1, the RISC-V system 100 can be divided into the following layers from bottom to top: Reduced Instruction Set Architecture 101 (including basic instruction set 101-1 and extended instruction set 101-2), hardware layer 102 (including processor 102-1, peripheral hardware circuits 102-2, etc.), interface layer 103, operating system layer 104 (supporting multiple operating systems 104-1, 104-2, ..., 104-n, such as Linux, Free SBD, RT-Tread, etc.), middleware and library layer 105 (including system library 105-1, API 105-2, and middleware service 105-3), and application layer 106 (including multiple user programs and services 106-1, 106-2, ..., 106-n). The RISC-V system 100 also includes a toolchain 107 that runs from the underlying hardware to the application layer. This toolchain may include compilers and assemblers 107-1, linkers 107-2, debuggers 107-3, simulators and emulators 107-4, integrated development environments 107-5, hardware description language tools 107-6, performance analysis tools 107-7, and version control systems 107-8, etc.

The instruction set architecture 101 defines the basic operations and instruction sets supported by the processor 102-1, including the basic instruction set and the extended instruction set. The basic instruction set represents the basic integer instruction set, such as RV32I and RV64I, while the extended instruction set can be floating-point, atomic operations, compressed instructions, etc.

Interface layer 103 includes the specific design of the processor, such as pipeline design, cache structure, execution units, branch prediction, etc. This layer is the process of mapping abstract instructions to physical hardware.

The operating system layer 104 resides in the hardware layer, providing a hardware abstraction layer and management mechanisms, enabling applications to interact with hardware through system calls. The operating system is responsible for managing processor resources, memory, device drivers, task scheduling, and more.

The middleware and library layer 105 provides a rich set of services and interfaces to help applications run more efficiently. For example, the standard library provides functions such as file operations and mathematical calculations, while middleware can provide complex services such as network communication and graphical user interfaces.

The application layer 106 utilizes the functions and services provided by the lower layer to implement specific application logic. These applications can be command-line tools, graphical interface applications, server-side services, etc.

Toolchain 107 is a key component connecting the underlying hardware to the upper-level software. The various tools in toolchain 107 play a role at different levels to support the entire process from hardware design to software development, ensuring the coherence and effectiveness of the entire system design.

It should be noted that the layered design of the RISC-V architecture allows for decoupling between different layers, enabling each layer to be developed and improved independently.

In one alternative embodiment, FIG2 is a schematic diagram of a system-on-chip according to an embodiment of the present disclosure. FIG2 shows a schematic diagram of a system-on-chip (SOC) using the RISC-V architecture shown in FIG1 above. As shown in FIG2, the SOC contains at least one RISC-V core 202 (only one is shown in the figure). The RISC-V core 202 is connected to peripheral devices through bus 204, including but not limited to ROM 206, RAM 208, timer 210, UART (Universal Asynchronous Receiver/Transmitter) 212, GPIO (General Purpose Input/Output) 214, SPI (Serial Peripheral Interface Bus) 216, etc.

Under the above operating environment, this disclosure provides an instruction processing method as shown in Figure 3. Figure 3 is a flowchart of the instruction processing method according to Embodiment 1 of this disclosure. The method includes:

Step S302: Monitor the processing flow of the source instruction file of the first language through the toolchain, and determine whether the instruction to be processed in the source instruction file is a preset instruction.

The aforementioned toolchain refers to a collection of tools used in the software development process to support different stages of work, such as development, building, testing, and deployment.

The aforementioned preset instructions can be pre-defined instructions or unknown instructions. If the instruction to be processed is a preset instruction, it needs to be interpreted by the toolchain to obtain instruction elements that the toolchain can recognize.

The source code file mentioned above is a file containing the original code of a computer program, typically written in a specific programming language. Source code files are usually processed by a compiler or interpreter, converting them into an executable program or allowing for interpreted execution. Source code files can contain different file formats (C, C++, Java, Python, etc.). In software development, source code files are fundamental to program development; the design and functionality of a program can be implemented by editing and modifying source code files.

The first language mentioned above can include, but is not limited to, various programming languages (C, C++, Java, Python), and no limitation is made on the first language here.

In one alternative embodiment, the processing flow of source instruction files in the first language processed by the toolchain can be monitored to see if the toolchain encounters preset instructions that need to be interpreted when processing the source instruction files, so that the toolchain can successfully execute and process the source instruction files.

Step S304: If the instruction to be processed is a preset instruction, the interpretation component in the toolchain is called to process the instruction description information of the instruction to be processed, and multiple instruction elements in the second language are obtained.

When the instruction to be processed is a preset instruction, the instruction description information of the instruction to be processed can be interpreted by calling the interpretation component in the toolchain, so as to convert the instruction to be processed into multiple instruction elements in a second language that the toolchain can recognize.

The aforementioned interpreting component can refer to an interpreter, which is a software component capable of directly interpreting and executing program source code. An interpreter interprets the program source code line by line and executes the code on demand, without first converting the code into machine code or intermediate code. Interpreters are often used to interpret and execute dynamic languages such as Python, Ruby, and JavaScript. In some cases, interpreters can also be used to execute programs in statically typed languages, such as executing Java source code via an interpreter instead of first compiling it into bytecode.

The aforementioned interpretation component is used to process the instruction description information of the instructions to be processed, in order to obtain multiple instruction elements in the second language. The interpreter can parse the source code of the first language and convert it into multiple instruction elements in the second language for subsequent processing and execution. This disclosure uses a Python interpreter as an example for illustration.

The instruction description information of the aforementioned instructions to be processed can be the description information of instructions or commands that need to be executed and are contained in a program or script. Instruction description information can include the command name, parameters, options, and other relevant information. In computer programming and scripting, programmers typically write a series of instructions to be executed. This instruction description information is processed and executed by an interpreter, compiler, or other tools. The instruction description information can include the program's control flow, function calls, variable assignments, etc. The interpreter can convert the instruction description information of the instructions to be processed into instruction elements in a second language, enabling the toolchain to process and execute the predefined instructions.

The aforementioned instruction elements of a second language can be instruction elements that can be recognized by the toolchain. Instruction elements can be basic instructions or primitive operations in the second language. Specifically, instruction elements may refer to basic program operations, such as variable assignment, conditional statements, loop operations, and function calls. These instruction elements are the fundamental components of a program; after being processed by the interpreter or compiler, they are ultimately converted into instructions or code that the computer can execute.

In an optional embodiment, when the instruction to be processed is a preset instruction, the interpretation component in the toolchain can be invoked to interpret the instruction description information of the instruction to be processed, thereby obtaining multiple instruction elements in the second language. This allows the toolchain to process the multiple instruction elements in the second language and obtain the processing result of the instruction to be processed.

Step S306: Execute multiple instruction elements of the second language through the toolchain to obtain the processing result of the instruction to be processed.

In one optional embodiment, the instruction description information of the instructions to be processed is processed by invoking the interpretation component in the toolchain to obtain multiple instruction elements in a second language that the toolchain can recognize. The type of the toolchain can be determined first, and then the semantic actions corresponding to that type can be performed on the multiple instruction elements through the toolchain to obtain the aforementioned processing result.

The core of this disclosure is a Python library used to describe instruction semantics. This library models the basic operands and opcodes used in the description of instruction semantics using predefined elements, making it easy for users to construct complex instruction semantics using these basic elements. It should be noted that element modeling means the Python library pre-standardizes and defines the semantics of some basic operation types and operations, allowing users to directly combine and use these elements. The definition and set of basic elements are similar to the basic instructions and types in the Low-Level Virtual Instruction Set (LLVM Intermediate Representation, or LLVM IR for short), while also reserving space for user-defined types. The Low-Level Virtual Instruction Set is used to represent the intermediate representation of a program in the compiler. This Low-Level Virtual Instruction Set can be a type-safe, low-level representation that can be used by high-level language compilers to generate machine code or other forms of object code.

For example, when a user needs to describe an instruction with 3 operands as input, it can be represented as follows:

import TripleOp from thead.dsa.op;

class CustomOp1: TripleOp(Custom class CustomOp1, which inherits from class TripleOp);

def asmString():

return "muladd" (define the asmString method, which returns the string "muladd");

def execute(r1, r2, r3):

return r1*r2+r3(Define the execute method, which accepts three parameters r1, r2, and r3, and returns the result of r1 multiplied by r2 and r3).

The aforementioned `TripleOp` is a defined class library representing ternary operators, while `CustomOp1` is a user-defined class that is used through inheritance. The user defines the semantics of this instruction using `def execute`, which is operand 1 * operand 2 + operand 3. In the `execute` function, `r1`, `r2`, and `r3` are all basic operand element types defined in this publication. Multiplication (*) and addition (+) are defined basic opcode elements. Because classes like `r1`, `r2`, and `r3` define operator overloading capabilities, users can directly construct operations using addition (+) and multiplication (*).

Users can use predefined Python libraries to express the semantics of their own instructions, including a character representation of the instruction, as described in the `asmString` function. This character representation is used to represent the names of ternary operators and is generally used in assembly and disassembly. The `asmString` function is used to convert a string into assembly code, transforming it into a series of assembly instructions that allow the program to dynamically generate and execute.

Through the above steps, the processing flow of the first language source instruction file processed by the toolchain is monitored to determine whether the instruction to be processed in the source instruction file is a preset instruction. If the instruction to be processed is a preset instruction, the interpretation component in the toolchain is called to process the instruction description information of the instruction to be processed, thereby obtaining multiple instruction elements in the second language. The toolchain executes the multiple instruction elements in the second language to obtain the processing result of the instruction to be processed, thus improving the accuracy of instruction processing. It is worth noting that when processing the first language source instruction file through the toolchain, if there is an instruction to be processed that is a preset instruction, the interpretation component in the toolchain can be called to interpret the instruction description information of the instruction to be processed, so as to obtain multiple instruction elements in the second language that the toolchain can execute. This allows the toolchain to efficiently and accurately process and execute the source instruction file without introducing additional language learning costs, thereby improving the accuracy of instruction processing and solving the technical problem of low accuracy in instruction processing in related technologies.

In the above embodiments of this disclosure, the interpretation component in the toolchain is invoked to process the instruction description information of the instruction to be processed to obtain multiple instruction elements in the second language. This includes: processing the instruction description information through the interpretation component to generate a directed acyclic graph, wherein the multiple nodes contained in the directed acyclic graph correspond one-to-one with the multiple instruction elements, and the edges connecting different nodes in the directed acyclic graph are used to represent the association relationship between different instruction elements.

The Directed Acyclic Graph (DAG) described above is a graph structure composed of multiple nodes and directed edges between them. Each node corresponds one-to-one with an instruction element, and the edges represent the relationships between different instruction elements. DAGs can be used to represent the instruction flow and dependencies during program execution. Each node represents an instruction element, such as variable assignment, conditional judgment, or function call. Directed edges represent the relationships between different instruction elements, such as dependencies and execution order.

If the instruction description information to be processed contains a section of program control flow, the interpretation component can generate a directed acyclic graph (DAG) based on this description information. The nodes in the graph represent various instruction elements of the program, such as assignment operations, conditional statements, and loop operations, while the edges represent the execution order and dependencies between these instruction elements. Such a DAG can help with program analysis and improvement, and also visually represent the program's execution flow and the relationships between instructions.

After determining the instruction description information of the instruction to be processed, a directed acyclic graph (DAG) describing the instruction semantics can be constructed on the Python side. This DAG can then be loaded into different toolchains, each capable of performing different semantic actions on the DAG for different purposes. Optionally, the entire DAG can be loaded into a toolchain. For example, if the DAG is loaded into a simulator, the semantic actions on each node are executed within the simulator, representing the semantics of that node. If the DAG is loaded into a compiler, the semantic actions on each node are matched against the higher-level representative of the corresponding semantics to generate the user-described instruction.

Figure 4 is a schematic diagram of a directed acyclic graph according to an embodiment of the present disclosure. As shown in Figure 4, instruction description information can be input into a Python interpreter. The Python interpreter can process the instruction description information to generate a directed acyclic graph of instruction description information. The directed acyclic graph includes +, *, R1, R2, and R3. The directed acyclic graph is interpreted and executed to perform a semantic action on each node in the directed acyclic graph.

In the above embodiments of this disclosure, the method further includes: loading a configuration file into the toolchain, wherein the configuration file contains instruction description information of at least one preset instruction; matching the character representation of at least one preset instruction with the character representation of an instruction to be processed to determine the instruction description information of the instruction to be processed.

In one alternative embodiment, Python code can be interpreted and executed by embedding a Python interpreter in the toolchain to obtain a directed acyclic graph of at least one preset instruction. This directed acyclic graph can then be interpreted and executed by mutual calls between Python and other languages through binding relationships, such as C++ calling Python's binding.

In another alternative embodiment, the instruction description information of preset instructions can be stored in a configuration file, and then the configuration file is loaded into the toolchain. This instruction description information may include the instruction's name, parameters, options, and other instruction-related information. When the character representation of the instruction to be processed is matched with the character representation of the preset instructions in the configuration file, the toolchain can use this information to determine the instruction description information of the instruction to be processed.

For example, the configuration file contains a preset instruction named "print," which represents the print operation. When the character representation of the instruction to be processed contains the instruction "print," the toolchain can determine the instruction description information of the instruction to be processed by matching the instruction description information of the preset instruction in the configuration file, so as to facilitate subsequent processing and execution. The toolchain can automatically identify and process the instruction to be processed based on the instruction description information of the preset instruction, thereby improving the flexibility and configurability of the toolchain. This makes it easier for developers to define and use their own instruction description information to adapt to different development needs.

Different software tools perform different semantic actions when interpreting directed acyclic graphs. For example, an assembler performs text matching, matching different nodes to complete an instruction matching, a simulator performs a simulated execution operation on different nodes, and a compiler performs intermediate code matching of a higher-level language on different nodes.

Figure 5 is a schematic diagram of a character representation matching relationship according to an embodiment of the present disclosure. As shown in Figure 5, instruction description information can be input into different toolchains for execution. The upper toolchain shown in Figure 5 can be a simulation toolchain, and the executor of the simulation toolchain can be a simulator. The lower toolchain shown in Figure 5 can be a compilation toolchain, and the executor of the compilation toolchain can be a compiler. The Python interpreter in the simulation toolchain can generate a directed acyclic graph (DAG) based on the instruction description information and interpret and execute the DAG. This interpretation and execution process can be simulated execution based on the DAG. Similarly, the Python interpreter in the compilation toolchain can generate a DAG based on the instruction description information and interpret and execute the DAG. This interpretation and execution process can be instruction selection based on the DAG. Through the method shown in Figure 5, the purpose of using the same instruction description information to construct different toolchains is achieved.

In the above embodiments of this disclosure, matching the character representation of at least one preset instruction with the character representation of an instruction to be processed to determine the instruction description information of the instruction to be processed includes: if the character representation of any preset instruction is the same as the character representation of the instruction to be processed, determining the instruction description information of any preset instruction as the instruction description information of the instruction to be processed.

In an optional embodiment, if the character representation of any preset instruction is the same as the character representation of the instruction to be processed, determining the instruction description information of any preset instruction as the instruction description information of the instruction to be processed means that when the character representation of the instruction to be processed matches the character representation in the preset instruction, the toolchain will set the instruction description information of the instruction to be processed to the instruction description information of the matched preset instruction. Optionally, a similarity match can be performed between the character representations of the preset instructions and the character representations of the instruction to be processed, thereby determining the instruction description information of the instruction to be processed based on the instruction description information of any preset instruction.

In the above embodiments of this disclosure, the processing result of the instruction to be processed is obtained by executing multiple instruction elements of the second language through a toolchain, including: determining the target type of the toolchain and determining the target semantic action corresponding to the target type; and performing target semantic actions on multiple instruction elements through the toolchain to obtain the processing result.

The target types mentioned above can be categorized based on the purpose and function of the toolchain. Toolchain target types include compiler chains, interpreter chains, and build toolchains. Compiler chains include, but are not limited to, preprocessing, compilation, assembly, and linking processes; interpreter chains include, but are not limited to, translating source code into machine code for immediate execution; and build toolchains include, but are not limited to, those used for automating software building, testing, and deployment.

The target semantic actions corresponding to the aforementioned target types can be determined based on the specific toolchain and target type. For example, for a compiler chain, target types may include executable files, dynamic link libraries, static libraries, etc., and the corresponding target semantic actions may include translating the source code into the machine code or intermediate code required by the target type, and performing linking operations.

The aforementioned target semantic actions refer to the operations performed by the toolchain when processing instruction elements in software development to satisfy a specific target type. These operations are to transform the source code into the form required by the target type or to perform specific functions. Target semantic actions can include compilation, linking, improvement, and interpreted execution, depending on the toolchain type and the target type. For interpreter chains, the target type might be executing a specific script or program, while the target semantic action is interpreting and executing the instructions in the source code. This is only an illustrative example; the specific target semantic actions corresponding to a particular target type can be determined based on the actual situation.

In one optional embodiment, the target type of the toolchain can be determined first, and the target semantic action corresponding to the target type can be obtained. The toolchain can execute the target semantic action on multiple instruction elements, thereby enabling the toolchain to process multiple instruction elements accurately and obtain processing results.

Figure 6 is a schematic diagram of a simulator scenario according to an embodiment of the present disclosure. As shown in Figure 6, instruction description information written in Python can be loaded into the simulator's toolchain as a configuration file. Then, the source file input of the toolchain is processed normally. The source file can be a target assembly language. When an unknown instruction or a user-defined instruction is encountered, the custom instruction description information loaded in the Python interpreter is called back. The instruction description information can be processed by the Python interpreter to generate a directed acyclic graph. Multiple instruction elements are obtained through the directed acyclic graph, and the multiple instruction elements are executed by the executor to obtain the target semantic action of the instruction elements.

In the above embodiments of this disclosure, determining the target semantic action corresponding to the target type includes: when the target type is a simulator, determining the target semantic action as executing the semantics of multiple instruction elements in the simulator; when the target type is an assembler, determining the target semantic action as matching multiple instruction elements with text; and when the target type is a compiler, determining the target semantic action as matching multiple instruction elements with intermediate instructions of a first language.

The simulator described above can be a computer program that simulates the behavior of a hardware platform, allowing users to execute instructions from an instruction set architecture in a simulated environment for software development, debugging, and performance analysis. Simulators are typically used to simulate specific computer architectures, processors, or devices, enabling developers to develop and test software without actual hardware. The assembler described above is a tool that translates assembly language code into machine code or object files. An assembler converts programmer-written assembly language instructions into executable binary code that a computer can directly execute. The assembler is an important component of the programming toolchain, used to convert assembly language code into machine code for computer execution. The compiler described above is a tool that translates high-level programming language code into machine code or intermediate code for a target platform. A compiler converts programmer-written high-level language code (such as C, C++, Java, etc.) into executable code for the target platform, including executable files, library files, etc. A compiler can also translate high-level language code into an intermediate representation for subsequent improvements and target code generation.

When the target type is a simulator, the target semantic action is the semantics of executing multiple instruction elements in the simulator. The toolchain can simulate the behavior of the target hardware platform, executing multiple instruction elements one by one, so as to observe and analyze the program's behavior and performance in a simulation environment.

When the target type is an assembler, the target semantic action is to match multiple instruction elements with text. The toolchain can translate these instruction elements into their corresponding assembly text representations; this process is the assembly process.

When the target type is a compiler, the target semantic action is to match multiple instruction elements with intermediate instructions in the first language. The toolchain can translate these instruction elements into an intermediate representation in the first language; this process is the compilation process.

In the embodiments described above, the preset instruction is used to characterize an instruction not included in the simplified instruction set, or an instruction set by the target object.

The aforementioned reduced instruction set architecture can be obtained through the open-source instruction set architecture (RV architecture). RV architecture is a reduced instruction set computer architecture designed to simplify the instruction set and improve processor performance and power efficiency. If a computer's processor uses the RV architecture, it means that the computer can use the RV instruction set and can execute specific instructions from the RV architecture, thereby achieving higher performance and power efficiency.

The target object mentioned above can be a user or any object.

The toolchain described above can be used to process a reduced instruction set. The preset instructions can be unknown instructions or instructions pre-set by the user.

This disclosure standardizes the implementation of instruction set semantics in toolchains, resolving potential semantic inconsistencies that may arise when individual tools implement instruction set semantics independently, and reducing errors and redundant work during toolchain implementation. Furthermore, this disclosure can be applied to the semantic description and implementation of extended instruction sets used by customer-specific accelerators, facilitating customers' independent description of extended instruction set semantics and enabling immediate toolchain support for extended instructions. The innovation of this disclosure lies in its avoidance of reinventing a new instruction semantic description language; instead, it utilizes existing programming languages as the host language to describe instruction semantics, creating a domain-specific accelerator that simplifies the learning curve and allows for easy and immediate embedding into various toolchains.

Users can independently describe the semantics of the extended instruction set using Python and generate configuration files. This allows domain-specific accelerators to use Python-to-language bindings to call back the semantics of the extended instruction set and respond to nodes in the Directed Acyclic Graph (DAG) to handle specific processes, thereby increasing the capabilities of the toolchain.

The nodes in the aforementioned directed acyclic graph (DAG) can be any data node in the DAG, representing a specific element or entity in the graph and connected to other nodes via directed edges. In toolchains, nodes in a DAG typically represent a specific processing step or operation within the toolchain.

In this disclosure, since no new domain-specific language is used to describe the semantics of instructions, no additional language learning costs are introduced, there is no need to build an interpreter for a new language, and there is no intermediate layer caused by design patterns (Generator pattern), making the debugging process more direct. Optionally, by using a dynamic language like Python, users can easily load and debug on existing toolchain distribution packages, facilitating secondary development. This disclosure, using Python as the host language to describe the semantics of the instruction set, offers greater dynamism and flexibility than other methods, reducing the cost of secondary development. By designing a Python semantic description library, the threshold for semantic description is lowered, providing a unified instruction description interface and paradigm, reducing repetitive work.

It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this disclosure are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of the relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation portals are provided for users to choose to authorize or refuse.

It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this disclosure is not limited to the described order of actions, because according to this disclosure, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this disclosure.

Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, they can also be implemented by hardware. Based on this understanding, the technical solutions of this disclosure, in essence, or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk), and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of this disclosure.

Example 2

According to an embodiment of the present disclosure, an instruction processing device for implementing the above-described instruction processing method is also provided. FIG7 is a schematic diagram of an instruction processing device according to an embodiment of the present disclosure. As shown in FIG7, the device 700 includes: a monitoring module 702, a calling module 704, and an execution module 706.

The monitoring module is used to monitor the processing flow of the source instruction file of the first language through the toolchain and determine whether the instruction to be processed in the source instruction file is a preset instruction; the calling module is used to call the interpretation component in the toolchain to process the instruction description information of the instruction to be processed when the instruction to be processed is a preset instruction, so as to obtain multiple instruction elements of the second language; the execution module is used to execute multiple instruction elements of the second language through the toolchain to obtain the processing result of the instruction to be processed.

It should be noted that the monitoring module 702, the calling module 704, and the execution module 706 mentioned above correspond to steps S302 to S306 in Embodiment 1. The three modules and their corresponding steps implement the same instances and application scenarios, but are not limited to the content disclosed in Embodiment 1. It should be noted that the above modules or units can be hardware or software components stored in memory (e.g., memory 104) and processed by one or more processors (e.g., processors 102a, 102b, ..., 102n). The above modules can also be part of a device and run in the computer terminal 10 provided in Embodiment 1.

In the above embodiments of this disclosure, the calling module is further configured to process the instruction description information through the interpretation component to generate a directed acyclic graph, wherein the multiple nodes contained in the directed acyclic graph correspond one-to-one with multiple instruction elements, and the edges connecting different nodes in the directed acyclic graph are used to characterize the association relationship between different instruction elements.

In the above embodiments of this disclosure, the device further includes: a loading module and a matching module.

The loading module is used to load the configuration file into the toolchain. The configuration file contains instruction description information for at least one preset instruction. The matching module is used to match the character representation of at least one preset instruction with the character representation of the instruction to be processed to determine the instruction description information of the instruction to be processed.

In the above embodiments of this disclosure, the matching module is further configured to determine the instruction description information of any preset instruction as the instruction description information of the instruction to be processed when the character representation of any preset instruction is the same as the character representation of the instruction to be processed.

In the above embodiments of this disclosure, the execution module is further configured to determine the target type of the toolchain and the target semantic action corresponding to the target type; and to perform target semantic actions on multiple instruction elements through the toolchain to obtain the processing result.

In the above embodiments of this disclosure, the execution module is further configured to determine the target semantic action as executing multiple instruction elements in the simulator when the target type is a simulator; determine the target semantic action as matching multiple instruction elements with text when the target type is an assembler; and determine the target semantic action as matching multiple instruction elements with intermediate instructions of the first language when the target type is a compiler.

In the embodiments described above, the preset instruction is used to characterize an instruction not included in the simplified instruction set, or an instruction set by the target object.

It should be noted that the preferred implementation schemes involved in the above embodiments of this disclosure are the same as the schemes, application scenarios and implementation processes provided in Embodiment 1, but are not limited to the schemes provided in Embodiment 1.

Example 3

According to an embodiment of the present disclosure, an instruction processing system is also provided. FIG8 is a schematic diagram of an instruction processing system according to an embodiment of the present disclosure. As shown in FIG8, the system 800 includes: a toolchain 802, which includes at least an execution component 8021 and an interpretation component 8022.

The toolchain includes at least an execution component and an interpretation component. The execution component is used to process the source instruction file of the first language and determine whether the instruction to be processed in the source instruction file is a preset instruction. The interpretation component is used to process the instruction description information of the instruction to be processed to obtain multiple instruction elements of the second language. The execution component is also used to execute the multiple instruction elements of the second language to obtain the processing result of the instruction to be processed.

The execution components mentioned above can refer to components used to execute program source code. They translate the source code into machine code or intermediate code, and then run it on the target platform. Execution components can be compilers, assemblers, linkers, etc., which are responsible for converting source code into executable programs or libraries.

The aforementioned interpreting component can represent a component used to interpret and execute program source code. It can achieve the program's functionality by interpreting and executing the source code line by line. The interpreting component can be an interpreter, which can directly interpret and execute scripts or program source code.

In the above embodiments of this disclosure, the interpretation component includes: an interpreter, used to process instruction description information and generate a directed acyclic graph, wherein the multiple nodes in the directed acyclic graph correspond one-to-one with multiple instruction elements, and the edges connecting different nodes in the directed acyclic graph are used to characterize the association relationship between different instruction elements; wherein the execution component is used to execute the directed acyclic graph to obtain the processing result.

The interpreter mentioned above can be a Python interpreter. This is just an example and is not a limitation. The specific interpreter can be adjusted according to the actual use case.

In the embodiments disclosed above, the execution component includes one of the following: a simulator for executing the semantics of multiple instruction elements; an assembler for matching the multiple instruction elements with text; and a compiler for matching the multiple instruction elements with intermediate instructions of a first language.

It should be noted that the preferred implementation schemes involved in the above embodiments of this disclosure are the same as the schemes, application scenarios and implementation processes provided in Embodiment 1, but are not limited to the schemes provided in Embodiment 1.

Example 4

According to embodiments of this disclosure, a system-on-a-chip is also provided, including: an instruction processing system according to any one of the above embodiments.

Example 5

Embodiments of this disclosure can provide an electronic device, which can be any one of a group of electronic devices. Optionally, in this embodiment, the aforementioned electronic device can also be replaced with a terminal device such as a mobile terminal.

Optionally, in this embodiment, the aforementioned electronic device may be located in at least one of a plurality of network devices in a computer network.

In this embodiment, the computer terminal described above can execute the program code in the method.

Optionally, FIG9 is a structural block diagram of an electronic device according to an embodiment of the present disclosure. As shown in FIG9, the electronic device A may include: one or more (only one is shown in the figure) processors 102, memory 104, memory controller, and peripheral interface, wherein the peripheral interface is connected to a radio frequency module, an audio module, and a display.

The memory can be used to store software programs and modules, such as the program instructions/modules corresponding to the methods and apparatus in the embodiments of this disclosure. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory, thereby implementing the methods in the above embodiments. The memory may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory may further include memory remotely located relative to the processor, and these remote memories can be connected to terminal A via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

The processor can access information and applications stored in memory via a transmission device to perform the following steps: monitor the processing flow of a source instruction file in the first language processed by a toolchain, and determine whether the instruction to be processed in the source instruction file is a preset instruction; if the instruction to be processed is a preset instruction, call the interpretation component in the toolchain to process the instruction description information of the instruction to be processed to obtain multiple instruction elements in the second language; execute the multiple instruction elements in the second language through the toolchain to obtain the processing result of the instruction to be processed.

Optionally, the processor may also execute program code that performs the following steps: processes instruction description information through an interpretation component to generate a directed acyclic graph, wherein multiple nodes in the directed acyclic graph correspond one-to-one with multiple instruction elements, and the edges connecting different nodes in the directed acyclic graph are used to characterize the association between different instruction elements.

Optionally, the processor may also execute program code that performs the following steps: loading a configuration file into the toolchain, wherein the configuration file contains instruction description information for at least one preset instruction; matching the character representation of at least one preset instruction with the character representation of the instruction to be processed to determine the instruction description information of the instruction to be processed.

Optionally, the processor may also execute program code that performs the following steps: if the character representation of any preset instruction is the same as the character representation of the instruction to be processed, determine the instruction description information of any preset instruction as the instruction description information of the instruction to be processed.

Optionally, the processor may also execute program code that performs the following steps: determines the target type of the toolchain and the target semantic action corresponding to the target type; performs target semantic actions on multiple instruction elements through the toolchain to obtain the processing result.

Optionally, the processor may also execute program code that performs the following steps: when the target type is a simulator, determines the target semantic action as executing multiple instruction elements in the simulator; when the target type is an assembler, determines the target semantic action as matching multiple instruction elements with text; when the target type is a compiler, determines the target semantic action as matching multiple instruction elements with intermediate instructions of the first language.

Optionally, the processor may also execute program code that includes the following steps: preset instructions used to characterize instructions not included in the reduced instruction set, or instructions set by the target object.

By employing the embodiments of this disclosure, the processing flow of a source instruction file in a first language processed by a toolchain is monitored to determine whether the instruction to be processed in the source instruction file is a preset instruction. If the instruction to be processed is a preset instruction, the interpretation component in the toolchain is invoked to process the instruction description information of the instruction to be processed, thereby obtaining multiple instruction elements in a second language. The multiple instruction elements in the second language are executed by the toolchain to obtain the processing result of the instruction to be processed, thus improving the accuracy of instruction processing. It is noteworthy that when processing a source instruction file in a first language through a toolchain, if there is an instruction to be processed that is a preset instruction, the interpretation component in the toolchain can be invoked to interpret the instruction description information of the instruction to be processed, so as to obtain multiple instruction elements in the second language that the toolchain can execute. This allows the toolchain to efficiently and accurately process and execute the source instruction file without introducing additional language learning costs, thereby improving the accuracy of instruction processing and solving the technical problem of low accuracy in instruction processing in related technologies.

It will be understood by those skilled in the art that the structure shown in Figure 9 is merely illustrative, and the electronic device may also be a smartphone (such as an Android phone, an iOS phone, etc.), a tablet computer, a PDA, a mobile internet device (MID), a PAD, or other terminal device. Figure 9 does not limit the structure of the aforementioned electronic device. For example, electronic device A may include more or fewer components (such as a network interface, a display device, etc.) than shown in the figure, or may have a different configuration than that shown in Figure 9.

Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing the hardware related to the terminal device. The program can be stored in a computer-readable storage medium, which may include: flash drive, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

Example 6

Embodiments of this disclosure also provide a computer-readable storage medium. Optionally, in this embodiment, the computer-readable storage medium can be used to store program code executed by the method provided in the above embodiments.

Optionally, in this embodiment, the storage medium may be located in any one of the electronic devices in the group of electronic devices in the computer network, or in any one of the mobile terminals in the group of mobile terminals.

Optionally, in this embodiment, the computer-readable storage medium is configured to store program code for performing the following steps: monitoring the processing flow of a source instruction file of the first language processed by a toolchain, and determining whether the instruction to be processed in the source instruction file is a preset instruction; if the instruction to be processed is a preset instruction, calling the interpretation component in the toolchain to process the instruction description information of the instruction to be processed to obtain multiple instruction elements of the second language; executing the multiple instruction elements of the second language through the toolchain to obtain the processing result of the instruction to be processed.

Optionally, the computer-readable storage medium is further configured to store program code for performing the following steps: processing instruction description information through an interpretation component to generate a directed acyclic graph, wherein the directed acyclic graph contains multiple nodes that correspond one-to-one with multiple instruction elements, and the edges connecting different nodes in the directed acyclic graph are used to characterize the association relationships between different instruction elements.

Optionally, the computer-readable storage medium is further configured to store program code for performing the following steps: loading a configuration file into a toolchain, wherein the configuration file contains instruction description information for at least one preset instruction; matching the character representation of at least one preset instruction with the character representation of an instruction to be processed to determine the instruction description information of the instruction to be processed.

Optionally, the computer-readable storage medium is further configured to store program code for performing the following steps: determining the instruction description information of any preset instruction as the instruction description information of the instruction to be processed, provided that the character representation of any preset instruction is the same as the character representation of the instruction to be processed.

Optionally, the computer-readable storage medium is further configured to store program code for performing the following steps: determining the target type of the toolchain and determining the target semantic action corresponding to the target type; performing target semantic actions on multiple instruction elements through the toolchain to obtain the processing result.

Optionally, the computer-readable storage medium is further configured to store program code for performing the following steps: if the target type is an emulator, determining the target semantic action as executing multiple instruction elements in the emulator; if the target type is an assembler, determining the target semantic action as matching multiple instruction elements with text; if the target type is a compiler, determining the target semantic action as matching multiple instruction elements with intermediate instructions of a first language.

Optionally, the computer-readable storage medium is also configured to store program code for performing the following steps: preset instructions for characterizing instructions not included in the reduced instruction set, or instructions set by the target object.

By employing the embodiments of this disclosure, the processing flow of a source instruction file in a first language processed by a toolchain is monitored to determine whether the instruction to be processed in the source instruction file is a preset instruction. If the instruction to be processed is a preset instruction, the interpretation component in the toolchain is invoked to process the instruction description information of the instruction to be processed, thereby obtaining multiple instruction elements in a second language. The multiple instruction elements in the second language are executed by the toolchain to obtain the processing result of the instruction to be processed, thus improving the accuracy of instruction processing. It is noteworthy that when processing a source instruction file in a first language through a toolchain, if there is an instruction to be processed that is a preset instruction, the interpretation component in the toolchain can be invoked to interpret the instruction description information of the instruction to be processed, so as to obtain multiple instruction elements in the second language that the toolchain can execute. This allows the toolchain to efficiently and accurately process and execute the source instruction file without introducing additional language learning costs, thereby improving the accuracy of instruction processing and solving the technical problem of low accuracy in instruction processing in related technologies.

Example 7

Embodiments of this disclosure also provide a computer program product. Optionally, in this embodiment, the computer program product may include a computer program that, when executed by a processor, implements the methods provided in the embodiments described above.

Example 8

Embodiments of this disclosure also provide a computer program product. Optionally, the computer program product may include a non-volatile computer-readable storage medium, which can be used to store a computer program that, when executed by a processor, implements the methods provided in the embodiments described above.

Example 9

Embodiments of this disclosure also provide a computer program. Optionally, in this embodiment, when the computer program is executed by a processor, it implements the method provided in the above embodiments.

The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

In the above embodiments of this disclosure, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

In the several embodiments provided in this disclosure, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some interfaces; indirect couplings or communication connections between units or modules may be electrical or other forms.

The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

Furthermore, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard drive, magnetic disk, or optical disk.

The above description is only a preferred embodiment of this disclosure. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims (15)

An instruction processing method, comprising: Monitor the processing flow of source instruction files of the first language through the toolchain, and determine whether the instruction to be processed in the source instruction file is a preset instruction; If the instruction to be processed is the preset instruction, the interpretation component in the toolchain is invoked to process the instruction description information of the instruction to be processed, thereby obtaining multiple instruction elements in the second language. The toolchain is used to execute multiple instruction elements of the second language to obtain the processing result of the instruction to be processed. According to the method of claim 1, wherein the step of invoking the interpretation component in the toolchain to process the instruction description information of the instruction to be processed to obtain multiple instruction elements of the second language includes: The instruction description information is processed by the interpretation component to generate a directed acyclic graph, wherein the multiple nodes in the directed acyclic graph correspond one-to-one with the multiple instruction elements, and the edges connecting different nodes in the directed acyclic graph are used to represent the association relationship between different instruction elements. The method according to claim 2, wherein the method further comprises: Load the configuration file into the toolchain, wherein the configuration file contains instruction description information for at least one of the preset instructions; The character representation of at least one preset instruction is matched with the character representation of the instruction to be processed to determine the instruction description information of the instruction to be processed. According to the method of claim 3, the step of matching the character representation of the at least one preset instruction with the character representation of the instruction to be processed to determine the instruction description information of the instruction to be processed includes: If the character representation of any of the preset instructions is the same as the character representation of the instruction to be processed, then the instruction description information of any of the preset instructions is determined as the instruction description information of the instruction to be processed. According to the method of claim 1, wherein executing multiple instruction elements of the second language through the toolchain to obtain the processing result of the instruction to be processed includes: Determine the target type of the toolchain, and determine the target semantic action corresponding to the target type; The target semantic action is performed on the multiple instruction elements through the toolchain to obtain the processing result. According to the method of claim 5, wherein determining the target semantic action corresponding to the target type includes: When the target type is a simulator, the target semantic action is determined to be the semantics of executing the plurality of instruction elements in the simulator; When the target type is an assembler, the target semantic action is determined to be matching the plurality of instruction elements with text; When the target type is a compiler, the target semantic action is determined to be matching the plurality of instruction elements with intermediate instructions of the first language. According to the method of claim 1, the preset instruction is used to characterize an instruction not included in the simplified instruction set, or an instruction set by the target object. According to the method of claim 7, the instructions in the reduced instruction set are obtained through an open-source instruction set architecture. The method according to claim 3, wherein the method further comprises: The configuration file is generated based on the semantics of the Python description extension instruction set. An instruction processing system, comprising: A toolchain must contain at least execution components and interpretation components; The execution component is used to process the source instruction file of the first language and determine whether the instruction to be processed in the source instruction file is a preset instruction; the interpretation component is used to process the instruction description information of the instruction to be processed to obtain multiple instruction elements of the second language; the execution component is also used to execute the multiple instruction elements of the second language to obtain the processing result of the instruction to be processed. The system of claim 10, wherein the interpretation component comprises: An interpreter is used to process the instruction description information and generate a directed acyclic graph, wherein the multiple nodes contained in the directed acyclic graph correspond one-to-one with the multiple instruction elements, and the edges connecting different nodes in the directed acyclic graph are used to represent the association relationship between different instruction elements. The execution component is used to execute the directed acyclic graph to obtain the processing result. The system according to claim 10, wherein the execution component comprises one of the following: A simulator for executing the semantics of the plurality of instruction elements; An assembler is used to match the plurality of instruction elements with text; A compiler for matching the plurality of instruction elements with intermediate instructions of the first language. A system-on-a-chip includes: the instruction processing system according to any one of claims 10 to 12. A computer-readable storage medium comprising a stored executable program, wherein, when the executable program is executed, it controls the device on which the storage medium is located to perform the method according to any one of claims 1 to 9. A computer program product includes a computer program that, when executed by a processor, implements the method according to any one of claims 1 to 9.