WO2025231634A1

WO2025231634A1 - Routing based direct-through imaging processing

Info

Publication number: WO2025231634A1
Application number: PCT/CN2024/091590
Authority: WO
Inventors: Bohan HUANG; Jeffery DU; Chao Li; Kai Liu; Fei Zhang; Kui Wang; Kebin AN
Original assignee: Qualcomm Inc
Current assignee: Qualcomm Inc
Priority date: 2024-05-08
Filing date: 2024-05-08
Publication date: 2025-11-13
Anticipated expiration: 2026-11-08

Abstract

This disclosure provides systems, methods, and devices for image signal processing that support routing based direct-through image processing. In a first aspect, an apparatus for image processing includes a memory, and an image signal processor. The image signal processor includes: a first image signal processing (ISP) node configured to determine first image data, a routing module configured to route the first image data to a second ISP node, and a second ISP node configured to determine second image data based on the first image data. Other aspects and features are also claimed and described.

Description

ROUTING BASED DIRECT-THROUGH IMAGING PROCESSING

TECHNICAL FIELD

Aspects of the present disclosure relate generally to signal processing, and more particularly, to data routing for image processing. Some features may enable and provide improved image signal routing and processing, including improved circuit and techniques to reduce memory spaces, memory bandwidth, and buffer delay.

INTRODUCTION

Image capture devices are devices that can capture one or more digital images, whether still images for photos or sequences of images for videos. Capture devices can be incorporated into a wide variety of devices. By way of example, image capture devices may comprise stand-alone digital cameras or digital video camcorders, camera-equipped wireless communication device handsets, such as mobile telephones, cellular or satellite radio telephones, personal digital assistants (PDAs) , panels or tablets, gaming devices, computing devices such as webcams, video surveillance cameras, or other devices with digital imaging or video capabilities.

The amount of image data and the frame rate captured by an image sensor has increased through subsequent generations of image capture devices. The amount of information captured by an image sensor is related to a number of pixels in an image sensor of the image capture device, which may be measured as a number of megapixels indicating the number of millions of sensors in the image sensor. For example, a 12-megapixel image sensor has 12 million pixels. Higher megapixel values generally represent higher resolution images that are more desirable for viewing by the user. The frame rate is the frequency at which consecutive images or frames are captured by the image sensor. For example, the frame rate of the image sensor may be 24 frames per second (fps) . When the frame rate of image frames or a video captured by the image sensor or device is higher than 24 fps, the frame rate of a video is considered high frame rate (HFR) .

The increasing amount of image data captured by the image capture device and the increased frame rate have some negative effects that accompany the increasing resolution obtained by the additional image data and the reduced time to process each frame. Additional image data within a certain time period increases the amount of processing performed by the image capture device in determining image frames and videos from the image data, as well as in performing other operations related to the image data. For example, the image data may be processed through several processing blocks for enhancing the image before the image data is displayed to a user on a display or transmitted to a recipient in a message. Each of the processing blocks consumes additional power proportional to the amount of image data, or number of megapixels, in the image capture. The additional power consumption may shorten the operating time of an image capture device using battery power, such as a mobile phone.

BRIEF SUMMARY OF SOME EXAMPLES

The following summarizes some aspects of the present disclosure to provide a basic understanding of the discussed technology. This summary is not an extensive overview of all contemplated features of the disclosure and is intended neither to identify key or critical elements of all aspects of the disclosure nor to delineate the scope of any or all aspects of the disclosure. Its sole purpose is to present some concepts of one or more aspects of the disclosure in summary form as a prelude to the more detailed description that is presented later.

In some aspects, the present disclosure provides systems, apparatus, methods, and computer-readable media that support routing-based direct-through image signal processing. Direct-through image signal processing includes transferring image data from one ISP node to another ISP node through a routing module, without accessing a shared memory system accessible to the ISP and other components, and/or without accessing a shared memory system addressable by the ISP nodes coupled to the routing module. For example, an image signal processor may include a first image signal processing (ISP) node, a second ISP node, and a routing module coupling the first ISP node to the second ISP node. The first ISP node determines first image data. Then, the routing module routes the first image data to the second ISP node that determines second image data based on the first image data. In some examples, when the image signal processor is unavailable or has limited capability to process the first image data, the image signal processor may store the first image data in a memory (e.g., a random-access memory (RAM) , a double data rate dynamic RAM (DDR SDRAM) , DDR2, DDR3, DDR4, or DDR5) . Then, at a later time when the ISP has sufficient capability to resume operations on the data, the routing module may retrieve the first image data from the memory and route the first data to the second ISP node. In some examples, the first or second ISP node may correspond to an ISP engine or a hardware component with a fixed ISP circuits (e.g., an image front end engine (IFE) , an image post-processing engine (IPE) , an auto exposure compensation engine (AEC) , an engine for video analytics (EVA) , or a Bayer processing section engine (BPS) ) . In other examples, the first or second ISP node may be configured based on input image data (e.g., an image frame) . In such examples, the second ISP nodes may reuse a source or sink circuit of the first ISP node.

The use of the routing-based direct-through image data processing may improve the image processing flow. For example, the disclosed technique reduces memory consumption and reduces memory bandwidth, and has low latency across ISP nodes because the disclosed technique routes the image data between ISP nodes without normally accessing a shared memory system. In addition, the disclosed technique may use less hardware circuits by redefining ISP nodes to reuse source or sink circuits. Thus, the improved image processing flow may result in efficient and less power consumption of the image capture device and lead to the longer operation time of the image capture device using battery power.

In one aspect of the disclosure, an apparatus includes a memory and an image signal processor. The image signal processor includes a first image signal processing (ISP) node configured to determine first image data, a routing module configured to route the first image data to a second ISP node, and the second ISP node configured to determine second image data based on the first image data.

In an additional aspect of the disclosure, a method for image processing includes determining, in a first image signal processing (ISP) node of an image signal processor, first image data; routing, by a routing module of the image signal processor, the first image data to a second ISP node; and determining, in the second ISP node of the image signal processor, second image data based on the first image data.

In an additional aspect of the disclosure, an image capture device includes a first image sensor and an image signal processor coupled to the first image sensor. The image processor includes a first image signal processing (ISP) node configured to determine first image data, a routing module configured to route the first image data to a second ISP node, and the second ISP node configured to determine second image data based on the first image data.

Methods of image processing described herein may be performed by an image capture device and/or performed on image data captured by one or more image capture devices. Image capture devices, devices that can capture one or more digital images, whether still image photos or sequences of images for videos, can be incorporated into a wide variety of devices. By way of example, image capture devices may comprise stand-alone digital cameras or digital video camcorders, camera-equipped wireless communication device handsets, such as mobile telephones, cellular or satellite radio telephones, personal digital assistants (PDAs) , panels or tablets, gaming devices, computing devices such as webcams, video surveillance cameras, or other devices with digital imaging or video capabilities.

The image processing techniques described herein may involve digital cameras having image sensors and processing circuitry (e.g., application specific integrated circuits (ASICs) , digital signal processors (DSP) , graphics processing unit (GPU) , or central processing units (CPU) ) . An image signal processor (ISP) may include one or more of these processing circuits and configured to perform operations to obtain the image data for processing according to the image processing techniques described herein and/or involved in the image processing techniques described herein. The ISP may be configured to control the capture of image frames from one or more image sensors and determine one or more image frames from the one or more image sensors to generate a view of a scene in an output image frame. The output image frame may be part of a sequence of image frames forming a video sequence. The video sequence may include other image frames received from the image sensor or other images sensors.

In an example application, the image signal processor (ISP) may receive an instruction to capture a sequence of image frames in response to the loading of software, such as a camera application, to produce a preview display from the image capture device. The image signal processor may be configured to produce a single flow of output image frames, based on images frames received from one or more image sensors. The single flow of output image frames may include raw image data from an image sensor, binned image data from an image sensor, or corrected image data processed by one or more algorithms within the image signal processor. For example, an image frame obtained from an image sensor, which may have performed some processing on the data before output to the image signal processor, may be processed in the image signal processor by processing the image frame through an image post-processing engine (IPE) and/or other image processing circuitry for performing one or more of tone mapping, portrait lighting, contrast enhancement, gamma correction, etc. The output image frame from the ISP may be stored in memory and retrieved by an application processor executing the camera application, which may perform further processing on the output image frame to adjust an appearance of the output image frame and reproduce the output image frame on a display for view by the user.

After an output image frame representing the scene is determined by the image signal processor and/or determined by the application processor, such as through image processing techniques described in various embodiments herein, the output image frame may be displayed on a device display as a single still image and/or as part of a video sequence, saved to a storage device as a picture or a video sequence, transmitted over a network, and/or printed to an output medium. For example, the image signal processor (ISP) may be configured to obtain input frames of image data (e.g., pixel values) from the one or more image sensors, and in turn, produce corresponding output image frames (e.g., preview display frames, still-image captures, frames for video, frames for object tracking, etc. ) . In other examples, the image signal processor may output image frames to various output devices and/or camera modules for further processing, such as for 3A parameter synchronization (e.g., automatic focus (AF) , automatic white balance (AWB) , and automatic exposure control (AEC) ) , producing a video file via the output frames, configuring frames for display, configuring frames for storage, transmitting the frames through a network connection, etc. Generally, the image signal processor (ISP) may obtain incoming frames from one or more image sensors and produce and output a flow of output frames to various output destinations.

In some aspects, the output image frame may be produced by combining aspects of the image correction of this disclosure with other computational photography techniques such as high dynamic range (HDR) photography or multi-frame noise reduction (MFNR) . With HDR photography, a first image frame and a second image frame are captured using different exposure times, different apertures, different lenses, and/or other characteristics that may result in improved dynamic range of a fused image when the two image frames are combined. In some aspects, the method may be performed for MFNR photography in which the first image frame and a second image frame are captured using the same or different exposure times and fused to generate a corrected first image frame with reduced noise compared to the captured first image frame.

In some aspects, a device may include an image signal processor or a processor (e.g., an application processor) including specific functionality for camera controls and/or processing, such as enabling or disabling the binning module or otherwise controlling aspects of the image correction. The methods and techniques described herein may be entirely performed by the image signal processor or a processor, or various operations may be split between the image signal processor and a processor, and in some aspects split across additional processors.

The device may include one, two, or more image sensors, such as a first image sensor. When multiple image sensors are present, the image sensors may be differently configured. For example, the first image sensor may have a larger field of view (FOV) than the second image sensor, or the first image sensor may have different sensitivity or different dynamic range than the second image sensor. In one example, the first image sensor may be a wide-angle image sensor, and the second image sensor may be a tele image sensor. In another example, the first sensor is configured to obtain an image through a first lens with a first optical axis and the second sensor is configured to obtain an image through a second lens with a second optical axis different from the first optical axis. Additionally or alternatively, the first lens may have a first magnification, and the second lens may have a second magnification different from the first magnification. Any of these or other configurations may be part of a lens cluster on a mobile device, such as where multiple image sensors and associated lenses are located in offset locations on a frontside or a backside of the mobile device. Additional image sensors may be included with larger, smaller, or same field of views. The image processing techniques described herein may be applied to image frames captured from any of the image sensors in a multi-sensor device.

In an additional aspect of the disclosure, a device configured for image processing and/or image capture is disclosed. The apparatus includes means for capturing image frames. The apparatus further includes one or more means for capturing data representative of a scene, such as image sensors (including charge-coupled devices (CCDs) , Bayer-filter sensors, infrared (IR) detectors, ultraviolet (UV) detectors, complimentary metal-oxide-semiconductor (CMOS) sensors) and time of flight detectors. The apparatus may further include one or more means for accumulating and/or focusing light rays into the one or more image sensors (including simple lenses, compound lenses, spherical lenses, and non-spherical lenses) . These components may be controlled to capture the first and/or second image frames input to the image processing techniques described herein.

Other aspects, features, and implementations will become apparent to those of ordinary skill in the art, upon reviewing the following description of specific, exemplary aspects in conjunction with the accompanying figures. While features may be discussed relative to certain aspects and figures below, various aspects may include one or more of the advantageous features discussed herein. In other words, while one or more aspects may be discussed as having certain advantageous features, one or more of such features may also be used in accordance with the various aspects. In similar fashion, while exemplary aspects may be discussed below as device, system, or method aspects, the exemplary aspects may be implemented in various devices, systems, and methods.

The method may be embedded in a computer-readable medium as computer program code comprising instructions that cause a processor to perform the steps of the method. In some embodiments, the processor may be part of a mobile device including a first network adaptor configured to transmit data, such as images or videos in a recording or as streaming data, over a first network connection of a plurality of network connections; and a processor coupled to the first network adaptor and the memory. The processor may cause the transmission of output image frames described herein over a wireless communications network such as a 5G NR communication network.

The foregoing has outlined, rather broadly, the features and technical advantages of examples according to the disclosure in order that the detailed description that follows may be better understood. Additional features and advantages will be described hereinafter. The conception and specific examples disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. Such equivalent constructions do not depart from the scope of the appended claims. Characteristics of the concepts disclosed herein, both their organization and method of operation, together with associated advantages will be better understood from the following description when considered in connection with the accompanying figures. Each of the figures is provided for the purposes of illustration and description, and not as a definition of the limits of the claims.

While aspects and implementations are described in this application by illustration to some examples, those skilled in the art will understand that additional implementations and use cases may come about in many different arrangements and scenarios. Innovations described herein may be implemented across many differing platform types, devices, systems, shapes, sizes, and packaging arrangements. For example, aspects and/or uses may come about via integrated chip implementations and other non-module-component based devices (e.g., end-user devices, vehicles, communication devices, computing devices, industrial equipment, retail/purchasing devices, medical devices, artificial intelligence (AI) -enabled devices, etc. ) . While some examples may or may not be specifically directed to use cases or applications, a wide assortment of applicability of described innovations may occur. Implementations may range in spectrum from chip-level or modular components to non-modular, non-chip-level implementations and further to aggregate, distributed, or original equipment manufacturer (OEM) devices or systems incorporating one or more aspects of the described innovations. In some practical settings, devices incorporating described aspects and features may also necessarily include additional components and features for implementation and practice of claimed and described aspects. For example, transmission and reception of wireless signals necessarily includes a number of components for analog and digital purposes (e.g., hardware components including antenna, radio frequency (RF) -chains, power amplifiers, modulators, buffer, processor (s) , interleaver, adders/summers, etc. ) . It is intended that innovations described herein may be practiced in a wide variety of devices, chip-level components, systems, distributed arrangements, end-user devices, etc. of varying sizes, shapes, and constitution.

BRIEF DESCRIPTION OF THE DRAWINGS

A further understanding of the nature and advantages of the present disclosure may be realized by reference to the following drawings. In the appended figures, similar components or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If just the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.

Figure 1 shows a block diagram of an example device for performing image capture from one or more image sensors.

Figure 2 is a block diagram illustrating an example data flow path for image data processing in an image capture device according to one or more embodiments of the disclosure.

Figure 3 shows a flow chart of an example method for routing based direct-through image signal processing according to some embodiments of the disclosure.

Figure 4 is a block diagram illustrating image signal processing (ISP) engine-based ISP nodes of an image signal processor for direct-through image signal processing using imaging signal processing nodes in an image capture device according to one or more embodiments of the disclosure.

Figure 5 is a block diagram illustrating including category based multiple ISP nodes of an image signal processor for direct-through image data processing according to some embodiments of the disclosure.

Figure 6 is a block diagram illustrating a routing process for direct-through image data processing according to some embodiments of the disclosure.

Like reference numbers and designations in the various drawings indicate like elements.

DETAILED DESCRIPTION

The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to limit the scope of the disclosure. Rather, the detailed description includes specific details for the purpose of providing a thorough understanding of the inventive subject matter. It will be apparent to those skilled in the art that these specific details are not required in every case and that, in some instances, well-known structures and components are shown in block diagram form for clarity of presentation.

In one conventional technique, an image buffer stored in a shared memory is transferred across image signal processing nodes. The transferred buffer across nodes may lead to unnecessary memory consumption, high bandwidth cost, unstable per frame processing time, large buffer delay across nodes, and unnecessary power consumption, all of which are worse at high frame rates. Shortcomings mentioned here are only representative and are included to highlight problems that the inventors have identified with respect to existing devices and sought to improve upon. Aspects of devices described below may address some or all of the shortcomings as well as others known in the art. Aspects of the improved devices described herein may present other benefits than, and be used in other applications than, those described above.

The present disclosure provides systems, apparatus, methods, and computer-readable media that support routing-based direct-through image signal processing. Direct-through image signal processing includes transferring image data from one ISP node to another ISP node through a routing module, without accessing a shared memory system accessible to the ISP and other components, and/or without accessing a shared memory system addressable by the ISP nodes coupled to the routing module. For example, an image signal processor may include a first image signal processing (ISP) node, a second ISP node, and a routing module coupling the first ISP node to the second ISP node. The first ISP node determines first image data. Then, the routing module routes the first image data to the second ISP node that determines second image data based on the first image data. In some examples, when the image signal processor is unavailable or has limited capability to process the first image data, the image signal processor may store the first image data in a memory (e.g., a random-access memory (RAM) , a double data rate dynamic RAM (DDR SDRAM) , DDR2, DDR3, DDR4, or DDR5) . Then, at a later time when the ISP has sufficient capability to resume operations on the data, the routing module may retrieve the first image data from the memory and route the first data to the second ISP node. In some examples, the first or second ISP node may correspond to an ISP engine or a hardware component with a fixed ISP circuits (e.g., an image front end engine (IFE) , an image post-processing engine (IPE) , an auto exposure compensation engine (AEC) , an engine for video analytics (EVA) , or a Bayer processing section engine (BPS) ) . In other examples, the first or second ISP node may be configured based on input image data (e.g., an image frame) . In such examples, the second ISP nodes may reuse a source or sink circuit of the first ISP node.

In the description of embodiments herein, numerous specific details are set forth, such as examples of specific components, circuits, and processes to provide a thorough understanding of the present disclosure. The term “coupled” as used herein means connected directly to or connected through one or more intervening components or circuits. Also, in the following description and for purposes of explanation, specific nomenclature is set forth to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that these specific details may not be required to practice the teachings disclosed herein. In other instances, well known circuits and devices are shown in block diagram form to avoid obscuring teachings of the present disclosure.

Some portions of the detailed descriptions which follow are presented in terms of procedures, logic blocks, processing, and other symbolic representations of operations on data bits within a computer memory. In the present disclosure, a procedure, logic block, process, or the like, is conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, although not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system.

An example device for capturing image frames using one or more image sensors, such as a smartphone, may include a configuration of one, two, three, four, or more camera modules on a backside (e.g., a side opposite a primary user display) and/or a front side (e.g., a same side as a primary user display) of the device. The devices may include one or more image signal processors (ISPs) , Computer Vision Processors (CVPs) (e.g., AI engines) , or other suitable circuitry for processing images captured by the image sensors. The one or more image signal processors (ISP) may store output image frames (such as through a bus) in a memory and/or provide the output image frames to processing circuitry (such as an applications processor) . The processing circuitry may perform further processing, such as for encoding, storage, transmission, or other manipulation of the output image frames.

As used herein, a camera module may include the image sensor and certain other components coupled to the image sensor used to obtain a representation of a scene in image data comprising an image frame. For example, a camera module may include other components of a camera, including a shutter, buffer, or other readout circuitry for accessing individual pixels of an image sensor. In some embodiments, the camera module may include one or more components including the image sensor included in a single package with an interface configured to couple the camera module to an image signal processor or other processor through a bus.

Figure 1 shows a block diagram of a device 100 for performing image capture from one or more image sensors. The device 100 may include, or otherwise be coupled to, an image signal processor (e.g., ISP 112) for processing image frames from one or more image sensors, such as a first image sensor 101, a second image sensor 102, and a depth sensor 140. In some implementations, the device 100 also includes or is coupled to a processor 104 and a memory 106 storing instructions 108 (e.g., a memory storing processor-readable code or a non-transitory computer-readable medium storing instructions) . The device 100 may also include or be coupled to a display 114 and components 116. Components 116 may be used for interacting with a user, such as a touch screen interface and/or physical buttons.

Components 116 may also include network interfaces for communicating with other devices, including a wide area network (WAN) adaptor (e.g., WAN adaptor 152) , a local area network (LAN) adaptor (e.g., LAN adaptor 153) , and/or a personal area network (PAN) adaptor (e.g., PAN adaptor 154) . A WAN adaptor 152 may be a 4G LTE or a 5G NR wireless network adaptor. A LAN adaptor 153 may be an IEEE 802.11 WiFi wireless network adapter. A PAN adaptor 154 may be a Bluetooth wireless network adaptor. Each of the WAN adaptor 152, LAN adaptor 153, and/or PAN adaptor 154may be coupled to an antenna, including multiple antennas configured for primary and diversity reception and/or configured for receiving specific frequency bands. In some embodiments, antennas may be shared for communicating on different networks by the WAN adaptor 152, LAN adaptor 153, and/or PAN adaptor 154. In some embodiments, the WAN adaptor 152, LAN adaptor 153, and/or PAN adaptor 154 may share circuitry and/or be packaged together, such as when the LAN adaptor 153 and the PAN adaptor 154 are packaged as a single integrated circuit (IC) .

The device 100 may further include or be coupled to a power supply 118 for the device 100, such as a battery or an adaptor to couple the device 100 to an energy source. The device 100 may also include or be coupled to additional features or components that are not shown in Figure 1. In one example, a wireless interface, which may include a number of transceivers and a baseband processor in a radio frequency front end (RFFE) , may be coupled to or included in WAN adaptor 152 for a wireless communication device. In a further example, an analog front end (AFE) to convert analog image data to digital image data may be coupled between the first image sensor 101 or second image sensor 102 and processing circuitry in the device 100. In some embodiments, AFEs may be embedded in the ISP 112.

The device may include or be coupled to a sensor hub 150 for interfacing with sensors to receive data regarding movement of the device 100, data regarding an environment around the device 100, and/or other non-camera sensor data. One example non-camera sensor is a gyroscope, which is a device configured for measuring rotation, orientation, and/or angular velocity to generate motion data. Another example non-camera sensor is an accelerometer, which is a device configured for measuring acceleration, which may also be used to determine velocity and distance traveled by appropriately integrating the measured acceleration. In some aspects, a gyroscope in an electronic image stabilization system (EIS) may be coupled to the sensor hub. In another example, a non-camera sensor may be a global positioning system (GPS) receiver, which is a device for processing satellite signals, such as through triangulation and other techniques, to determine a location of the device 100. The location may be tracked over time to determine additional motion information, such as velocity and acceleration. The data from one or more sensors may be accumulated as motion data by the sensor hub 150. One or more of the acceleration, velocity, and/or distance may be included in motion data provided by the sensor hub 150 to other components of the device 100, including the ISP 112 and/or the processor 104.

The ISP 112 may receive captured image data. In one embodiment, a local bus connection couples the ISP 112 to the first image sensor 101 and second image sensor 102 of a first camera 103 and second camera 105, respectively. In another embodiment, a wire interface couples the ISP 112 to an external image sensor. In a further embodiment, a wireless interface couples the ISP 112 to the first image sensor 101 or second image sensor 102.

The first image sensor 101 and the second image sensor 102 are configured to capture image data representing a scene in the field of view of the first camera 103 and second camera 105, respectively. In some embodiments, the first camera 103 and/or second camera 105 output analog data, which is converted by an analog front end (AFE) and/or an analog-to-digital converter (ADC) in the device 100 or embedded in the ISP 112. In some embodiments, the first camera 103 and/or second camera 105 output digital data. The digital image data may be formatted as one or more image frames, whether received from the first camera 103 and/or second camera 105or converted from analog data received from the first camera 103 and/or second camera 105.

The first camera 103 may include the first image sensor 101 and a first lens 131. The second camera may include the second image sensor 102 and a second lens 132. Each of the first lens 131 and the second lens 132 may be controlled by an associated an autofocus (AF) algorithm (e.g., AF 133) executing in the ISP 112, which adjusts the first lens 131 and the second lens 132 to focus on a particular focal plane located at a certain scene depth. The AF 133 may be assisted by depth data received from depth sensor 140. The first lens 131 and the second lens 132 focus light at the first image sensor 101 and second image sensor 102, respectively, through one or more apertures for receiving light, one or more shutters for blocking light when outside an exposure window, and/or one or more color filter arrays (CFAs) for filtering light outside of specific frequency ranges. The first lens 131 and second lens 132 may have different field of views to capture different representations of a scene. For example, the first lens 131 may be an ultra-wide (UW) lens and the second lens 132 may be a wide (W) lens. The multiple image sensors may include a combination of ultra-wide (high field-of-view (FOV) ) , wide, tele, and ultra-tele (low FOV) sensors.

Each of the first camera 103 and second camera 105 may be configured through hardware configuration and/or software settings to obtain different, but overlapping, field of views. In some configurations, the cameras are configured with different lenses with different magnification ratios that result in different fields of view for capturing different representations of the scene. The cameras may be configured such that a UW camera has a larger FOV than a W camera, which has a larger FOV than a T camera, which has a larger FOV than a UT camera. For example, a camera configured for wide FOV may capture fields of view in the range of 64-84 degrees, a camera configured for ultra-side FOV may capture fields of view in the range of 100-140 degrees, a camera configured for tele FOV may capture fields of view in the range of 10-30 degrees, and a camera configured for ultra-tele FOV may capture fields of view in the range of 1-8 degrees.

In some embodiments, one or more of the first camera 103 and/or second camera 105may be a variable aperture (VA) camera in which the aperture can be adjusted to set a particular aperture size. Example aperture sizes include f/2.0, f/2.8, f/3.2, f/8.0, etc. Larger aperture values correspond to smaller aperture sizes, and smaller aperture values correspond to larger aperture sizes. A variable aperture (VA) camera may have different characteristics that produced different representations of a scene based on a current aperture size. For example, a VA camera may capture image data with a depth of focus (DOF) corresponding to a current aperture size set for the VA camera.

The ISP 112 processes image frames captured by the first camera 103 and second camera 105. While Figure 1 illustrates the device 100 as including first camera 103 and second camera 105, any number (e.g., one, two, three, four, five, six, etc. ) of cameras may be coupled to the ISP 112. In some aspects, depth sensors such as depth sensor 140 may be coupled to the ISP 112. Output from the depth sensor 140 may be processed in a similar manner to that of first camera 103 and second camera 105. Examples of depth sensor 140 include active sensors, including one or more of indirect Time of Flight (iToF) , direct Time of Flight (dToF) , light detection and ranging (Lidar) , mmWave, radio detection and ranging (Radar) , and/or hybrid depth sensors, such as structured light sensors. In embodiments without a depth sensor 140, similar information regarding depth of objects or a depth map may be determined from the disparity between first camera 103 and second camera 105, such as by using a depth-from-disparity algorithm, a depth-from-stereo algorithm, phase detection auto-focus (PDAF) sensors, or the like. In addition, any number of additional image sensors or image signal processors may exist for the device 100.

In some embodiments, the ISP 112 may execute instructions from a memory, such as instructions 108 from the memory 106, instructions stored in a separate memory coupled to or included in the ISP 112, or instructions provided by the processor 104. In addition, or in the alternative, the ISP 112 may include specific hardware (such as one or more integrated circuits (ICs) ) configured to perform one or more operations described in the present disclosure. For example, the ISP 112 may include image front end engines (e.g., IFE 135) , image post-processing engines (e.g., IPE 136) , auto exposure compensation engines (e.g., AEC 134) , one or more engines for video analytics (e.g., EVA 137) , and/or Bayer processing section engines (e.g., BPS 138) . An image pipeline may be formed by a sequence of one or more of the IFE 135, IPE 136, EVA 137, and/or BPS 138. In some embodiments, the image pipeline may be reconfigurable in the ISP 112 by changing connections between the IFE 135, IPE 136, EVA 137, and/or BPS 138. The AF 133, AEC 134, IFE 135, IPE 136, EVA 137, and BPS 138 may each include application-specific circuitry, be embodied as software or firmware executed by the ISP 112, and/or a combination of hardware and software or firmware executing on the ISP 112.

The memory 106 may include a non-transient or non-transitory computer readable medium storing computer-executable instructions as instructions 108 to perform all or a portion of one or more operations described in this disclosure. The instructions 108 may include a camera application (or other suitable application such as a messaging application) to be executed by the device 100 for photography or videography. The instructions 108 may also include other applications or programs executed by the device 100, such as an operating system and applications other than for image or video generation. Execution of the camera application, such as by the processor 104, may cause the device 100 to record images using the first camera 103 and/or second camera 105and the ISP 112.

In addition to instructions 108, the memory 106 may also store image frames. The image frames may be output image frames stored by the ISP 112. Further, the memory 106 may store image data as a buffer or a shared memory when the image data are transferred from one ISP node or engine to another ISP node or engine. The output image frames may be accessed by the processor 104 for further operations. In some embodiments, the device 100 does not include the memory 106. For example, the device 100 may be a circuit including the ISP 112, and the memory may be outside the device 100. The device 100 may be coupled to an external memory and configured to access the memory for writing output image frames for display or long-term storage. In some embodiments, the device 100 is a system-on-chip (SoC) that incorporates the ISP 112, the processor 104, the sensor hub 150, the memory 106, and/or components 116 into a single package.

In some embodiments, at least one of the ISP 112 or the processor 104 executes instructions to perform various operations described herein, including routing based image signal processing. For example, execution of the instructions can instruct the ISP 112 to begin or end capturing an image frame or a sequence of image frames, in which the capture includes correction as described in embodiments herein. In some embodiments, the processor 104 may include one or more general-purpose processor cores 104A-N capable of executing instructions to control operation of the ISP 112. For example, the cores 104A-N may execute a camera application (or other suitable application for generating images or video) stored in the memory 106 that activate or deactivate the ISP 112 for capturing image frames and/or control the ISP 112 in the application of routing-based image signal processing to the image frames. The operations of the cores 104A-N and ISP 112 may be based on user input. For example, a camera application executing on processor 104 may receive a user command to begin a video preview display upon which a video comprising a sequence of image frames is captured and processed from first camera 103 and/or the second camera 105 through the ISP 112 for display and/or storage. Image processing to determine “output” or “corrected” image frames, such as according to techniques described herein, may be applied to one or more image frames in the sequence.

In some embodiments, the processor 104 may include ICs or other hardware (e.g., an artificial intelligence (AI) engine such as AI engine 124 or other co-processor) to offload certain tasks from the cores 104A-N. The AI engine 124 may be used to offload tasks related to, for example, face detection and/or object recognition performed using machine learning (ML) or artificial intelligence (AI) . The AI engine 124 may be referred to as an Artificial Intelligence Processing Unit (AI PU) . The AI engine 124 may include hardware configured to perform and accelerate convolution operations involved in executing machine learning algorithms, such as by executing predictive models such as artificial neural networks (ANNs) (including multilayer feedforward neural networks (MLFFNN) , the recurrent neural networks (RNN) , and/or the radial basis functions (RBF) ) . The ANN executed by the AI engine 124 may access predefined training weights for performing operations on user data. The ANN may alternatively be trained during operation of the image capture device 100, such as through reinforcement training, supervised training, and/or unsupervised training. In some other embodiments, the device 100 does not include the processor 104, such as when all of the described functionality is configured in the ISP 112.

In some embodiments, the display 114 may include one or more suitable displays or screens allowing for user interaction and/or to present items to the user, such as a preview of the output of the first camera 103 and/or second camera 105. In some embodiments, the display 114 is a touch-sensitive display. The input/output (I/O) components, such as components 116, may be or include any suitable mechanism, interface, or device to receive input (such as commands) from the user and to provide output to the user through the display 114. For example, the components 116 may include (but are not limited to) a graphical user interface (GUI) , a keyboard, a mouse, a microphone, speakers, a squeezable bezel, one or more buttons (such as a power button) , a slider, a toggle, or a switch.

While shown to be coupled to each other via the processor 104, components (such as the processor 104, the memory 106, the ISP 112, the display 114, and the components 116) may be coupled to each another in other various arrangements, such as via one or more local buses, which are not shown for simplicity. One example of a bus for interconnecting the components is a peripheral component interface (PCI) express (PCIe) bus.

While the ISP 112 is illustrated as separate from the processor 104, the ISP 112 may be a core of a processor 104 that is an application processor unit (APU) , included in a system on chip (SoC) , or otherwise included with the processor 104. While the device 100 is referred to in the examples herein for performing aspects of the present disclosure, some device components may not be shown in Figure 1 to prevent obscuring aspects of the present disclosure. Additionally, other components, numbers of components, or combinations of components may be included in a suitable device for performing aspects of the present disclosure. As such, the present disclosure is not limited to a specific device or configuration of components, including the device 100.

The exemplary image capture device of Figure 1 may be operated to route image data between ISP nodes of the image signal processor without storing the image a shared memory. One example method of operating one or more cameras, such as first camera 103 and/or second camera 105, is shown in Figure 2 and described below.

Figure 2 is a block diagram illustrating an example data flow path for image data processing in an image capture device according to one or more embodiments of the disclosures. Processor 104 of system 200 may communicate with ISP 112 through a bi-directional bus and/or separate control and data lines. The processor 104 may control the first camera 103 through camera control 210. The camera control 210 may be a camera driver executed by the processor 104 for configuring the first camera 103, such as to active or deactivate image capture, configure exposure settings, and/or configure aperture size. Camera control 210 may be managed by a camera application 204 executing on the processor 104. The camera application 204 provides settings accessible to a user such that a user can specify individual camera settings or select a profile with corresponding camera settings. Camera control 210 communicates with the first camera 103 to configure the first camera 103 in accordance with commands received from the camera application 204. The camera application 204 may be, for example, a photography application, a document scanning application, a messaging application, or other application that processes image data acquired from the first camera 103.

The camera configuration may include parameters that specify, for example, a frame rate, an image resolution, a readout duration, an exposure level, an aspect ratio, an aperture size, etc. The first camera 103 may apply the camera configuration and obtain image data representing a scene using the camera configuration. In some embodiments, the camera configuration may be adjusted to obtain different representations of the scene. For example, the processor 104 may execute a camera application 204 to instruct the first camera 103, through camera control 210, to set a first camera configuration for the first camera 103, to obtain first image data from the first camera 103 operating in the first camera configuration, to instruct the first camera 103 to set a second camera configuration for the first camera 103, and to obtain second image data from the first camera 103 operating in the second camera configuration.

In some embodiments in which the first camera 103 is a variable aperture (VA) camera system, the processor 104 may execute a camera application 204 to instruct the first camera 103 to configure to a first aperture size, obtain first image data from the first camera 103, instruct the first camera 103 to configure to a second aperture size, and obtain second image data from the first camera 103. The reconfiguration of the aperture and obtaining of the first and second image data may occur with little or no change in the scene captured at the first aperture size and the second aperture size. Example aperture sizes are f/2.0, f/2.8, f/3.2, f/8.0, etc. Larger aperture values correspond to smaller aperture sizes, and smaller aperture values correspond to larger aperture sizes. That is, f/2.0 corresponds to a larger aperture size than f/8.0.

The image data received from the first camera 103 may be processed in one or more blocks of the ISP 112 to determine output image frames 230 that may be stored in memory 106 and/or otherwise provided to the processor 104. The processor 104 may further process the image data to apply effects to the output image frames 230. Effects may include Bokeh, lighting, color casting, and/or high dynamic range (HDR) merging. In some embodiments, the effects may be applied in the ISP 112.

The output image frames 230 by the ISP 112 may include representations of the scene using the techniques improved by aspects of this disclosure, such that routing or transmitting the first image data to the second ISP node without storing the first image data in a shared memory shared by a first ISP node (e.g., AF 33, AEC 134, IFE 135, IPE 136, EVA 137, or BPS 138) and a second ISP node (e.g., AF 33, AEC 134, IFE 135, IPE 136, EVA 137, or BPS 138) of the ISP 112. The processor 104 may display these output image frames 230 to a user, and the improvements provided by the described processing implemented in the ISP 112 and/or processor 104 improve the energy efficiency and the user experience by reducing memory space and bandwidth usage and latency between ISP nodes. For example, a routing module 212 in the ISP 112 may route first image data of the first ISP node to the second ISP node without storing the first image data in the shared memory. In some examples, the routing module 212 may routing the first image data based on a routing indication from the processor 104 that indicates whether the processor uses less system resources than a threshold or not.

The system 200 of Figure 2 may be configured to perform the operations described with reference to Figure 3 to route date between ISP nodes. Figure 3 shows a flow chart of an example method for routing based direct-through image data processing according to some embodiments of the disclosure. The method in Figure 3 may lead to reduced memory space and bandwidth use and low latency to obtain a digital representation of a scene, which results in a photograph or video. Each of the operations described with reference to Figure 3 may be performed by a processor (e.g., one or a combination of the ISP 112 (including the AF 133, the AEC 134, the IFE 135, the IPE 136, the EVA 137, the BPS 138, and/or the routing module 212) and/or the processor 104 (including cores 104A-N and/or AI engine 124) ) .

At block 302, the processor determines, in a first ISP node of an image signal processor, first image data. The image signal processor may correspond to the ISP 112 in Figures 1 and 2. An ISP node (e.g., the first ISP node or the second ISP node) may include a set of one or more source circuits and one or more sink circuits to perform an image processing function (e.g., tone mapping, image format converting, noise reduction, portrait lighting, contrast enhancement, gamma correction, or any other suitable imaging processing) . A source circuit or source image quality (IQ) circuit is an ISP circuit configured to receive image data in an ISP node. A sink circuit or sink IQ circuit is an ISP circuit configured to determine or transmit output image data to another ISP node. The sink circuit may be electrically coupled to a routing module rather than directly connected to the shared memory. In some examples, a source circuit or source IQ may indicate a circuit or IQ, which may be connected to or electrically coupled with the routing module 212. The source circuit or source IQ may receive a decoded strip frame buffer from a decoder or a router in the routing module 212. The source circuit or source IQ may fetch or retrieve buffers from the routing module 212 or an outside standalone hardware module. A sink circuit or sink IQ may indicate a circuit or IQ, which may be connected to or electrically coupled with the routing module 212. The sink circuit or IQ may transmit a strip frame buffer to the routing module 212 or a data encoder for routing an encoded stripe frame buffer. The sink circuit or sink IQ may write a buffer into the routing module 212 or an outside standalone hardware module. A source and sink circuit or IQ may indicate a circuit or IQ which may be connected to or electrically coupled with the routing module 212 and may either transmit a strip frame or receive a decoded stripe frame to or from the routing module 212. The source and sink circuit or IQ may retrieve and write buffer from and to the routing module 212 or an outside standalone hardware module.

In some examples, the ISP node may be a hardware component of the image signal processor or a predefined set of one or more source circuits and one or more sink circuits to perform an image processing function. The ISP node may be a fixed hardware component corresponding to a particular function (e.g., the AF 133, the AEC 134, the IFE 135, the IPE 136, the EVA 137, or the BPS 138 in Figure 1) of the image processor 112. In some examples, the ISP node may include one or more source circuits 402 and one or more sink circuits 404 to perform an image processing function. For example, Figure 4 shows a block diagram of an ISP (e.g., the ISP 112 in Figures 1 and 2) including multiple ISP nodes for direct-through image data processing according to some embodiments of the disclosure. In Figure 4, the ISP 112 may include multiple engines to process input image data received from an image sensor (e.g., the first image sensor 101 and/or the second image sensor 102) to store one or more output image frames (e.g., the output image frames 230 in Figure 2) in a memory (e.g., the memory 106 in Figures 1 and 2) . For example, the ISP 112 may include an image front end engine (e.g., the IFE 135 in Figure 1) , the Bayer processing section engine (e.g., the BPS 138 in Figure 1) , and first and second image post-processing engine IPE 136A, 136B (e.g., the IPE 136 of Figure 1) . Referring again to Figure 3, the first ISP node may be the IFE 135, the BPS 138, or any other suitable engine in the ISP 112 to determine the first image data.

In some examples, the first ISP node may be the IFE 135 to receive input image data from the sensor 101, 102 to determine one or more processed image data (e.g., the first image data) . In such examples, the input image data may be received by the first ISP node from the image sensor 101, 102, such as while the image sensor is configured with the camera configuration. The input image data may be received, for example, from a bus coupled to the camera 103, 105 or from an analog front end (AFE) coupled to the camera 103, 105. The input image data may alternatively be received from a wireless camera, in which the image data is received through one or more of the WAN adaptors 152, the LAN adaptor 153, and/or the PAN adaptor 154. The input image data may alternatively be received from a memory location or a network storage location, such as when the image data was previously captured and is now retrieved from memory 106 and/or a remote location through one or more of the WAN adaptor 152, the LAN adaptor 153, and/or the PAN adaptor 154. In some examples, the first ISP node may further include a converter 406. For example, the first ISP node may receive the input image data that includes line frame image data and determine processed line frame image date. The line frame image data may include a row of an image frame.

In further examples, the first ISP node may be the BPS 138 that converts first raw image data in a first data format to second raw image data (e.g., the first image data) in a second data format being different from the first data format. For example, the first raw image data in the first data format may include raw image data while the second image data in the second data format may include YUV image data. When the first ISP node is the BPS 138, the first image data may be the second raw image data (e.g., YUV image data) . In addition, the first node may determine multiple image data sets as the first image data. For example, the BPS 138 as the first node may receive raw stripe image data and determines two processed image data sets (e.g., YUV 2 stripe image data and YUV 3 stripe image data) as the first image data. In other examples, the first ISP node may be any other suitable ISP engine.

In other examples, when the ISP 112 receives an image frame (e.g., input image data) , the processor may determine a categorized set of one or more source circuits and one or more sink circuits for an ISP node to perform an image processing function based on the data received. For example, Figure 5 shows a block diagram including category-based ISP nodes that can be configured with routing modules to function as an image signal processor (e.g., the ISP 112 in Figures 1 and 2) . In some examples, the processor may include ISP circuits of different categories, e.g., different IQ types or circuit types 502. Each circuit or IQ type 502 may include one or more ISP circuits (e.g., one or more source circuits, one or more sink circuits, and/or one or more source or sink circuits) . One circuit type 502 may include one or more source circuits while another circuit type may include one or more sink circuits or any other combination of source and sink circuits. In some examples, each circuit in the same circuit type 502 may perform an image processing function (e.g., tone-mapping, denoising, HDR processing, or any other suitable processing function) . In such examples, different ISP processing stages may perform the same processing function. Then, the same type IQ or circuit can be used in the different ISP processing stages to perform the same function. For example, different ISP nodes 504, 512 may use the same IQ type circuit (e.g., to perform tone-mapping, denoising, HDR processing, or any other image processing function) . In such examples, multiple IQ modules instances or circuits inside one IQ type may be used to balance loading and achieve a faster and more efficient processing system.

In some aspects, the circuit types may enable the processor to efficiently select and configure ISP circuits for an ISP node. For example, to perform a tone mapping function (i.e., the image processing function) , the processor may configure the first ISP node 504 or the categorized set of ISP circuits that are related to the tone mapping function. The ISP circuits in the categorized set may be selected from one or more circuit types 502. In further scenarios, the processor may configure the first ISP node 504 or a categorized set of ISP circuits to operate as the IFE 135 in Figure 4. For example, the processor may configure a categorized set or the first ISP node 504 to include a source circuit 506 to receive line frame image data from the sensor 101, 102 and convert the line frame image data to stripe frame image data and one or more sink circuits 508, 510 to determine processed image data (e.g., the first image data at block 304 or the second image data at block 306) .

In some examples, the processor may reuse one or more ISP circuits of one ISP node for another ISP node. When the processor configures first and second ISP nodes in the image signal processor based on the input image data, the processor may configure the second ISP node to include a source circuit and/or a sink circuit in the first ISP node if the first and second ISP nodes may use the same function of the circuit. For example, the first ISP node 504 may include a type 5 sink circuit 508 to determine output image data of the first ISP node 504 that may be routed to another ISP node 512. Another ISP node 512 may be configured to include the type 5 sink circuit 508 to determine another output image data. Thus, the category-based ISP nodes may be flexibly configured based on each image frame or input image data, which can reduce the circuitry used for frame processing.

Referring back to Figure 3, at block 304, the processor routes, by a routing module of the image signal processor, the first image data to a second ISP node. In some examples, to route the first image data, the processor may transmit the first image data to the second ISP node without storing the first image data in a memory. The routing module may route data without using a shared memory system (e.g., memory addressable by the ISP nodes or memory shared by the ISP with other components) . In some examples, the processor or the routing module may determine routing of the first image data based on a resource usage of the image signal processor. For example, if an ISP node is under high demand, such as a utilization level above a threshold level, the routing module may route the image data to a memory for storage until the ISP node meets certain criteria to begin processing the first image.

Figure 6 shows a block diagram illustrating a routing process for direct-through image data processing according to some embodiments of the disclosure. The routing module 212 may perform a routing process to transmit the first image data to the second ISP node. The routing module 212 may include a congestion controller 602, a stripe parser 604, and/or a router 606.

The congestion controller 602 may receive the first image data from the first ISP node and determine whether the first image data is to be transmitted to the memory or to be routed to the second ISP node based on a resource usage of the image signal processor. For example, the congestion controller 602 may determine that resource usage of the second ISP node meets a criterion (e.g., whether the second ISP node has capability to process the first image data) and route the first image data to the second ISP node in response to the resource usage meeting the criterion or criteria. The resource usage of the image signal processor may indicate an availability of image signal processor capability (e.g., data processing throughput) . For example, the congestion controller 602 may determine whether the first image data is to be transmitted to the memory or the second ISP node based on whether the resource utilization of the image signal processor is less than a resource usage threshold or not. In some examples, when the second ISP node has enough resources to process the first image data, the congestion controller 602 may route the first image data to the second ISP node. In other examples, the congestion controller 602 may store the first image data (e.g., in the buffer) in the memory and later retrieve the first image data for processing at the second ISP node when the criterion regarding the second ISP node is met (e.g., resource usage below a second threshold) . The memory 106 may be the memory 106 in Figure 1 or any other suitable memory (e.g., a RAM, a DDR SDRAM, DDR2, DDR3, DDR4, or DDR5) that the congestion controller 602 can access. In some examples, the memory 106 may be a shared memory shared with ISP nodes. In other examples, the memory 106 may be accessed by the congestion controller 602 and may not be necessarily a shared memory shared with ISP nodes because the congestion controller 602 is the entity to store and retrieve data (e.g., the first image data) .

The stripe parser 604 may receive the first image data that is determined by the congestion controller 602 to be routed. For example, the stripe parser 604 may decode the first image data that was encoded by a data encoder 608 to obtain communication information (e.g., process identification, destination ISP node, destination circuits, source ISP node, and source circuits) . In such examples, the first image data may include image buffer data and/or the communication information. In other examples, the communication information may be directly obtained by retrieving the information from the memory or receiving the information from the first ISP node. In such examples, the first image data may include image buffer data, and the stripe parser 604 may be optional.

The router 606 may receive the first image data and/or the communication information from the stripe parser 604. Based on the communication information, the router 606 may route the first image data (e.g., from the buffer) to destination circuits or the second ISP node. In some examples, the router 606 may include a demultiplexer that receives the first image data and select one or more source circuits to transmit the first image data. For example, the router 606 may receive the first image data and transmit the same first image data to one or more source circuits in the second ISP. In other examples, the router 606 may receive the first image data and transmit the same first image data to one or more source circuits in the second ISP and one or more source circuits in another ISP. In further examples, the first image data includes a first image data subset and a second image data subset. In such examples, the router 606 may receive the first image data and transmit the first image data subset and the second image data subset to different source circuits in the second ISP. In even further examples, the router 606 may receive the first image data and transmit the first image data subset to the second ISP and the second image data subset to another ISP. In some examples, when the router 606 transmits the first image data to multiple source circuits in the second ISP and/or another ISP, the processor may synchronize the signals to be transmitted to the source circuits.

In some examples, the second ISP node may directly access the hardware buffer including the first image data. The routing may pass the image buffers or the first image data the second ISP without using the software message control or memory shared across ISP nodes. This reduces CPU loading and stabilizes the image signal processor per-frame processing time cost. Also, when the image signal processor has enough resources, the image signal processor does not need to read and write the first image data into the memory or shared memory.

In some examples, the routing module 212 may further include the data encoder 608 that is electrically coupled or connected to the congestion controller 602. In other examples, the data encoder 608 may be a separate component from the routing module 212 and the first ISP node or may be included in the first ISP node. In some examples, the data encoder 608 may receive the first image data from the first ISP node and encode the first image data with the communication information. The encoded first image data may be transmitted to the congestion controller 602. When the first image data includes multiple first image data subsets, the processor may synchronize the first image data subsets.

In further examples, the routing module 212 may additionally or optionally include a converter 406. In such examples, some post-process ISP nodes may use stripe frame image data or stripe frame buffer for processing due to space information of pixels to handle the processing like bilinear-interpolation and local tone mapping. Thus, the converter 406 may convert the processed line frame image data (e.g., the first image data) to stripe frame image data. The stripe frame image data may include a grid that includes multiple rows of the image frame and/or one or more columns of the image frame. The one or more columns may be the same as or shorter than the width of the image frame. In such examples, to route the first image data to the second ISP node, the routing module 212 may route the stripe frame image data to the second ISP node. In other examples, the input image data may be stripe frame image data. In such examples, the first ISP node may not perform a conversion function using the converter 406 to the stripe frame image data.

Referring again to Figure 4, the ISP 112 may include a routing module between two consecutive ISP modules in the ISP processing flow. For example, the ISP 112 may include two routing modules 212A, 212B to facilitate the routing process. For example, a first routing module 212A may be electrically coupled between the IFE 135 (i.e., the first ISP node) and the BPS 138 (i.e., the second ISP node) and/or between the IFE 135 (i.e., the first ISP node) and the first IPE 136A (i.e., the second ISP node) . The first routing module 212A may receive the first image data (e.g., stripe frame image data, converted stripe frame image data, or encoded stripe frame image data) from the IFE 135 and route the first image data to the BPS 138 and/or the first IPE 136A. In such examples, the first image data may include stripe frame raw image data and stripe frame YUV image data. Then, the first routing module 212A may route the stripe frame raw image data to the BPS 138 and the stripe frame YUV image data to the first IPE 136A. However, when the IPE has insufficient resources to process the first image data in the BPS 138 and/or the first IPE 136A, the first routing module 212A may store the first image data in the memory 106 and route the first image data based on the resource usage of the image signal processor.

The second routing module 212B may be electrically coupled between the BPS 138 (i.e., the first ISP node) and the second IPE 136B (i.e., the second ISP node) . The first routing module 212A may receive the first image data (e.g., stripe frame YUV image data) from the BPS 138 and route the first image data to the second IPE 136B. In such examples, the first image data may include first stripe frame YUV image data from a first sink circuit of the BPS 138 and second stripe frame YUV image data from a second sink circuit of the BPS 138. Then, the second routing module 212B may route the first stripe frame YUV image data to a first source circuit of the second IPE 136B and the second stripe frame YUV image data to a second source circuit of the second IPE 136B.

Referring again to Figure 5, the processor may configure a routing module 212C between the first ISP node and the second ISP node. Because the processor configures each ISP node based on input image data from the sensor 101, 102, the processor may also configure each routing module 212C between two consecutive ISP nodes in the ISP processing flow. The processor may configure the routing module 212C per image frame or per use case. In some examples, all ISP circuits (e.g., all sink circuits) that use buffer transitions may be electrically coupled to the routing module 212C (e.g., via bus hardware linkages) . Then, when the processor configures the routing module 212C, the processor may enable or activate the electrical connection of the routing module to the configured first ISP node and the second ISP node. For example, the first ISP node 504 may determine the first image data that may include two stripe frame image data sets. The routing module 212C may receive the first image data and route the first image data to the second ISP node 512 and a third ISP node 514. For example, the routing module 212C may route the first stripe image data set to a first source circuit of the second ISP node 512 and to a source or sink circuit of the third ISP node 514. The routing module 212C may also route the second stripe image data set to a second source circuit of the second ISP node 512. In further examples, the routing module 212C may determine the routing based on a resource usage of the image signal processor. Thus, when the image signal processor has enough resources, the routing module 212C may route the first image data to the second and/or third ISP node 512, 514. On the other hand, when the image signal processor has not enough resources, the routing module 212C may store the first image data to the memory and route the first image data to the second and/or third ISP node 512, 514.

At block 306, the processor determines, in a second ISP node of the image signal processor, second image data based on the first image data. Similar to block 302, the second ISP node may include one or more source circuits and one or more sink circuit to perform an image processing function. Referring again to Figure 4, the second ISP node may be the BPS 138, the first IPE 136A, the second IPE 136B, or any other suitable ISP engine or a hardware component including a predefined set of ISP circuits. For example, the second ISP node may be the BPS 138. In such examples, the first image data may include first raw image data in a first data format (e.g., raw data format) while the second image data may include second raw image data in a second data format (e.g., YUV data format) different from the first data format. The BPS 138 may convert the first raw image data to the second raw image data. Referring again to Figure 5, the second ISP node 512, 514 may be a configured ISP node based on the input image data similar to the first ISP node at block 302.

In one or more aspects, techniques for supporting image processing may include additional aspects, such as any single aspect or any combination of aspects described below or in connection with one or more other processes or devices described elsewhere herein. In a first aspect, supporting image processing may include an apparatus for image processing. The apparatus includes a memory and an image signal processor. The image signal processor includes a first image signal processing (ISP) node configured to determine first image data, a routing module configured to route the first image data to a second ISP node, and the second ISP node configured to determine second image data based on the first image data.

Additionally, the apparatus may perform or operate according to one or more aspects as described below. In some implementations, the apparatus includes a wireless device, such as a UE. In some implementations, the apparatus includes a remote server, such as a cloud-based computing solution, which receives image data for processing to determine output image frames. In some implementations, the apparatus may include at least one processor, and a memory coupled to the processor. The processor may be configured to perform operations described herein with respect to the apparatus. In some other implementations, the apparatus may include a non-transitory computer-readable medium having program code recorded thereon and the program code may be executable by a computer for causing the computer to perform operations described herein with reference to the apparatus. In some implementations, the apparatus may include one or more means configured to perform operations described herein. In some implementations, a method of wireless communication may include one or more operations described herein with reference to the apparatus.

In a second aspect, in combination with the first aspect, the routing module is configured to transmit the first image data to the second ISP node without storing the first image data in the memory.

In a third aspect, in combination with one or more of the first aspect or the second aspect, the routing module is configured to determine that resource usage of the second ISP node meets a criterion., and route the first image data to the second ISP node in response to the resource usage meeting the criterion

In a fourth aspect, in combination with one or more of the first aspect through the third aspect, the routing module is configured to: in response to the resource usage not meeting the criterion: store the first image data in the memory; retrieve the first image data from the memory; and route the first image data to the second ISP node.

In a fifth aspect, in combination with one or more of the first aspect through the fourth aspect, the first image data comprises first raw image data in a first data format, the second image data comprises second raw image data in a second data format different from the first data format, and the second ISP node is configured to convert the first raw image data to the second raw image data.

In a sixth aspect, in combination with one or more of the first aspect through the fifth aspect, the first image data comprises line frame image data, the routing module is further configured to encode the line frame image data to determine stripe frame image data, and the routing module is configured to transmit the stripe frame image data to the second ISP node.

In a seventh aspect, in combination with one or more of the first aspect through the sixth aspect, the apparatus further comprises a processor, the processor is configured to configure the first ISP node and the second ISP node, the first ISP node comprises a first source circuit and a first sink circuit, and the second ISP node comprises at least one of the first source circuit or the first sink circuit of the first ISP node.

In an eighth aspect, in combination with one or more of the first aspect through the seventh aspect, the processor is further configured to configure a routing module between the first ISP node and the second ISP node.

In a ninth aspect, in combination with one or more of the first aspect through the eighth aspect, a method comprises: determining, in a first image signal processing (ISP) node of an image signal processor, first image data; routing, by a routing module of the image signal processor, the first image data to a second ISP node; and determining, in the second ISP node of the image signal processor, second image data based on the first image data.

In a tenth aspect, in combination with one or more of the first aspect through the ninth aspect, an image capture device comprises: a first image sensor, and an image signal processor coupled to the first image sensor. The image signal processor comprises: a first image signal processing (ISP) node configuredto determine first image data; a routing module configured to route the first image data to a second ISP node; and the second ISP node configured to determine second image data based on the first image data.

In the figures, a single block may be described as performing a function or functions. The function or functions performed by that block may be performed in a single component or across multiple components, and/or may be performed using hardware, software, or a combination of hardware and software. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps are described below generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure. Also, the example devices may include components other than those shown, including well-known components such as a processor, memory, and the like.

Aspects of the present disclosure are applicable to any electronic device including, coupled to, or otherwise processing data from one, two, or more image sensors capable of capturing image frames (or “frames” ) . The terms “output image frame, ” “modified image frame, ” and “corrected image frame” may refer to an image frame that has been processed by any of the disclosed techniques to adjust raw image data received from an image sensor. Further, aspects of the disclosed techniques may be implemented for processing image data received from image sensors of the same or different capabilities and characteristics (such as resolution, shutter speed, or sensor type) . Further, aspects of the disclosed techniques may be implemented in devices for processing image data, whether or not the device includes or is coupled to image sensors. For example, the disclosed techniques may include operations performed by processing devices in a cloud computing system that retrieve image data for processing that was previously recorded by a separate device having image sensors.

Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present application, discussions using terms such as “accessing, ” “receiving, ” “sending, ” “using, ” “selecting, ” “determining, ” “normalizing, ” “multiplying, ” “averaging, ” “monitoring, ” “comparing, ” “applying, ” “updating, ” “measuring, ” “deriving, ” “settling, ” “generating, ” or the like, refer to the actions and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system’s registers and memories into other data similarly represented as physical quantities within the computer system’s registers, memories, or other such information storage, transmission, or display devices. The use of different terms referring to actions or processes of a computer system does not necessarily indicate different operations. For example, “determining” data may refer to “generating” data. As another example, “determining” data may refer to “retrieving” data.

The terms “device” and “apparatus” are not limited to one or a specific number of physical objects (such as one smartphone, one camera controller, one processing system, and so on) . As used herein, a device may be any electronic device with one or more parts that may implement at least some portions of the disclosure. While the description and examples herein use the term “device” to describe various aspects of the disclosure, the term “device” is not limited to a specific configuration, type, or number of objects. As used herein, an apparatus may include a device or a portion of the device for performing the described operations.

Certain components in a device or apparatus described as “means for accessing, ” “means for receiving, ” “means for sending, ” “means for using, ” “means for selecting, ” “means for determining, ” “means for normalizing, ” “means for multiplying, ” or other similarly-named terms referring to one or more operations on data, such as image data, may refer to processing circuitry (e.g., application specific integrated circuits (ASICs) , digital signal processors (DSP) , graphics processing unit (GPU) , central processing unit (CPU) , computer vision processor (CVP) , or neural signal processor (NSP) ) configured to perform the recited function through hardware, software, or a combination of hardware configured by software.

Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

Components, the functional blocks, and the modules described herein with respect to the Figures referenced above include processors, electronics devices, hardware devices, electronics components, logical circuits, memories, software codes, firmware codes, among other examples, or any combination thereof. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, application, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, and/or functions, among other examples, whether referred to as software, firmware, middleware, microcode, hardware description language or otherwise. In addition, features discussed herein may be implemented via specialized processor circuitry, via executable instructions, or combinations thereof.

Those of skill in the art that one or more blocks (or operations) described with reference to Figures 3-6 may be combined with one or more blocks (or operations) described with reference to another of the figures. For example, one or more blocks (or operations) of Figures 3-6 may be combined with one or more blocks (or operations) of Figures 1-2.

Those of skill in the art would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure. Skilled artisans will also readily recognize that the order or combination of components, methods, or interactions that are described herein are merely examples and that the components, methods, or interactions of the various aspects of the present disclosure may be combined or performed in ways other than those illustrated and described herein.

The various illustrative logics, logical blocks, modules, circuits and algorithm processes described in connection with the implementations disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. The interchangeability of hardware and software has been described generally, in terms of functionality, and illustrated in the various illustrative components, blocks, modules, circuits, and processes described above. Whether such functionality is implemented in hardware or software depends upon the particular application and design constraints imposed on the overall system.

The hardware and data processing apparatus used to implement the various illustrative logics, logical blocks, modules and circuits described in connection with the aspects disclosed herein may be implemented or performed with a general purpose single-or multi-chip processor, a digital signal processor (DSP) , an application specific integrated circuit (ASIC) , a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, or, any conventional processor, controller, microcontroller, or state machine. In some implementations, a processor may be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. In some implementations, particular processes and methods may be performed by circuitry that is specific to a given function.

In one or more aspects, the functions described may be implemented in hardware, digital electronic circuitry, computer software, firmware, including the structures disclosed in this specification and their structural equivalents thereof, or in any combination thereof. Implementations of the subject matter described in this specification also may be implemented as one or more computer programs, which is one or more modules of computer program instructions, encoded on a computer storage media for execution by, or to control the operation of, data processing apparatus.

If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. The processes of a method or algorithm disclosed herein may be implemented in a processor-executable software module which may reside on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that may be enabled to transfer a computer program from one place to another. A storage media may be any available media that may be accessed by a computer. By way of example, and not limitation, such computer-readable media may include random-access memory (RAM) , read-only memory (ROM) , electrically erasable programmable read-only memory (EEPROM) , CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to store desired program code in the form of instructions or data structures and that may be accessed by a computer. Also, any connection may be properly termed a computer-readable medium. Disk and disc, as used herein, includes compact disc (CD) , laser disc, optical disc, digital versatile disc (DVD) , floppy disk, and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. Additionally, the operations of a method or algorithm may reside as one or any combination or set of codes and instructions on a machine readable medium and computer-readable medium, which may be incorporated into a computer program product.

Various modifications to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to some other implementations without departing from the spirit or scope of this disclosure. Thus, the claims are not intended to be limited to the implementations shown herein but are to be accorded the widest scope consistent with this disclosure, the principles and the novel features disclosed herein.

Additionally, a person having ordinary skill in the art will readily appreciate, opposing terms such as “upper” and “lower, ” or “front” and back, ” or “top” and “bottom, ” or “forward” and “backward” are sometimes used for ease of describing the figures, and indicate relative positions corresponding to the orientation of the figure on a properly oriented page, and may not reflect the proper orientation of any device as implemented.

Certain features that are described in this specification in the context of separate implementations also may be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation also may be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination may in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown, or in sequential order, or that all illustrated operations be performed to achieve desirable results. Further, the drawings may schematically depict one or more example processes in the form of a flow diagram. However, other operations that are not depicted may be incorporated in the example processes that are schematically illustrated. For example, one or more additional operations may be performed before, after, simultaneously, or between any of the illustrated operations. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems may generally be integrated together in a single software product or packaged into multiple software products. Additionally, some other implementations are within the scope of the following claims. In some cases, the actions recited in the claims may be performed in a different order and still achieve desirable results.

As used herein, including in the claims, the term “or, ” when used in a list of two or more items, means that any one of the listed items may be employed by itself, or any combination of two or more of the listed items may be employed. For example, if a composition is described as containing components A, B, or C, the composition may contain A alone; B alone; C alone; A and B in combination; A and C in combination; B and C in combination; or A, B, and C in combination. Also, as used herein, including in the claims, “or” as used in a list of items prefaced by “at least one of” indicates a disjunctive list such that, for example, a list of “at least one of A, B, or C” means A or B or C or AB or AC or BC or ABC (that is A and B and C) or any of these in any combination thereof.

The term “substantially” is defined as largely, but not necessarily wholly, what is specified (and includes what is specified; for example, substantially 90 degrees includes 90 degrees and substantially parallel includes parallel) , as understood by a person of ordinary skill in the art. In any disclosed implementations, the term “substantially” may be substituted with “within [apercentage] of” what is specified, where the percentage includes . 1, 1, 5, or 10 percent.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

An apparatus comprising:

a memory; and

an image signal processor coupled to the memory, the image signal processor comprising:

a first image signal processing (ISP) node configured to determine first image data;

a routing module configured to route the first image data to a second ISP node; and

the second ISP node configured to determine second image data based on the first image data.
The apparatus of claim 1, wherein the routing module is configured to transmit the first image data to the second ISP node without storing the first image data in the memory.
The apparatus of claim 1, wherein the routing module is configured to:

determine that resource usage of the second ISP node meets a criterion; and

route the first image data to the second ISP node in response to the resource usage meeting the criterion.
The apparatus of claim 3, wherein the routing module is configured to:

in response to the resource usage not meeting the criterion:

store the first image data in the memory;

retrieve the first image data from the memory; and

route the first image data to the second ISP node.
The apparatus of claim 1, wherein:

the first image data comprises first raw image data in a first data format,

the second image data comprises second raw image data in a second data format different from the first data format, and

the second ISP node is configured to convert the first raw image data to the second raw image data.
The apparatus of claim 1, wherein:

the first image data comprises line frame image data,

the routing module is further configured to encode the line frame image data to determine stripe frame image data, and

the routing module is configured to transmit the stripe frame image data to the second ISP node.
The apparatus of claim 1, further comprising: a processor, wherein:

the processor is configured to configure the first ISP node and the second ISP node,

the first ISP node comprises a first source circuit and a first sink circuit, and

the second ISP node comprises at least one of the first source circuit or the first sink circuit of the first ISP node.
The apparatus of claim 7, wherein the processor is further configured to configure a routing module between the first ISP node and the second ISP node.
A method, comprising:

determining, in a first image signal processing (ISP) node of an image signal processor, first image data;

routing, by a routing module of the image signal processor, the first image data to a second ISP node; and

determining, in the second ISP node of the image signal processor, second image data based on the first image data.
The method of claim 9, wherein the routing comprises transmitting the first image data to the second ISP node without storing the first image data in a memory.
The method of claim 9, wherein the routing comprises:

determining that resource usage of the second ISP node meets a criterion; and

routing the first image data to the second ISP node in response to the resource usage meeting the criterion.
The method of claim 11, wherein the routing comprises:

in response to the resource usage not meeting the criterion:

storing the first image data in a memory;

retrieving the first image data from the memory; and

routing the first image data to the second ISP node.
The method of claim 9, wherein:

the first image data comprises first raw image data in a first data format,

the second image data comprises second raw image data in a second data format different from the first data format, and

the second ISP node is configured to convert the first raw image data to the second raw image data.
The method of claim 9, wherein:

the first image data comprises line frame image data, and

the method further comprises: encoding, by the routing module, the line frame image data to determine stripe frame image data, and

routing the first image data comprises: transmitting the stripe frame image data to the second ISP node.
The method of claim 9, further comprising:

configuring the first ISP node and the second ISP node,

wherein the first ISP node comprises a first source circuit and a first sink circuit, and

wherein the second ISP node comprises at least one of the first source circuit or the first sink circuit of the first ISP node.
An image capture device, comprising:

a first image sensor; and

an image signal processor coupled to the first image sensor, the image signal processor comprising:

a first image signal processing (ISP) node configured to determine first image data;

a routing module configured to route the first image data to a second ISP node; and

the second ISP node configured to determine second image data based on the first image data.
The image capture device of claim 16, wherein the routing module is configured to transmit the first image data to the second ISP node without storing the first image data in a memory.
The image capture device of claim 16, wherein the routing module is configured to:

determine that resource usage of the second ISP node meets a criterion; and

route the first image data to the second ISP node in response to the resource usage meeting the criterion.
The image capture device of claim 18, wherein the routing module is configured to:

in response to the resource usage not meeting the criterion:

store the first image data in a memory;

retrieve the first image data from the memory; and

route the first image data to the second ISP node.
The image capture device of claim 16, wherein:

the first image data comprises line frame image data,

the routing module is further configured to encode the line frame image data to determine stripe frame image data, and

the routing module is configured to transmit the stripe frame image data to the second ISP node.