WO2025228388A1 - Gate drive circuit, display panel, display screen, and display device - Google Patents

Abstract

A gate drive circuit (10), comprising: a first switch transistor (QP1), having a first end configured to be connected to a high-level voltage source (VGH), and a control end used for receiving a first clock signal (CKB), wherein the first switch transistor (QP1) is a first-type switch transistor, and the first-type switch transistor is configured to be turned on when the signal received by the control end is in a low level state; a second switch transistor (QN1), having a first end configured to be connected to a low-level voltage source (VGL), and a control end configured to receive a second clock signal (CK), wherein the level state of the second clock signal (CK) is opposite to that of the first clock signal (CKB), the second switch transistor (QN1) is a second-type switch transistor, and the second-type switch transistor is configured to be turned on when the signal received by the control end is in a high level state; and a first inverter (111) separately connected to a second end of the first switch transistor (QP1) and a second end of the second switch transistor (QN1), wherein the first inverter (111) is configured to, when the first switch transistor (QP1) and the second switch transistor (QN1) are turned on, flip the level state of a trigger signal (P-in) inputted into the first inverter (111), so as to generate a gate drive signal, wherein the trigger signal (P-in) comes from a display drive chip (50) or another gate drive circuit (10).

Description

Gate driving circuit, display panel, display screen and display device

Cross-references to related applications

This application claims priority to Chinese Patent Application No. 202410536492X, filed on April 29, 2024, entitled "Gate Driving Circuit, Display Panel, Display Screen and Display Device", the entire contents of which are incorporated herein by reference.

Technical Field

This application relates to the field of display, and in particular to a gate driving circuit, a display panel, a display screen, and a display device.

Background Technology

The statements herein are provided only as background information in connection with this application and do not necessarily constitute exemplary technology.

In the display industry, gate drive circuits are key circuit structures in display panels, used to drive the transistors in pixel circuits to turn on and off. Currently, gate drive circuits mostly adopt a cascaded architecture, with the gate drive signal output from one gate drive circuit triggering the next, causing the next gate drive circuit to output its own gate drive signal, thereby achieving line-by-line control of the pixel circuits. Therefore, if the quality of any gate drive signal is poor, it will affect the gate drive signal output by the next gate drive circuit it triggers, and this effect will accumulate line by line, ultimately leading to display abnormalities in the display panel.

Summary of the Invention

According to various embodiments of this application, a gate driving circuit, a display panel, a display screen, and a display device are provided.

In a first aspect, this application provides a gate driving circuit, comprising:

The first switch has a first terminal for connecting to a high-level voltage source and a control terminal for receiving a first clock signal. The first switch is a first type of switch and is used to turn on when the signal received at the control terminal is low.

The second switch has a first terminal for connecting to a low-level voltage source and a control terminal for receiving a second clock signal. The level of the second clock signal is opposite to that of the first clock signal. The second switch is a second type of switch, which is turned on when the signal received at the control terminal is high.

The first inverter is connected to the second terminal of the first switch and the second terminal of the second switch respectively. The first inverter is used to flip the level state of the trigger signal input to the first inverter when the first switch and the second switch are turned on, so as to generate a gate drive signal.

The trigger signal comes from the display driver chip or from another gate driver circuit.

Secondly, this application provides a display panel, including:

Multiple pixel circuits are arranged in multiple rows, and each pixel circuit includes multiple transistors.

Multiple gate driving circuits as described above, each gate driving circuit's output terminal is respectively connected to at least a portion of the transistors in the multiple pixel circuits located in each row, so as to control the connected transistors to be turned on and off by the gate driving signal.

Thirdly, this application provides a display screen, including:

As shown in the display panel above;

A cover plate is disposed on the light-emitting side of the display panel and covers the display panel.

Fourthly, this application provides a display device, comprising:

As shown in the display panel above.

Details of one or more embodiments of this application are set forth in the following drawings and description. Other features, objects, and advantages of this application will become apparent from the specification, drawings, and claims.

Attached Figure Description

To more clearly illustrate the technical solutions in the embodiments or exemplary technologies of this application, the accompanying drawings used in the description of the embodiments or exemplary technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

Figure 1 is a circuit diagram of a pixel circuit according to an embodiment;

Figure 2 is a circuit diagram of one embodiment of the gate drive circuit;

Figure 3 is one of the signal timing diagrams of a gate drive circuit according to an embodiment;

Figure 4 is a second circuit diagram of a gate drive circuit according to an embodiment;

Figure 5 is a circuit diagram of the third embodiment of the gate drive circuit;

Figure 6 is a second signal timing diagram of a gate drive circuit according to an embodiment;

Figure 7 is a fourth circuit diagram of a gate drive circuit according to an embodiment;

Figure 8 is a fifth circuit diagram of a gate drive circuit according to an embodiment;

Figure 9 is a circuit diagram of the sixth embodiment of the gate drive circuit;

Figure 10 is a schematic diagram of the structure of a display panel according to one embodiment;

Figure 11 is a second schematic diagram of the structure of a display panel according to an embodiment;

Figure 12 is a third schematic diagram of the structure of a display panel according to an embodiment;

Figure 13 is a schematic diagram of the structure of a display screen according to one embodiment;

Figure 14 is a second schematic diagram of the structure of a display screen according to an embodiment;

Figure 15 is a third schematic diagram of the structure of a display screen according to an embodiment;

Figure 16 is an internal structural diagram of a display device according to an embodiment.

Component designation explanation:
Gate drive circuit: 10; First inverter: 111; Holding module: 200; Locking unit: 210;
Second inverter: 211; Third inverter: 212; Reset module: 300; Output module: 400; Fourth inverter: 401; Pixel circuit: 20; Interstage switch: 30; Cover plate: 40; Display driver chip: 50.

Detailed Implementation

To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

It is understood that the terms "first," "second," etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first clock signal may be referred to as a second clock signal, and similarly, a second clock signal may be referred to as a first clock signal.

Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. "Multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. "Several" means at least one, such as one, two, etc., unless otherwise explicitly specified.

In the display field, the display area (Active Area, AA) of a display panel includes multiple light-emitting elements and multiple pixel circuits. The pixel circuits include connected storage capacitors and multiple transistors. The non-display area of the display panel has multiple gate driving circuits, each connected to a transistor in one of the pixel circuits located in the same row. The gate driving circuits control the pixel circuits to perform reset, write, and light-emitting processes via gate driving signals, thereby driving the light-emitting elements to emit light, thus displaying an image on the display panel. The light-emitting elements can be, but are not limited to, organic light-emitting diodes (OLEDs) and micro light-emitting diodes (Micro-LEDs). The transistors in the pixel circuits can be fabricated using low-temperature polycrystalline silicon (LTPS) or low-temperature polycrystalline oxide (LTPO) technology. LTPO type transistors can be IGZO type transistors. IGZO type transistors have low leakage current, which can effectively reduce the power consumption of display panels and are increasingly used in display devices.

Furthermore, to reduce the size of the gate driving circuit in display devices, current display devices mostly adopt the GOA (Gate On Array) approach to integrate the gate driving circuit on the array substrate. LTPS type pixel circuits typically only require two GOAs: P_gate GOA and EM GOA. The P_gate GOA controls the reset and writing of the pixel circuit, while the EM GOA controls the illumination of the light-emitting devices driven by the pixel circuit. However, because the switching mode of IGZO type transistors differs from that of LTPS, pixel circuits including IGZO type transistors require three or even five GOAs to achieve control over all transistors in the pixel circuit. These three GOAs are P_GOA, N_GOA, and EM GOA. Figure 1 is a circuit diagram of a pixel circuit according to an embodiment. Referring to Figure 1, N_GOA is used to control IGZO TFTs (T1 and T2), P_GOA is used to control P_TFTs (T4, T7 and T8) to realize the reset and writing of the pixel circuit, and EM_GOA is used to control P_TFTs (T5 and T6) to drive the light-emitting device to emit light. It should be noted that the 7T1C pixel circuit shown in Figure 1 is only for illustrative purposes. The gate driving circuit of this embodiment can also be applied to other pixel circuits, such as 8T1C, etc.

Multiple gate drive circuits are cascaded, and during screen refresh, the gate drive signal is passed from top to bottom to refresh the pixel circuit line by line. However, the driving capability of existing gate drive circuits is insufficient, resulting in excessively long rise time (TR) and/or fall time (TF) of the cascaded gate drive signal. That is, the switching speed of the gate drive signal's level is slow, causing slow switching speed of transistors in the pixel circuit, leading to problems such as insufficient charging of the storage capacitor. Moreover, since subsequent gate drive circuits completely depend on the gate drive signal output from previous gate drive circuits, errors in the gate drive signal accumulate line by line, ultimately causing display abnormalities on the display panel. Therefore, this application provides a gate drive circuit that can effectively improve the quality of the gate drive signal. It should be noted that since the display panel includes multiple sets of gate drive circuits, the gate drive circuit of this embodiment can replace all the gate drive circuits in an existing display panel, or it can only replace a portion of the gate drive circuits in the display panel; this application is not limited to this.

Figure 2 is a circuit diagram of one embodiment of the gate drive circuit 10. Referring to Figure 2, in one embodiment, the gate drive circuit 10 includes a first switch, a second switch, and a first inverter 111. The first switch is a first type of switch, which is turned on when the signal received at the control terminal is a low-level signal. The second switch is a second type of switch, which is turned on when the signal received at the control terminal is a high-level signal. That is, the first switch can be a first PMOS transistor QP1, and the second switch can be a first NMOS transistor QN1. It should be noted that, for ease of explanation, in subsequent embodiments, the first type of switch is a PMOS transistor and the second type of switch is an NMOS transistor, but the switches in each embodiment can also be other types of voltage-controlled transistors, which is not limited in this application.

The first terminal of the first switch QP1 is connected to a high-level voltage source VHG, and the control terminal of the first switch QP1 is used to receive the first clock signal CKB. Therefore, the first switch QP1 is turned on when the first clock signal CKB is low and turned off when the first clock signal CKB is high. The first terminal of the second switch QN1 is connected to a low-level voltage source VGL, and the control terminal of the second switch QN1 is used to receive the second clock signal CK. Therefore, the first switch QP1 is turned on when the second clock signal CK is high and turned off when the second clock signal CK is low. The level of the second clock signal CK is opposite to that of the first clock signal CKB, causing the first switch QP1 and the second switch QN1 to turn on synchronously. Therefore, at the falling edge of the first clock signal CKB, the high-level voltage VHG is transmitted to the first inverter 111, and simultaneously, at the rising edge of the second clock signal CK, the low-level voltage VGL is also transmitted to the first inverter 111. Understandably, the clock signals are directly powered by the chip, resulting in a very fast transition speed when the clock signals switch levels. Consequently, the rise and fall times are both short, making the edges of the first clock signal CKB and the second clock signal CK steeper, and the signal quality higher than the signal output by the preceding gate drive circuit 10.

The first inverter 111 is connected to the second terminal of the first switch QP1 and the second terminal of the second switch QN1, respectively. When the first switch QP1 and the second switch QN1 are turned on, the first inverter 111 flips the level of the trigger signal P-in input to the first inverter 111 to generate a gate drive signal. Optionally, the gate drive circuit 10 can directly output the signal flipped by the first inverter 111 as the gate drive signal. Alternatively, the gate drive circuit 10 can be connected to other circuit modules after the first inverter 111 and process the signal flipped by the first inverter 111 to generate the gate drive signal. That is, this embodiment only limits the signal output by the first inverter 111 to be associated with the gate drive signal, but does not limit the signal output by the first inverter 111 to be the gate drive signal.

The trigger signal P-in originates from either the display driver chip or another gate driver circuit 10. Specifically, the trigger signal P-in received by the first-level gate driver circuit 10 originates from the previous-level gate driver circuit 10; that is, the trigger signal P-in received by the nth-level gate driver circuit 10 originates from the (n-1)th-level gate driver circuit 10. The nth-level gate driver circuit 10 refers to the gate driver circuit 10 connected to the nth row of pixel circuits. For example, if the gate driver circuit 10 is connected to the first row of pixel circuits on the display panel, then there is necessarily no previous-level gate driver circuit 10, and the trigger signal P-in it receives originates from the display driver chip. For another example, if the gate driver circuit 10 is any level other than the first level, it can receive signals from the previous-level gate driver circuit 10 or signals output by the display driver chip. Therefore, the gate driver circuit 10 can select one of these as the trigger signal P-in according to the scenario to generate the gate driving signal. It should be noted that the signal received by the gate driving circuit 10 from the previous stage gate driving circuit 10 can be the gate driving signal output by the previous stage, or it can be the signal generated by the previous stage gate driving circuit 10 after flipping the received trigger signal P-in, or it can be other process signals between the signal generated after flipping and the final output gate driving signal. This embodiment does not limit it. As long as the trigger signal P-in can enable the gate driving circuits 10 of different stages to output gate driving signals in sequence, they are all within the protection scope of this embodiment.

Furthermore, the level of the trigger signal P-in received by the first inverter 111 is switched when the first clock signal CKB is at a high level. That is, the level of the trigger signal P-in is switched when both the first switch QP1 and the second switch QN1 are off, so that the output of the first inverter 111 can remain unchanged when the first switch QP1 and the second switch QN1 are on, thereby avoiding abnormal gate drive signal output by the gate drive circuit 10 due to timing conflicts.

In this embodiment, because the first terminal of the first switch QP1 is connected to a high-level voltage source VHG, the first switch QP1 will be turned on when the first clock signal CKB is low. Similarly, the second switch QN1 will be turned on when the second clock signal CK is low. Since the levels of the first clock signal CKB and the second clock signal CK are opposite, the first switch QP1 and the second switch QN1 will be turned on synchronously. Therefore, at the falling edge of the first clock signal CKB, the high-level voltage VHG will be transmitted to the first inverter 111, and at the same time, at the rising edge of the second clock signal CK, the low-level voltage VGL will also be transmitted to the first inverter 111, enabling the first inverter 111 to flip the trigger signal P-in under the combined action of the high-level voltage VHG and the low-level voltage VGL, thereby generating the gate drive signal. Thus, in this application, the switching timing of the gate drive signal level is only subject to the clock signal and is independent of the trigger signal P-in, while the trigger signal P-in is only used to determine the level of the gate drive signal. Therefore, even if the trigger signal P-in has problems with excessively long rise or fall times, it will not affect the timing and speed of the switching of the gate drive signal level, thereby improving the quality of the output gate drive signal and thus improving the display effect and reliability of the display panel.

Referring again to Figure 2, in one embodiment, the first inverter 111 includes a ninth switch and a tenth switch. The ninth switch is a fifth PMOS transistor QP5 of a first type, and the tenth switch is a fifth NMOS transistor QN5 of a second type. The first terminal of the ninth switch QP5 is connected to the second terminal of the first switch QP1, and the second terminal of the ninth switch QP5 serves as the output terminal of the first inverter 111. The control terminal of the ninth switch QP5 is used to receive the trigger signal P-in. The first terminal of the tenth switch QN5 is connected to the second terminal of the second switch QN1, and the second terminal of the tenth switch QN5 is connected to the second terminal of the ninth switch QP5. The control terminal of the tenth switch QN5 is used to receive the trigger signal P-in. Therefore, when the first switch QP1 is turned on, the first terminal of the ninth switch QP5 receives a high-level voltage VHG. Simultaneously, the second switch QN1 is turned on, causing the first terminal of the tenth switch QN5 to receive a low-level voltage VGL, thus forming the structure of the first inverter 111. Figure 3 is one of the signal timing diagrams of a gate driving circuit 10 according to an embodiment. Referring to Figures 2 and 3, the explanation will focus on the trigger signal P-in as the start vertical (STV) signal output by the display driver chip. At time T1, when the trigger signal P-in is low, the signal at point P, the output of the first inverter 111, is high. At time T2, when the trigger signal P-in is high, the signal at point P, the output of the first inverter 111, is low. In this embodiment, the first inverter 111 is formed using the ninth switch QP5 and the tenth switch QN5, resulting in fewer circuit components and simpler connections, thus providing a small-sized gate driving circuit 10.

Figure 4 is a second circuit diagram of the gate driving circuit 10 according to one embodiment. Referring to Figure 4, in one embodiment, the gate driving circuit 10 further includes a holding module 200. The holding module 200 is connected to the output terminal of the first inverter 111 and is used to maintain the level state of the output terminal of the first inverter 111 when the first clock signal CKB is in a high-level state. It is understood that the pixel circuit of the display panel needs to be refreshed line by line. Accordingly, the first switch QP1 and the second switch QN1 in the gate driving circuit 10 corresponding to the non-refreshed line will not always be turned on. Therefore, the first inverter 111 will not receive the high-level voltage VHG and the low-level voltage VGL during some periods, which will cause the first inverter 111 to be unable to flip the input trigger signal P-in, so that the first inverter 111 has no signal output during those periods. Therefore, this embodiment introduces the holding module 200, which can maintain the level state of the output terminal of the first inverter 111, thereby improving the stability of the gate driving signal received by the downstream pixel circuit. Optionally, the holding module 200 can be, for example, an output capacitor, which can store charge when the first switch QP1 and the second switch QN1 are turned on, and release charge when the first switch QP1 and the second switch QN1 are turned off, so as to maintain the level state of the output terminal of the first inverter 111.

Furthermore, the holding module 200 is also used to generate an initial drive signal, which has the opposite level to the signal output by the first inverter 111, and the gate drive signal has the same waveform as the initial drive signal. That is, the gate drive signal and the initial drive signal have the same duty cycle, but the voltage amplitude and phase of the signal may not be exactly the same. It is understood that even when the first switch QP1 and the second switch QN1 are off, there may still be residual charge in the first inverter 111, which will cause slight fluctuations in the output signal of the first inverter 111. In this embodiment, by inverting the input signal based on the internal structure of the holding module 200, slight fluctuations in the input signal can be filtered out, thereby making the stability of the output initial drive signal higher than that of the signal output by the first inverter 111. Optionally, the initial drive signal can be directly used as the gate drive signal, or the gate drive signal can be generated by adjusting the amplitude and/or delay of the initial drive signal. However, regardless of which method is used, the reliability of the gate drive signal can be greatly improved while ensuring that the information carried by the signal remains unchanged.

Referring again to Figure 4, in one embodiment, the holding module 200 includes a third switch, a fourth switch, and a locking unit 210. The third switch is a first-type second PMOS transistor QP2, and the fourth switch is a second-type second NMOS transistor QN2.

The third switch QP2 has its second terminal connected to a high-level voltage source VHG, and its control terminal receives the second clock signal CK. Therefore, the third switch QP2 is turned on when the second clock signal CK is low and turned off when CK is high. The fourth switch QN2 has its second terminal connected to a low-level voltage source VGL, and its control terminal receives the first clock signal CKB. Therefore, the third switch QP2 is turned on when the first clock signal CKB is high and turned off when CKB is low. The locking unit 210 is connected to the output of the first inverter 111, the first terminal of the third switch QP2, and the first terminal of the fourth switch QN2. The locking unit 210 maintains the output level of the first inverter 111 unchanged and generates an initial drive signal when the third switch QP2 and the fourth switch QN2 are on. Specifically, the locking unit 210 can be understood as a 1-bit latch used to latch the input signal. It is understandable that while the output capacitor can maintain the stability of the output signal to a certain extent, the signal at the output terminal Q of the gate drive circuit 10 will drift as the output capacitor continues to discharge, which may lead to control errors in the pixel circuit. In this embodiment, the latching unit 210, which adopts a latch structure, is directly powered by the high-level voltage VHG and the low-level voltage VGL when the third switch QP2 and the fourth switch QN2 are turned on. This can provide a stable initial drive signal, thereby improving the stability and reliability of the gate drive signal output by the gate drive circuit 10.

Figure 5 is a third circuit diagram of a gate drive circuit 10 according to an embodiment. Referring to Figure 5, in one embodiment, the locking unit 210 includes a second inverter 211 and a third inverter 212.

The second inverter 211 is connected to the first terminal of the third switch QP2 and the first terminal of the fourth switch QN2, respectively. The second inverter 211 is used to flip the level state of the input signal when the third switch QP2 and the fourth switch QN2 are turned on. The input terminal of the third inverter 212 is connected to the output terminal of the first inverter 111 and the output terminal of the second inverter 211, respectively. The output terminal of the third inverter 212 is connected to the input terminal of the second inverter 211, and the third inverter 212 is used to flip the level state of the input signal. Specifically, Figure 6 is a signal timing diagram of the gate drive circuit 10 of one embodiment. Referring to Figures 5 and 6, taking point P as a high-level state as an example, the third inverter 212 will output a low-level signal to the input terminal of the second inverter 211 under the influence of the high-level state at point P. The second inverter 211 will then output a high-level signal to point P under the influence of the low-level state at its input terminal. Through this cyclical action, the initial drive signal level at point Q is stabilized at a low level. Similarly, when point P is at a low level, point Q can also be stabilized at a high level under the combined action of the second inverter 211 and the third inverter 212. That is, this embodiment provides a strong point interlocking locking unit 210 structure, where the outputs of the two inverters are each other's inputs, forming a bistable structure. This structure can maintain a constant level until a new state is written. Therefore, it can effectively resist interference factors such as temperature, making the initial drive signal output by the locking unit 210 more stable, thereby improving the stability of the gate drive signal output by the gate drive circuit 10. Moreover, the latch structure is relatively simple, not only occupying less space, but also able to quickly respond to changes in the input signal, achieving fast signal processing.

Referring again to Figure 5, in one embodiment, the second inverter 211 includes a fifth switch and a sixth switch. The fifth switch is a first-type third PMOS transistor QP3, and the sixth switch is a second-type third PMOS transistor QN3. The second terminal of the fifth switch QP3 is connected to the first terminal of the third switch QP2, and the first terminal of the fifth switch QP3 is connected to the output terminal of the first inverter 211. The control terminal of the fifth switch QP3 is connected to the output terminal of the third inverter 212. The second terminal of the sixth switch QN3 is connected to the first terminal of the fourth switch QN2, and the first terminal of the sixth switch QN3 is connected to the first terminal of the fifth switch QP3. The control terminal of the sixth switch QN3 is connected to the output terminal of the third inverter 212. Therefore, when the third switch QP2 is turned on, the second terminal of the fifth switch QP3 receives a high-level voltage VHG. Simultaneously, the fourth switch QN2 is turned on, causing the second terminal of the sixth switch QN3 to receive a low-level voltage VGL, thus forming the structure of the second inverter 211. In this embodiment, the fifth switch QP3 and the sixth switch QN3 are used to form the second inverter 211. The circuit components are few and the connection relationship is simple, thereby providing a small-volume gate drive circuit 10.

Referring again to Figure 5, in one embodiment, the third inverter 212 includes a seventh switch and an eighth switch. The seventh switch is a first-type fourth PMOS transistor QP4, and the eighth switch is a second-type fourth NMOS transistor QN4. The first terminal of the seventh switch QP4 is connected to a high-level voltage source VHG, the second terminal of the seventh switch QP4 is connected to the input terminal of the second inverter 211, and the control terminal of the seventh switch QP4 is connected to the output terminal of the second inverter 211. The first terminal of the eighth switch QN4 is connected to a low-level voltage source VGL, the second terminal of the eighth switch QN4 is connected to the second terminal of the seventh switch QP4, and the control terminal of the eighth switch QN4 is connected to the output terminal of the third inverter 212. In this embodiment, the third inverter 212 is formed using the seventh switch QP4 and the eighth switch QN4, resulting in fewer circuit components and simpler connections, thereby providing a small-sized gate drive circuit 10.

Figure 7 is a fourth circuit diagram of a gate driving circuit according to one embodiment. Referring to Figure 7, in one embodiment, the gate driving circuit 10 further includes a reset module 300. The reset module 300 is connected to the output terminal of the holding module 200 and is used to receive a reset control signal RST. In response to the rising or falling edge of the reset control signal RST, the reset module 200 switches the level state of its output terminal to a target level state. Specifically, the target level state is one of a low level state and a high level state, and the target level state is determined according to the transistor type in the pixel circuit connected to the gate driving circuit 10. In this embodiment, the reset module 300 can release the charge at point Q by switching the level state of the output terminal of the holding module 200, thereby reducing the distortion of the gate driving signal and improving the reliability of the gate driving signal. It is understood that resetting point Q during display may cause the display panel to flicker. Therefore, the display driver chip can provide the aforementioned edge that controls the reset module 300 to reset when the display panel is not displaying an image. For example, the reset module 300 can be reset when the display panel is powered on or off, thereby reducing the flickering problem of the display panel and improving the user's viewing experience.

Referring again to Figure 7, in one embodiment, the reset module 300 includes an eleventh switch. The eleventh switch is a sixth PMOS transistor QP6 of the first type. The first terminal of the eleventh switch QP6 is connected to a high-level voltage source VHG, the second terminal of the eleventh switch QP6 is connected to the output of the holding module 200, and the control terminal of the eleventh switch QP6 is used to receive a reset control signal RST. The eleventh switch QP6 is used to switch the level state of the output of the holding module 200 to a high level when it is turned on. That is, the eleventh switch QP6 turns on in response to the falling edge of the reset control signal RST to switch the level state of the output of the holding module 200 to a high level. Specifically, the gate drive circuit 10 can use the eleventh switch QP6 when driving P-type transistors (e.g., T4-T8 shown in Figure 1) in the pixel circuit. Figure 8 is a fifth circuit diagram of the gate drive circuit 10 of one embodiment. Referring to Figure 8, in one embodiment, the reset module 300 includes a twelfth switch. In this embodiment, the twelfth switch is a sixth NMOS transistor of the second type, QN6. The first terminal of the twelfth switch QN6 is connected to a low-level voltage source VGL, and the second terminal is connected to the output of the holding module 200. The control terminal of the twelfth switch QN6 receives the reset control signal RST. When turned on, the twelfth switch QN6 switches the output of the holding module 200 to a low level. That is, the twelfth switch QN6 turns on in response to the rising edge of the reset control signal RST to switch the output of the holding module 200 to a low level. Specifically, the gate drive circuit 10 can use the twelfth switch QN6 when driving N-type transistors (e.g., T1 and T2 shown in Figure 1) in the pixel circuit. In this embodiment, different reset modules 300 can be adaptively selected for different types of transistors in the pixel circuit, thereby achieving accurate release of charge at the target node (Q point) and improving the reliability of the output gate drive signal.

Figure 9 is a sixth circuit diagram of a gate driving circuit 10 according to one embodiment. Referring to Figure 9, in one embodiment, the gate driving circuit 10 further includes an output module 400. The output module 400 is connected to the output terminal of the locking unit 210 and is used to amplify the initial driving signal to generate a gate driving signal. Specifically, by amplifying the initial driving signal through the output module 400, a larger driving current can be generated, thereby providing a gate driving signal with greater load-carrying capacity. Based on the greater load-carrying capacity, the gate driving signal output by one gate driving circuit 10 can drive a larger number of pixel circuits, thereby better adapting to display panels with more pixels and higher resolution.

Referring again to Figure 9, in one embodiment, the output module 400 includes multiple fourth inverters 401 connected in series. Specifically, the fourth inverters 401 can effectively filter out minute fluctuations in the input signal through analog amplification, thereby making the output signal more stable and improving the reliability of the gate drive circuit 10. Further, the fourth inverters 401 include a thirteenth switch and a fourteenth switch. The first terminal of the thirteenth switch QP7 is connected to a high-level voltage source VHG, and the second terminal of the thirteenth switch QP7 serves as the output terminal of the fourth inverter 401. The first terminal of the fourteenth switch QN7 is connected to a low-level voltage source VGL, and the second terminal of the fourteenth switch QN7 is connected to the second terminal of the thirteenth switch QP7. The input terminal of the first fourth inverter 401 is connected to the output terminal of the holding module 200, and the input terminals of the remaining fourth inverters 401 are respectively connected to the output terminal of the preceding fourth inverter 401. The output terminal of the last fourth inverter 401 serves as the output terminal of the output module 400, used to output the gate drive signal. Specifically, the amplification factor of the output module 400 can be adjusted by adjusting the size of the thirteenth switch QP7 and the fourteenth switch QN7 in each of the fourth inverters 401. The larger the size of the thirteenth switch QP7 and the fourteenth switch QN7, the greater the amplification factor of the output module 400 and the stronger its load-carrying capacity.

It should be noted that Figure 9 shows two fourth inverters 401 in the output module 400, but in reality, the number of fourth inverters 401 in the output module 400 can be adjusted according to requirements. This embodiment does not limit the number of fourth inverters 401. For example, if the gate drive signal needs to have the opposite level to the initial drive signal, an odd number of fourth inverters 401 can be set. If the gate drive signal needs to have the same level as the initial drive signal, an even number of fourth inverters 401 can be set. Moreover, since there is a certain delay in the signal transmission process of the fourth inverter 401, the number of fourth inverters 401 can be determined according to the required delay time between the gate drive signal and the initial drive signal.

This application also provides a display panel. FIG10 is a schematic diagram of the structure of one embodiment of the display panel. Referring to FIG10, in one embodiment, the display panel includes a plurality of pixel circuits 20 and a plurality of gate driving circuits 10 as described above. The plurality of pixel circuits 20 are arranged in multiple rows, and each pixel circuit 20 includes a plurality of transistors. The output terminal of each gate driving circuit 10 is respectively connected to at least a portion of the transistors in the plurality of pixel circuits 20 located in each row, so as to control the connected transistors to turn on and off through a gate driving signal. In this embodiment, based on the aforementioned gate driving circuit 10 with better output signal quality, the driving reliability of the transistors in the pixel circuits 20 can be improved, thereby providing a display panel with better display effect.

Referring again to Figure 10, in one embodiment, multiple gate driving circuits 10 are connected in stages. The trigger signal of a first-stage gate driving circuit 10 comes from the display driver chip or another connected gate driving circuit 10. That is, the first-stage gate driving circuit 10 is connected to both the display driver chip and another gate driving circuit 10, so that the gate driving circuit 10 can receive two signals respectively and select one of the two signals as the trigger signal. Specifically, if the display panel is in a global refresh scenario, each row of pixel circuits 20 needs to be refreshed row by row. The gate driving signal of each row of pixel circuits 20 can be generated by triggering the nth-stage gate driving circuit 10 by the (n-1)th-stage gate driving circuit 10, which is simple and convenient for control logic. If the display panel is in a local high refresh scenario, only some rows of pixel circuits 20 need to be refreshed during certain periods. Therefore, the gate driving circuit 10 corresponding to the first row pixel circuit 20 in the high refresh region can receive the frame start signal, and the gate driving circuit 10 corresponding to the other row pixel circuits 20 in the high refresh region can generate gate driving signals under the triggering of the corresponding previous stage gate driving circuit 10, thereby realizing flexible and high-frequency refresh of some row pixel circuits 20.

Figure 11 is a second schematic diagram of the structure of a display panel according to an embodiment. Referring to Figure 11, in one embodiment, multiple pixel circuits 20 are arranged in M rows, and the display panel also includes N inter-level switches 30. The first terminal of each inter-level switch 30 is connected to the input terminal of the gate driving circuit 10 corresponding to each row of pixel circuits 20. A second terminal of the nth inter-level switch 30 is connected to the output terminal of the gate driving circuit 10 corresponding to the (n-1)th row of pixel circuits 20, and the other second terminal of each inter-level switch 30 is used to receive the frame start signal from the display driver chip. The inter-level switch 30 is used to turn on any second terminal of the inter-level switch 30 to the first terminal of the inter-level switch 30. Wherein, M is an integer greater than 2, n is an integer greater than 2, n≤N, N＝M-1. That is, the input terminal of the gate driving circuit 10 corresponding to the first row of pixel circuits 20 only needs to receive the frame start signal, so there is no need to set up inter-level switches 30, thereby reducing the number of inter-level switches 30. In this embodiment, by setting the inter-level switch 30, different sources of trigger signals can be selected in different refresh scenarios, thereby achieving flexible refresh of different areas of the display panel.

In one embodiment, when the gate driving circuit includes a holding module, the trigger signal of the first-stage gate driving circuit 10 comes from the display driver chip or the initial driving signal output by the holding module of another connected stage of the gate driving circuit 10. Accordingly, FIG12 is a third schematic diagram of the structure of a display panel according to an embodiment. Referring to FIG12, in one embodiment, multiple pixel circuits 20 are arranged in M rows. When the gate driving circuit 10 includes an output module 400, the display panel also includes N inter-stage switches 30. The first terminal of each inter-stage switch 30 is connected to the input terminal of the gate driving circuit 10 corresponding to each row of pixel circuits 20. A second terminal of the nth-stage inter-stage switch 30 is connected to the input terminal of the output module 400 in the gate driving circuit 10 corresponding to the (n-1)th row of pixel circuits 20. The other second terminal of each inter-stage switch 30 is used to receive the frame start signal from the display driver chip. The inter-stage switch 30 is used to turn on any second terminal of the inter-stage switch 30 to the first terminal of the inter-stage switch 30. Where M is an integer greater than 2, n is an integer greater than 2, n≤N, and N＝M-1. It is understood that the control logic in this embodiment is the same as that in the previous embodiment, and will not be repeated here.

The difference between this embodiment and the previous embodiment is that, when the gate drive circuit 10 is triggered by the previous stage gate drive circuit 10, it is not triggered by the amplified gate drive signal, but by the initial drive signal before amplification. It is understood that the triggering function does not require excessive drive current; the voltage of the trigger signal only needs to meet the transistor's on/off conditions. Therefore, this embodiment uses the initial drive signal for triggering, which not only reduces the power consumption of the gate drive circuit 10 but also reduces the current input of the trigger signal to the first inverter, preventing excessive input current from damaging the first inverter, thereby protecting the first inverter and improving its lifespan and output reliability. Moreover, even if the load driven by the gate drive signal is large, causing some changes in the waveform of the gate drive signal, the impact on the initial drive signal is negligible, thus providing better reliability when used as the trigger signal for the next stage.

This application also provides a display screen. FIG13 is a schematic diagram of the structure of one embodiment of the display screen. Referring to FIG13, the display screen includes a cover plate 40 and a display panel as described above. The cover plate 40 is disposed on the light-emitting side of the display panel and covers the display panel. In this embodiment, by providing the cover plate 40, the display panel can be protected, reducing damage to the display panel from external forces, thereby improving the reliability of the display panel. It should be noted that this embodiment provides a schematic diagram of the display screen based on the embodiment of FIG10, but it is understood that the display panel of other embodiments can also be combined with the cover plate 40 to form, for example, the display screens shown in FIG14 and FIG15, which will not be described in detail here.

In one embodiment, continuing to refer to Figures 13 to 15, the display screen further includes a display driver chip 50. The display driver chip 50 is connected to the display panel and is used to output a frame start signal and at least one of a first clock signal CKB and a second clock signal CK. The display driver chip 50 is used to switch the level state of the frame start signal when the first clock signal CKB is in a high-level state. In this embodiment, by controlling the switching timing of the level state of the frame start signal output by the display driver chip 50, timing conflicts between the frame start signal and the clock signal can be effectively avoided, thereby preventing abnormalities in the gate drive circuit caused by timing conflicts and improving the operational reliability of the gate drive circuit.

Referring again to Figures 14 and 15, in one embodiment, when the display panel includes inter-stage switches 30, the display driver chip 50 is connected to a second terminal of each inter-stage switch 30 in the display panel. The display driver chip 50 is used to transmit the frame start signal to each of the inter-stage switches 30. Specifically, the inter-stage switch 30 can selectively turn on the (n-1)th stage gate drive circuit to the nth stage gate drive circuit, so that the initial drive signal or gate drive signal generated by the (n-1)th stage gate drive circuit is used as the trigger signal of the nth stage gate drive circuit. The inter-stage switch 30 can also selectively turn on the display driver chip 50 to any stage gate drive circuit, so that the frame start signal generated by the display driver chip 50 is used as the trigger signal.

This application also provides a display device, such as the display screen described above. In this embodiment, based on the aforementioned display screen, a display device with stable and reliable image display is provided.

Specifically, the display device can be, but is not limited to, various personal computers, laptops, smartphones, tablets, IoT devices, and portable wearable devices. IoT devices can include smart speakers, smart TVs, smart air conditioners, smart in-vehicle devices, etc. Portable wearable devices can include smartwatches, smart bracelets, head-mounted devices, etc. Figure 16 is an internal structural diagram of a display device according to an embodiment. The display device includes a processor, memory, communication interface, display panel, and input device connected via a system bus. The processor of the display device provides computing and control capabilities. The memory of the display device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The communication interface of the display device is used for wired or wireless communication with external terminals. Wireless communication can be achieved through WIFI, mobile cellular networks, NFC (Near Field Communication), or other technologies. The input device of the display device can be a touch layer covering the display panel, or buttons, trackballs, or touchpads provided on the display device casing, or external keyboards, touchpads, or mice, etc.

Those skilled in the art will understand that the structure shown in FIG16 is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the display device to which the present application is applied. A specific display device may include more or fewer components than those shown in FIG16, or combine certain components, or have different component arrangements.

The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

The above embodiments merely illustrate several implementation methods of the embodiments of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the embodiments of this application, and these all fall within the protection scope of the embodiments of this application. Therefore, the protection scope of the patent for the embodiments of this application should be determined by the appended claims.

Claims (22)

A gate drive circuit, comprising: The first switch has a first terminal for connecting to a high-level voltage source and a control terminal for receiving a first clock signal. The first switch is a first type of switch and is used to turn on when the signal received at the control terminal is low. The second switch has a first terminal for connecting to a low-level voltage source and a control terminal for receiving a second clock signal. The level of the second clock signal is opposite to that of the first clock signal. The second switch is a second type of switch, which is turned on when the signal received at the control terminal is high. The first inverter is connected to the second terminal of the first switch and the second terminal of the second switch respectively. The first inverter is used to flip the level state of the trigger signal input to the first inverter when the first switch and the second switch are turned on, so as to generate a gate drive signal. The trigger signal comes from the display driver chip or from another gate driver circuit. The gate driving circuit according to claim 1 further includes: A holding module, connected to the output of the first inverter, is used to maintain the level of the output of the first inverter and generate an initial drive signal when the first clock signal is high. The initial drive signal has the opposite level to the signal output by the first inverter, and the gate drive signal has the same waveform as the initial drive signal. According to claim 2, the gate driving circuit, wherein the holding module comprises: The third switch has a second terminal for connecting to a high-level voltage source and a control terminal for receiving the second clock signal; the third switch is a first type of switch. The fourth switch is used to connect its second terminal to a low-level voltage source and its control terminal to receive the first clock signal. The fourth switch is a second type of switch. A locking unit is connected to the output terminal of the first inverter, the first terminal of the third switch, and the first terminal of the fourth switch, respectively. The locking unit is used to maintain the level state of the output terminal of the first inverter unchanged when the third switch and the fourth switch are turned on, and to generate an initial drive signal. According to claim 3, the gate driving circuit, wherein the locking unit comprises: The second inverter is connected to the first terminal of the third switch and the first terminal of the fourth switch respectively. The second inverter is used to flip the level state of the input signal when the third switch and the fourth switch are turned on. The third inverter has its input terminals connected to the output terminals of the first inverter and the second inverter, respectively, and its output terminal connected to the input terminal of the second inverter. The third inverter is used to flip the level state of the input signal. According to claim 4, the gate drive circuit, wherein the second inverter comprises: The fifth switch is connected to the second end of the third switch, the first end of the fifth switch is connected to the output end of the first inverter, and the control end of the fifth switch is connected to the output end of the third inverter. The fifth switch is a first type of switch. The sixth switch is connected to the second terminal of the fourth switch, the first terminal of the sixth switch is connected to the first terminal of the fifth switch, and the control terminal of the sixth switch is connected to the output terminal of the third inverter. The sixth switch is a second type of switch. According to claim 4, the gate drive circuit, wherein the third inverter comprises: The seventh switch has its first terminal connected to a high-level voltage source, its second terminal connected to the input terminal of the second inverter, and its control terminal connected to the output terminal of the second inverter. The seventh switch is a first type of switch. The eighth switch is connected to a low-level voltage source at its first terminal and to the second terminal of the seventh switch at its second terminal. The control terminal of the eighth switch is connected to the output terminal of the third inverter. The eighth switch is a second type of switch. According to claim 1, the gate driving circuit, wherein the first inverter comprises: The ninth switch is a switch whose first end is connected to the second end of the first switch. The second end of the ninth switch serves as the output end of the first inverter. The control end of the ninth switch is used to receive the trigger signal. The ninth switch is a first type of switch. The tenth switch is connected to the second terminal of the second switch and to the second terminal of the ninth switch. The control terminal of the tenth switch is used to receive the trigger signal. The tenth switch is a second type of switch. The gate driving circuit according to claim 2 further includes: A reset module, connected to the output of the holding module, is used to receive a reset control signal and, in response to the rising edge of the reset control signal, switch the level state of the output of the holding module to the target level state. The gate driving circuit according to claim 2 further includes: A reset module, connected to the output of the holding module, is used to receive a reset control signal and, in response to the falling edge of the reset control signal, switch the level state of the output of the holding module to the target level state. The gate drive circuit according to claim 8 or 9, wherein the reset module comprises: The eleventh switch has its first terminal connected to a high-level voltage source, its second terminal connected to the output terminal of the holding module, its control terminal receiving the reset control signal, and its ability to switch the output level of the holding module to a high level when the switch is on. The eleventh switch is a first type of switch. The gate drive circuit according to claim 8 or 9, wherein the reset module comprises: The twelfth switch has a first terminal connected to a low-level voltage source and a second terminal connected to the output terminal of the holding module. The control terminal of the twelfth switch is used to receive the reset control signal. When the twelfth switch is turned on, it switches the level state of the output terminal of the holding module to a low level. The twelfth switch is a second type of switch. The gate driving circuit according to claim 2 further includes: An output module, connected to the output of the holding module, is used to amplify the initial drive signal to generate the gate drive signal. According to claim 12, the gate drive circuit, wherein the output module includes a plurality of fourth inverters connected in series. According to the gate drive circuit of claim 1, the first type of switch is a PMOS transistor, and the second type of switch is an NMOS transistor. A display panel, comprising: Multiple pixel circuits are arranged in multiple rows, and each pixel circuit includes multiple transistors. Multiple gate driving circuits as described in any one of claims 1 to 14, wherein the output terminal of each gate driving circuit is respectively connected to at least a portion of the transistors in the multiple pixel circuits located in each row, so as to control the connected transistors to be turned on and off by the gate driving signal. The display panel according to claim 15, wherein the plurality of gate driving circuits are connected in stages, and the trigger signal of the first-stage gate driving circuit comes from the display driver chip or another connected gate driving circuit. The display panel according to claim 16, wherein the plurality of pixel circuits are arranged in M rows, and the display panel further comprises: There are N inter-level switches. The first terminal of each inter-level switch is connected to the input terminal of the gate driving circuit corresponding to the pixel circuit of each row. A second terminal of the nth inter-level switch is connected to the output terminal of the gate driving circuit corresponding to the pixel circuit of the (n-1)th row. The other second terminal of each inter-level switch is used to receive the frame start signal from the display driver chip. The inter-level switch is used to turn on any second terminal of the inter-level switch to the first terminal of the inter-level switch. Where M is an integer greater than 2, n is an integer greater than 2, n≤N, and N＝M-1. The display panel according to claim 16, wherein the plurality of pixel circuits are arranged in M rows, and wherein the gate driving circuit includes an output module, the display panel further includes: There are N inter-level switches. The first terminal of each inter-level switch is connected to the input terminal of the gate driving circuit corresponding to the pixel circuit of each row. A second terminal of the nth inter-level switch is connected to the input terminal of the output module in the gate driving circuit corresponding to the pixel circuit of the (n-1)th row. The other second terminal of each inter-level switch is used to receive the frame start signal from the display driver chip. The inter-level switch is used to turn on any second terminal of the inter-level switch to the first terminal of the inter-level switch. Where M is an integer greater than 2, n is an integer greater than 2, n≤N, and N＝M-1. A display screen, comprising: The display panel as described in any one of claims 15 to 18; A cover plate is disposed on the light-emitting side of the display panel and covers the display panel. The display screen according to claim 19 further comprises: The display driver chip is connected to the display panel and is used to output a frame start signal and at least one of a first clock signal and a second clock signal. The display driver chip is used to switch the level state of the frame start signal when the first clock signal is in a high level state. According to the display screen of claim 20, wherein when the display panel includes inter-stage switches, the display driver chip is connected to a second terminal of each inter-stage switch in the display panel, and the display driver chip is used to transmit the frame start signal to each of the inter-stage switches. A display device, comprising: The display screen as claimed in any one of claims 19 to 21.