WO2025227381A1 - Shift register unit and driving method therefor, and display driver and display apparatus - Google Patents

Abstract

Provided are a shift register unit and a driving method therefor, and a display driver and a display apparatus, which belong to the technical field of displays. An input control circuit can control the connection/disconnection between an input end and an input node under the control of a clock signal; an output control circuit can output a display driving signal to a pixel on the basis of the potential of the input node and an enable signal provided by an enable end; and a switch control circuit can control the connection/disconnection between the enable end and the output control circuit under the control of a control signal. In this way, by flexibly setting a control signal, whether to connect an enable end to an output control circuit can be chosen, such that the output control circuit outputs a required driving signal to a pixel, so as to drive the pixel to emit light. On this basis, by further flexibly setting the enable signal and a clock signal, a shift register unit can further output signals matching a P-type transistor and/or an N-type transistor in the pixel. The shift register unit has rich driving modes, and the working power consumption thereof is relatively low.

Description

Shift register unit and its driving method, display driver, display device Technical Field

This application relates to the field of display technology, and in particular to a shift register unit and its driving method, a display driver, and a display device.

Background Technology

Display devices generally include a display driver and a display panel. The display driver transmits display driving signals, including gate driving signals, reset control signals, and light emission control signals, to multiple rows of pixels on the display panel to drive multiple pixels to emit light. Furthermore, considering narrow bezel designs, gate driver on array (GOA) technology is currently widely used to integrate the display driver onto the display panel.

In related technologies, display drivers using GOA (Gate of Area) technology typically include multiple cascaded GOA units. These multiple GOA units can be connected one-to-one with multiple rows of pixels on the display panel via multiple signal lines, and are used to transmit gate drive signals to the pixels row by row to illuminate the pixels sequentially, achieving line-by-line scanning and refreshing, enabling the display panel to display an image.

However, due to the limitation of cascading multiple GOA units, the driving method of GOA units in current display drivers is fixed and singular, and the power consumption is relatively large.

Summary of the Invention

A shift register unit and its driving method, a display driver, and a display device are provided. The technical solution is as follows:

On the one hand, a shift register unit is provided, the shift register unit comprising:

An input control circuit is connected to a first clock terminal, a second clock terminal, an input terminal, and an input node, respectively, and is used to control the connection and disconnection of the input terminal and the input node in response to a first clock signal provided by the first clock terminal and a second clock signal provided by the second clock terminal.

An output control circuit, connected to the input node, enable terminal, and output terminal respectively, is used to control the potential of the output terminal based on the potential of the input node and the enable signal provided by the enable terminal, so as to write the data to the pixel through the output terminal to the transistor output gate drive signal or to the pixel. The reset transistor outputs a reset signal to drive the pixel to emit light;

A switch control circuit is connected between the enable terminal and the output control circuit, and is also connected to at least two first control terminals and at least two second control terminals respectively, and is used to control the on/off state of the enable terminal and the output control circuit in response to a first control signal provided by each first control terminal and a second control signal provided by each second control terminal.

Optionally, the output control circuit includes:

The first output control sub-circuit is connected to the input node and the first intermediate node respectively, and is used to control the potential of the first intermediate node based on the potential of the input node;

The second output control sub-circuit is connected to the first intermediate node, the enable terminal, and the output terminal, respectively, and is used to control the potential of the output terminal based on the potential of the first intermediate node and the enable signal.

Optionally, the second output control sub-circuit includes:

A first output control unit is connected to the first intermediate node and the second intermediate node respectively, and is used to control the potential of the second intermediate node based on the potential of the first intermediate node;

The second output control unit is connected to the second intermediate node, the enable terminal, and the output terminal respectively, and is used to control the potential of the output terminal based on the potential of the second intermediate node and the enable signal.

Optionally, the first output control unit in the second output control sub-circuit is also connected to the reset control terminal and is also used to control the potential of the second intermediate node based on the reset control signal provided by the reset control terminal.

Optionally, the second output control unit in the second output control sub-circuit is also connected to the reset control terminal and is also used to control the potential of the output terminal based on the reset control signal provided by the reset control terminal.

Optionally, the first output control sub-circuit is also connected to the reset control terminal and is also used to control the potential of the first intermediate node based on the reset control signal provided by the reset control terminal.

Optionally, the switch control circuit is connected to two first control terminals and two second control terminals respectively, and the two first control terminals and the two second control terminals correspond one-to-one;

Furthermore, a first control terminal and a second control terminal, each corresponding to one of the preceding shift register units, are respectively connected to the second intermediate node and the first intermediate node of the cascaded shift register unit. The other first control terminal and the other second control terminal, each corresponding to one of the preceding shift register units, are respectively connected to the shift register unit's... Connect the first intermediate node and the second intermediate node.

Optionally, the shift register unit further includes:

The latch circuit is connected to the third clock terminal, the fourth clock terminal, the first intermediate node, and the input node respectively, and is used to control the on/off state of the first intermediate node and the input node in response to the third clock signal provided by the third clock terminal and the fourth clock signal provided by the fourth clock terminal, and outputs the potential of the first intermediate node to the input node after inverting the potential.

Optionally, the first clock terminal and the third clock terminal are shared, and the second clock terminal and the fourth clock terminal are shared.

Optionally, the latch circuit includes a first NOT gate and a first transmission gate connected in series between the first intermediate node and the input node, and the first transmission gate is also connected to the third clock terminal and the fourth clock terminal respectively.

Optionally, in the first output control sub-circuit and the second output control sub-circuit, the circuit connected to the enable terminal or the reset control terminal includes a NOR gate or a NAND gate, and the circuit not connected to the enable terminal and the reset control terminal includes a second NOT gate.

Furthermore, when the first output control sub-circuit is connected to the reset control terminal and the second output control sub-circuit is not connected to the reset control terminal, the first NOT gate included in the latch circuit is shared with the second NOT gate included in the second output control sub-circuit.

Optionally, the shift register unit further includes:

A drive enhancement circuit is connected between the output control circuit and the output terminal, and is used to invert the potential of the output signal of the output control circuit at least once before outputting it to the output terminal.

Optionally, the drive enhancement circuit includes at least one third NOT gate connected in series between the output control circuit and the output terminal, and when the drive enhancement circuit includes multiple third NOT gates, the multiple third NOT gates are connected in series between the output control circuit and the output terminal in sequence;

Each of the plurality of third NOT gates is also connected to a first power supply terminal and a second power supply terminal respectively, and is used to operate based on a first power supply signal provided by the first power supply terminal and a second power supply signal provided by the second power supply terminal, wherein the potential of the first power supply signal is greater than the potential of the second power supply signal.

Optionally, among the plurality of third NOT gates, the first power signal provided by the first power supply terminal connected to the last third NOT gate is greater than or equal to the first power signal provided by the first power supply terminal connected to the other third NOT gates, and the last third NOT gate is the third NOT gate connected to the output terminal among the plurality of third NOT gates.

Optionally, among the plurality of third NOT gates, the second power signal provided by the second power supply terminal connected to the last third NOT gate is less than or equal to the second power signal provided by the second power supply terminals connected to the other third NOT gates, and the last third NOT gate is the third NOT gate connected to the output terminal among the plurality of third NOT gates.

Optionally, the output terminal includes: a first output terminal and a second output terminal, and during the same time period, the potential of the first output terminal is opposite to the potential of the second output terminal; the drive enhancement circuit includes:

The first drive enhancement sub-circuit is connected between the output control circuit and the first output terminal, and is used to invert the potential of the output signal of the output control circuit an even number of times and then output it to the first output terminal.

The second drive enhancement sub-circuit is connected between the output control circuit and the second output terminal, and is used to invert the potential of the output signal of the output control circuit an odd number of times before outputting it to the second output terminal.

Optionally, the first drive enhancement sub-circuit includes an even number of third NOT gates connected in series, the second drive enhancement sub-circuit includes an odd number of third NOT gates connected in series, and the first drive enhancement sub-circuit and the second drive enhancement sub-circuit share at least one third NOT gate.

Optionally, the input control circuit includes: a second transmission gate;

The second transmission gate is connected between the input terminal and the input node, and is also connected to the first clock terminal and the second clock terminal respectively.

Optionally, the switch control circuit includes at least two third transmission gates;

The at least two third transmission gates are connected in series between the enable terminal and the output control circuit, and are also connected to the at least two first control terminals and the at least two second control terminals respectively, and each of the third transmission gates is connected to a first control terminal and a second control terminal respectively.

Optionally, when the shift register unit is used to write the transistor output gate drive signal to the data in the pixel through the output terminal:

The output terminal of the shift register unit is used to connect to the N-type data writing transistor in the pixel, and is used to output a gate drive signal to the N-type data writing transistor through the output terminal;

And/or,

The output terminal of the shift register unit is used to connect to the P-type data writing transistor in the pixel, and is used to output a gate drive signal to the P-type data writing transistor through the output terminal.

Optionally, the shift register unit is used to send a reset crystal to the pixel via the output terminal. When the tube outputs a reset signal:

The output terminal of the shift register unit is used to connect to the N-type reset transistor in the pixel, and is used to output a reset signal to the N-type reset transistor through the output terminal;

And/or,

The output terminal of the shift register unit is used to connect to the P-type reset transistor in the pixel, and is used to output a reset signal to the P-type reset transistor through the output terminal.

Optionally, the input control circuit includes a second transmission gate; the output control circuit includes a first output control sub-circuit and a second output control sub-circuit, wherein the first output control sub-circuit includes a two-input NOR gate, and the second output control sub-circuit includes a two-input NAND gate; the switch control circuit includes two third transmission gates; the shift register unit further includes a latch circuit and a drive enhancement circuit, wherein the latch circuit includes a first NOT gate and a first transmission gate, and the drive enhancement circuit includes three third NOT gates;

The second transmission gate is connected between the input terminal of the shift register unit and the input node, and is also connected to the first clock terminal and the second clock terminal respectively.

The two input terminals of the two-input NOR gate are respectively connected to the input node and the reset control terminal, and the output terminal of the two-input NOR gate is connected to the first intermediate node.

One input terminal of the two-input NAND gate is connected to the first intermediate node, and the other input terminal of the two-input NAND gate is connected to the enable terminal through the two third transmission gates. The output terminal of the two-input NAND gate is connected to the output terminal of the shift register unit through the three third NOT gates. The two third transmission gates are connected in series, and the three third NOT gates are connected in series. Among the two third transmission gates, one third transmission gate is also connected to the second intermediate node and the first intermediate node of the previous stage shift register unit cascaded with the shift register unit, and the other third transmission gate is also connected to the first intermediate node and the second intermediate node of the shift register unit, respectively.

The input terminal of the first NOT gate is connected to the first intermediate node of the shift register unit, the output terminal of the first NOT gate is connected to the input node through the first transmission gate, and the first transmission gate is also connected to the third clock terminal and the fourth clock terminal respectively.

Furthermore, the output of the shift register unit is used to connect to the N-type transistor in the pixel.

On the other hand, a method for driving a shift register unit is provided, for driving the shift register unit as described in the above aspect; the method includes:

In response to the first scan command, a first clock signal is provided to the first clock terminal, and a second clock signal is provided to the second clock terminal. Provide a second clock signal and provide an enable signal with a first potential to the enable terminal;

In response to a second scan command, a first clock signal is provided to the first clock terminal, a second clock signal is provided to the second clock terminal, and an enable signal of a second potential is provided to the enable terminal;

Wherein, the first clock signal and the second clock signal are used to drive the input control circuit to control the on/off state of the input terminal and the input node; the enable signal is used to drive the output control circuit to control the potential of the output terminal based on the potential of the input node and the enable signal, so as to output a gate drive signal to the data writing transistor in the pixel or output a reset signal to the reset transistor in the pixel through the output terminal, so as to drive the pixel to emit light; and the refresh frequency indicated by the first scan command is greater than the refresh frequency indicated by the second scan command.

In another aspect, a display driver is provided, the display driver comprising: at least two cascaded shift register units as described in the preceding aspect.

In another aspect, a display device is provided, the display device comprising: a display panel, and a display driver as described in yet another aspect above;

The display panel includes multiple pixels, and the display driver is connected to the multiple pixels and is used to transmit gate drive signals or reset signals to the multiple pixels to drive the multiple pixels to emit light.

Attached Figure Description

To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

Figure 1 is a schematic diagram of the structure of a shift register unit provided in an embodiment of this application;

Figure 2 is a schematic diagram of a pixel circuit provided in an embodiment of this application;

Figure 3 is a schematic diagram of the driving timing of a pixel circuit provided in an embodiment of this application;

Figure 4 is a schematic diagram of the driving timing of another pixel circuit provided in an embodiment of this application;

Figure 5 is a schematic diagram of another shift register unit provided in an embodiment of this application;

Figure 6 is a schematic diagram of another shift register unit provided in an embodiment of this application;

Figure 7 is a schematic diagram of another shift register unit provided in an embodiment of this application;

Figure 8 is a schematic diagram of another shift register unit provided in an embodiment of this application;

Figure 9 is a schematic diagram of another shift register unit provided in an embodiment of this application;

Figure 10 is a schematic diagram of another shift register unit provided in an embodiment of this application;

Figure 11 is a schematic diagram of another shift register unit provided in an embodiment of this application;

Figure 12 is a schematic diagram of the circuit structure of a shift register unit provided in an embodiment of this application;

Figure 13 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this application;

Figure 14 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this application;

Figure 15 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this application;

Figure 16 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this application;

Figure 17 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this application;

Figure 18 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this application;

Figure 19 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this application;

Figure 20 is a schematic diagram of the transistor structure of a shift register unit based on Figure 15;

Figure 21 is a schematic diagram of the transistor structure of a shift register unit based on Figure 18;

Figure 22 is a schematic diagram of the transistor structure of a shift register unit based on Figure 19;

Figure 23 is a modular equivalent schematic diagram of a shift register unit provided in an embodiment of this application;

Figure 24 is a schematic flowchart of a driving method for a shift register unit provided in an embodiment of this application;

Figure 25 is a schematic diagram of the driving timing of a shift register unit provided in an embodiment of this application;

Figure 26 is a schematic diagram of the driving timing simulation of a shift register unit provided in an embodiment of this application;

Figure 27 is a schematic diagram of the driving timing of another shift register unit provided in an embodiment of this application;

Figure 28 is a schematic diagram of the driving timing of another shift register unit provided in an embodiment of this application;

Figure 29 is a schematic diagram of the driving timing of another shift register unit provided in an embodiment of this application;

Figure 30 is a schematic diagram of the driving timing of another shift register unit provided in an embodiment of this application;

Figure 31 is a schematic diagram of a display driver provided in an embodiment of this application;

Figure 32 is a schematic diagram of the structure of a display device provided in an embodiment of this application.

Detailed Implementation

To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

It is understood that the transistors used in all embodiments of this application can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in the embodiments of this application are mainly switching transistors. This is because the source and drain of the switching transistors used here are symmetrical. Therefore, the source and drain are interchangeable. In the embodiments of this application, the source is referred to as the first electrode and the drain as the second electrode. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is the control electrode, also known as the gate; the signal input terminal is the source; and the signal output terminal is the drain. Furthermore, the switching transistors used in the embodiments of this application can include either P-type or N-type switching transistors. The P-type switching transistor is turned on when the gate is low and turned off when the gate is high; the N-type switching transistor is turned on when the gate is high and turned off when the gate is low. In addition, multiple signals in the various embodiments of this application correspond to a first potential and a second potential. The first potential and the second potential only represent that the potential of the signal has two states; they do not represent that the first potential or the second potential has a specific value throughout the text.

This application provides a shift register unit that not only effectively matches the timing requirements of N-type and/or P-type transistors in a pixel, but also enables local reset, offers diverse driving modes, provides good driving flexibility, and consumes relatively little power. As shown in Figure 1, the shift register unit includes an input control circuit 01 and an output control circuit 02.

The input control circuit 01 is connected to the first clock terminal CKn, the second clock terminal CB, the input terminal IN_n and the input node Q_n respectively, and is used to control the on/off state of the input terminal IN_n and the input node Q_n in response to the first clock signal provided by the first clock terminal CKn and the second clock signal provided by the second clock terminal CB.

For example, the input control circuit 01 can control the input terminal IN_n to be connected to the input node Q_n when the potential of the first clock signal is the first potential and the potential of the second clock signal is the first potential, so that the input signal provided by the input terminal IN_n is output to the input node Q_n, thereby controlling the potential of the input node Q_n to be the potential of the input signal; and the input control circuit 01 can control the input terminal IN_n to be disconnected from the input node Q_n when the potential of the first clock signal is the second potential or the potential of the second clock signal is the second potential.

Understandably, "n" indicates that the shift register unit is the nth stage shift register unit. Correspondingly, "n-1" represents the previous stage shift register unit cascaded with this unit, and "n+1" represents the next stage shift register unit cascaded with this unit. n can be an integer greater than 1. Generally, multi-stage shift register units can be connected one-to-one with multiple rows of pixels, but this is not limited to a one-to-one correspondence. For example, each stage shift register unit can be connected to at least two rows of pixels.

Optionally, in this embodiment, the first potential can be an effective potential, and the second potential can be an ineffective potential. Furthermore, for a P-type transistor in a pixel, the first potential can be a low potential (low, L) relative to the second potential. For an N-type transistor in a pixel, the first potential is lower than the second potential. The potential can be high (high, H). Correspondingly, the reset signal output to the P-type transistor means that the potential of the signal output to the P-type transistor is high (H); the reset signal output to the N-type transistor means that the potential of the signal output to the N-type transistor is low (L). Furthermore, high potential can be represented by binary "1", and low potential can be represented by binary "0".

Referring again to Figure 1, the output control circuit 02 is connected to the input node Q_n, the enable terminal EN, and the output terminal OUT_n. Based on the potential of the input node Q_n and the enable signal provided by the enable terminal EN, it controls the potential of the output terminal OUT_n. This allows the output terminal OUT_n to output a gate drive signal to the data write transistor in the pixel or a reset signal to the reset transistor in the pixel, thereby driving the pixel to emit light. In other words, the shift register unit can output display drive signals such as gate drive signals or reset control signals to the pixel.

For example, the output control circuit 02 can control the output terminal OUT_n to a low potential 0 when the potential of the input node Q_n is high potential 1 and/or the potential of the enable signal is high potential 1; and the output control circuit 02 can control the output terminal OUT_n to a high potential 1 when the potential of the input node Q_n is low potential 0 and the potential of the enable signal is low potential 0. Thus, a gate drive signal including high potential 1 and low potential 0 (i.e., including the first potential and the second potential) can be output through the output terminal OUT_n, which can realize the output of the required timing pulses to the P-type transistors and/or N-type transistors in the pixel, satisfying the driving requirements of PMOS switching pixels, or NMOS switching pixels, or CMOS switching pixels.

Furthermore, output reset and partial refresh control can be achieved by flexibly configuring the enable signal provided by the enable terminal EN. For example, in normal output or high refresh rate areas, the enable signal can be set to a high potential (1) to ensure the output control circuit 02 operates normally; while in the reset phase or low refresh rate area, the enable signal can be set to a low potential (0) to make the output control circuit 02 control the output signal's potential invalid, thus completing the reset. Low refresh rate areas and high refresh rate areas refer to display partitions with relatively low and relatively high refresh rates, respectively. Generally, the display area can be divided into multiple display partitions, and different refresh rates can be used for different display partitions.

For example, for the N-type transistor connected to the output terminal OUT_n in the pixel, during the Porch period (or when the display panel is powered on/off), the enable signal provided by the enable terminal EN can be set to a high potential of 1, that is, the enable signal is set high, so that the output control circuit 02 controls the potential of the output terminal OUT_n to a low potential of 0, thereby resetting the display drive signal output to the N-type transistor. The same applies to the P-type transistor, and will not be elaborated further.

It's understandable that a PMOS switching pixel refers to a pixel whose pixel circuitry includes multiple P-type transistors; an NMOS switching pixel refers to a pixel whose pixel circuitry includes multiple N-type transistors; and a CMOS switching pixel refers to a pixel whose pixel circuitry includes at least one P-type transistor and at least one N-type transistor. MOS is short for metal-oxide-semiconductor, meaning the transistors in the pixel circuitry can be MOS transistors. Additionally, the transistors can also be thin-film transistors (TFTs). That is, the transistors in the pixel circuitry can be MOS TFTs; P-type transistors can be called PMOS TFTs, and N-type transistors can be called NMOS TFTs. Of course, this is just an illustrative explanation.

Optionally, taking a CMOS switch-type pixel as an example, Figure 2 shows a schematic diagram of the circuit structure of a pixel provided in an embodiment of this application. As shown in Figure 2, the pixel may include a pixel circuit and a light-emitting element L1. The pixel circuit may include eight transistors T1 to T8 and one capacitor Cst, that is, it can be an 8T1C structure circuit. The light-emitting element L1 can be an organic light-emitting diode (OLED). The connection method of each part is shown in Figure 2 and will not be repeated. In addition, the signal terminals connected to the pixel include: gate signal terminal Gate, reset signal terminals Reset1, Reset2 and Reset3, data signal terminal Vdata, reset power supply terminals V1, V2 and V3, light emission control terminal EM, pull-up power supply terminal EVDD, and pull-down power supply terminal ELVSS. Of course, in some other embodiments, the pixel circuit can also be other structures, such as an 8T2C structure. The light-emitting element L1 can also be other types, such as a micro-LED, also known as an MLED. This application embodiment does not limit this.

For PMOS switching pixels, all eight transistors T1 to T8 can be PMOS TFTs; for NMOS switching pixels, all eight transistors T1 to T8 can be NMOS TFTs; and for CMOS switching pixels, as shown in Figure 2, T2, T3, T5, and T6 can be NMOS TFTs, while the other transistors can be PMOS TFTs. Correspondingly, taking the gate signal terminal as an example, the gate signal terminal connected to transistor T2 is labeled Gate_N, and the gate signal terminal connected to transistor T1 is labeled Gate_P. "N" indicates the relevant signal terminal connected to the NMOS TFT, and "P" indicates the relevant signal terminal connected to the PMOS TFT. The labeling of other signal terminals can be similar.

Taking the gate drive signal as an example, for a PMOS switching pixel, since transistors T1 and T2 that receive the gate drive signal are both PMOS TFTs, the same or similar P-type gate drive signal can be used to drive transistors T1 and T2. For an NMOS switching pixel, since transistors T1 and T2 that receive the gate control signal are both NMOS TFTs, the same or similar N-type gate drive signal can be used. The driving signal drives transistors T1 and T2 to operate. For the CMOS switch-type pixel shown in Figure 2, since transistor T1, which receives the gate driving signal, is a PMOS TFT and T2 is an NMOS TFT, inverted P-type and N-type gate driving signals are needed to drive transistors T1 and T2 respectively. As mentioned earlier, the P-type gate driving signal refers to a gate driving signal with a first potential low (0) and a second potential high (1); the N-type control signal refers to a gate driving signal with a first potential high (1) and a second potential low (0).

Optionally, taking the pixel circuit shown in Figure 2 as an example, Figure 3 shows a driving timing diagram of a pixel circuit. As shown in Figure 3, the driving timing may include stages t1 to t5 executed sequentially.

In stage t1, the potential of the light-emitting control signal provided by the light-emitting control terminal EM_P can be high, and the potential of the light-emitting control signal provided by the light-emitting control terminal EM_N can be low. Accordingly, transistors T4 and T5 can be turned off. Furthermore, the connection between the pull-up power supply terminal EVDD and the pull-down power supply terminal EVSS can be disconnected, thereby turning off the light emission of the light-emitting element L1.

In stage t2, the gate drive signal provided by the gate signal terminal Gate_N is at a high potential, and the reset signal provided by the reset signal terminal Reset1 is also at a high potential. Accordingly, transistors T2 and T3 can both be turned on. Furthermore, the reset power supply terminal V2 can sequentially output reset power supply signals to nodes P3 and P1 via the turned-on transistors T3 and T2, respectively, to reset nodes P1 and P3 to the potential V20 of the reset power supply signal provided by the reset power supply terminal V2. This causes the potential of node P2 to gradually become V20 - Vth_Td, where Vth_Td refers to the threshold voltage of transistor T8.

In stage t3, the reset signal provided by the reset signal terminal Reset1 becomes low, the gate drive signal provided by the gate signal terminal Gate_P becomes low, and the gate drive signal provided by the gate signal terminal Gate_N becomes high. Accordingly, transistor T3 can be turned off, and transistors T1, T2, and T8 can all be turned on. Furthermore, the data signal terminal Vdata can transmit a data signal to node P2 via the turned-on transistor T1, thereby charging the potential of node P2 to the potential Vdata0 of the data signal, and charging nodes P3 and P1 to a potential of Vdata0 + Vth_Td.

In stage t4, the gate drive signal provided by the gate signal terminal Gate_N becomes low, the reset signal provided by the reset signal terminal Reset2 (i.e., Reset_P) is low, and the reset signal provided by the reset signal terminal Reset3 (i.e., Reset_N) is high. Correspondingly, transistors T2 are turned off, and transistors T6 and T7 are turned on. Furthermore, the reset power supply terminal V3 outputs a reset power supply signal to node P2 via the turned-on transistor T7, resetting node P2 to the potential V30 of the reset power supply signal provided by the reset power supply terminal V3. If V30 > Vdata0, then node P3... The potential of node P3 can be changed to V30 + Vth_Td; otherwise, the potential of node P3 can remain at Vdata0 + Vth_Td. Furthermore, the reset power supply terminal V1 can output a reset power supply signal to node P4 (i.e., the anode of the OLED) via the conducting transistor T6, thereby resetting node P4 to the potential of the reset power supply signal provided by the reset power supply terminal V1.

In stage t5, the reset signal provided by Reset2 (i.e., Reset_P) becomes high, the reset signal provided by Reset3 (i.e., Reset_N) becomes low, the light-emitting control signal provided by EM_P becomes low, and the light-emitting control signal provided by EM_N can become high. Correspondingly, transistors T6 and T7 are turned off, and transistors T4, T5, and T8 are turned on. This allows a path to be formed between the pull-up power supply EVDD and the pull-down power supply EVSS, enabling the light-emitting element L1 to emit light. The luminous current Id, which is positively correlated with the luminous intensity, is determined by the potentials of node P1 and node P2. The potential of node P1 is Vdata0 + Vth_Td, and the potential of node P2 is the potential EVDD0 of the pull-up power supply signal provided by the pull-up power supply EVDD. Accordingly, based on the current calculation formula, Id = K(Vdata0 - EVDD0) ^² . K is determined by the inherent characteristics of transistor T8, such as its width-to-length ratio W/L, capacitance Cox, and mobility μ. That is, the luminous current transmitted from the pixel circuit to the light-emitting element L1 can be independent of the threshold voltage Vth_Td of the driving transistor. Therefore, the drift of the threshold voltage Vth_Td of transistor T8 will not affect the luminous brightness of the light-emitting element L1, ensuring a good luminous effect for the light-emitting element L1.

It is understandable that, based on the above introduction to the driving principle, transistors T1 and T2 can be called data writing transistors, transistors T3, T6 and T7 can be called reset transistors, transistors T4 and T5 can be called light-emitting control transistors, and transistor T8 can be called driving transistors.

Of course, in some other embodiments, referring to the timing diagram of another pixel circuit shown in Figure 4, it can be seen that during the time period when the light emission control signal provided by the light emission control terminal EM_P becomes high and the light emission control signal provided by the light emission control terminal EM_N becomes low, such as in stage t1, the same action as in stage t4 can be performed once more to add a reset process for nodes P2 and P4. This achieves the purpose of quickly resetting the anode of the light-emitting element L1, ensuring good contrast when the light-emitting element L1 emits light. Simultaneously, it can also increase the refresh and strong bias process for transistor T8, making it easier to meet the display requirements of low-frequency drive and low flicker. That is, it can ensure a better display effect of the display panel. Optionally, the reset signal provided by the reset signal terminal Reset3 can be the same as the reset signal provided by the reset signal terminal Reset2.

Furthermore, in some other embodiments, referring to the timing diagram of another pixel circuit shown in FIG5, it can be seen that, compared to FIG3, the duration of stage t4 can be longer. That is, the reset signal terminal Reset_P The low-level reset signal and the high-level reset signal at the Reset_N terminal can be provided for a longer duration, constituting a wide pulse signal. This allows transistors T6 and T7 to conduct for a longer period, thereby enabling reliable reset of nodes P2 and P4, resulting in a better reset effect.

Optionally, the output terminal OUT_n of the shift register unit provided in this application embodiment can be connected to the gate signal terminal of the pixel circuit (e.g., Gate_N or Gate_P shown in FIG2) and used to provide the required gate drive signal to the gate signal terminal. For example, an inverted P-type gate drive signal or an N-type gate drive signal as shown in FIG3 can be provided to drive transistors T1 and T2 in FIG2 to operate reliably, respectively. Alternatively, the output terminal OUT_n of the shift register unit provided in this application embodiment can be connected to the reset signal terminal of the pixel circuit (e.g., Reset_N and/or Reset_P shown in FIG2) and used to provide the required reset signal to the reset signal terminal, such as providing any of the reset signals shown in FIG3 to FIG5. Of course, in some other embodiments, the output terminal OUT_n of the shift register unit can also be connected to other signal terminals of the pixel circuit (e.g., light emission control terminals EM_N and EM_P) and used to provide signals to other signal terminals.

Referring again to Figure 1, the switch control circuit 03 is connected between the enable terminal EN and the output control circuit 02, and is also connected to at least two first control terminals and at least two second control terminals, respectively. It is used to control the on/off state of the enable terminal EN and the output control circuit 02 in response to a first control signal provided by each first control terminal and a second control signal provided by each second control terminal. That is, the output control circuit 02 and the enable terminal EN are not directly connected, but are indirectly connected through the switch control circuit 03.

For example, the switch control circuit 03 shown in Figure 1 is connected to two first control terminals Con11 and Con12, and to two second control terminals Con21 and Con22. When the potential of the first control signal provided by each first control terminal is the first potential, and the potential of the second control signal provided by each second control terminal is the first potential, the control enable terminal EN is connected to the output control circuit 02, thereby transmitting the enable signal provided by the enable terminal EN to the output control circuit 02. In this case, it can also be considered that the enable terminal EN is connected to the output control circuit 02. Conversely, when the potential of the first control signal provided by each first control terminal is the second potential, and/or the potential of the second control signal provided by each second control terminal is the second potential, the control enable terminal EN is disconnected from the output control circuit 02. In this case, it can also be considered that the enable terminal EN is not connected to the output control circuit 02.

As described above, by connecting the enable terminal EN to the output control circuit 02, the output control circuit 02 can control the potential of the output terminal OUT_n based on the enable signal and the potential of the input node Q_n, thereby outputting a display drive signal to the pixel. In this way, the output of the shift register unit can be controlled by flexibly setting the control signal to connect or not connect the enable terminal EN to the output control circuit 02, thus increasing the drive flexibility. It is better. By resetting the output signal of some shift register units, compared to resetting the output signal of all shift register units, the power consumption of the shift register units can be reduced.

In summary, this disclosure provides a shift register unit. This shift register unit includes an input control circuit, an output control circuit, and a switch control circuit. The input control circuit controls the connection and disconnection of the input terminal and the input node under the control of clock signals provided by a first clock terminal and a second clock terminal. The output control circuit, based on the potential of the input node and the enable signal provided by the enable terminal, outputs a display driving signal to the pixel through the output terminal to drive the pixel to emit light. The switch control circuit controls the connection and disconnection of the enable terminal and the output control circuit under the control of control signals provided by the first control terminal and the second control terminal. Thus, by flexibly setting the control signal, the enable terminal can be connected to or not connected to the output control circuit. With the enable terminal connected to the output control circuit, the output control circuit can control the potential of the output terminal to output the required driving signal to the pixel to drive the pixel to emit light. Furthermore, by flexibly setting the enable signal and the clock signal, the shift register unit can further output display driving signals to the output terminal that match the P-type transistors and/or N-type transistors in the pixel. Therefore, this shift register unit offers rich driving modes and has low power consumption.

Alternatively, as described above, when the shift register unit writes the transistor output gate drive signal to the pixel through the output terminal OUT_n:

The output terminal OUT_n of the shift register unit can be connected to the N-type data write transistor in the pixel, and used to output the gate drive signal to the N-type data write transistor through the output terminal OUT_n. For example, referring to Figure 2, the output terminal OUT_n of the shift register unit can be connected to the gate signal terminal Gate_N connected to the N-type data write transistor T2 in the pixel, and output the required N-type gate drive signal to the gate signal terminal Gate_N.

And/or,

The output terminal OUT_n of the shift register unit can be connected to the P-type data write transistor in the pixel, and used to output the gate drive signal to the P-type data write transistor through the output terminal OUT_n. For example, referring to Figure 2, the output terminal OUT_n of the shift register unit can be connected to the gate signal terminal Gate_P connected to the P-type data write transistor T1 in the pixel, and output the required P-type gate drive signal to the gate signal terminal Gate_P.

Alternatively, as mentioned earlier, in the case where the shift register unit outputs a reset signal to the reset transistor in the pixel through the output terminal OUT_n:

The output terminal OUT_n of the shift register unit is used to connect to the N-type reset transistor in the pixel and to output a reset signal to the N-type reset transistor through the output terminal OUT_n. For example, referring to Figure 2, the output terminal OUT_n of the shift register unit can be connected to the reset signal terminal Reset3 connected to the N-type reset transistor T6 in the pixel, and output the required N-type reset signal to the reset signal terminal Reset3.

And/or,

The output terminal OUT_n of the shift register unit is used to connect to the P-type reset transistor in the pixel and to output a reset signal to the P-type reset transistor through the output terminal OUT_n. For example, referring to Figure 2, the output terminal OUT_n of the shift register unit can be connected to the reset signal terminal Reset2 connected to the P-type reset transistor T7 in the pixel, and output the required P-type reset signal to the reset signal terminal Reset2.

Optionally, Figure 6 shows a schematic diagram of another shift register unit provided in an embodiment of this application. As shown in Figure 6, the output control circuit 02 includes: a first output control sub-circuit 021 and a second output control sub-circuit 022.

The first output control sub-circuit 021 can be connected to the input node Q_n and the first intermediate node Q1_n respectively, and is used to control the potential of the first intermediate node Q1_n based on the potential of the input node Q_n.

For example, the first output control sub-circuit 021 can invert the potential of the input node Q_n and output it to the first intermediate node Q1_n, that is, it can control the potential of the first intermediate node Q1_n to be opposite to the potential of the input node Q_n.

The second output control sub-circuit 022 can be connected to the first intermediate node Q1_n, the enable terminal EN, and the output terminal OUT_n respectively, and can be used to control the potential of the output terminal OUT_n based on the potential of the first intermediate node Q1_n and the enable signal.

For example, the second output control sub-circuit 022 can control the output terminal OUT_n to a low potential 0 when the potential of the first intermediate node Q1_n is high potential 1 and/or the potential of the enable signal is high potential 1; and the second output control sub-circuit 022 can control the output terminal OUT_n to a high potential 1 when the potential of the first intermediate node Q1_n is low potential 0 and the potential of the enable signal is low potential 0.

Optionally, based on Figure 6, Figure 7 shows a schematic diagram of another shift register unit provided in an embodiment of this application. As shown in Figure 7, the second output control sub-circuit 022 may include: a first output control unit 0221 and a second output control unit 0222.

The first output control unit 0221 can be connected to the first intermediate node Q1_n and the second intermediate node Q2_n respectively, and can be used to control the potential of the second intermediate node Q2_n based on the potential of the first intermediate node Q1_n.

For example, the first output control unit 0221 can invert the potential of the first intermediate node Q1_n and output it to the second intermediate node Q2_n, that is, it can control the potential of the second intermediate node Q2_n to be opposite to the potential of the first intermediate node Q1_n.

The second output control unit 0222 can be connected to the second intermediate node Q2_n, the enable terminal EN, and the output terminal OUT_n respectively, and can be used to control the potential of the output terminal OUT_n based on the potential of the second intermediate node Q2_n and the enable signal.

For example, the second output control unit 0222 can control the output terminal OUT_n to be at a low potential 0 when the potential of the second intermediate node Q2_n is high potential 1 and/or the potential of the enable signal is high potential 1; and the second output control unit 0222 can control the output terminal OUT_n to be at a high potential 1 when the potential of the second intermediate node Q2_n is low potential 0 and the potential of the enable signal is low potential 0.

Of course, in some other embodiments, the first output control unit 0221 may be connected to the enable terminal EN to control the potential of the second intermediate node Q2_n based on the enable signal and the potential of the first intermediate node Q1_n.

Alternatively, based on Figure 7, as an optional implementation: as shown in Figure 8, the first output control unit 0221 in the second output control sub-circuit 022 can also be connected to the reset control terminal Trst, and can also be used to control the potential of the second intermediate node Q2_n based on the reset control signal provided by the reset control terminal Trst.

Alternatively, based on Figure 7, as another optional implementation: as shown in Figure 9, the second output control unit 0222 in the second output control sub-circuit 022 can also be connected to the reset control terminal Trst, and can also be used to control the potential of the output terminal OUT_n based on the reset control signal provided by the reset control terminal Trst.

Alternatively, based on Figure 6, as another optional implementation: as shown in Figure 10, the first output control sub-circuit 021 can also be connected to the reset control terminal Trst, and can also be used to control the potential of the first intermediate node Q1_n based on the reset control signal provided by the reset control terminal Trst.

That is, in the embodiments of this application, in the output control circuit 02, the first output control sub-circuit 021 or the second output control sub-circuit 022 can also be connected to the reset control terminal Trst, and can also control the output potential based on the reset signal provided by the reset control terminal Trst.

Understandably, in addition to setting the enable terminal EN, a reset control terminal Trst is also set. This allows for flexible configuration of the reset signal provided by the reset signal terminal Trst during power-on or power-off of the display panel, or during Porch periods. This controls the potential of the output terminal OUT_n to be an invalid potential, i.e., the gate drive signal of the reset output, thus improving performance. This enhances the reliability of power-on and power-off operation. Furthermore, it avoids driver anomalies during the switch between low and high refresh rates in partial refresh scenarios, and further reduces the power consumption of the shift register unit.

Optionally, referring to Figures 7 to 10, it can also be seen that the switch control circuit 03 can be connected to two first control terminals Con11 and Con12, and two second control terminals Con21 and Con22 respectively. Furthermore, the two first control terminals Con11 and Con12 correspond one-to-one with the two second control terminals Con21 and Con22.

Furthermore, a first control terminal Con11 and a second control terminal Con21, each corresponding to a previous stage shift register unit, can be connected to the second intermediate node Q2_n-1 and the first intermediate node Q1_n-1, respectively. Similarly, another first control terminal Con12 and another second control terminal Con22, also corresponding to each other, can be connected to the first intermediate node Q1_n and the second intermediate node Q2_n, respectively. Therefore, the signals at the first intermediate node Q1_n and the second intermediate node Q2_n can be used as cascading signals to drive the cascaded shift register units.

Based on this, it can be seen that by controlling the switch control circuit 03 through the cascading signal of the adjacent two rows of shift register units, the enable terminal EN can be connected step by step. This allows the shift register unit to reset only the GOA unit at the cascading start boundary, without resetting the GOA units that have started but have not completed shifting, until the shifting is complete. In this way, not only can the driving requirement of consistent pixel local refresh output pulse width be met, but also the power consumption is saved compared to resetting all outputs. For example, for the switch control circuit 03, the switch control circuit 03 only controls the enable terminal EN to be connected to the output control circuit 02 when the potential of the first intermediate node Q1_n-1 and the potential of the second intermediate node Q2_n-1 controlled by the previous stage shift register unit are both valid potentials, and the potential of the first intermediate node Q1_n and the potential of the second intermediate node Q2_n controlled by the previous stage shift register unit are also valid potentials. Only then does the switch control circuit 03 control the enable terminal EN to be connected to the output control circuit 02, so that the output control circuit 02 still controls the potential of the output signal based on the enable signal provided by the enable terminal EN.

Optionally, referring further to Figures 6 to 10, it can also be seen that the shift register unit described in the embodiments of this application may further include: latch circuit 04.

Furthermore, the latch circuit 04 can be connected to the third clock terminal CBn, the fourth clock terminal CK, the first intermediate node Q1_n, and the input node Q_n respectively. It can be used to control the on/off state of the first intermediate node Q1_n and the input node Q_n in response to the third clock signal provided by the third clock terminal CBn and the fourth clock signal provided by the fourth clock terminal CK, and output the potential of the first intermediate node Q1_n to the input node Q_n after inverting the potential.

For example, the latch circuit 04 can control the first intermediate node Q1_n to conduct with the input node Q_n when the potential of the third clock signal is the first potential and the potential of the fourth clock signal is the first potential. Simultaneously, the potential of the first intermediate node Q1_n is inverted and output to the input node Q_n; and the latch circuit 04 can control the first intermediate node Q1_n to disconnect from the input node Q_n when the potential of the third clock signal is the second potential, or when the potential of the fourth clock signal is the second potential. In this way, the potential of the input node Q_n can be made the same as the potential of the first intermediate node Q1_n, achieving the purpose of latching the potential of the input node Q_n. Alternatively, the latch circuit 04 can be described as storing the potential of the input node Q_n, preventing leakage of the potential of the input node Q_n.

Optionally, based on Figure 10, Figure 11 shows a schematic diagram of another shift register unit. As shown in Figure 11, the first clock terminal CKn and the fourth clock terminal CK can be shared, and the second clock terminal CB and the third clock terminal CBn can be shared. For example, the first clock terminal CKn and the fourth clock terminal CK can both be the fourth clock terminal CK, and the second clock terminal CB and the third clock terminal CBn can both be the second clock terminal CB. That is, in one optional implementation, as shown in Figure 11, two sets of clock terminals (i.e., two sets of clock signals) can be used: CK and CB. Alternatively, in another optional implementation, as shown in Figures 6 to 10, four sets of clock terminals (i.e., four sets of clock signals) can be used: CKn, CK, CBn, and CB.

Optionally, the period of the four clock signals can be 2H, and the clock signals provided by clock terminal CK and clock terminal CB can differ by 1H. The clock signals provided by clock terminal CKn and clock terminal CB can be inverted signals, and the clock signals provided by clock terminal CBn and clock terminal CK can be inverted signals. Furthermore, the pulse width of the low potential 0 of the clock signals provided by clock terminal CK and clock terminal CB is generally 0 to 2 microseconds (μs) shorter than 1H, and can be selected based on the load resistor RC. This is to eliminate the influence of clock delay and avoid the risk of competition between different circuits during state switching caused by the simultaneous control of the two ends of the input control circuit 01 and latch circuit 04. Here, "H" can refer to one row period and can be flexibly adjusted according to the number of cascaded shift register units.

Optionally, referring further to Figures 6 to 11, it can also be seen that the shift register unit may also include: drive enhancement circuit 05.

Furthermore, the drive enhancement circuit 05 can be connected between the output control circuit 02 and the output terminal OUT_n, and can be used to invert the potential of the output signal of the output control circuit 02 at least once before outputting it to the output terminal OUT_n. In this way, the driving capability of the shift register unit can be enhanced.

Optionally, in some embodiments, as can be seen from FIG11, the output terminal OUT_n may include: a first output terminal OUTN_n and a second output terminal OUTP_n, and, at the same time, the first output terminal... The potential of OUTN_n can be opposite to the potential of the second output terminal OUTP_n.

For example, referring to Figure 2, both the first output terminal OUTN_n and the second output terminal OUTP_n can be connected to the gate signal terminal Gate_N, which is connected to the N-type transistor T2 in the pixel, and used to provide gate drive signals with opposite potentials to the gate signal terminal Gate_N, respectively. Of course, these gate drive signals with opposite potentials will not be provided to the N-type transistor T2 simultaneously. Alternatively, referring to Figure 2, the first output terminal OUTN_n and the second output terminal OUTP_n can be connected to the reset signal terminal Reset3, which is connected to the N-type transistor T6, and the reset signal terminal Reset2, which is connected to the P-type transistor T7, respectively, and used to provide reset signals with opposite potentials to the reset signal terminals Reset3 and Reset2, respectively.

Based on this, referring to Figure 11, it can be seen that the drive enhancement circuit 05 may include: a first drive enhancement sub-circuit 051 and a second drive enhancement sub-circuit 052.

The first drive enhancement sub-circuit 051 can be connected between the output control circuit 02 and the first output terminal OUTN_n, and can be used to invert the potential of the output signal of the output control circuit 02 an even number of times before outputting it to the first output terminal OUTN_n. That is, the potential of the first output terminal OUTN_n is controlled to be the same as the potential of the output signal of the output control circuit 02.

The second drive enhancement sub-circuit 052 can be connected between the output control circuit 02 and the second output terminal OUTP_n, and is used to invert the potential of the output signal of the output control circuit 02 an odd number of times before outputting it to the second output terminal OUTP_n. That is, the potential of the second output terminal OUTP_n is controlled to be opposite to the potential of the output signal of the output control circuit 02.

Accordingly, it can be understood that the output terminal OUT_n shown in Figures 6 to 10 can be either the first output terminal OUTN_n or the second output terminal OUTP_n. In other words, the drive enhancement circuit 05 shown in Figures 6 to 10 can be either the first drive enhancement sub-circuit 051 or the second drive enhancement sub-circuit 052.

Optionally, based on the different embodiments described above, Figures 12 to 19 respectively show schematic diagrams of various circuit structures of the shift register unit. In the scenario where the output terminal OUT_n is connected to the gate signal terminal Gate_N to provide a gate drive signal to the gate signal terminal Gate, the first output terminal OUTN_n can also be identified as NN_n, the second output terminal OUTP_n can also be identified as NP_n, the first intermediate node Q1_n can be identified as NNc_n, and the second intermediate node Q2_n can be identified as NPc_n. The first intermediate node Q1_n of the previous stage shift register unit can be identified as NNc_n-1, and the second intermediate node Q2_n of the previous stage shift register unit can be identified as NPc_n-1. Furthermore, the input terminal IN_n can be connected to the second intermediate node NPc_n-1 of the cascaded previous stage shift register unit. Of course, the input terminal IN_1 of the first stage shift register unit needs to be connected to the enable signal terminal STV to receive the enable signal from the enable signal terminal STV. Start signal. Therefore, NPc_n and NNc_n can be called cascade nodes, used for cascade signal transmission.

Optionally, referring to Figures 12 to 19, the latch circuit 04 may include a first NOT gate INV1 and a first transmission gate Tg1 connected in series between the first intermediate node Q1_n and the input node Q_n. The first transmission gate Tg1 can also be connected to the third clock terminal CBn and the fourth clock terminal CK, respectively. That is, the input terminal of the first NOT gate INV1 can be connected to the first intermediate node Q1_n, the output terminal of the first NOT gate INV1 can be connected to one end of the first transmission gate Tg1, and the other end of the first transmission gate Tg1 can be connected to the input node Q_n. It is understood that a NOT gate can also be called an inverter, and a transmission gate can also be called a transmission switch.

Optionally, referring to Figures 12 to 19, the input control circuit 01 may include a second transmission gate Tg2, which can be connected between the input terminal IN_n and the input node Q_n, and can also be connected to the first clock terminal CKn and the second clock terminal CB respectively.

In the circuit structures shown in Figures 12 to 16, the first clock terminal CKn and the fourth clock terminal CK are shared, both being the fourth clock terminal CK; the second clock terminal CB and the third clock terminal CBn are shared, both being the second clock terminal CB. In the structures shown in Figures 17 to 19, the first clock terminal CKn, the second clock terminal CB, the third clock terminal CBn, and the fourth clock terminal CK are independent of each other.

Optionally, referring to Figures 12 to 19, it can be seen that in the first output control sub-circuit 021 and the second output control sub-circuit 022, the circuit connected to the enable terminal EN or the reset control terminal Trst may include a NOR gate or a NAND gate, and the circuit not connected to the enable terminal EN and not connected to the reset control terminal Trst includes a second NOT gate INV2.

Furthermore, when the first output control sub-circuit 021 is connected to the reset control terminal Trst, and the second output control sub-circuit 022 is not connected to the reset control terminal Trst, it can also be seen from Figure 18 that the first NOT gate INV1 included in the latch circuit 04 and the second NOT gate INV2 included in the second output control sub-circuit 022 can be shared. In this way, the structure can be simplified and costs can be saved.

It is understandable that the logic principle of a NOR gate is: all 0s output 1, and any 1 outputs 0; that is, when all received signals are at a low potential (0), the output signal can be controlled to be at a high potential (1); otherwise, as long as any received signal is at a high potential (1), the output signal is controlled to be at a low potential (0). The logic principle of a NAND gate is: all 1s output 0, and any 0 outputs 1; that is, when all received signals are at a high potential (1), the output signal can be controlled to be at a low potential (0); otherwise, as long as any received signal is at a low potential (0), the output signal is controlled to be at a high potential (1). Different gate circuits correspond to different control methods; the examples listed above all use the NOR gate as an example.

For example, referring to Figures 12 and 13, the first output control sub-circuit 021 shown includes a second NOT gate INV2-1, and the first output control unit 0221 in the second output control sub-circuit 022 includes another second NOT gate INV2-2. The second output control unit 0222 includes a NOR gate. The difference is that the NOR gate in Figure 12 is a two-input NOR gate, while the NOR gate in Figure 13 is a three-input NOR gate. The input of the second NOT gate INV2-1 is connected to the input node Q_n, and the output of the second NOT gate INV2-1 is connected to the first intermediate node Q1_n. The input of the second NOT gate INV2-2 is connected to the first intermediate node Q1_n, and the output of the second NOT gate INV2-2 is connected to the second intermediate node Q2_n. The two inputs of the NOR gate in Figure 12 are connected to the second intermediate node Q2_n and the enable terminal EN, respectively. In Figure 13, the three inputs of the NOR gate are connected to the second intermediate node Q2_n, the enable terminal EN, and the reset control terminal Trst, respectively. The NOR gate is indirectly connected to the enable terminal EN via the switch control circuit 03. Furthermore, in Figures 12 and 13, the outputs of the NOR gates are indirectly connected to the first output terminal OUTN_n via the first drive enhancement circuit 051, and indirectly connected to the second output terminal OUTP_n via the second drive enhancement circuit 052.

For example, referring to Figure 14, the first output control sub-circuit 021 shown includes a second NOT gate INV2-1, and the first output control unit 0221 in the second output control sub-circuit 022 includes another second NOT gate INV2-2. The second output control unit 0222 includes a NAND gate, and the NAND gate is a three-input NAND gate. The input terminal of the second NOT gate INV2-1 is connected to the input node Q_n, and the output terminal of the second NOT gate INV2-1 is connected to the first intermediate node Q1_n. The input terminal of the second NOT gate INV2-2 is connected to the first intermediate node Q1_n, and the output terminal of the second NOT gate INV2-2 is connected to the second intermediate node Q2_n. The three input terminals of the NAND gate are respectively connected to the second intermediate node Q2_n, the enable terminal EN, and the reset control terminal Trst, and the NAND gate is indirectly connected to the enable terminal EN through the switch control circuit 03. The output terminal of the NAND gate is indirectly connected to the first output terminal OUTN_n through the first driver enhancement circuit 051, and indirectly connected to the second output terminal OUTP_n through the second driver enhancement circuit 052.

For example, referring to Figure 15, the first output control sub-circuit 021 shown includes a second NOT gate INV2. The first output control unit 0221 in the second output control sub-circuit 022 includes a NAND gate, and the second output control unit 0222 includes a NOR gate. The NAND gate is a two-input NAND gate, and the NOR gate is a two-input NOR gate. The input terminal of the second NOT gate INV2 is connected to the input node Q_n, and the output terminal of the second NOT gate INV2 is connected to the first intermediate node Q1_n. The two input terminals of the NAND gate are respectively connected to the first intermediate node Q1_n and the reset control terminal Trst. The NAND gate's output is connected to the second intermediate node Q2_n. The two inputs of the NOR gate are connected to the second intermediate node Q2_n and the enable terminal EN, respectively. The NOR gate is indirectly connected to the enable terminal EN via the switch control circuit 03. The output of the NOR gate is indirectly connected to the first output terminal OUTN_n via the first drive enhancement circuit 051, and indirectly connected to the second output terminal OUTP_n via the second drive enhancement circuit 052.

For example, referring to Figure 16, the first output control sub-circuit 021 shown includes a second NOT gate INV2. The first output control unit 0221 in the second output control sub-circuit 022 includes a NOR gate, and the second output control unit 0222 includes a NAND gate. The NOR gate is a two-input NOR gate, and the NAND gate is a two-input NAND gate. The input terminal of the second NOT gate INV2 is connected to the input node Q_n, and the output terminal of the second NOT gate INV2 is connected to the first intermediate node Q1_n. The two input terminals of the NOR gate are connected to the first intermediate node Q1_n and the reset control terminal Trst, respectively, and the output terminal of the NOR gate is connected to the second intermediate node Q2_n. The two input terminals of the NAND gate are connected to the second intermediate node Q2_n and the enable terminal EN, respectively. The NAND gate is indirectly connected to the enable terminal EN through the switch control circuit 03. The output terminal of the NAND gate is indirectly connected to the first output terminal OUTN_n through the first drive enhancement circuit 051, and indirectly connected to the second output terminal OUTP_n through the second drive enhancement circuit 052.

For example, referring to Figures 17 and 18, the first output control sub-circuit 021 shown includes a NOR-1 NOR gate, and the first output control unit 0221 in the second output control sub-circuit 022 includes a second NOT gate INV2, and the second output control unit 0222 includes another NOR-2 NOR gate. Both NOR-1 and NOR-2 are two-input NOR gates. The two inputs of NOR-1 are connected to the input node Q_n and the reset control terminal Trst, respectively, and the output is connected to the first intermediate node Q1_n. The input of the second NOT gate INV2 is connected to the first intermediate node Q1_n, and the output is connected to the second intermediate node Q2_n. The two inputs of NOR-2 are connected to the second intermediate node Q2_n and the enable terminal EN, respectively, and NOR-2 is indirectly connected to the enable terminal EN through the switch control circuit 03. The difference lies in the following: In Figure 17, the output of the NOR-2 gate is connected to the first output OUTN_n via the driver enhancement circuit 05. In Figure 18, the output of the NOR-2 gate is connected to the second output OUTP_n via the driver enhancement circuit 05. Also, in Figure 17, the second NOT gate INV2 and the first NOT gate INV1 are independent of each other. In Figure 18, the second NOT gate INV2 and the first NOT gate INV1 are shared.

For example, referring to Figure 19, the first output control sub-circuit 021 shown includes a NOR gate. The second output control sub-circuit 022 includes a NAND gate, a NOR gate (two-input NOR gate), and a NAND gate (two-input NAND gate). The two inputs of the NOR gate are connected to the input node Q_n and the reset control terminal Trst, respectively, and the output of the NOR gate is connected to the first intermediate node Q1_n. The two inputs of the NAND gate are connected to the first intermediate node Q1_n and the enable terminal EN, respectively. The NAND gate is indirectly connected to the enable terminal EN via a switch control circuit 03, and the output of the NAND gate is indirectly connected to the first output terminal OUTN_n via a drive enhancement circuit 05. It should be noted that in this structure, the second intermediate node Q2_n (i.e., node NPc_n) is the connection node between the first NOT gate INV1 and the first transmission gate Tg1.

Optionally, referring to Figures 12 to 19, the drive enhancement circuit 05 may include at least one third NOT gate INV3 connected in series between the output control circuit 02 and the output terminal OUT_n. When the drive enhancement circuit 05 includes multiple third NOT gates INV3, these gates can be connected in series sequentially between the output control circuit 02 and the output terminal OUT_n. That is, the input terminal of the first third NOT gate INV3 is connected to the output control circuit 02, the input terminals of the other third NOT gates INV3 are connected to the output terminal of the preceding third NOT gate INV3, and the output terminal of the last third NOT gate INV3 is connected to the output terminal OUT_n.

For example, taking the structure shown in Figure 11 as an example, and referring to Figures 12 to 16, it can be seen that the first drive enhancement sub-circuit 051 connected to the first output terminal OUTN_n may include an even number of third NOT gates INV3 connected in series, used to invert the potential of the output signal of the output control circuit 02 an even number of times before outputting it to the first output terminal OUTN_n. Similarly, the second drive enhancement sub-circuit 052 connected to the second output terminal OUTP_n may include an odd number of third NOT gates INV3 connected in series, used to invert the potential of the output signal of the output control circuit 02 an odd number of times before outputting it to the second output terminal OUTP_n.

Optionally, in some embodiments, the first drive enhancement sub-circuit 051 and the second drive enhancement sub-circuit 052 may share at least one third NOT gate INV3. This simplifies the structure and saves costs.

For example, referring to Figures 12 to 16, it can be seen that the first drive enhancement sub-circuit 051 shown therein includes two third NOT gates INV3-1 and INV3-2, and the second drive enhancement sub-circuit 052 includes three third NOT gates INV3-1, INV3-3 and INV3-4. That is, the first drive enhancement sub-circuit 051 and the second drive enhancement sub-circuit 052 share the third NOT gate INV3-1.

It is understandable that by setting the drive enhancement circuit 05 to include multiple series-connected third NOT gates INV3, the driving capability of the output signal through the output terminal OUT_n can be amplified step by step, thus enhancing the driving capability.

Optionally, referring further to Figures 12 to 19, the switch control circuit 03 may include: to There are two missing third transmission gates, Tg3.

Furthermore, at least two third transmission gates Tg3 can be connected in series between the enable terminal EN and the output control circuit 02, and are also connected to at least two first control terminals Con11 and Con12, and at least two second control terminals Con21 and Con22 respectively, and each third transmission gate Tg3 can be connected to a first control terminal and a second control terminal respectively.

For example, referring to Figures 12 and 19, the switch control circuit 03 shown includes two third transmission gates, Tg3-1 and Tg3-2. Specifically, the third transmission gate Tg3-1 is connected to the corresponding first control terminal Con11 and the second control terminal Con21. The first control terminal Con11 is connected to the second intermediate node Q2_n-1 (i.e., NPc_n-1) of the cascaded previous-stage shift register unit, and the second control terminal Con21 is connected to the first intermediate node Q1_n-1 (i.e., NNc_n-1) of the cascaded previous-stage shift register unit. The third transmission gate Tg3-2 is connected to the corresponding first control terminal Con12 and the second control terminal Con22. The first control terminal Con12 is connected to the first intermediate node Q1_n (i.e., NNc_n) of the shift register unit, and the second control terminal Con22 is connected to the second intermediate node Q2_n (i.e., NPc_n) of the shift register unit. Based on this, it can be seen that for the third transmission gates Tg3-1 and Tg3-2, in the current first-stage shift register unit, the potential of the stage transmission signal provided by NPc_n-1 is low, and the potential of the stage transmission signal provided by NNc_n-1 is high. Furthermore, in the current stage shift register unit, the potential of the signal provided by NNc_n is low, and the potential of the signal provided by NPc_n is high. Only then can both third transmission gates Tg3-1 and Tg3-2 be turned on, allowing the enable terminal EN to be connected to the output control circuit 02. For example, it can be connected to the two-input NAND gate shown in Figure 19.

Optionally, based on the structures shown in Figures 12 to 19, by setting the pulse width of the low potential 0 of the clock signal provided by the clock terminal CK and the clock signal provided by the clock terminal CB to be about 0 to 2 μs smaller than 1H, the risk of competition between the gate circuit in the first output control sub-circuit 021 and the first NOT gate INV1 in the latch circuit 04 can be avoided, which would otherwise occur when the first transmission gate Tg1 and the second transmission gate Tg2 are turned on simultaneously.

That is, the embodiments of this application can provide shift register units in the following various embodiments:

Example 1, referring to Figure 12, the shift register unit may include four transmission gates (i.e., one first transmission gate Tg1, one second transmission gate Tg2, and two third transmission gates Tg3-1 and Tg3-2), one NOR gate, and seven NOT gates (i.e., one first NOT gate INV1, two second NOT gates INV2-1 and INV2-2, and four third NOT gates INV3-1, INV3-2, INV3-3, and INV3-4), totaling 12 gate circuits. Among them, the third NOT gates INV3-1 and INV3-2 belong to the first driver enhancement sub-circuit 051, and are connected to the first... The output terminal OUTN_n is connected; the third NOT gates INV3-1, INV3-3, and INV3-4 belong to the second driver enhancement sub-circuit 052 and are connected to the second output terminal OUTP_n. That is, the output terminal OUT_n can include the first output terminal OUTN_n and the second output terminal OUTP_n.

The pulse width output by this shift register unit is adjustable. During normal output or in the high refresh rate region, the enable signal provided by the low enable terminal EN can be set to a low level, ensuring normal output of the display drive signal. During reset (e.g., when the display panel is powered on, powered off, or during the Porch period) or in the low refresh rate region, the enable signal provided by the high enable terminal EN can be set to a high level, making the levels of the first output terminal OUTN_n and the second output terminal OUTP_n both invalid, thus achieving output reset but not resetting the stage transmission signal.

It is understood that the setting of the enable signal to match the clock signals provided by the clock terminals CK and CB is based on a 2H cycle as an example. In some other embodiments, in other cycle scenarios, the enable signal can be matched with clock signals provided by more clock terminals.

Example 2, referring to Figure 13, the shift register unit may include four transmission gates (i.e., one first transmission gate Tg1, one second transmission gate Tg2, and two third transmission gates Tg3-1 and Tg3-2), one NOR gate, and seven NOT gates (i.e., one first NOT gate INV1, two second NOT gates INV2-1 and INV2-2, and four third NOT gates INV3-1, INV3-2, INV3-3, and INV3-4), for a total of 12 gate circuits. The difference from Example 1 shown in Figure 12 is the addition of a reset control terminal Trst, and the corresponding change from a two-input NOR gate to a three-input NOR gate.

Understandably, based on the preceding description, this structure allows for output reset by setting the reset control signal provided by the reset control terminal Trst to a high potential during power-on, power-off, or Porch periods of the display panel. This controls the potentials of the first output terminal OUTN_n and the second output terminal OUTP_n to be invalid, thus achieving output reset. This can be achieved by globally resetting the output signals of all shift register units. This improves the reliability of power-on and power-off operations.

Example 3, referring to Figure 14, the shift register unit may include four transmission gates (i.e., one first transmission gate Tg1, one second transmission gate Tg2, and two third transmission gates Tg3-1 and Tg3-2), one NAND gate, and seven NOT gates (i.e., one first NOT gate INV1, two second NOT gates INV2-1 and INV2-2, and four third NOT gates INV3-1, INV3-2, INV3-3, and INV3-4), for a total of 12 gate circuits. The difference from Example 2 shown in Figure 13 is that the three-input NOR gate is replaced with a three-input NAND gate. Based on this structure and the logic operation method, the difference in driving method compared to the structure shown in Figure 13 is that a reset can be set during power-on, power-off, or Porch periods of the display panel. The reset control signal provided by the control terminal Trst is at a low potential, so that the potentials of the first output terminal OUTN_n and the second output terminal OUTP_n are both invalid potentials, thereby achieving output reset and improving the reliability of power on/off.

Example 4, referring to Figure 15, the shift register unit may include four transmission gates (i.e., one first transmission gate Tg1, one second transmission gate Tg2, and two third transmission gates Tg3-1 and Tg3-2), one NOR gate, one NAND gate, and six NOT gates (i.e., one first NOT gate INV1, one second NOT gate INV2, and four third NOT gates INV3-1, INV3-2, INV3-3, and INV3-4), for a total of 12 gate circuits. The difference from Example 1 shown in Figure 12 is that the second NOT gate INV2-2 is replaced with a two-input NAND gate, and a reset control terminal Trst is added and connected to the NAND gate.

Understandably, based on the above description, this structure allows for output reset by setting the reset control signal provided by the reset control terminal Trst to a low potential during power-on, power-off, or Porch periods on the display panel. This controls the potentials of the first output terminal OUTN_n and the second output terminal OUTP_n to be invalid, thereby improving the reliability of power-on and power-off.

Example 5, referring to Figure 16, the shift register unit may include four transmission gates (i.e., one first transmission gate Tg1, one second transmission gate Tg2, and two third transmission gates Tg3-1 and Tg3-2), one NOR gate, one NAND gate, and six NOT gates (i.e., one first NOT gate INV1, one second NOT gate INV2, and four third NOT gates INV3-1, INV3-2, INV3-3, and INV3-4), totaling 12 gate circuits. The difference from Example 4 shown in Figure 15 is that the NAND gate and the NOR gate are swapped. Based on this structure and the logical operation method, the difference in driving method compared to the structure shown in Figure 15 is that, during power-on, power-off, or Porch periods of the display panel, the potential of the reset control signal provided by the reset control terminal Trst is set to a high potential to control the potentials of the first output terminal OUTN_n and the second output terminal OUTP_n to be invalid potentials, thereby achieving output reset and improving the reliability of power-on and power-off.

Example 6, referring to Figure 17, the shift register unit may include four transmission gates (i.e., one first transmission gate Tg1, one second transmission gate Tg2, and two third transmission gates Tg3-1 and Tg3-2), two NOR gates (i.e., NOR-1 and NOR-2), and four NOT gates (i.e., one first NOT gate INV1, one second NOT gate INV2, and two third NOT gates INV3-1 and INV3-2), for a total of 10 gate circuits. The difference from Example 1 in Figure 12 is that the second NOT gate INV2-1 is replaced with a NOR gate NOR-1, and this NOR gate NOR-1 is connected to the reset control terminal Trst. Furthermore, only the drive enhancement circuit 05 is connected to the first output terminal OUTN_n, and four sets of clock signals are used.

Example 7, referring to Figure 18, the shift register unit may include four transmission gates (i.e., one first transmission gate Tg1, one second transmission gate Tg2, and two third transmission gates Tg3-1 and Tg3-2), two NOR gates (i.e., NOR-1 and NOR-2), and four NOT gates (i.e., one first NOT gate INV1, and three third NOT gates INV3-1, INV3-2, and INV3-3), for a total of 10 gate circuits. The difference from Example 6 in Figure 17 is that the first NOT gate INV1 and the second NOT gate INV2 are shared, and only the driver enhancement circuit 05 is connected to the second output terminal OUTP_n.

Example 8, referring to Figure 19, the shift register unit may include four transmission gates (i.e., one first transmission gate Tg1, one second transmission gate Tg2, and two third transmission gates Tg3-1 and Tg3-2), one NOR gate, one NAND gate, and four NOT gates (i.e., one first NOT gate INV1, and three third NOT gates INV3-1, INV3-2, and INV3-3), for a total of 10 gate circuits. The difference from Example 6 in Figure 17 is that the second NOT gate INV2 is deleted, and the NOR gate NOR-2 is replaced with the NAND gate, and only the driver enhancement circuit 05 is connected to the second output terminal OUTP_n.

It is understood that the above descriptions of various embodiments are merely illustrative, and any combination of gate circuits that satisfies the above control method can be applied to the embodiments of this application. For example, the input terminal IN_n can also be connected to the first intermediate node Q1_n-1 (i.e., NNc_n-1) of the previous stage shift register unit. As another example, in Figures 12 and 13, the NOR gate can also be moved to the second NOT gate INV2.

Optionally, the shift register unit provided in this application embodiment can be the structure shown in FIG19. That is, the input control circuit 01 may include: a second transmission gate Tg2; the output control circuit 02 may include a first output control sub-circuit 021 and a second output control sub-circuit 022, and the first output control sub-circuit 021 may include: a two-input NOR gate, and the second output control sub-circuit 022 may include: a two-input NAND gate; the switch control circuit 03 may include: two third transmission gates Tg3-1 and Tg3-2; the shift register unit may also include: a latch circuit 04 and a drive enhancement circuit 05, and the latch circuit 04 may include: a first NOT gate INV1 and a first transmission gate Tg1, and the drive enhancement circuit 05 may include: three third NOT gates INV3-1, INV3-2 and INV3-3.

The second transmission gate Tg2 can be connected between the input terminal IN_n and the input node Q_n of the shift register unit, and can also be connected to the first clock terminal CKn and the second clock terminal CB respectively.

The two inputs of the two-input NOR gate can be connected to the input node Q_n and the reset control terminal Trst, respectively, and the output of the two-input NOR gate can be connected to the first intermediate node Q1_n.

One input of the two-input NAND gate NAND can be connected to the first intermediate node Q1_n, and the other input of the two-input NAND gate NAND can be connected to the first intermediate node Q1_n through two third transmission gates Tg3-1 and Tg3-2. With the EN terminal connected, the output of the two-input NAND gate can be connected to the output of the shift register unit OUT_n through three third NOT gates INV3-1, INV3-2, and INV3-3. Furthermore, the two third transmission gates Tg3-1 and Tg3-2 can be connected in series. Additionally, of the two third transmission gates Tg3-1 and Tg3-2, one Tg3-1 can be connected to the second intermediate node Q2_n-1 and the first intermediate node Q1_n-1 of the preceding cascaded shift register unit, respectively. The other third transmission gate Tg3-2 can be connected to the first intermediate node Q1_n and the second intermediate node Q2_n of the shift register unit, respectively.

The input of the first NOT gate INV1 can be connected to the first intermediate node Q1_n of the shift register unit. The output of the first NOT gate INV1 can be connected to the input node Q_n through the first transmission gate Tg1. The first transmission gate Tg1 can also be connected to the third clock terminal CBn and the fourth clock terminal CK respectively.

Furthermore, the output terminal OUT_n of the shift register unit can be connected to an N-type transistor in a pixel. For example, referring to Figure 2, it can be connected to the gate signal terminal Gate_N connected to the N-type transistor T2.

Optionally, based on Figures 15, 18, and 19, Figures 20 to 22 also show schematic diagrams of the transistor TFT structure of the shift register unit. Taking the structure in Figure 15 as an example, referring to Figure 20, it can be seen that the circuit structure shown in Figure 15 can include 14 PMOS TFTs and 14 NMOS TFTs, for a total of 28 TFTs. The connection relationship is shown in Figure 20 and will not be repeated. The circuit structures of other shift register units can be derived from this, and can be formed by combining and reducing basic modules, which will not be described in detail.

Optionally, referring to Figures 20 to 22, it can also be seen that each of the plurality of third NOT gates INV3 can be connected to the first power supply terminal VGH and the second power supply terminal VGL respectively, and can be used to operate based on the first power supply signal provided by the first power supply terminal VGH and the second power supply signal VGL provided by the second power supply terminal. The potential of the first power supply signal can be greater than the potential of the second power supply signal.

Furthermore, among the multiple third NOT gates INV3, the potential of the first power supply signal provided by the first power supply terminal VGH connected to the last third NOT gate INV3 can be greater than or equal to the potential of the first power supply signal provided by the first power supply terminal VGH connected to the other third NOT gates INV3.

The potential of the second power supply signal provided by the second power supply terminal VGL connected to the last third NOT gate INV3 can be less than or equal to the potential of the second power supply signal provided by the second power supply terminal VGL connected to the other third NOT gates INV3.

Among them, the last third NOT gate INV3 is the third NOT gate INV3 connected to the output terminal OUT among multiple third NOT gates INV3.

To distinguish them, the first power supply terminal VGH connected to the last third NOT gate INV3 in the diagram is labeled as... VGH2, the first power supply terminal VGH to which the other third NOT gate INV3 is connected is identified as VGH1; similarly, the second power supply terminal VGL to which the last third NOT gate INV3 is connected is identified as VGL2, and the second power supply terminal VGL to which the other third NOT gate INV3 is connected is identified as VGL1. Furthermore, the first NOT gate INV1 and the second NOT gate INV2, etc., can also be connected to the first power supply terminal VGH1 and the second power supply terminal VGL1 respectively, to operate based on the first power supply signal and the second power supply signal.

That is, in one embodiment, dual VGH and dual VGL power supply can be used. Alternatively, in another embodiment, single VGH and single VGL power supply can be used, that is, any NOT gate in the shift register unit is connected to the same first power supply terminal VGH and second power supply terminal VGL.

Taking the structure shown in Figure 20 as an example, generally, the larger the channel width of the transistor, the closer the threshold voltage Vth of the transistor is to 0. Thus, for the last third NOT gate INV3 directly connected to the output terminal OUT, and for the third NOT gate INV3-4 connected to the second output terminal OUTP_n, taking the second power supply terminal VGL as an example:

To control the second output terminal OUTP_n to a high potential, the PMOS TFT in the third NOT gate INV3-4 needs to be turned on and the NMOS TFT turned off. This will enable the first power supply terminal VGH2 connected to the third NOT gate INV3-4 to conduct with the second output terminal OUTP_n, outputting a high-potential first power supply signal to the second output terminal OUTP_n. Conversely, to enable the PMOS TFT in the third NOT gate INV3-4, the preceding third NOT gate INV3-3 needs to control the second power supply terminal VGL1 to conduct with the third NOT gate INV3-4, outputting a low-potential second power supply signal to the third NOT gate INV3-4. Furthermore, to enable the third NOT gate INV3-3 to control the second power supply terminal VGL1 to conduct with the third NOT gate INV3-4, the NMOS TFT in the third NOT gate INV3-3 needs to be turned on, and the PMOS TFT in the third NOT gate INV3-3 needs to be turned off. Therefore, for the NMOS TFT in the third NOT gate INV3-4, its gate-source voltage difference Vgs should be equal to the difference between the potential Vgl1 of the second power supply signal provided by the second power supply terminal VGL1 and the potential Vgl2 of the second power supply signal provided by the second power supply terminal VGL2. That is, Vgs = Vgl1 - Vgl2. Furthermore, if it is necessary to ensure that the NMOS TFT in the third NOT gate INV3-4 is reliably turned off, it is necessary to control the gate-source voltage difference Vgs of the NMOS TFT to be less than the threshold voltage Vth, that is, Vgs < Vth must be satisfied. Since Vgs = Vgl1 - Vgl2, it can be seen that Vgl1 - Vgl2 < Vth must be satisfied. Based on this, when using dual VGL power supply, the potential Vgl2 of the second power signal provided by the second power supply terminal VGL2 can be lowered, or the potential Vgl1 of the second power signal provided by the second power supply terminal VGL1 can be raised, so that Vgl1 - Vgl2 < Vth. This ensures that the NMOS TFT in the third NOT gate INV3-4 can be completely turned off, allowing the shift register unit to reliably control the potential of the second output terminal OUTP_n to be high. In other words, the absolute value of the potential Vgl2 of the second power signal provided by the second power supply terminal VGL2 can be set relative to the potential provided by the second power supply terminal VGL1. The absolute value of the potential Vgl1 of the second power supply signal is smaller. For example, the potential Vgl2 of the second power supply signal provided by the second power supply terminal VGL2 can be -5V, and the potential Vgl1 of the second power supply signal provided by the second power supply terminal VGL1 can be -7V.

The same applies to the first power supply terminal VGH. For example, taking the third NOT gate INV3-4 connected to the second output terminal OUTP_n in Figure 20 as an example, when using dual VGL power supply, the potential Vgh1 of the first power signal provided by the first power supply terminal VGH1 can be lowered, or the potential Vgh2 of the first power signal provided by the first power supply terminal VGH2 can be raised, so that Vgh1-Vgh2<Vth. This ensures that the PMOS TFT in the third NOT gate INV3-4 can be completely turned off, with only the NMOS TFT conducting, making the second power supply terminal VGL2 and the second output terminal OUTP_n conduct, and outputting a low-potential second power signal to the second output terminal OUTP_n. That is, it enables the shift register unit to reliably control the potential of the second output terminal OUTP_n to be low.

Furthermore, by employing dual VGH and dual VGL power supplies, the charging and discharging speed of the third NOT gate INV3, which is directly connected to the output terminal OUT_n, can be accelerated, thereby further enhancing the driving capability of the shift register unit and reducing leakage current and saving power consumption.

Of course, in some other embodiments, the power supply is not limited to dual VGH and dual VGL. For example, referring to Figure 20, the third NOT gate INV3-2 connected to the first input terminal OUTN_n can also be connected to the first power supply terminal VGH3 and the second power supply terminal VGL3 respectively, that is, a three-VGH and three-VGL power supply can be used.

Optionally, the potential of the first power signal provided by the first power terminal VGH3 can be the same as the potential of the first power signal provided by the first power terminal VGH2 or the first power terminal VGH1; or, the potential of the first power signal provided by the first power terminal VGH3 can be different from the potentials of the first power signals provided by the first power terminals VGH2 and VGH1, that is, the first power terminals VGH3, VGH2, and VGH1 can be independent of each other. Similarly, the potential of the second power signal provided by the second power terminal VGL3 can be the same as the potential of the second power signal provided by the second power terminal VGL2 or the second power terminal VGL1; or, the potential of the second power signal provided by the second power terminal VGL3 can be different from the potentials of the second power signals provided by the second power terminals VGL2 and VGL1, that is, the second power terminals VGL3, VGL2, and VGL1 can be independent of each other.

It is understandable that, based on the premise that the first power supply terminals VGH3 and VGH2 are independent of each other, and the second power supply terminals VGL3 and VGL2 are independent of each other, it can be considered that the third NOT gate INV3 connected to the first output terminal OUTN_n and the third NOT gate INV3 connected to the second output terminal OUTP_n are respectively connected to different first power supply terminals VGH and different second power supply terminals VGL.

Optionally, as can be seen from the foregoing description, in some embodiments, as shown in FIG23, this application The shift register unit provided in the embodiment can actually be divided into three modules: input shift module, transmission and control module, and driver enhancement module.

For example, taking the structure shown in Figure 6 as an example, the input shift module can refer to a module composed of circuits that control the potential of the first intermediate node Q1_n based on the input signal provided by the input terminal IN_n; the transmission and control module can refer to a module composed of circuits that control the potential received by one end of the drive enhancement circuit 05 based on the potential of the first intermediate node Q1_n; the drive enhancement module can refer to the drive enhancement circuit 05. Furthermore, the shift register unit can be connected to at least the following signal terminals: VGH, VGL, CK, CB, NPc_n-1, NNc_n-1, Trst, EN, NPc_n, NNc_n, OUTN_n, and OUTP_n. The connection method is shown in Figure 23 and will not be repeated here.

In summary, this disclosure provides a shift register unit. This shift register unit includes an input control circuit, an output control circuit, and a switch control circuit. The input control circuit controls the connection and disconnection of the input terminal and the input node under the control of clock signals provided by a first clock terminal and a second clock terminal. The output control circuit, based on the potential of the input node and the enable signal provided by the enable terminal, outputs a display driving signal to the pixel through the output terminal to drive the pixel to emit light. The switch control circuit controls the connection and disconnection of the enable terminal and the output control circuit under the control of control signals provided by the first control terminal and the second control terminal. Thus, by flexibly setting the control signal, the enable terminal can be connected to or not connected to the output control circuit. With the enable terminal connected to the output control circuit, the output control circuit can control the potential of the output terminal to output the required driving signal to the pixel to drive the pixel to emit light. Furthermore, by flexibly setting the enable signal and the clock signal, the shift register unit can further output display driving signals to the output terminal that match the P-type transistors and/or N-type transistors in the pixel. Therefore, this shift register unit offers rich driving modes and has low power consumption.

This application also provides a method for driving a shift register unit, which can be used to drive a shift register unit as described above. As shown in Figure 24, the method includes:

Step 2401: In response to the first scan command, provide a first clock signal to the first clock terminal, provide a second clock signal to the second clock terminal, and provide an enable signal of the first potential to the enable terminal.

Step 2402: In response to the second scan command, provide a first clock signal to the first clock terminal, provide a second clock signal to the second clock terminal, and provide an enable signal of the second potential to the enable terminal.

The first and second clock signals are used to drive the input control circuit to control the on/off state of the input terminal and the input node. The enable signal is used to drive the output control circuit based on the potential of the input node and enable signal. The signal controls the potential at the output terminal to output a gate drive signal to the data write transistor in the pixel or a reset signal to the reset transistor in the pixel. Furthermore, the refresh frequency indicated by the first scan command is greater than the refresh frequency indicated by the second scan command. That is, the refresh area indicated by the first scan command can be a high refresh rate area, and the refresh area indicated by the second scan command can be a low refresh rate area.

Optionally, taking the structures shown in Figures 12 to 16 as examples, Figure 25 shows a driving timing diagram of a shift register unit. Based on the structure shown in Figure 20, Figure 26 also schematically shows a signal simulation diagram. Figures 25 and 26 both show a set of inverted clock signals provided by the clock terminals CK and CB, and a set of output display drive signals NP_n and NN_n. Figure 25 also shows a set of stage transmission signals provided by nodes NPc_n-1 and NNc_n-1 in the previous stage shift register unit, and a set of output stage transmission signals NNp_n and NNc_n. Figure 26 also shows the enable signal provided by the enable signal terminal STV. The timing relationship is shown in the figures and will not be elaborated further. Furthermore, combining Figures 25 and 26, it can be seen that in the stage transmission signals provided by NPc_n-1, the low-level pulse width can be an integer multiple of the clock signal period provided by the clock terminal CK, thereby ensuring the complete output of the display drive signal. Non-integer multiples are generally reduced to integer multiples of the pulse width.

Furthermore, the enable signal provided by the enable terminal EN and the reset control signal provided by the reset control terminal Trst are not shown in Figures 25 and 26. Based on the preceding description, a brief explanation is provided here with reference to the structure shown in Figure 20:

When the display panel is powered on or off, or during porch operations, the reset control signal can be set low to reset the output signal and cascade signal, improving power-on/off reliability. At other times, the reset control signal can be set high. During normal output or in the high refresh rate region, the enable signal can be set low to ensure normal output from the shift register unit. During reset or in the low refresh rate region, the enable signal can be set high to reset the output signal without resetting the cascade signal. Furthermore, the enable signal can be passed step-by-step to the shift register unit. For example, when the preceding stage shift register unit outputs a high-level stage transfer signal to the first intermediate node Q1_n-1 (i.e., NNc_n-1) and a corresponding low-level stage transfer signal to the second intermediate node Q2_n-1 (i.e., NPc_n-1), and the current stage shift register unit outputs a low-level stage transfer signal to the first intermediate node Q1_n (i.e., NNc_n) and a corresponding high-level stage transfer signal to the second intermediate node Q2_n (i.e., NPc_n), the signal is then passed to the current stage shift register unit. This achieves the reset of only the shift register unit at the stage transfer start boundary, without resetting shift register units that have started but not completed the stage transfer. In this way, compared to resetting all outputs, the power consumption can be reduced while meeting the local brush output requirements. It is understood that the driving timing of other structures can be derived from Figure 25 by deletion, and will not be elaborated here.

Optionally, taking the circuit structures shown in Figures 12, 13, and 15, i.e., setting the NOR gate to be connected to the EN enable terminal, Figure 27 shows a partial brush driving timing diagram for one shift register unit. Taking the circuit structures shown in Figures 14 and 16, i.e., setting the NAND gate to be connected to the EN enable terminal, Figure 28 shows a partial brush driving timing diagram for another shift register unit.

Comparing Figures 27 and 28, it can be seen that, with the NOR gate connected to the enable terminal EN, in any low-refresh-rate region (two low-refresh-rate regions and one high-refresh-rate region are schematically shown in the figure), the output can be reset by setting the enable signal provided by the enable terminal EN high, i.e., controlling the enable signal's potential to be high. Conversely, with the NAND gate connected to the enable terminal EN, in any low-refresh-rate region, the output can be reset by setting the enable signal provided by the enable terminal EN low, i.e., controlling the enable signal's potential to be low. Furthermore, referring to Figures 27 and 28, it can be seen that in the high-refresh-rate region, the enable terminal EN can be configured to provide an enable signal with an opposite potential to that in the low-refresh-rate region to control the normal output of the shift register unit.

Alternatively, taking the circuit structures shown in Figures 21 and 22 as examples, Figures 29 and 30 respectively show the driving timing diagrams of another shift register unit, including the timing of A. high refresh region and B. low refresh region.

Referring to Figures 29 and 30, four sets of clock signals are shown. Each clock signal satisfies the descriptions above and will not be repeated here. Furthermore, for the circuit structures shown in Figures 21 and 22, the reset control signal provided by the reset control terminal Trst can be set to a high potential when the display panel is powered on or off. This controls the output terminal NP_n to be at an invalid potential (e.g., a high potential), thereby resetting the output signal.

Furthermore, regarding the structure shown in Figure 21, referring to Figure 29, it can be seen that in the high refresh rate region, the enable signal provided by the low enable terminal EN can be set, i.e., the potential of the enable signal is controlled to be low, so that the potential of the NOR-2 output signal changes with the potential of NPc_n, thus controlling the normal output of the shift register unit. In the low refresh rate region, the enable signal provided by the high enable terminal EN can be set, i.e., the potential of the enable signal is controlled to be high, so that the potential of the NOR-2 output signal can be kept low and does not change with the potential of NPc_n. Therefore, the potential of the output terminal NP_n can be kept high, so that the potential of the display drive signal output to the pixel is invalid, and the corresponding switch in the pixel is not activated. For the structure shown in Figure 22, referring to Figure 30, it can be seen that in the high refresh rate region, the enable signal provided by the high enable terminal EN can be set, that is, the potential of the enable signal is controlled to be high, so that the potential of the NAND gate output signal changes with the potential of NNc_n, thus controlling the normal output of the shift register unit; in the low refresh rate region, the enable signal provided by the low enable terminal EN can be set, that is, the potential of the enable signal is controlled to be low, so that the potential of the NAND gate output signal can be maintained at a high potential and does not change with the potential of NNc_n. However, this allows the output terminal NN_n to remain at a low potential, so that the potential of the display drive signal output to the pixel is invalid, and the corresponding switch in the pixel is not turned on.

Continuing with Figures 21 and 29, the driving principle of the shift register unit is explained as follows:

First, in the first stage t01 of the high refresh rate region, a high-level first clock signal can be provided to the first clock terminal CKn, and a low-level second clock signal can be provided to the second clock terminal CB, causing the second transmission gate Tg2 to conduct. This, in turn, connects the input terminal IN_n to the input node Q_n, allowing the input terminal IN_n (i.e., NPc_n-1) to output an input signal to the input node Q_n, at which point the output input signal's potential can be high. Furthermore, a high-level reset control signal can be provided to the reset control terminal Trst, which, after passing through the NOR-1 gate, controls the potential of node NNc_n to low, and then, after passing through the second NOT gate INV2, controls the potential of node NPc_n to high. Since the potential of node NPc_n-1 is high, it is known that the potential of node NNc_n-1 is low; therefore, transmission gate Tg3-1 is turned off, and the enable terminal EN is disconnected from the NOR-2 gate. Since the potential of node NPc_n is high, a low-potential signal can be output through NOR-2. This low-potential signal, after passing through an odd number of third NOT gates INV3, can make the potential of the output terminal NP_n high. Furthermore, in the first stage t01, a low-potential third clock signal can be provided to the third clock terminal CBn, and a high-potential fourth clock signal can be provided to the fourth clock terminal CK, causing the first transmission gate Tg1 to turn off, thereby disconnecting node NNc_n from the input node Q_n.

It is understandable that, as shown in Figure 29, the pulse width of the low-level clock signal provided by clock terminal CK and clock terminal CB is smaller than the pulse width of the high-level clock signal, generally about 0 to 2 μs less than 1H, which can be flexibly selected according to the load RC. Based on this setting, the influence of clock delay can be eliminated, avoiding the risk of competition between the gate circuit in the first output control sub-circuit 021 (such as the NOR-1 gate shown in Figure 21) and the first NOT gate INV1 in the latch circuit 04 when the input state changes, i.e., when the potential of the input signal provided by input terminal IN_n changes.

Secondly, in the second stage t02 of the high refresh region, a low-level first clock signal can be provided to the first clock terminal CKn, and a high-level second clock signal can be provided to the second clock terminal CB, causing the second transmission gate Tg2 to turn off, thereby disconnecting the input terminal IN_n from the input node Q_n. A high-level third clock signal can be provided to the third clock terminal CBn, and a low-level fourth clock signal can be provided to the fourth clock terminal CK, causing the first transmission gate Tg2 to turn on, thereby turning the node NNc_n on with the input node Q_n, thus latching the potential of the input node Q_n to the high potential of the node NPc_n. In addition, a low-level reset control signal can be provided to the reset control terminal Trst, so after passing through the NOR-1 gate, the node can be controlled. The potential of NNc_n is low, and after passing through the second NOT gate INV2, the potential of node NPc_n can be controlled to be high. Since the potential of node NPc_n-1 is low, it can be known that the potential of node NNc_n-1 is high, so transmission gate Tg3-1 is turned on. Since the potential of node NPc_n is high and the potential of node NNc_n is low, transmission gate Tg3-2 is turned on. Furthermore, the enable terminal EN and the NOR-2 gate can be turned on, and the NOR-2 gate can control the potential of the output signal based on the enable signal provided by the enable terminal EN. At this time, as shown in Figure 29, the potential of the enable signal is low, and since the potential of node NPc_n is high, a low-potential signal can be output through the NOR-2 gate. This low-potential signal, after passing through an odd number of third NOT gates INV3, can make the potential of the output terminal NP_n high.

In the third stage t03, a high-level first clock signal can be provided to the first clock terminal CKn, and a low-level second clock signal can be provided to the second clock terminal CB, causing the second transmission gate Tg2 to conduct. This, in turn, enables the input terminal IN_n to conduct with the input node Q_n, allowing the input terminal IN_n to output an input signal to the input node Q_n. At this time, the potential of the input signal (NPc_n-1) can be low. Furthermore, a low-level reset control signal can be provided to the reset control terminal Trst. This signal, after passing through the NOR-1 gate, controls the potential of node NNc_n to be high, and then, after passing through the second NOT gate INV2, controls the potential of node NPc_n to be low. Since the potential of node NPc_n-1 is low, it is known that the potential of node NNc_n-1 is high, therefore, transmission gate Tg3-1 is turned on. Since the potential of node NPc_n is low and the potential of node NNc_n is high, transmission gate Tg3-2 is turned off. Furthermore, the enable terminal EN can be disconnected from the NOR-2 gate. The enable signal's potential can remain at the low level of the previous stage. Since the potential of node NPc_n is low, a high-level signal can be output through the NOR-2 gate. This high-level signal, after passing through an odd number of third NOT gates INV3, can make the potential of the output terminal NP_n low. In the third stage t03, a low-level third clock signal can be provided to the third clock terminal CBn, and a high-level fourth clock signal can be provided to the fourth clock terminal CK, causing the first transmission gate Tg1 to turn off, thereby disconnecting node NNc_n from the input node Q_n.

The difference lies in the low-brush region. Because the enable signal remains at a high potential, as mentioned earlier, the output signal of the NOR-2 gate can remain at a low potential. Consequently, as shown in Figure 29, this low-potential signal, after passing through an odd number of third NOT gates INV3, can keep the output terminal NP_n at a high potential. The working principles of other stages are illustrated in the timing diagram shown in Figure 29 and will not be elaborated upon here.

Optionally, the shift register unit can also be connected to the display driver IC (DIC) and used to receive the aforementioned signals, such as clock signals, provided by the DIC. That is, the DIC can provide the required signals to the signal terminals connected to the shift register unit, so that the shift register unit can output the signals to the image... The display drive signal required for pixel output.

It is understandable that the driving methods for other shift register units are similar and will not be described in detail here. Furthermore, since the driving methods for shift register units can achieve essentially the same technical effects as those described in the preceding embodiments, for the sake of brevity, the technical effects of the driving methods for shift register units will not be repeated here.

This application also provides a display driver. As shown in FIG31, the display driver includes at least two cascaded shift register units (GOAs) as described above.

For example, the shift register unit GOA shown in Figure 31 provides the gate drive signal shift register unit NGate GOA to the gate signal terminal Gate_N connected to the N-type transistor, that is, the output terminal OUT_n is connected to the gate signal terminal Gate_N of the pixel. Accordingly, the display driver including this NGate GOA can also be called a gate drive circuit. In addition, the display driver shown in Figure 31 uses 4 sets of clock signals (including CK, CB, CKn and CBn, a total of 4 clock signal terminals), and is powered by dual VGH and dual VGL (including the first power supply terminals VGH1 and VGH2, and the second power supply terminals VGL1 and VGL2). The cascading method shown is as follows: the input terminal IN_1 of the first-stage shift register unit NGate GOA is connected to the enable signal terminal STV, and the input terminals of other-stage shift register units NGate GOA (e.g., IN_2, IN_n-1 and IN_n) are connected to the second intermediate node Q2_n (i.e., node NPc_n) of the previous-stage shift register unit NGate GOA. Furthermore, each shift register unit can also be connected to node NNc_n-1 of the previous shift register unit to receive the stage transmission signal provided by node NNc_n-1. This could be achieved by connecting the third transmission gate Tg3-1 of the shift register unit to node NNc_n-1.

It is understandable that, since the potential of node NNc_n is opposite to that of node NPc_n, for the first-stage shift register unit, an inverter F1, also known as a NOT gate, can be added between the enable signal terminal STV and the third transmission gate Tg3-1 to receive a signal with a potential opposite to that of the enable signal. For the design of other structures, please refer to the relevant descriptions of the shift register unit mentioned above; they will not be elaborated upon here.

Optionally, in some embodiments, a dummy shift register unit, i.e., a dummy GOA, may be added to the first or last line to meet the required timing requirements or drive the load.

It is understood that, since the display driver can have essentially the same technical effect as the shift register unit described in the various embodiments above, the technical effect of the display driver will not be repeated here for the sake of brevity.

This application also provides a display device. As shown in FIG32, the display device includes: a display panel 10, and a display driver 00 as shown in FIG31.

Referring to Figure 2, the display panel 10 includes multiple pixels (not shown in Figure 32). The display driver 00 is connected to the multiple pixels, such as to the gate signal terminal Gate_N of the pixel, and is used to transmit gate drive signals or reset signals to the multiple pixels to drive the multiple pixels to emit light.

It is understood that since the display device can have essentially the same technical effect as the shift register unit described in the various embodiments above, the technical effect of the display device will not be described again here for the sake of brevity.

Optionally, the display device can be any product or component with display functionality, such as an OLED display device, an active-matrix organic light-emitting diode (AMOLED) display device, or any other display device. Furthermore, the display device can also be any suitable display device, including but not limited to mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, and e-readers.

It is understood that the terminology used in the embodiments section of this application is for illustrative purposes only and is not intended to limit the application. Unless otherwise defined, the technical or scientific terms used in the implementation of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains.

For example, the use of words like "first," "second," "third," and similar terms does not indicate any order, quantity, or importance, but is merely used to distinguish different components. Similarly, words like "a" or "one" do not indicate a quantity limitation, but rather the presence of at least one. Words like "include" or "contain" mean that the element or object preceding "includes" covers the element or object listed after "includes" or "contains," and does not exclude other elements or objects. Words like "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up," "down," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly. "And/or" indicates that three relationships can exist; for example, A and/or B can represent: A alone, A and B simultaneously, and B alone. The character "/" generally indicates that the preceding and following objects have an "or" relationship.

The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims (25)

A shift register unit, the shift register unit comprising: An input control circuit is connected to a first clock terminal, a second clock terminal, an input terminal, and an input node, respectively, and is used to control the connection and disconnection of the input terminal and the input node in response to a first clock signal provided by the first clock terminal and a second clock signal provided by the second clock terminal. An output control circuit is connected to the input node, the enable terminal, and the output terminal respectively, and is used to control the potential of the output terminal based on the potential of the input node and the enable signal provided by the enable terminal, so as to output a gate drive signal of the data writing transistor in the pixel or output a reset signal to the reset transistor in the pixel through the output terminal, so as to drive the pixel to emit light. A switch control circuit is connected between the enable terminal and the output control circuit, and is also connected to at least two first control terminals and at least two second control terminals respectively, and is used to control the on/off state of the enable terminal and the output control circuit in response to a first control signal provided by each first control terminal and a second control signal provided by each second control terminal. According to claim 1, the shift register unit, wherein the output control circuit comprises: The first output control sub-circuit is connected to the input node and the first intermediate node respectively, and is used to control the potential of the first intermediate node based on the potential of the input node; The second output control sub-circuit is connected to the first intermediate node, the enable terminal, and the output terminal, respectively, and is used to control the potential of the output terminal based on the potential of the first intermediate node and the enable signal. According to claim 2, the shift register unit, wherein the second output control sub-circuit includes: A first output control unit is connected to the first intermediate node and the second intermediate node respectively, and is used to control the potential of the second intermediate node based on the potential of the first intermediate node; The second output control unit is connected to the second intermediate node, the enable terminal, and the output terminal respectively, and is used to control the potential of the output terminal based on the potential of the second intermediate node and the enable signal. According to claim 3, the shift register unit, wherein the first output control unit in the second output control sub-circuit is further connected to the reset control terminal and is further used to control the potential of the second intermediate node based on the reset control signal provided by the reset control terminal. According to claim 3, the shift register unit, wherein the second output control unit in the second output control sub-circuit is further connected to the reset control terminal and is further used to control the potential of the output terminal based on the reset control signal provided by the reset control terminal. According to claim 2, the shift register unit, wherein the first output control sub-circuit is further connected to the reset control terminal and is further used to control the potential of the first intermediate node based on the reset control signal provided by the reset control terminal. According to any one of claims 3 to 6, the shift register unit is wherein the switch control circuit is connected to two first control terminals and two second control terminals respectively, and the two first control terminals and the two second control terminals correspond one-to-one; Furthermore, a first control terminal and a second control terminal, each corresponding to one another, are respectively connected to the second intermediate node and the first intermediate node of the preceding stage shift register unit cascaded with the shift register unit, and another first control terminal and another second control terminal, each corresponding to one another, are respectively connected to the first intermediate node and the second intermediate node of the shift register unit. The shift register unit according to any one of claims 2 to 7, wherein the shift register unit further comprises: The latch circuit is connected to the third clock terminal, the fourth clock terminal, the first intermediate node, and the input node respectively, and is used to control the on/off state of the first intermediate node and the input node in response to the third clock signal provided by the third clock terminal and the fourth clock signal provided by the fourth clock terminal, and outputs the potential of the first intermediate node to the input node after inverting the potential. According to claim 8, the shift register unit is shared by the first clock terminal and the third clock terminal, and by the second clock terminal and the fourth clock terminal. According to claim 8 or 9, the shift register unit, wherein the latch circuit comprises: a first NOT gate and a first transmission gate connected in series between the first intermediate node and the input node, and the first transmission gate is also connected to the third clock terminal and the fourth clock terminal respectively. According to the shift register unit of claim 10, wherein in the first output control sub-circuit and the second output control sub-circuit, the circuit connected to the enable terminal or the reset control terminal includes a NOR gate or a NAND gate, and the circuit not connected to the enable terminal and not connected to the reset control terminal includes a second NOT gate. Furthermore, when the first output control sub-circuit is connected to the reset control terminal and the second output control sub-circuit is not connected to the reset control terminal, the first NOT gate included in the latch circuit is shared with the second NOT gate included in the second output control sub-circuit. The shift register unit according to any one of claims 1 to 11, wherein the shift register unit further comprises: A drive enhancement circuit is connected between the output control circuit and the output terminal, and is used to invert the potential of the output signal of the output control circuit at least once before outputting it to the output terminal. According to claim 12, the shift register unit, wherein the drive enhancement circuit includes at least one third NOT gate connected in series between the output control circuit and the output terminal, and in the case that the drive enhancement circuit includes a plurality of third NOT gates, the plurality of third NOT gates are connected in series between the output control circuit and the output terminal in sequence; Each of the plurality of third NOT gates is also connected to a first power supply terminal and a second power supply terminal respectively, and is used to operate based on a first power supply signal provided by the first power supply terminal and a second power supply signal provided by the second power supply terminal, wherein the potential of the first power supply signal is greater than the potential of the second power supply signal. According to the shift register unit of claim 13, wherein, among the plurality of third NOT gates, the first power signal provided by the first power supply terminal connected to the last third NOT gate is greater than or equal to the first power signal provided by the first power supply terminal connected to the other third NOT gates, and the last third NOT gate is the third NOT gate connected to the output terminal among the plurality of third NOT gates. According to claim 13 or 14, in the plurality of third NOT gates, the second power signal provided by the second power supply terminal connected to the last third NOT gate is less than or equal to the second power signal provided by the second power supply terminals connected to the other third NOT gates, and the last third NOT gate is the third NOT gate connected to the output terminal among the plurality of third NOT gates. The shift register unit according to any one of claims 13 to 15, wherein the output terminal includes: a first output terminal and a second output terminal, and, at the same time period, the potential of the first output terminal is opposite to the potential of the second output terminal; the drive enhancement circuit includes: The first drive enhancement sub-circuit is connected between the output control circuit and the first output terminal, and is used to invert the potential of the output signal of the output control circuit an even number of times and then output it to the first output terminal. The second drive enhancement sub-circuit is connected between the output control circuit and the second output terminal, and is used to invert the potential of the output signal of the output control circuit an odd number of times before outputting it to the second output terminal. According to the shift register unit of claim 16, the first drive enhancement sub-circuit includes an even number of third NOT gates connected in series, the second drive enhancement sub-circuit includes an odd number of third NOT gates connected in series, and the first drive enhancement sub-circuit and the second drive enhancement sub-circuit share at least one third NOT gate. The shift register unit according to any one of claims 1 to 17, wherein the input control circuit includes: a second transmission gate; The second transmission gate is connected between the input terminal and the input node, and is also connected to the first clock terminal and the second clock terminal respectively. The shift register unit according to any one of claims 1 to 18, wherein the switch control circuit comprises: at least two third transmission gates; The at least two third transmission gates are connected in series between the enable terminal and the output control circuit, and are also connected one-to-one with the at least two first control terminals and the at least two second control terminals, respectively. Each of the third transmission gates is connected to a corresponding first control terminal and a second control terminal. The shift register unit according to any one of claims 1 to 19, wherein, when the shift register unit is used to write a transistor output gate drive signal to data in a pixel through the output terminal: The output terminal of the shift register unit is used to connect to the N-type data writing transistor in the pixel, and is used to output a gate drive signal to the N-type data writing transistor through the output terminal; And/or, The output terminal of the shift register unit is used to connect to the P-type data writing transistor in the pixel, and is used to output a gate drive signal to the P-type data writing transistor through the output terminal. The shift register unit according to any one of claims 1 to 19, wherein, when the shift register unit is used to output a reset signal to the reset transistor in the pixel through the output terminal: The output terminal of the shift register unit is used to connect to the N-type reset transistor in the pixel, and is used to output a reset signal to the N-type reset transistor through the output terminal; And/or, The output terminal of the shift register unit is used to connect to the P-type reset transistor in the pixel, and is used to output a reset signal to the P-type reset transistor through the output terminal. The shift register unit according to any one of claims 1 to 21, wherein the input control circuit includes a second transmission gate; the output control circuit includes a first output control sub-circuit and a second output control sub-circuit, wherein the first output control sub-circuit includes a two-input NOR gate, and the second output control sub-circuit includes a two-input NAND gate; the switch control circuit includes two third transmission gates; the shift register unit further includes a latch circuit and a drive enhancement circuit, wherein the latch circuit includes a first NOT gate and a first transmission gate, and the drive enhancement circuit includes three third NOT gates; The second transmission gate is connected between the input terminal of the shift register unit and the input node, and is also connected to the first clock terminal and the second clock terminal respectively. The two input terminals of the two-input NOR gate are respectively connected to the input node and the reset control terminal, and the output terminal of the two-input NOR gate is connected to the first intermediate node. One input terminal of the two-input NAND gate is connected to the first intermediate node, and the other input terminal of the two-input NAND gate is connected to the enable terminal through the two third transmission gates. The output terminal of the two-input NAND gate is connected to the output terminal of the shift register unit through the three third NOT gates. The two third transmission gates are connected in series, and the three third NOT gates are connected in series. Among the two third transmission gates, one third transmission gate is also connected to the second intermediate node and the first intermediate node of the previous stage shift register unit cascaded with the shift register unit, and the other third transmission gate is also connected to the first intermediate node and the second intermediate node of the shift register unit, respectively. The input terminal of the first NOT gate is connected to the first intermediate node of the shift register unit, the output terminal of the first NOT gate is connected to the input node through the first transmission gate, and the first transmission gate is also connected to the third clock terminal and the fourth clock terminal respectively. Furthermore, the output of the shift register unit is used to connect to the N-type transistor in the pixel. A method for driving a shift register unit, used to drive the shift register unit as described in any one of claims 1 to 22; the method includes: In response to the first scan command, a first clock signal is provided to the first clock terminal, a second clock signal is provided to the second clock terminal, and an enable signal of the first potential is provided to the enable terminal; In response to a second scan command, a first clock signal is provided to the first clock terminal, a second clock signal is provided to the second clock terminal, and an enable signal of a second potential is provided to the enable terminal; Wherein, the first clock signal and the second clock signal are used to drive the input control circuit to control the on/off state of the input terminal and the input node; the enable signal is used to drive the output control circuit to control the potential of the output terminal based on the potential of the input node and the enable signal, so as to output a gate drive signal to the data writing transistor in the pixel or output a reset signal to the reset transistor in the pixel through the output terminal, so as to drive the pixel to emit light; and the refresh frequency indicated by the first scan command is greater than the refresh frequency indicated by the second scan command. A display driver comprising: at least two cascaded shift register units as described in any one of claims 1 to 22. A display device, the display device comprising: a display panel, and a display driver as described in claim 24; The display panel includes multiple pixels, and the display driver is connected to the multiple pixels and is used to transmit gate drive signals or reset signals to the multiple pixels to drive the multiple pixels to emit light.