WO2025222978A1 - Power consumption control method, electronic device, storage medium, and program product - Google Patents

Abstract

Embodiments of the present disclosure provide a power consumption control method, an electronic device, a storage medium, and a program product. The power consumption control method comprises: determining the power consumption of a chip at the current moment; and determining a target value of a working parameter of the chip on the basis of the power consumption of the chip at the current moment and a preset power consumption range, so that the power consumption of the chip under the target value of the working parameter is within the preset power consumption range, wherein the working parameter comprises a micro-architecture mode level, and the micro-architecture mode level is used for representing a micro-architecture state of the chip.

Description

Power consumption control methods, electronic devices, storage media, and software products

This disclosure claims priority to Chinese patent application No. 202410508758.X, filed on April 25, 2024, the entire contents of which are incorporated herein by reference.

Technical Field

This disclosure relates to the field of computer technology, and in particular to a power consumption control method, electronic device, storage medium, and program product.

Background Technology

With the significant increase in the integration of chip components (such as central processing unit (CPU), graphics processing unit (GPU), etc.), chip power consumption control has become particularly important.

Common power consumption control methods typically include, but are not limited to, Dynamic Voltage and Frequency Scaling (DVFS) and task migration techniques. DVFS controls power consumption by adjusting the chip's operating frequency and voltage. Task migration controls power consumption by scheduling the workload of each core within the chip.

Summary of the Invention

On the one hand, a power consumption control method is provided. This power consumption control method includes:

Determine the chip's power consumption at the current moment;

Based on the chip's power consumption at the current moment and the preset power consumption range, the target values of the chip's operating parameters are determined so that the chip's power consumption at the target values of the operating parameters is within the preset power consumption range; the operating parameters include the microarchitecture mode level, which is used to represent the chip's microarchitecture state.

On the other hand, a power consumption control device is provided. The power consumption control device includes: a processing unit;

The processing unit is used to determine the chip's power consumption at the current moment;

The processing unit is also used to determine the target value of the chip's operating parameters based on the chip's power consumption at the current moment and the preset power consumption range, so that the chip's power consumption at the target value of the operating parameters is within the preset power consumption range; the operating parameters include the microarchitecture mode level, which is used to represent the chip's microarchitecture state.

In another aspect, an electronic device is provided. This electronic device includes a processor; when the processor executes a computer program, it implements the power consumption control method described above.

In another aspect, a computer-readable storage medium is provided. This computer-readable storage medium includes computer instructions that, when executed, implement the power consumption control method described above.

In another aspect, a computer program product is provided. This computer program product includes a computer program or instructions that, when executed on a computer, implement the power consumption control method described above.

Attached Figure Description

To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are merely drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings.

Figure 1 is a power consumption control system architecture diagram according to some embodiments of the present disclosure.

Figure 2 is a flowchart illustrating a power consumption control method according to some embodiments of the present disclosure.

Figure 3 is a flowchart illustrating another power consumption control method according to some embodiments of the present disclosure.

Figure 4 is a flowchart illustrating another power consumption control method according to some embodiments of the present disclosure.

Figure 5 is a flowchart illustrating another power consumption control method according to some embodiments of the present disclosure.

Figure 6 is a flowchart illustrating another power consumption control method according to some embodiments of the present disclosure.

Figure 7 is a flowchart illustrating another power consumption control method according to some embodiments of the present disclosure.

Figure 8 is a flowchart illustrating another power consumption control method according to some embodiments of the present disclosure.

Figure 9 is a flowchart illustrating another power consumption control method according to some embodiments of the present disclosure.

Figure 10 is a flowchart illustrating another power consumption control method according to some embodiments of the present disclosure.

Figure 11 is a schematic diagram of the structure of an electronic device according to some embodiments of the present disclosure.

Figure 12 is a schematic diagram of the structure of another electronic device according to some embodiments of the present disclosure.

Detailed Implementation

To enable those skilled in the art to better understand the technical solutions of the embodiments of this disclosure, the technical solutions of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

It should be noted that, in this disclosure, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplarily" or "for example" in this disclosure should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the words "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.

In the following text, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with terms such as "first," "second," etc., may explicitly or implicitly include one or more of that feature.

In the description of this disclosure, unless otherwise stated, the symbol “/” means “or”, for example, A/B can mean A or B. The term “and/or” in this document merely represents a description of the relationship between related objects, indicating that three relationships can exist; for example, A and/or B can mean: only A, only B, and A and B. Furthermore, “at least one” means one or more, and “more than one” means two or more.

Before providing a detailed introduction to this disclosure, let me briefly introduce the relevant elements involved in this disclosure.

Microarchitecture: Microarchitecture is a crucial component of a chip, encompassing the pipeline execution mechanisms for various tasks during chip processing, instruction issuance and scheduling mechanisms, on-chip caches, memory management mechanisms, and more. These design elements work together to achieve efficient chip operation.

The power consumption of a chip can be controlled by adjusting the microarchitecture mode level. Different microarchitecture mode levels correspond to different microarchitecture state parameters. The power consumption of the chip differs under different microarchitecture mode levels (i.e., under different microarchitecture state parameters). Therefore, this disclosure allows for power consumption control of the chip by adjusting the microarchitecture mode level.

For example, to reduce chip power consumption, the microarchitecture mode level can be adjusted to a preset level. At the preset level, the chip can adjust at least one of the following microarchitecture state parameters to reduce chip power consumption:

Disabling unnecessary floating-point units and execution units in the chip (also known as reducing chip bandwidth), reducing the chip's memory access rate and/or data transfer rate (also known as reducing the chip's window depth), reducing the chip's number of parallel instructions, instruction scheduling complexity, and out-of-order execution range (also known as weakening the chip's transaction strength).

Next, the application scenarios of this disclosure will be introduced.

With the significant increase in chip component integration, chip power consumption control has become particularly important. By providing real-time, efficient, and reliable power consumption control, chips can better adapt to load changes, effectively solve thermal balance issues, and extend their lifespan.

Currently, various power consumption control technologies are widely used, including but not limited to DVFS technology and task migration technology. DVFS technology achieves power consumption control by adjusting the chip's operating frequency and voltage. However, in the process of power consumption control based on DVFS technology, if the adjustment step size of the operating frequency and voltage is not precise enough, it will cause a loss of system performance. Moreover, frequent adjustments to the operating frequency also greatly reduce the stability of the chip.

Task migration technology achieves power consumption control by scheduling the workload tasks of various cores in a chip; that is, it rationally distributes the workload tasks across all cores, thereby improving the overall utilization of the chip. However, task migration technology has a certain latency, which cannot meet the needs of chips with high real-time requirements.

To address the aforementioned technical problems, this disclosure provides a power consumption control method that can determine the power consumption of a chip at the current moment. Then, based on the chip's power consumption at the current moment and a preset power consumption range, a target value for the chip's operating parameters can be determined, ensuring that the chip's power consumption at the target value of the operating parameters remains within the preset power consumption range.

Operating parameters include the microarchitecture mode level, which represents the microarchitecture state of the chip.

As can be seen from the above, in the power consumption control process, this disclosure can determine the target value of the chip's operating parameters so that the chip's power consumption under the target value of the operating parameters is within a preset power consumption range. The operating parameters include the microarchitecture mode level. Because the adjustment granularity of the microarchitecture mode level is small and there is no need to schedule the load tasks of each core in the chip, this disclosure can ensure chip stability while also meeting the chip's real-time requirements.

Secondly, in common power consumption control methods, frequent adjustments to the chip's operating frequency can significantly reduce chip stability. However, this disclosure improves chip stability by adjusting the microarchitecture mode level, ensuring that the chip's power consumption remains within a preset range at the target operating parameters, without requiring adjustments to the chip's operating frequency.

The power consumption control method provided in this disclosure can be applied to the power consumption control system shown in FIG1. This power consumption control system can be applied to any electronic device requiring power consumption control, and can be used to control the power consumption of chips within the electronic device. As shown in FIG1, the power consumption control system may include a power consumption control module 101 and a configuration distribution module 102. The power consumption control module 101 and the configuration distribution module 102 are connected.

The power consumption control module 101 is used to determine the power consumption of the chip at the current moment, and to determine the target value of the chip's operating parameters based on the chip's power consumption at the current moment and the preset power consumption range.

The configuration sending module 102 can send the target value of the chip's operating parameters to the corresponding unit based on the target value of the chip's operating parameters determined by the power consumption control module 101, so as to complete the power consumption control of the chip.

In some implementations, the aforementioned operating parameters may include microarchitecture mode level and operating frequency. In this case, the power control module 101 may include: a configuration monitoring module 1011, a microarchitecture calculation module 1012, a power consumption calculation module 1013, and a frequency calculation module 1014. The configuration monitoring module 1011 is connected (directly or indirectly) to the microarchitecture calculation module 1012, the power consumption calculation module 1013, and the frequency calculation module 1014, respectively. The power consumption calculation module 1013 is connected to the microarchitecture calculation module 1012 and the frequency calculation module 1014, respectively.

The configuration monitoring module 1011 is used to obtain the chip's operating status parameters at the current moment.

The power consumption calculation module 1013 is used to determine the power consumption of the chip at the current moment based on the chip's operating status parameters obtained by the configuration monitoring module 1011 at the current moment.

The microarchitecture calculation module 1012 is used to determine the target value of the microarchitecture mode level based on the power consumption of the chip at the current moment determined by the power consumption calculation module 1013.

The frequency calculation module 1014 is used to determine the target value of the operating frequency based on the power consumption of the chip at the current moment determined by the power consumption calculation module 1013.

In some implementations, the power control system can also be divided into different subsystems based on different operating parameters. For example, when the operating parameters include microarchitecture mode level and operating frequency, the power control system can include a microarchitecture mode level regulation subsystem and a frequency regulation subsystem.

The microarchitecture pattern hierarchy tuning subsystem is used to determine the target value of the microarchitecture pattern hierarchy.

For example, as shown in FIG1, the configuration monitoring module 1011, power consumption calculation module 1013 and microarchitecture calculation module 1012 can form a microarchitecture mode level adjustment subsystem.

Accordingly, the frequency conditioning subsystem is used to determine the target value of the operating frequency.

For example, as shown in FIG1, the configuration monitoring module 1011, the power consumption calculation module 1013 and the frequency calculation module 1014 can form a frequency regulation subsystem.

It should be noted that the modules in the chip described above are only functional concepts. In practical applications, the modules in the chip can be merged or split to form one or more modules for use, or the modules can be integrated into other modules for use by other modules. This disclosure does not limit this.

It should be noted that the system architecture and application scenarios described in the embodiments of this disclosure are for the purpose of more clearly illustrating the technical solutions of the embodiments of this disclosure, and do not constitute a limitation on the technical solutions provided in the embodiments of this disclosure. As those skilled in the art will know, with the evolution of system architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this disclosure are also applicable to similar technical problems.

For example, the aforementioned power control system can be applied to chips based on the Advanced RISC Machine (ARM) architecture, as well as chips based on the x86 architecture.

The power consumption control method provided in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

The power consumption control method provided in this disclosure can be applied to electronic devices (which may be the electronic device to which the power consumption control system shown in Figure 1 belongs, or an external electronic device to which the power consumption control system shown in Figure 1 belongs) to achieve power consumption control of the chip to which the power consumption control system belongs. That is to say, the execution subject of this disclosure can be applied to the electronic device to which the chip to be power-controlled belongs, or it can be applied to an electronic device that accesses the chip remotely to perform configuration distribution, data acquisition, and functional calculation. This disclosure does not limit this aspect.

Figure 2 shows a flowchart of a power consumption control method. As shown in Figure 2, the power consumption control method includes S201-S202.

S201. The electronic device determines the power consumption of the chip at the current moment.

In some implementations, the aforementioned chip can be any chip in an electronic device that requires power consumption control, such as a CPU chip or a GPU chip.

In some implementations, to control chip power consumption in real time, the electronic device needs to determine the chip's power consumption at the current moment. The chip's power consumption is typically determined by its operating state parameters at that moment. Therefore, the electronic device can obtain the chip's operating state parameters at the current moment and determine its power consumption based on those parameters.

In some implementations, the electronic device can trigger a power control command after the chip is powered on, and in response to the power control command, obtain the chip's operating status parameters at the current moment.

In some implementations, users can also perform power control operations on the device itself via an external module connected to the chip, according to their own needs. The electronic device can respond to the user's operation, trigger a power control command, and obtain the chip's operating status parameters at the current moment in response to the power control command.

In some implementations, the operating status parameters may include at least one of the following: temperature, operating frequency, voltage, microarchitecture status parameters, number of instructions executed within a preset period, and amount of memory data read within a preset period.

In some implementations, the aforementioned microarchitecture state parameters may include at least one of the following: memory access rate, data transfer rate, cache size, number of pending task instructions, and number of parallel task instructions.

For example, the configuration monitoring module in an electronic device can obtain the chip's temperature through the chip's temperature control unit, the chip's operating frequency through the chip's frequency control unit, the chip's voltage through the chip's power control unit, the chip's microarchitecture status parameters through the microarchitecture control unit, and the number of instructions executed and the amount of memory access data read within a preset period through the performance event monitoring unit.

In addition to the operating status parameters listed above, the electronic device may also acquire other unlisted operating status parameters and determine the power consumption of the chip at the current moment based on the operating status parameters. This disclosure does not limit this.

S202. The electronic device determines the target value of the chip's operating parameters based on the chip's power consumption at the current moment and the preset power consumption range, so that the chip's power consumption at the target value of the operating parameters is within the preset power consumption range.

Operating parameters include microarchitecture mode level; the microarchitecture mode level is used to represent the microarchitecture state of the chip.

In some implementations, different system architectures of the chip correspond to different microarchitecture patterns, and the microarchitecture pattern levels of these different patterns may also differ. Correspondingly, the microarchitecture state of the chip differs under different microarchitecture pattern levels.

Understandably, the microarchitectural state of a chip can be reflected through its microarchitectural state parameters. For example, when the microarchitectural state parameter is memory access rate, a higher memory access rate results in higher microarchitectural performance, but also higher power consumption. Conversely, a lower memory access rate results in lower microarchitectural performance, but also lower power consumption.

For example, when the chip's system architecture is ARM, the microarchitecture mode is Performance-Defined Power (PDP) mode. Within PDP mode, different PDP level levels can represent different microarchitecture states of the chip.

For example, PDP mode levels can include: Level 1, Level 2, Level 3, Level 4, and Level 5.

When the chip's PDP mode level is level 1, the chip's memory access rate is A1, data transfer rate is B1, buffer size is C1, number of pending task instructions is D1, and number of parallel task instructions is E1.

When the chip's PDP mode level is level 2, the chip's memory access rate is A2, data transfer rate is B2, buffer size is C2, number of pending task instructions is D2, and number of parallel task instructions is E2.

When the chip's PDP mode level is three, the chip's memory access rate is A3, data transfer rate is B3, buffer size is C3, number of pending task instructions is D3, and number of parallel task instructions is E3.

When the chip's PDP mode level is four, the chip's memory access rate is A4, data transfer rate is B4, buffer size is C4, number of pending task instructions is D4, and number of parallel task instructions is E4.

When the chip's PDP mode level is five, the chip's memory access rate is A5, data transfer rate is B5, buffer size is C5, number of pending task instructions is D5, and number of parallel task instructions is E5.

A5<A4<A3<A2<A1, B5<B4<B3<B2<B1, C5<C4<C3<C2<C1, D5<D4<D3<D2<D1, E5<E4<E3<E2<E1.

In other words, in PDP mode, the chip's microarchitecture mode level is inversely proportional to its power consumption. A higher PDP mode level results in lower microarchitecture state parameters and thus lower power consumption. Conversely, a lower PDP mode level results in higher microarchitecture state parameters and thus higher power consumption.

As another example, when the chip's system architecture is x86, the microarchitecture mode is core hibernation mode. In core hibernation mode, the microarchitecture mode levels can include: level 1, level 2, and level 3.

When the chip's core sleep mode level is level one, all of the chip's cores are working.

When the chip's core sleep mode level is level 2, some cores of the chip are working while others are in sleep mode.

When the chip's core sleep mode level is three, all cores of the chip will go into sleep mode.

It should be understood that the more cores a chip has in operation, the higher its power consumption. Therefore, in core hibernation mode, the chip's microarchitecture level is inversely proportional to its power consumption. A higher core hibernation level results in lower power consumption, and vice versa.

As can be seen from the above, when the chip's operating parameters include the chip's microarchitecture mode level, the chip's microarchitecture mode level can affect the chip's power consumption. Therefore, electronic devices can adjust the chip's microarchitecture mode level according to the chip's power consumption at the current moment and the preset power consumption range to determine the target value of the chip's operating parameters.

In some implementations, the aforementioned preset power consumption range (also known as the expected power consumption range, i.e., the power consumption range to be achieved) can be set based on meeting the chip's stability and operating performance. For example, the preset power consumption range can be 140W-160W. This preset power consumption range can be reasonably set according to different chip requirements, and the embodiments disclosed herein do not limit this.

In some implementations, when the chip's power consumption control accuracy is high, the electronic device can also determine the target value of the chip's operating parameters based on the chip's power consumption at the current moment and the preset power consumption value (also known as the expected power consumption value, i.e., the power consumption value to be achieved, such as 150W), so that the chip's power consumption under the target value of the operating parameters is the preset power consumption value.

Based on the above examples, when the chip's microarchitecture mode is PDP mode or core hibernation mode, since the chip's microarchitecture mode level is inversely proportional to the chip's power consumption, when the chip's power consumption is high at the current moment (e.g., higher than the maximum value of the preset power consumption range), the electronic device can increase the chip's microarchitecture mode level and determine the increased microarchitecture mode level as the target value of the microarchitecture mode level.

Accordingly, when the chip's power consumption is low at the current moment (e.g., below the minimum value of the preset power consumption range), the electronic device can lower the chip's microarchitecture mode level and set the lowered microarchitecture mode level as the target value of the microarchitecture mode level.

Subsequently, the electronic device can send the target value of the microarchitecture mode level to the adjustment module that adjusts the microarchitecture mode level through the configuration distribution module, so that the power consumption of the chip at the target value of the microarchitecture mode level is within the preset power consumption range.

In some implementations, after determining the target value of the operating parameters, the electronic device can directly issue an adjustment to the operating parameters through the configuration issuing module. However, since the chip's power consumption is constantly changing, and the target value of the operating parameters determined by the electronic device may also affect the chip's power consumption, directly issuing an adjustment to the operating parameters through the configuration issuing module may not ensure that the chip's power consumption is within the preset power consumption range. In this case, the electronic device can determine the target value of the chip's operating parameters by determining the expected value of the operating parameters and the estimated power consumption of the chip under the expected value of the operating parameters. Referring to Figure 2 and Figure 3, the method in S202 above for the electronic device to determine the target value of the chip's operating parameters based on the chip's power consumption at the current moment and the preset power consumption range includes S301-S303.

S301. The electronic device determines the expected value of the operating parameters based on the chip's power consumption at the current moment and the preset power consumption range.

In some implementations, electronic devices can determine the expected values of operating parameters based on preset step sizes.

For example, suppose the operating parameter is the microarchitecture mode level, and the chip's current microarchitecture mode level is level 2, with a preset step size of 1 for adjusting the microarchitecture mode level. If the chip's power consumption at the current moment exceeds the maximum value of the preset power consumption range, the electronic device can increase the microarchitecture mode level by 1, resulting in an expected value of level 3.

S302, Electronic device determines the estimated power consumption of a chip under expected operating parameters.

For example, referring to Figure 1, the power consumption calculation module in the electronic device can not only determine the power consumption of the chip at the current moment based on the operating status parameters at the current moment, but also replace the working parameters in the operating status parameters at the current moment with the expected values of the working parameters, and determine the estimated power consumption of the chip at the expected values of the working parameters based on the replaced operating status parameters.

S303. When the power consumption estimate is within the preset power consumption range, or when the expected value of the operating parameter is the upper limit or lower limit of the operating parameter, the electronic device determines the expected value of the operating parameter as the target value of the operating parameter.

If the estimated power consumption is within the preset power consumption range, it means that the expected values of the operating parameters can make the chip's power consumption reach the expected level. Therefore, electronic devices can determine the expected values of the operating parameters as the target values of the operating parameters.

If the expected value of a working parameter is either its upper or lower limit, it means that the expected value has been adjusted to its upper or lower limit (i.e., hardware limitation) and cannot be adjusted further. Therefore, the electronic device can determine the expected value of the working parameter as its target value.

When there are multiple operating parameters, if the expected value of one operating parameter is the upper limit or lower limit of the operating parameter, but the power consumption estimate is not within the preset power consumption range, the electronic device can also determine the target values of other operating parameters so that the power consumption of the chip at the target value of the operating parameter is within the preset power consumption range.

In some implementations, the operating parameters include not only the microarchitecture mode level but also the operating frequency. Referring to Figure 2 and as shown in Figure 4, the method described in S202 above for the electronic device to determine the target values of the chip's operating parameters based on the chip's current power consumption and a preset power consumption range includes S401-S403.

S401. The electronic device determines the expected value of the first parameter based on the chip's power consumption at the current moment and the preset power consumption range.

The first parameter can be either the microarchitecture mode level or the operating frequency. For a description of S401, please refer to the description of S301; it will not be repeated here.

S402, Electronic device determines the power consumption estimate of the chip under the expected value of the first parameter.

For a description of S402, please refer to the description of S302; it will not be repeated here.

S403. The electronic device determines the target value of the first parameter and the target value of the second parameter based on the expected value of the first parameter and the estimated power consumption of the chip under the expected value of the first parameter.

One of the first and second parameters is the operating frequency, and the other is the microarchitecture pattern level.

It should be noted that adjusting the operating frequency may affect the chip's stability, but it can improve the chip's energy efficiency ratio. Similarly, adjusting the microarchitecture mode level may affect the chip's energy efficiency ratio, but it can improve the chip's stability. Therefore, electronic devices can determine the order in which to adjust the operating parameters based on different power consumption control requirements.

If power consumption control demands high chip stability but low energy efficiency, then the first parameter is the microarchitecture mode level, and the second parameter is the operating frequency. Conversely, if power consumption control demands high chip energy efficiency but low stability, then the first parameter is the operating frequency, and the second parameter is the microarchitecture mode level.

In other words, this disclosure can be used in any scenario with power control requirements. It can adjust only the microarchitecture mode level or adjust both the microarchitecture mode level and the operating frequency to achieve power control. That is, this disclosure can realize personalized customization of power control in various scenarios to meet different power control needs.

Given operating parameters including operating frequency and microarchitecture mode level, electronic devices can first determine the expected value of a parameter (i.e., the first parameter) and the estimated power consumption of the chip at the expected value of the first parameter.

If the chip's power consumption estimate under the expected value of the first parameter is within the preset power consumption range, it means that adjusting only the first parameter is sufficient to meet the chip's power consumption requirements. In this case, the electronic device can directly determine the expected value of the first parameter as the target value of the operating parameters without adjusting the second parameter.

Accordingly, if the chip's power consumption estimate under the expected value of the first parameter is not within the preset power consumption range, and the expected value of the first parameter is either the upper or lower limit of the first parameter, it indicates that the expected value of the operating parameter has been adjusted to the upper or lower limit and cannot be further adjusted. Therefore, the electronic device can determine the target value of the operating parameter by adjusting the second parameter.

In some implementations, as shown in Figure 5 in conjunction with Figure 4, the method by which the electronic device determines the target value of the first parameter and the target value of the second parameter based on the expected value of the first parameter and the estimated power consumption of the chip under the expected value of the first parameter in S403 includes S501-S503.

S501. If the estimated power consumption of the chip under the expected value of the first parameter is not within the preset power consumption range, and the expected value of the first parameter is the upper limit or lower limit of the first parameter, the electronic device determines the expected value of the second parameter based on the estimated power consumption of the chip under the expected value of the first parameter.

For example, taking the first parameter as the PDP mode level and the second parameter as the operating frequency, if the expected power consumption of the chip is still greater than the maximum value of the preset power consumption range when the expected value of the PDP mode level is level five, then it is impossible to continue adjusting the expected value of the PDP mode level. In this case, the electronic device can determine the expected value of the operating frequency.

In some implementations, the electronic device can determine the expected value of the operating frequency based on a preset step size of the operating frequency.

For example, suppose the chip is operating at a frequency of 3000MHz at the current moment, with a preset step size of 100MHz. If the expected power consumption of the chip is still greater than the maximum value of the preset power consumption range when the expected value of the chip in PDP mode is level five, the electronic device can determine that the expected value of the operating frequency is 2900MHz.

S502, Electronic device determines the estimated power consumption of the chip under the expected value of the second parameter.

For a description of S502, please refer to the description of S302, which will not be repeated here.

S503. If the estimated power consumption of the chip under the expected value of the second parameter is within the preset power consumption range, or if the expected value of the second parameter is the upper limit or lower limit of the second parameter, the electronic device determines the expected value of the first parameter as the target value of the first parameter, and determines the expected value of the second parameter as the target value of the second parameter.

Continuing with the example above, if the expected value of the chip in PDP mode is level 5 and the expected value of the operating frequency is 2900MHz, and if the estimated power consumption of the chip is already within the preset power consumption range, then the electronic device will determine level 5 as the target value of the PDP mode level and 2900MHz as the target value of the operating frequency.

If the expected value of the chip in PDP mode is level 5 and the expected value of the operating frequency is 2900MHz, and the estimated power consumption of the chip is still not within the preset power consumption range, the electronic device continues to determine the expected value of the operating frequency until the expected power consumption of the chip at the expected value of the operating frequency is within the preset power consumption range, or the expected value of the operating frequency is the upper limit or lower limit of the operating frequency.

In some implementations, when the electronic device needs to control power consumption based on the target values of the first parameter and the second parameter simultaneously, the electronic device can first determine the target value of the microarchitecture mode level and then determine the target value of the operating frequency (i.e., the first parameter is the microarchitecture mode level and the second parameter is the operating frequency), or it can first determine the target value of the operating frequency and then determine the target value of the microarchitecture mode level (i.e., the first parameter is the operating frequency and the second parameter is the microarchitecture mode level). This disclosure does not limit this approach.

In some implementations, the electronic device may also determine the expected value of the second parameter after determining the expected value of the first parameter, and if the expected value of the first parameter is not the upper limit or lower limit of the first parameter, so that the estimated power consumption of the chip is within the preset power consumption range. This disclosure does not limit this aspect.

As can be seen from the above, this disclosure can achieve the effect of controlling power consumption while improving the chip's energy efficiency ratio by adjusting the microarchitecture mode level (which essentially means turning off or on some microarchitecture designs, or reducing or increasing the resource usage corresponding to some microarchitecture state parameters in exchange for power consumption control) and operating frequency. Compared with general power consumption control methods, this disclosure can not only respond quickly and improve power consumption control accuracy, but also ensure chip stability and improve chip energy efficiency ratio.

In some implementations, the chip may include multiple cores. Referring to Figure 3 and as shown in Figure 6, the method in S301 above for the electronic device to determine the expected value of the operating parameters based on the chip's power consumption at the current moment and a preset power consumption range includes S601.

S601. The electronic device determines the expected value of the operating parameters of each of the multiple cores in turn based on the power consumption of the chip at the current moment, the preset power consumption range, and the preset order.

The preset order includes any of the following: the order of core numbers of multiple cores, the order of power consumption of each core, or a random order.

In some implementations, when the operating parameters include a first parameter and a second parameter, the method for determining the power consumption estimate of the chip under the expected value of the first parameter in S402 above includes:

The electronic device determines the expected value of the first parameter of each of the multiple cores in turn based on the chip's power consumption at the current moment, the preset power consumption range, and the preset order.

Accordingly, in S501 above, the method for determining the expected value of the second parameter based on the power consumption estimate of the chip under the expected value of the first parameter includes:

Based on the expected power consumption of the chip under the expected value of the first parameter and the preset order, the expected value of the second parameter of each of the multiple cores is determined sequentially.

For example, when the first parameter is the microarchitecture mode level and the second parameter is the operating frequency, the electronic device can first determine the expected value of the operating frequency of all cores in the chip, and then determine the expected value of the microarchitecture mode level of all cores; it can also first determine the expected value of the microarchitecture mode level of all cores in the chip, and then determine the expected value of the operating frequency of all cores; it can also first determine the expected value of the microarchitecture mode level of a portion of the cores in the chip, and then determine the expected value of the operating frequency of another portion of the cores; it can also first determine the expected value of the microarchitecture mode level and the expected value of the operating frequency of a certain core in the chip, and then determine the expected value of the microarchitecture mode level and the expected value of the operating frequency of the other cores in sequence. This disclosure does not limit this.

In some embodiments, when the units corresponding to each working parameter adjust the working parameters according to the target value of the working parameters, the working parameters can also be adjusted in the order described above, which will not be repeated here.

In some implementations, as shown in Figure 7 in conjunction with Figure 2, the method for determining the power consumption of the chip at the current moment in S201 above includes S701-S703.

S701. The electronic device determines the static power consumption of the chip at the current moment based on the chip's temperature and voltage at the current moment.

In some implementations, the chip's temperature, voltage, and static power consumption at the current moment satisfy the following formula:
P = (a*V + b)ec*T;

Where a, b, c, and e are constant parameters, P is the static power consumption of the chip at the current moment, V is the voltage of the chip at the current moment, and T is the temperature of the chip at the current moment.

S702. The electronic device determines the dynamic power consumption of the chip at the current moment based on the chip's microarchitecture state parameters at the current moment, the chip's operating frequency at the current moment, the chip's voltage at the current moment, the number of instructions executed by the chip in a preset cycle, and the amount of memory data read by the chip in a preset cycle at the current moment.

In some implementations, the chip's microarchitecture state parameters at the current moment, the chip's operating frequency at the current moment, the chip's voltage at the current moment, the number of instructions executed by the chip within a preset period, the amount of memory data read by the chip within a preset period, and the chip's dynamic power consumption at the current moment satisfy the following formula:
P＝a*C1+b*C2+c*C3+d*C4+e*C5+f*F*V2+g;

Where a, b, c, d, e, f, and g are constant parameters, P is the dynamic power consumption of the chip at the current moment, V is the voltage of the chip at the current moment, T is the temperature of the chip at the current moment, F is the operating frequency of the chip at the current moment, C1 is the number of instructions executed by the chip in a preset period, C2 is the amount of memory data read by the chip in a preset period, and C3-C5 are any three of the microarchitecture state parameters of the chip at the current moment.

In some implementations, C3-C5 can be three parameters related to the chip's cache in the microarchitecture state parameters.

S703: Electronic devices determine the sum of static power consumption and dynamic power consumption as the power consumption of the chip at the current moment.

The above mainly describes the solutions provided by the embodiments of this disclosure from the perspective of an electronic device. It is understood that, in order to achieve the above functions, the electronic device includes modules that perform each function, such as a configuration monitoring module and a power consumption calculation module. The embodiments of this disclosure will now be described from the perspective of each module in the electronic device. Figure 8 shows another power consumption control method provided by an embodiment of this disclosure. As shown in Figure 8, the power consumption control method includes:

S801, Configure the monitoring module to obtain the chip's operating status parameters at the current moment.

S802, The configuration monitoring module sends the chip's operating status parameters at the current moment to the power consumption calculation module.

S803, the power consumption calculation module determines the power consumption of the chip at the current moment based on the chip's operating status parameters at the current moment.

S804, the power consumption calculation module determines the power consumption adjustment strategy as either increasing or decreasing power consumption based on the chip's power consumption at the current moment and the preset power consumption range.

S805, the power consumption calculation module determines the target value of the operating parameters according to the power consumption adjustment strategy.

In some implementations, as shown in Figure 9, when the power consumption adjustment strategy is determined to be either increasing or decreasing power consumption, and the power consumption control requirement is high stability and low energy efficiency, the power consumption control method provided in this disclosure includes:

S901, the power consumption calculation module sends an instruction to the microarchitecture calculation module to determine the target value of the microarchitecture mode level.

S902, the microarchitecture computing module determines the expected value of the microarchitecture mode level, and the estimated power consumption of the chip at the expected value of the microarchitecture mode level.

S903, the microarchitecture computing module sends the power consumption estimate of the chip at the expected value of the microarchitecture mode level to the power consumption computing module.

S904, the power consumption calculation module determines whether the estimated power consumption of the chip at the expected value of the microarchitecture mode level reaches the preset power consumption range.

If yes, then the expected value of the microarchitecture mode level is determined as the target value of the microarchitecture mode level. If not, then continue to send instructions to the microarchitecture computing module to determine the target value of the microarchitecture mode level until the chip's power consumption estimate under the expected value of the microarchitecture mode level is within the preset power consumption range, or the expected value of the microarchitecture mode level is the upper limit or lower limit of the microarchitecture mode level.

For ease of understanding, Figure 9 describes the instruction sent by the power consumption calculation module to the microarchitecture calculation module to determine the target value of the microarchitecture mode level as a continuation instruction.

S905. Upon receiving the first message from the microarchitecture calculation module, the power consumption calculation module sends an instruction to the frequency calculation module to determine the target value of the operating frequency.

The first piece of information indicates that the estimated power consumption of the chip at the expected value of the microarchitecture mode level is not within the preset power consumption range, and the expected value of the microarchitecture mode level is the upper limit or the lower limit of the microarchitecture mode level.

S906, the frequency calculation module determines the expected value of the operating frequency and the estimated power consumption of the chip at the expected operating frequency.

S907, the frequency calculation module sends the power consumption estimate under the expected value of the operating frequency to the power consumption calculation module.

The S908 power consumption calculation module determines whether the estimated power consumption under the expected value of the operating frequency reaches the preset power consumption range.

If yes, then the expected value of the operating frequency is determined as the target value of the operating frequency. If not, then continue sending instructions to the frequency calculation module to determine the target value of the operating frequency until the estimated power consumption of the chip at the expected value of the operating frequency is within the preset power consumption range, and then determine the expected value of the operating frequency as the target value of the operating frequency.

For ease of understanding, Figure 9 describes the instruction sent by the power consumption calculation module to the frequency calculation module to determine the target value of the operating frequency as a continuation instruction.

In some implementations, as shown in Figure 10, when the power consumption adjustment strategy is determined to be either increasing or decreasing power consumption, and the power consumption control requirement is a high energy efficiency ratio and a low stability requirement, the power consumption control method provided in this disclosure includes:

S1001, The power consumption calculation module sends an instruction to the frequency calculation module to determine the target value of the operating frequency.

S1002, the frequency calculation module determines the expected value of the operating frequency and the estimated power consumption of the chip at the expected operating frequency.

S1003, the frequency calculation module sends the power consumption estimate of the chip at the expected value of the operating frequency to the power consumption calculation module.

S1004 The power consumption calculation module determines whether the estimated power consumption of the chip at the expected operating frequency reaches the preset power consumption range.

If yes, then the expected value of the operating frequency is determined as the target value of the operating frequency. If not, then continue to send instructions to the frequency calculation module to determine the target value of the operating frequency until the estimated power consumption of the chip at the expected value of the operating frequency is within the preset power consumption range, or the expected value of the operating frequency is the upper limit or lower limit of the operating frequency.

For ease of understanding, Figure 10 describes the instruction sent by the power consumption calculation module to the frequency calculation module to determine the target value of the operating frequency as a continuation instruction.

S1005. When the power consumption calculation module receives the second message sent by the frequency calculation module, it sends an instruction to the microarchitecture calculation module to determine the target value of the microarchitecture mode level.

The second piece of information indicates that the chip's power consumption estimate at the expected operating frequency is not within the preset power consumption range, and the expected operating frequency is either the upper limit or the lower limit of the operating frequency.

S1006, the microarchitecture computing module determines the expected value of the microarchitecture mode level, and the estimated power consumption of the chip at the expected value of the microarchitecture mode level.

S1007, The microarchitecture computing module sends the power consumption estimate under the expected value of the microarchitecture mode level to the power consumption computing module.

S1008, the power consumption calculation module determines whether the power consumption estimate under the expected value of the microarchitecture mode level reaches the preset power consumption range.

If yes, then the expected value of the microarchitecture mode level is determined as the target value of the microarchitecture mode level. If not, then continue sending instructions to the microarchitecture computing module to determine the target value of the microarchitecture mode level until the chip's power consumption estimate under the expected value of the microarchitecture mode level is within the preset power consumption range, and then determine the expected value of the operating frequency as the target value of the operating frequency.

For ease of understanding, Figure 10 describes the instruction sent by the power consumption calculation module to the microarchitecture calculation module to determine the target value of the microarchitecture mode level as a continuation instruction.

It is understood that, in order to achieve the above-mentioned functions, electronic devices include hardware structures and/or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, based on the algorithmic steps of the examples described in conjunction with the embodiments of this disclosure, this disclosure can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

This disclosure embodiment can divide an electronic device into functional modules according to the above method embodiment. For example, each function can be divided into a separate functional module, or two or more functions can be integrated into one functional module. The integrated module can be implemented in hardware or software. It should be noted that the module division in this disclosure embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods. The following description uses the example of dividing each functional module according to each function.

Figure 11 is a schematic diagram of an electronic device provided in an embodiment of this disclosure. The electronic device can execute the power consumption control method provided in the above-described method embodiment. As shown in Figure 11, the electronic device includes a processing unit 1101.

Processing unit 1101 is used to determine the power consumption of the chip at the current moment.

The processing unit 1101 is further configured to determine the target value of the chip's operating parameters based on the chip's power consumption at the current moment and a preset power consumption range, so that the chip's power consumption at the target value of the operating parameters is within the preset power consumption range; the operating parameters include the microarchitecture mode level; the microarchitecture mode level is used to represent the chip's microarchitecture state.

In some implementations, the processing unit 1101 is used for:

The expected values of the operating parameters are determined based on the chip's current power consumption and the preset power consumption range.

Determine the estimated power consumption of the chip under the expected values of its operating parameters;

If the power consumption estimate is within the preset power consumption range, or if the expected value of the operating parameter is the upper limit or lower limit of the operating parameter, the expected value of the operating parameter is determined as the target value of the operating parameter.

In some implementations, the chip includes multiple cores; the processing unit 1101 is used for:

The expected values of the operating parameters are determined based on the chip's current power consumption and the preset power consumption range, including:

Based on the chip's power consumption at the current moment, the preset power consumption range, and the preset order, the expected values of the operating parameters of each core in the multiple cores are determined sequentially; the preset order includes any one of the following: the core number order of the multiple cores, the power consumption order of each core, or a random order.

In some implementations, the operating parameters also include the operating frequency; the processing unit 1101 is used for:

The expected value of the first parameter is determined based on the chip's power consumption at the current moment and the preset power consumption range;

Determine the estimated power consumption of the chip under the expected value of the first parameter;

Based on the expected value of the first parameter and the estimated power consumption of the chip under the expected value of the first parameter, the target values of the first parameter and the second parameter are determined; wherein, one of the first parameter and the second parameter is the operating frequency, and the other is the microarchitecture mode level.

In some implementations, the processing unit 1101 is used for:

If the estimated power consumption of the chip under the expected value of the first parameter is not within the preset power consumption range, and the expected value of the first parameter is the upper limit or lower limit of the first parameter, the expected value of the second parameter shall be determined based on the estimated power consumption of the chip under the expected value of the first parameter.

Determine the estimated power consumption of the chip under the expected value of the second parameter;

If the estimated power consumption of the chip under the expected value of the second parameter is within the preset power consumption range, or if the expected value of the second parameter is the upper limit or lower limit of the second parameter, the expected value of the first parameter is determined as the target value of the first parameter, and the expected value of the second parameter is also determined as the target value of the second parameter.

In some implementations, the chip includes multiple cores; the processing unit 1101 is used for:

Based on the chip's power consumption at the current moment, the preset power consumption range, and the preset order, the expected value of the first parameter of each of the multiple cores is determined sequentially; the preset order includes any one of the following: the core number order of the multiple cores, the power consumption order of each core, or a random order;

Based on the expected power consumption of the chip under the expected value of the first parameter and the preset order, the expected value of the second parameter of each of the multiple cores is determined sequentially.

In some implementations, the processing unit 1101 is used for:

The static power consumption of the chip at the current moment is determined based on the chip's temperature and voltage at the current moment.

The dynamic power consumption of the chip at the current moment is determined based on the chip's microarchitecture state parameters, chip's operating frequency, chip's voltage, the number of instructions executed by the chip in a preset period, and the amount of memory data read by the chip in a preset period.

The sum of static power consumption and dynamic power consumption is determined as the power consumption of the chip at the current moment.

In some implementations, the microarchitecture state parameters include at least one of the following: memory access rate, data transfer rate, cache size, number of pending task instructions, and number of parallel task instructions.

In some implementations, the microarchitecture mode level corresponds to the microarchitecture mode, which includes: the PDP mode in the ARM architecture or the core hibernation mode in the x86 architecture.

In the case of implementing the functions of the integrated modules described above in hardware, this disclosure provides another structure of the electronic device involved in the above embodiments. As shown in FIG12, the electronic device 120 includes: a memory 1201, a processor 1202, a communication interface 1203, and a bus 1204.

The memory 1201 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions; it may be random access memory (RAM) or other type of dynamic storage device capable of dynamically storing information and instructions; it may also be electrically erasable programmable read-only memory (EEPROM), disk storage media or other magnetic storage devices; or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but is not limited thereto.

Processor 1202 may be a logic block, module, or circuit that implements or performs the various exemplary methods described in conjunction with embodiments of this disclosure. Processor 1202 may be a central processing unit, a general-purpose processor, a digital signal processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. Processor 1202 may implement or perform the various exemplary logic blocks, modules, and circuits described in conjunction with embodiments of this disclosure. Processor 1202 may also be a combination that implements computational functions, such as a combination of one or more microprocessors, a combination of a DSP (digital signal processor) and a microprocessor, etc.

The communication interface 1203 is used to connect with other devices via a communication network. This communication network can be Ethernet, wireless access network, wireless local area network (WLAN), etc.

In some implementations, the memory 1201 can exist independently of the processor 1202. The memory 1201 can be connected to the processor 1202 via a bus 1204 and is used to store instructions or program code. When the processor 1202 calls and executes the instructions or program code stored in the memory 1201, it can implement the power consumption control method provided in the embodiments of this disclosure.

In some implementations, the memory 1201 can also be integrated with the processor 1202.

Bus 1204 can be an extended industry standard architecture (EISA) bus, etc. Bus 1204 can be divided into address bus, data bus, control bus, etc. For ease of representation, only one thick line is used to represent bus 1204 in Figure 12, but this does not mean that there is only one bus or only one type of bus.

Some embodiments of this disclosure provide an electronic device that can perform the power consumption control method as described in any of the above embodiments.

Some embodiments of this disclosure provide a computer-readable storage medium (e.g., a non-transitory computer-readable storage medium) storing computer program instructions that, when executed on a computer, cause the computer to perform a power consumption control method as described in any of the above embodiments.

Exemplary examples show that the aforementioned computer-readable storage media may include, but are not limited to: magnetic storage devices (e.g., hard disks, floppy disks, or magnetic tapes), optical disks (e.g., compact disks (CDs), digital versatile disks (DVDs), etc.), smart cards, and flash memory devices (e.g., erasable programmable read-only memory (EPROMs), cards, sticks, or key drives, etc.). The various computer-readable storage media described in this disclosure may represent one or more devices for storing information and/or other machine-readable storage media. The term "machine-readable storage media" may include, but is not limited to, wireless channels and various other media capable of storing, containing, and/or carrying instructions and/or data.

This disclosure provides a computer program product containing instructions that, when run on a computer, cause the computer to execute the power consumption control method described in any of the above embodiments.

The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions within the technical scope disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims (12)

A power consumption control method, comprising: Determine the chip's power consumption at the current moment; Based on the chip's power consumption at the current moment and a preset power consumption range, a target value for the chip's operating parameters is determined so that the chip's power consumption at the target value of the operating parameters is within the preset power consumption range; wherein, the operating parameters include a microarchitecture mode level, which is used to represent the chip's microarchitecture state. According to the power consumption control method of claim 1, the step of determining the target value of the chip's operating parameters based on the chip's power consumption at the current moment and a preset power consumption range includes: The expected value of the operating parameters is determined based on the power consumption of the chip at the current moment and the preset power consumption range; Determine the estimated power consumption of the chip under the expected values of the operating parameters; If the estimated power consumption is within the preset power consumption range, or if the expected value of the operating parameter is the upper limit or lower limit of the operating parameter, the expected value of the operating parameter is determined as the target value of the operating parameter. According to claim 2, the power consumption control method, wherein the chip includes multiple cores; Determining the expected value of the operating parameters based on the chip's power consumption at the current moment and the preset power consumption range includes: Based on the chip's power consumption at the current moment, the preset power consumption range, and the preset order, the expected values of the operating parameters of each of the plurality of cores are determined sequentially; the preset order includes any one of the following: the core number order of the plurality of cores, the power consumption order of each core, or a random order. According to claim 1, the power consumption control method further includes an operating frequency as the operating parameter; The step of determining the target values of the chip's operating parameters based on the chip's power consumption at the current moment and a preset power consumption range includes: The expected value of the first parameter is determined based on the power consumption of the chip at the current moment and the preset power consumption range; Determine the estimated power consumption of the chip under the expected value of the first parameter; Based on the expected value of the first parameter and the estimated power consumption of the chip under the expected value of the first parameter, the target value of the first parameter and the target value of the second parameter are determined; wherein, one of the first parameter and the second parameter is the operating frequency, and the other is the microarchitecture mode level. According to the power consumption control method of claim 4, the step of determining the target value of the first parameter and the target value of the second parameter based on the expected value of the first parameter and the estimated power consumption of the chip under the expected value of the first parameter includes: If the estimated power consumption of the chip under the expected value of the first parameter is not within the preset power consumption range, and the expected value of the first parameter is the upper limit or the lower limit of the first parameter, the expected value of the second parameter is determined based on the estimated power consumption of the chip under the expected value of the first parameter. Determine the estimated power consumption of the chip under the expected value of the second parameter; If the estimated power consumption of the chip at the expected value of the second parameter is within the preset power consumption range, or if the expected value of the second parameter is the upper limit or lower limit of the second parameter, then the expected value of the first parameter is determined as the target value of the first parameter, and the expected value of the second parameter is also determined as the target value of the second parameter. According to claim 5, the power consumption control method, wherein the chip includes multiple cores; Determining the expected value of the first parameter based on the chip's power consumption at the current moment and the preset power consumption range includes: Based on the chip's power consumption at the current moment, the preset power consumption range, and the preset order, the expected value of the first parameter of each of the plurality of cores is determined sequentially; the preset order includes any one of the following: the core number order of the plurality of cores, the power consumption order of each core, or a random order; Determining the expected value of the second parameter based on the estimated power consumption of the chip under the expected value of the first parameter includes: Based on the estimated power consumption of the chip under the expected value of the first parameter and the preset order, the expected value of the second parameter of each of the plurality of cores is determined sequentially. According to the power consumption control method of claim 1, determining the power consumption of the chip at the current moment includes: The static power consumption of the chip at the current moment is determined based on the chip's temperature and voltage at the current moment. The dynamic power consumption of the chip at the current moment is determined based on the chip's microarchitecture state parameters at the current moment, the chip's operating frequency at the current moment, the chip's voltage at the current moment, the number of instructions executed by the chip in a preset period, and the amount of memory data read by the chip in a preset period. The sum of the static power consumption and the dynamic power consumption is determined as the power consumption of the chip at the current moment. According to the power consumption control method of claim 7, the microarchitecture state parameters include at least one of: memory access rate, data transfer rate, buffer size, number of pending task instructions, and number of parallel task instructions. The power consumption control method according to any one of claims 1-8, wherein the microarchitecture mode corresponding to the microarchitecture mode level includes: the performance-defined power (PDP) mode in the Advanced Reduced Instruction Set Machine (ARM) architecture or the core hibernation mode in the x86 architecture. An electronic device includes a processor, wherein, when the processor executes a computer program, it implements the power consumption control method according to any one of claims 1-9. A computer-readable storage medium comprising computer instructions; wherein, when the computer instructions are executed, the power consumption control method according to any one of claims 1-9 is implemented. A computer program product comprising: a computer program or instructions that, when executed on a computer, cause the computer to perform the power consumption control method according to any one of claims 1-9.