WO2025221624A1 - Stress modification of leg structures for bolometer stiffening and associated systems and methods - Google Patents

Abstract

Techniques are provided for facilitating stress modification of leg structures for bolometer stiffening and associated systems and methods. In one example, a method includes determining a resonant frequency associated with a leg structure. The method further includes determining a score associated with the leg structure based at least on the resonant frequency. The method further includes adjusting the leg structure based on the score to obtain an adjusted leg structure. The adjusting of the leg structure includes adjusting a stress of one or more layers of the leg structure, adjusting one or more dimensions of one or more layers of the leg structure, and/or adding one or more layers to the leg structure to obtain an adjusted leg structure. Related devices and systems are also provided.

Description

Docket No.70052.2043WO01 STRESS MODIFICATION OF LEG STRUCTURES FOR BOLOMETER STIFFENING AND ASSOCIATED SYSTEMS AND METHODS George D. Skidmore; Marin Sigurdson; Eric Kurth; and Sean A. MacKenzie CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application claims the benefit of and priority to U.S. Provisional Patent Application No.63/636,643 filed April 19, 2024 and entitled “STRESS MODIFICATION OF LEG STRUCTURES FOR BOLOMETER STIFFENING AND ASSOCIATED SYSTEMS AND METHODS,” which is incorporated herein by reference in its entirety. [0002] This application is related to U.S. Patent Application No.63/636,647 filed April 19, 2024 and entitled “LEG STRUCTURES FOR MICROBOLOMETER FOCAL PLANE ARRAYS AND ASSOCIATED SYSTEMS AND METHODS,” which is incorporated herein by reference in its entirety. TECHNICAL FIELD [0003] One or more embodiments relate generally to infrared imaging systems and more particularly, for example, to stress modification of leg structures for bolometer stiffening and associated systems and methods. BACKGROUND [0004] Imaging systems may include an array of detectors arranged in rows and columns, with each detector functioning as a pixel to produce a portion of a two-dimensional image. For example, an individual detector of the array of detectors captures an associated pixel value. There are a wide variety of image detectors, such as visible-light image detectors, infrared image detectors, or other types of image detectors that may be provided in an image detector array for capturing an image. As an example, a plurality of sensors may be provided in an image detector array to detect electromagnetic (EM) radiation at desired wavelengths. In some cases, such as for infrared imaging, readout of image data captured by the detectors may be performed in a time-multiplexed manner by a readout integrated circuit (ROIC). The image data that is read out may be communicated to other circuitry, such as for processing, storage, and/or display. In some cases, a combination of a detector array and an ROIC may be referred to as a focal plane array (FPA). Advances in process technology for FPAs and Docket No.70052.2043WO01 image processing have led to increased capabilities and sophistication of resulting imaging systems. SUMMARY [0005] In one or more embodiments, a method includes determining a resonant frequency associated with a leg structure. The method further includes determining a score associated with the leg structure based at least on the resonant frequency. The method further includes adjusting the leg structure based on the score to obtain an adjusted leg structure. The adjusting of the leg structure includes adjusting a stress of one or more layers of the leg structure, adjusting one or more dimensions of one or more layers of the leg structure, and/or adding one or more layers to the leg structure to obtain an adjusted leg structure. [0006] In one or more embodiments, a method of making a leg structure includes forming a first cap layer based on predetermined deposition parameters such that the first cap layer is associated with a predetermined stress. The method further includes forming a first dielectric layer on the first cap layer. The method further includes forming a conductive layer on the first dielectric layer. The method further includes forming a second dielectric layer on the conductive layer. The predetermined stress associated with the first cap layer is higher, in magnitude, than a stress associated with each of the first dielectric layer, the conductive layer, and the second dielectric layer. The leg structure has a lowest resonant frequency indicated by a stress profile of the leg structure. [0007] In one or more embodiments, an infrared imaging device includes a substrate including a plurality of contacts. The infrared imaging device further includes a microbolometer array coupled to the substrate. The microbolometer array includes a plurality of microbolometers. Each microbolometer includes a bridge and a leg structure coupled to the bridge and to one of the plurality of contacts. The leg structure includes a first cap layer. The leg structure further includes a first dielectric layer disposed on the first cap layer. The leg structure further includes a conductive layer disposed on the first dielectric layer. The leg structure further includes a second dielectric layer disposed on the conductive layer. A stress associated with the first cap layer is higher, in magnitude, than a stress associated with each of the first dielectric layer, the conductive layer, and the second dielectric layer. The leg structure has a lowest resonant frequency indicated by a stress profile of the leg structure. [0008] The scope of the present disclosure is defined by the claims, which are incorporated into this section by reference. A more complete understanding of embodiments of the present Docket No.70052.2043WO01 disclosure will be afforded to those skilled in the art, as well as a realization of additional advantages thereof, by a consideration of the following detailed description of one or more embodiments. Reference will be made to the appended sheets of drawings that will first be described briefly. BRIEF DESCRIPTION OF THE DRAWINGS [0009] FIG.1 illustrates a block diagram of an example imaging system in accordance with one or more embodiments of the present disclosure. [0010] FIG.2 illustrates a block diagram of an example image sensor assembly in accordance with one or more embodiments of the present disclosure. [0011] FIG.3 shows a physical layout diagram of a microbolometer in accordance with one or more embodiments of the present disclosure. [0012] FIGS.4A through 4T illustrate cross-sectional side views associated with an example process for forming a bolometer in accordance with one or more embodiments of the present disclosure. [0013] FIG.5 illustrates a top-down view of the bolometer corresponding to the cross- sectional side view of FIG.4T in accordance with one or more embodiments of the present disclosure. [0014] FIGS.6A through 6J each illustrate an example leg structure in accordance with one or more embodiments of the present disclosure. [0015] FIGS.7A through 7C illustrate cross-sectional side views associated with an example process/flow for forming the leg structure of FIG.6A in accordance with one or more embodiments of the present disclosure. [0016] FIGS.8A through 8C illustrate cross-sectional side views associated with an example process/flow for forming the leg structure of FIG.6B in accordance with one or more embodiments of the present disclosure. [0017] FIGS.9A and 9B illustrate cross-sectional side views associated with an example process/flow for forming the leg structure of FIG.6D in accordance with one or more embodiments of the present disclosure. [0018] FIG.10A and 10B illustrate cross-sectional side views associated with an example process/flow for forming the leg structure of FIG.6F in accordance with one or more Docket No.70052.2043WO01 embodiments of the present disclosure. [0019] FIGS.11A through 11D illustrate perspective views associated with an example process/flow for forming a leg structure in accordance with one or more embodiments. [0020] FIGS.12A through 12R illustrate perspective views associated with an example process/flow for forming a pixel of an infrared imaging device in accordance with one or more embodiments of the present disclosure. [0021] FIGS.13A through 13E illustrate perspective views associated with an example process/flow for forming leg structures of a pixel of an infrared imaging device in accordance with one or more embodiments of the present disclosure. [0022] FIG.13F illustrates an example leg structure formed by the example process/flow of FIGS.13A-13E in accordance with one or more embodiments of the present disclosure. [0023] FIG.14A illustrates a pixel in accordance with one or more embodiments of the present disclosure. [0024] FIG.14B illustrates a cross-sectional view of a bolometer leg of the pixel of FIG. 14A in accordance with one or more embodiments of the present disclosure. [0025] FIG.14C illustrates an example symmetric stress profile associated with the bolometer leg of FIG.14B in accordance with one or more embodiments of the present disclosure. [0026] FIG.14D illustrates a graph depicting an example relationship between a stress of layers of a bolometer leg and a lowest resonant frequency of the bolometer leg in accordance with one or more embodiments of the present disclosure. [0027] FIG.15A illustrates a pixel in accordance with one or more embodiments of the present disclosure. [0028] FIG.15B illustrates a cross-sectional view of a bolometer leg of the pixel of FIG. 15A in accordance with one or more embodiments of the present disclosure. [0029] FIG.15C illustrates an example asymmetric stress profile associated with the bolometer leg of FIG.15B in accordance with one or more embodiments of the present disclosure. [0030] FIG.15D illustrates a graph depicting an example relationship between a stress of a layer of a bolometer leg and a lowest resonant frequency of the bolometer leg in accordance Docket No.70052.2043WO01 with one or more embodiments of the present disclosure. [0031] FIG.15E illustrates a graph of an example relationship between a stress of a layer of a bolometer leg and a leg bow of the bolometer leg in accordance with one or more embodiments of the present disclosure. [0032] FIG.16A illustrates a cross section of a simplified bolometer leg. [0033] FIG.16B illustrates a bolometer leg formed by the bolometer leg of FIG.16A with layers of equal stress added in accordance with one or more embodiments of the present disclosure. [0034] FIG.16C illustrates a bolometer leg formed by the bolometer leg of FIG.16A with layers of equal stress added in accordance with one or more embodiments of the present disclosure. [0035] FIGS.16D and 16E illustrate an effect of a symmetric stress modification and an asymmetric stress modification, respectively, on a lowest resonant frequency of the bolometer leg of FIG.16A in accordance with one or more embodiments of the present disclosure. [0036] FIG.16F illustrates a graph depicting an example relationship between a leg bow of the bolometer legs of FIG.16B and 16C and their respective stress modification in accordance with one or more embodiments of the present disclosure. [0037] FIG.17 is a flowchart of illustrative operations that may be performed for forming a pixel in accordance with one or more embodiments of the present disclosure. [0038] FIG.18 is a flowchart of illustrative operations that may be performed for bolometer stiffening in accordance with one or more embodiments of the present disclosure. [0039] Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It is noted that sizes of various components and distances between these components are not drawn to scale in the figures. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures. DETAILED DESCRIPTION [0040] The detailed description set forth below is intended as a description of various configurations of the subject technology and is not intended to represent the only Docket No.70052.2043WO01 configurations in which the subject technology can be practiced. The appended drawings are incorporated herein and constitute a part of the detailed description. The detailed description includes specific details for the purpose of providing a thorough understanding of the subject technology. However, it will be clear and apparent to those skilled in the art that the subject technology is not limited to the specific details set forth herein and may be practiced using one or more embodiments. In one or more instances, structures and components are shown in block diagram form in order to avoid obscuring the concepts of the subject technology. One or more embodiments of the subject disclosure are illustrated by and/or described in connection with one or more figures and are set forth in the claims. [0041] Systems and methods are disclosed herein to provide leg structures (e.g., also referred to simply as legs) for infrared detectors, in accordance with one or more embodiments. For example, in accordance with an embodiment, bolometer legs are disclosed, such as for microbolometers within a focal plane array. Each microbolometer of an infrared detector array is generally coupled to one or more contacts that extend (e.g., extend vertically) from the array down to the ROIC. In some cases, the contacts may be used for providing a reference voltage for the microbolometer and/or a signal path from the microbolometer to the ROIC. Microbolometers often include a light-sensitive portion formed from resistive material suspended on a bridge, with the resistive material coupled to its contacts via legs that run from the bridge to the contacts. The legs may attach to resistive material through a resistive material contact. [0042] One of the challenges in designing efficient microbolometers involves increasing a fill factor of the array. The fill factor of the array may refer to a ratio of a light-sensitive area (e.g., an active pixel area) to a total area of the array. Since leg supports for each microbolometer occupy a portion of the array area, it may generally be desirable to reduce the amount of area occupied by the legs when a higher fill factor is needed for an application and/or otherwise desired. However, in order to maintain device performance, the width and length of each leg support should scale with the area of each pixel. [0043] Using various embodiments, the leg structures are formed with a thin and narrow conductive layer. The leg structures may include one or more dielectric layers in contact with at least a portion of the conductive layer. Such leg structures may be formed with shape and dimensions appropriate to provide structural integrity and electrical conductivity while minimizing thermal conductivity (e.g., to limit heat transmission between the bridge and the Docket No.70052.2043WO01 ROIC) and/or fill factor. As further shown and described herein, a pixel, including a bridge and leg structures, may extend along three directions (e.g., three orthogonal directions) x, y, and z. A leg structure may have a length extending primarily along a y-direction, a width extending along an x-direction, and a height extending along a z-direction. In some embodiments, a leg structure may be formed with a thin (e.g., dimension along the z- direction) and narrow (e.g., dimension along the x-direction) conductive layer. [0044] In some embodiments, the leg structures may be mechanically stiffened through use of one or more layers having a respective desired stress. In this regard, during a process to design and simulate a bolometer, one or more stress layers may be added to a bolometer design, a stress of one or more constituent layers of a bolometer design may be tuned, and/or dimensions (e.g., thickness) of one or more constituent layers of the bolometer design may be tuned. In some aspects, such stiffening may correspond to and/or otherwise be associated with an increase in a resonant frequency (e.g., a lowest resonant frequency) associated with the bolometers. A desired resonant frequency associated with the bolometer may be a resonant frequency higher than environmental shock and vibration to increase a robustness of the bolometer to such environmental shock and vibration. In some cases, the bolometer design process may take into consideration other characteristics associated with a leg structure or portion thereof such as, by way of non-limiting examples, a leg bow, a fill factor, an electrical conductivity, a thermal conductivity, and/or costs (e.g., material and/or manufacturing costs) associated with the leg structure or portion thereof. [0045] Referring now to the drawings, FIG.1 illustrates a block diagram of an example imaging system 100 in accordance with one or more embodiments of the present disclosure. Not all of the depicted components may be required, however, and one or more embodiments may include additional components not shown in the figure. Variations in the arrangement and type of the components may be made without departing from the spirit or scope of the claims as set forth herein. Additional components, different components, and/or fewer components may be provided. [0046] The imaging system 100 may be utilized for capturing and processing images in accordance with an embodiment of the disclosure. The imaging system 100 may represent any type of imaging system that detects one or more ranges (e.g., wavebands) of EM radiation and provides representative data (e.g., one or more still image frames or video image frames). The imaging system 100 may include an imaging device 105. By way of Docket No.70052.2043WO01 non-limiting examples, the imaging device 105 may be, may include, or may be a part of an infrared camera (e.g., thermal infrared camera), a visible-light camera, a tablet computer, a laptop, a personal digital assistant (PDA), a mobile device, a desktop computer, or other electronic device. The imaging device 105 may include a housing (e.g., a camera body) that at least partially encloses components of the imaging device 105, such as to facilitate compactness and protection of the imaging device 105. For example, the solid box labeled 105 in FIG.1 may represent a housing of the imaging device 105. The housing may contain more, fewer, and/or different components of the imaging device 105 than those depicted within the solid box in FIG.1. In an embodiment, the imaging system 100 may include a portable device and may be incorporated, for example, into a vehicle or a non-mobile installation requiring images to be stored and/or displayed. The vehicle may be a land-based vehicle (e.g., automobile, truck), a naval-based vehicle, an aerial vehicle (e.g., unmanned aerial vehicle (UAV)), a space vehicle, or generally any type of vehicle that may incorporate (e.g., installed within, mounted thereon, etc.) the imaging system 100. In another example, the imaging system 100 may be coupled to various types of fixed locations (e.g., a home security mount, a campsite or outdoors mount, or other location) via one or more types of mounts. [0047] The imaging system 100 includes, according to one implementation, a logic device 110, a memory component 115, an image capture component 120 (e.g., an imager, an image sensor device), an image interface 125, a control component 130, a display component 135, a sensing component 140, and/or a network interface 145. The logic device 110, according to various embodiments, includes one or more of a processor, a microprocessor, a central processing unit (CPU), a graphics processing unit (GPU), a single-core processor, a multi- core processor, a microcontroller, a programmable logic device (PLD) (e.g., field programmable gate array (FPGA)), an application specific integrated circuit (ASIC), a digital signal processing (DSP) device, or other logic device, one or more memories for storing executable instructions (e.g., software, firmware, or other instructions), and/or or any other appropriate combination of processing device and/or memory to execute instructions to perform any of the various operations described herein. The logic device 110 may be configured, by hardwiring, executing software instructions, or a combination of both, to perform various operations discussed herein for embodiments of the disclosure. The logic device 110 may be configured to interface and communicate with the various other components (e.g., 115, 120, 125, 130, 135, 140, 145, etc.) of the imaging system 100 to Docket No.70052.2043WO01 perform such operations. For example, the logic device 110 may be configured to process captured image data received from the imaging capture component 120, store the image data in the memory component 115, and/or retrieve stored image data from the memory component 115. In one aspect, the logic device 110 may be configured to perform various system control operations (e.g., to control communications and operations of various components of the imaging system 100), design operations (e.g., simulate manufacturing processes), calibration operations, and other image processing operations (e.g., debayering, sharpening, color correction, offset correction, bad pixel replacement, data conversion, data transformation, data compression, video analytics, etc.). [0048] The memory component 115 includes, in one embodiment, one or more memory devices configured to store data and information, including infrared image data and information. The memory component 115 may include one or more various types of memory devices including volatile and non-volatile memory devices, such as random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), non-volatile random-access memory (NVRAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically-erasable programmable read-only memory (EEPROM), flash memory, hard disk drive, and/or other types of memory. As discussed above, the logic device 110 may be configured to execute software instructions stored in the memory component 115 so as to perform method and process steps and/or operations. The logic device 110 and/or the image interface 125 may be configured to store in the memory component 115 images or digital image data captured by the image capture component 120. In some aspects, the memory component 115 may include non-volatile memory to store various non-uniformity correction (NUC) maps and/or other parameters and/or maps determined or derivable from factory calibration and/or run-time/in-field calibration. [0049] In some embodiments, a separate machine-readable medium 150 (e.g., a memory, such as a hard drive, a compact disk, a digital video disk, or a flash memory) may store the software instructions and/or configuration data which can be executed or accessed by a computer (e.g., a logic device or processor-based system) to perform various methods and operations, such as methods and operations associated with processing image data. In one aspect, the machine-readable medium 150 may be portable and/or located separate from the imaging device 105, with the stored software instructions and/or data provided to the imaging device 105 by coupling the machine-readable medium 150 to the imaging device 105 and/or Docket No.70052.2043WO01 by the imaging device 105 downloading (e.g., via a wired link and/or a wireless link) from the machine-readable medium 150. It should be appreciated that various modules may be integrated in software and/or hardware as part of the logic device 110, with code (e.g., software or configuration data) for the modules stored, for example, in the memory component 115. [0050] The imaging device 105 may be a video and/or still camera to capture and process images and/or videos of a scene 175. In this regard, the image capture component 120 of the imaging device 105 may be configured to capture images (e.g., still and/or video images) of the scene 175 in a particular spectrum or modality. The image capture component 120 includes an image detector circuit 165 (e.g., a visible-light detector circuit, a thermal infrared detector circuit) and a readout circuit 170 (e.g., an ROIC). For example, the image capture component 120 may include an IR imaging sensor (e.g., an IR imaging sensor array) configured to detect IR radiation in the near, middle, and/or far IR spectrum and provide IR images (e.g., IR image data or signal) representative of the IR radiation from the scene 175. For example, the image detector circuit 165 may capture (e.g., detect, sense) IR radiation with wavelengths in the range from around 700 nm to around 2 mm, or portion thereof. For example, in some aspects, the image detector circuit 165 may be sensitive to (e.g., better detect) SWIR radiation, mid-wave IR (MWIR) radiation (e.g., EM radiation with wavelength of 2 μm to 5 μm), and/or long-wave IR (LWIR) radiation (e.g., EM radiation with wavelength of 7 μm to 14 μm), or any desired IR wavelengths (e.g., generally in the 0.7 μm to 14 μm range). In other aspects, the image detector circuit 165 may capture radiation from one or more other wavebands of the EM spectrum, such as visible light, ultraviolet light, and so forth. [0051] The image detector circuit 165 may capture image data (e.g., infrared image data) associated with the scene 175. To capture an image, the image detector circuit 165 may detect image data of the scene 175 (e.g., in the form of EM radiation) received through an aperture 180 of the imaging device 105 and generate pixel values of the image based on the scene 175. An image may be referred to as a frame or an image frame. In some cases, the image detector circuit 165 may include an array of detectors (e.g., also referred to as an array of pixels) that can detect radiation of a certain waveband, convert the detected radiation into electrical signals (e.g., voltages, currents, etc.), and generate the pixel values based on the electrical signals. Each detector in the array may capture a respective portion of the image data and generate a pixel value based on the respective portion captured by the detector. The Docket No.70052.2043WO01 pixel value generated by the detector may be referred to as an output of the detector. By way of non-limiting examples, each detector may be a photodetector, such as an avalanche photodiode, an infrared photodetector, a quantum well infrared photodetector, a microbolometer, or other detector capable of converting EM radiation (e.g., of a certain wavelength) to a pixel value. The array of detectors may be arranged in rows and columns. In some embodiments, each detector may be referred to as a pixel and may include a bridge and a leg structure to propagate signals from the bridge to the readout circuit 170. [0052] The image may be, or may be considered, a data structure that includes pixels and is a representation of the image data associated with the scene 175, with each pixel having a pixel value that represents EM radiation emitted or reflected from a portion of the scene 175 and received by a detector that generates the pixel value. Based on context, a pixel may refer to a detector of the image detector circuit 165 that generates an associated pixel value or a pixel (e.g., pixel location, pixel coordinate) of the detector output image formed from the generated pixel values. In an embodiment, the image may be an infrared image (e.g., a thermal infrared image). For a thermal infrared image (e.g., also referred to as a thermal image), each pixel value of the thermal infrared image may represent a temperature of a corresponding portion of the scene 175. [0053] In an aspect, the pixel values generated by the image detector circuit 165 may be represented in terms of digital count values generated based on the electrical signals obtained from converting the detected radiation. For example, in a case that the image detector circuit 165 includes or is otherwise coupled to an analog-to-digital (ADC) circuit, the ADC circuit may generate digital count values based on the electrical signals. For an ADC circuit that can represent an electrical signal using 14 bits, the digital count value may range from 0 to 16,383. In such cases, the pixel value of the detector may be the digital count value output from the ADC circuit. In other cases (e.g., in cases without an ADC circuit), the pixel value may be analog in nature with a value that is, or is indicative of, the value of the electrical signal. As an example, for infrared imaging, a larger amount of IR radiation being incident on and detected by the image detector circuit 165 (e.g., an IR image detector circuit) is associated with higher digital count values and higher temperatures. [0054] The readout circuit 170 may be utilized as an interface between the image detector circuit 165 that detects the image data and the logic device 110 that processes the detected image data as read out by the readout circuit 170, with communication of data from the Docket No.70052.2043WO01 readout circuit 170 to the logic device 110 facilitated by the image interface 125. An image capturing frame rate may refer to the rate (e.g., detector output images per second) at which images are detected/output in a sequence by the image detector circuit 165 and provided to the logic device 110 by the readout circuit 170. The readout circuit 170 may read out the pixel values generated by the image detector circuit 165 in accordance with an integration time (e.g., also referred to as an integration period). In various embodiments, a combination of the image detector circuit 165 and the readout circuit 170 may be, may include, or may together provide an FPA. In some aspects, the image detector circuit 165 may be a thermal image detector circuit that includes an array of microbolometers, and the combination of the image detector circuit 165 and the readout circuit 170 may be referred to as a microbolometer FPA. In some cases, the array of microbolometers may be arranged in rows and columns. A microbolometer is an example of a type of infrared detector that may be used within an infrared imaging device (e.g., an infrared camera). For example, the microbolometer may be fabricated on a monolithic silicon substrate to form an infrared (image) detector array, with each microbolometer of the infrared detector array functioning as a pixel to produce a two-dimensional image. The change in resistance of each microbolometer may be translated into a time-multiplexed electrical signal by an ROIC. Additional details regarding FPAs and microbolometers may be found, for example, in U.S. Patent Nos.5,756,999, 6,028,309, 6,812,465, 7,034,301, and 11,824,078, which are herein incorporated by reference in their entireties. [0056] The microbolometers may detect IR radiation and generate pixel values based on the detected IR radiation. For example, in some cases, the microbolometers may be thermal IR detectors that detect IR radiation in the form of heat energy and generate pixel values based on the amount of heat energy detected. The microbolometers may absorb incident IR radiation and produce a corresponding change in temperature in the microbolometers. The change in temperature is associated with a corresponding change in resistance of the microbolometers. With each microbolometer functioning as a pixel, a two-dimensional image or picture representation of the incident IR radiation can be generated by translating the changes in resistance of each microbolometer into a time-multiplexed electrical signal. The translation may be performed by the ROIC. The microbolometer FPA may include an IR sensing element formed of IR detecting materials such as amorphous silicon (a-Si), vanadium oxide (VOx), a combination thereof, and/or other detecting material(s). In an aspect, for a microbolometer FPA, the integration time may be, or may be indicative of, a time interval Docket No.70052.2043WO01 during which the microbolometers are biased. In this case, a longer integration time may be associated with higher gain of the IR signal, but not more IR radiation being collected. The IR radiation may be collected in the form of heat energy by the microbolometers. [0057] In some cases, the image capture component 120 may include one or more optical components and/or one or more filters. The optical component(s) may include one or more windows, lenses, mirrors, beamsplitters, beam couplers, and/or other components to direct and/or focus radiation to the image detector circuit 165. The optical component(s) may include components each formed of material and appropriately arranged according to desired transmission characteristics, such as desired transmission wavelengths and/or ray transfer matrix characteristics. The filter(s) may be adapted to pass radiation of some wavelengths but substantially block radiation of other wavelengths. For example, the image capture component 120 may be an IR imaging device that includes one or more filters adapted to pass IR radiation of some wavelengths while substantially blocking IR radiation of other wavelengths (e.g., MWIR filters, thermal IR filters, and narrow-band filters). In this example, such filters may be utilized to tailor the image capture component 120 for increased sensitivity to a desired band of IR wavelengths. In an aspect, an IR imaging device may be referred to as a thermal imaging device when the IR imaging device is tailored for capturing thermal IR images. Other imaging devices, including IR imaging devices tailored for capturing infrared IR images outside the thermal range, may be referred to as non-thermal imaging devices. [0058] In one specific, not-limiting example, the image capture component 120 may include an IR imaging sensor having an FPA of detectors responsive to IR radiation including near infrared (NIR), SWIR, MWIR, LWIR, and/or very-long wave IR (VLWIR) radiation. In some other embodiments, alternatively or in addition, the image capture component 120 may include a complementary metal oxide semiconductor (CMOS) sensor or a charge-coupled device (CCD) sensor that can be found in any consumer camera (e.g., visible light camera). [0059] In some embodiments, the imaging system 100 includes a shutter 185. The shutter 185 may be operated to be selectively inserted into an optical path between the scene 175 and the image capture component 120 to expose or block the aperture 180. In some cases, the shutter 185 may be moved (e.g., slid, rotated, etc.) manually (e.g., by a user of the imaging system 100) and/or via an actuator (e.g., controllable by the logic device 110 in response to Docket No.70052.2043WO01 user input or autonomously, such as an autonomous decision by the logic device 110 to perform a calibration of the imaging device 105). [0060] When the shutter 185 is outside of the optical path to expose the aperture 180, the electromagnetic radiation from the scene 175 may be received by the image detector circuit 165 (e.g., via one or more optical components and/or one or more filters). As such, the image detector circuit 165 captures images of the scene 175. The shutter 185 may be referred to as being in an open position or simply as being open. When the shutter 185 is inserted into the optical path to block the aperture 180, the electromagnetic radiation from the scene 175 is blocked from the image detector circuit 165. As such, the image detector circuit 165 captures images of the shutter 185. The shutter 185 may be referred to as being in a closed position or simply as being closed. In some cases, the shutter 185 may block the aperture 180 during a calibration process, in which the shutter 185 may be used as a uniform blackbody (e.g., a substantially uniform blackbody). For example, in some cases, a surface of the shutter 185 imaged by the image detector circuit 165 may be implemented by a uniform blackbody coating. In some cases, such as for an imaging device without a shutter or with a broken shutter or as an alternative to the shutter 185, a case or holster of the imaging device 105, a lens cap, a cover, a wall of a room, or other suitable object/surface may be used to provide a uniform blackbody (e.g., substantially uniform blackbody). [0061] Other imaging sensors that may be embodied in the image capture component 120 include a photonic mixer device (PMD) imaging sensor or other time of flight (ToF) imaging sensor, LIDAR imaging device, RADAR imaging device, millimeter imaging device, positron emission tomography (PET) scanner, single photon emission computed tomography (SPECT) scanner, ultrasonic imaging device, or other imaging devices operating in particular modalities and/or spectra. It is noted that for some of these imaging sensors that are configured to capture images in particular modalities and/or spectra (e.g., infrared spectrum, etc.), they are more prone to produce images with low frequency shading, for example, when compared with a typical CMOS-based or CCD-based imaging sensors or other imaging sensors, imaging scanners, or imaging devices of different modalities. [0062] The images, or the digital image data corresponding to the images, provided by the image capture component 120 may be associated with respective image dimensions (also referred to as pixel dimensions). An image dimension, or pixel dimension, generally refers to the number of pixels in an image, which may be expressed, for example, in width multiplied Docket No.70052.2043WO01 by height for two-dimensional images or otherwise appropriate for relevant dimension or shape of the image. Thus, images having a native resolution may be resized to a smaller size (e.g., having smaller pixel dimensions) in order to, for example, reduce the cost of processing and analyzing the images. Filters (e.g., a non-uniformity estimate) may be generated based on an analysis of the resized images. The filters may then be resized to the native resolution and dimensions of the images, before being applied to the images. [0063] The image interface 125 may include, in some embodiments, appropriate input ports, connectors, switches, and/or circuitry configured to interface with external devices (e.g., a remote device 155 and/or other devices) to receive images (e.g., digital image data) generated by or otherwise stored at the external devices. In an aspect, the image interface 125 may include a serial interface and telemetry line for providing metadata associated with image data. The received images or image data may be provided to the logic device 110. In this regard, the received images or image data may be converted into signals or data suitable for processing by the logic device 110. For example, in one embodiment, the image interface 125 may be configured to receive analog video data and convert it into suitable digital data to be provided to the logic device 110. [0064] The image interface 125 may include various standard video ports, which may be connected to a video player, a video camera, or other devices capable of generating standard video signals, and may convert the received video signals into digital video/image data suitable for processing by the logic device 110. In some embodiments, the image interface 125 may also be configured to interface with and receive images (e.g., image data) from the image capture component 120. In other embodiments, the image capture component 120 may interface directly with the logic device 110. [0065] The control component 130 includes, in one embodiment, a user input and/or an interface device, such as a rotatable knob (e.g., a potentiometer), push buttons, slide bar, keyboard, and/or other devices, that is adapted to generate a user input control signal. The logic device 110 may be configured to sense control input signals from a user via the control component 130 and respond to any sensed control input signals received therefrom. The logic device 110 may be configured to interpret such a control input signal as a value, as generally understood by one skilled in the art. In one embodiment, the control component 130 may include a control unit (e.g., a wired or wireless handheld control unit) having push buttons adapted to interface with a user and receive user input control values. In one Docket No.70052.2043WO01 implementation, the push buttons and/or other input mechanisms of the control unit may be used to control various functions of the imaging device 105, such as calibration initiation and/or related control, shutter control, autofocus, menu enable and selection, field of view, brightness, contrast, noise filtering, image enhancement, and/or various other features. [0066] The display component 135 includes, in one embodiment, an image display device (e.g., a liquid crystal display (LCD)) or various other types of generally known video displays or monitors. The logic device 110 may be configured to display image data and information on the display component 135. The logic device 110 may be configured to retrieve image data and information from the memory component 115 and display any retrieved image data and information on the display component 135. The display component 135 may include display circuitry, which may be utilized by the logic device 110 to display image data and information. The display component 135 may be adapted to receive image data and information directly from the image capture component 120, logic device 110, and/or image interface 125, or the image data and information may be transferred from the memory component 115 via the logic device 110. In some aspects, the control component 130 may be implemented as part of the display component 135. For example, a touchscreen of the imaging device 105 may provide both the control component 130 (e.g., for receiving user input via taps and/or other gestures) and the display component 135 of the imaging device 105. [0067] The sensing component 140 includes, in one embodiment, one or more sensors of various types, depending on the application or implementation requirements, as would be understood by one skilled in the art. Sensors of the sensing component 140 provide data and/or information to at least the logic device 110. In one aspect, the logic device 110 may be configured to communicate with the sensing component 140. In various implementations, the sensing component 140 may provide information regarding environmental conditions, such as outside temperature, lighting conditions (e.g., day, night, dusk, and/or dawn), humidity level, specific weather conditions (e.g., sun, rain, and/or snow), distance (e.g., laser rangefinder or time-of-flight camera), and/or whether a tunnel or other type of enclosure has been entered or exited. The sensing component 140 may represent conventional sensors as generally known by one skilled in the art for monitoring various conditions (e.g., environmental conditions) that may have an effect (e.g., on the image appearance) on the image data provided by the image capture component 120. Docket No.70052.2043WO01 [0068] In some implementations, the sensing component 140 (e.g., one or more sensors) may include devices that relay information to the logic device 110 via wired and/or wireless communication. For example, the sensing component 140 may be adapted to receive information from a satellite, through a local broadcast (e.g., radio frequency (RF)) transmission, through a mobile or cellular network and/or through information beacons in an infrastructure (e.g., a transportation or highway information beacon infrastructure), or various other wired and/or wireless techniques. In some embodiments, the logic device 110 can use the information (e.g., sensing data) retrieved from the sensing component 140 to modify a configuration of the image capture component 120 (e.g., adjusting a light sensitivity level, adjusting a direction or angle of the image capture component 120, adjusting an aperture, etc.). The sensing component 140 may include a temperature sensing component to provide temperature data (e.g., one or more measured temperature values) various components of the imaging device 105, such as the image detection circuit 165 and/or the shutter 185. By way of non-limiting examples, a temperature sensor may include a thermistor, thermocouple, thermopile, pyrometer, and/or other appropriate sensor for providing temperature data. [0069] In some embodiments, various components of the imaging system 100 may be distributed and in communication with one another over a network 160. In this regard, the imaging device 105 may include a network interface 145 configured to facilitate wired and/or wireless communication among various components of the imaging system 100 over the network 160. In such embodiments, components may also be replicated if desired for particular applications of the imaging system 100. That is, components configured for same or similar operations may be distributed over a network. Further, all or part of any one of the various components may be implemented using appropriate components of the remote device 155 (e.g., a conventional digital video recorder (DVR), a computer configured for image processing, and/or other device) in communication with various components of the imaging system 100 via the network interface 145 over the network 160, if desired. Thus, for example, all or part of the logic device 110, all or part of the memory component 115, and/or all of part of the display component 135 may be implemented or replicated at the remote device 155. In some embodiments, the imaging system 100 may not include imaging sensors (e.g., image capture component 120), but instead receive images or image data from imaging sensors located separately and remotely from the logic device 110 and/or other components of the imaging system 100. It will be appreciated that many other combinations of distributed Docket No.70052.2043WO01 implementations of the imaging system 100 are possible, without departing from the scope and spirit of the disclosure. [0070] Furthermore, in various embodiments, various components of the imaging system 100 may be combined and/or implemented or not, as desired or depending on the application or requirements. In one example, the logic device 110 may be combined with the memory component 115, image capture component 120, image interface 125, display component 135, sensing component 140, and/or network interface 145. In another example, the logic device 110 may be combined with the image capture component 120, such that certain functions of the logic device 110 are performed by circuitry (e.g., a processor, a microprocessor, a logic device, a microcontroller, etc.) within the image capture component 120. [0071] FIG.2 illustrates a block diagram of an example image sensor assembly 200 in accordance with one or more embodiments of the present disclosure. Not all of the depicted components may be required, however, and one or more embodiments may include additional components not shown in the figure. Variations in the arrangement and type of the components may be made without departing from the spirit or scope of the claims as set forth herein. Additional components, different components, and/or fewer components may be provided. In an embodiment, the image sensor assembly 200 may be an FPA, for example, implemented as the image capture component 120 of FIG.1. [0072] The image sensor assembly 200 includes a unit cell array 205, column multiplexers 210 and 215, column amplifiers 220 and 225, a row multiplexer 230, control bias and timing circuitry 235, a digital-to-analog converter (DAC) 240, and a data output buffer 245. In some aspects, operations of and/or pertaining to the unit cell array 205 and other components may be performed according to a system clock and/or synchronization signals (e.g., line synchronization (LSYNC) signals). The unit cell array 205 includes an array of unit cells. In an aspect, each unit cell may include a detector (e.g., a pixel) and interface circuitry. The interface circuitry of each unit cell may provide an output signal, such as an output voltage or an output current, in response to a detection signal (e.g., detection current, detection voltage) provided by the detector of the unit cell. The output signal may be indicative of the magnitude of EM radiation received by the detector and may be referred to as image pixel data or simply image data. The column multiplexer 215, column amplifiers 220, row multiplexer 230, and data output buffer 245 may be used to provide the output signals from the unit cell array 205 as a data output signal on a data output line 250. The output signals on Docket No.70052.2043WO01 the data output line 250 may be provided to components downstream of the image sensor assembly 200, such as processing circuitry (e.g., the logic device 110 of FIG.1), memory (e.g., the memory component 115 of FIG.1), display device (e.g., the display component 135 of FIG.1), and/or other component to facilitate processing, storage, and/or display of the output signals. The data output signal may be an image formed of the pixel values for the image sensor assembly 200. In this regard, the column multiplexer 215, the column amplifiers 220, the row multiplexer 230, and the data output buffer 245 may collectively provide an ROIC (or portion thereof) of the image sensor assembly 200. In an aspect, the interface circuitry may be considered part of the ROIC, or may be considered an interface between the detectors and the ROIC. In some embodiments, components of the image sensor assembly 200 may be implemented such that the unit cell array 205 and the ROIC may be part of a single die. [0073] The column amplifiers 225 may generally represent any column processing circuitry as appropriate for a given application (analog and/or digital), and is not limited to amplifier circuitry for analog signals. In this regard, the column amplifiers 225 may more generally be referred to as column processors in such an aspect. Signals received by the column amplifiers 225, such as analog signals on an analog bus and/or digital signals on a digital bus, may be processed according to the analog or digital nature of the signal. As an example, the column amplifiers 225 may include circuitry for processing digital signals. As another example, the column amplifiers 225 may be a path (e.g., no processing) through which digital signals from the unit cell array 205 traverses to get to the column multiplexer 215. As another example, the column amplifiers 225 may include an ADC for converting analog signals to digital signals (e.g., to obtain digital count values). These digital signals may be provided to the column multiplexer 215. [0074] Each unit cell may receive a bias signal (e.g., bias voltage, bias current) to bias the detector of the unit cell to compensate for different response characteristics of the unit cell attributable to, for example, variations in temperature, manufacturing variances, and/or other factors. For example, the control bias and timing circuitry 235 may generate the bias signals and provide them to the unit cells. By providing appropriate bias signals to each unit cell, the unit cell array 205 may be effectively calibrated to provide accurate image data in response to light (e.g., visible-light, IR light) incident on the detectors of the unit cells. In an aspect, the control bias and timing circuitry 235 may be, may include, or may be a part of, a logic circuit. Docket No.70052.2043WO01 [0075] The control bias and timing circuitry 235 may generate control signals for addressing the unit cell array 205 to allow access to and readout of image data from an addressed portion of the unit cell array 205. The unit cell array 205 may be addressed to access and readout image data from the unit cell array 205 row by row, although in other implementations the unit cell array 205 may be addressed column by column or via other manners. [0076] The control bias and timing circuitry 235 may generate bias values and timing control voltages. In some cases, the DAC 240 may convert the bias values received as, or as part of, data input signal on a data input signal line 255 into bias signals (e.g., analog signals on analog signal line(s) 260) that may be provided to individual unit cells through the operation of the column multiplexer 210, column amplifiers 220, and row multiplexer 230. For example, the DAC 240 may drive digital control signals (e.g., provided as bits) to appropriate analog signal levels for the unit cells. In some technologies, a digital control signal of 0 or 1 may be driven to an appropriate logic low voltage level or an appropriate logic high voltage level, respectively. In another aspect, the control bias and timing circuitry 235 may generate the bias signals (e.g., analog signals) and provide the bias signals to the unit cells without utilizing the DAC 240. In this regard, some implementations do not include the DAC 240, data input signal line 255, and/or analog signal line(s) 260. In an embodiment, the control bias and timing circuitry 235 may be, may include, may be a part of, or may otherwise be coupled to the logic device 110 and/or image capture component 120 of FIG.1. [0077] In an embodiment, the image sensor assembly 200 may be implemented as part of an imaging device (e.g., the imaging device 105). In addition to the various components of the image sensor assembly 200, the imaging device may also include one or more processors, memories, logic, displays, interfaces, optics (e.g., lenses, mirrors, beamsplitters), and/or other components as may be appropriate in various implementations. In an aspect, the data output signal on the data output line 250 may be provided to the processors (not shown) for further processing. For example, the data output signal may be an image formed of the pixel values from the unit cells of the image sensor assembly 200. The processors may perform operations such as non-uniformity correction (e.g., flat-field correction or other calibration technique), spatial and/or temporal filtering, and/or other operations. The images (e.g., processed images) may be stored in memory (e.g., external to or local to the imaging system) and/or displayed on a display device (e.g., external to and/or integrated with the imaging Docket No.70052.2043WO01 system). The various components of FIG.2 may be implemented on a single chip or multiple chips. Furthermore, while the various components are illustrated as a set of individual blocks, various of the blocks may be merged together or various blocks shown in FIG.2 may be separated into separate blocks. [0078] It is noted that in FIG.2 the unit cell array 205 is depicted as an 8×8 (e.g., 8 rows and 8 columns of unit cells. However, the unit cell array 205 may be of other array sizes. By way of non-limiting examples, the unit cell array 205 may include 512×512 (e.g., 512 rows and 512 columns of unit cells), 1024×1024, 2048×2048, 4096×4096, 8192×8192, and/or other array sizes. In some cases, the array size may have a row size (e.g., number of detectors in a row) different from a column size (e.g., number of detectors in a column). Examples of frame rates may include 30 Hz, 60 Hz, and 120 Hz. In an aspect, each unit cell of the unit cell array 205 may represent a pixel. [0079] FIG.3 shows a physical layout diagram of a microbolometer 300 in accordance with one or more embodiments of the present disclosure. The microbolometer 300 includes a bridge portion 302 having a light sensor 304 and bridge contacts 306 that couple the sensor 304 to a first end of legs 308. The legs 308 each couple the sensor 304 to one of contacts 310. [0080] Each contact 310 may couple one or more associated microbolometers 300 to associated readout circuitry of a readout integrated circuit (ROIC, not shown). For example, a first contact 310 may be used to provide a reference or bias voltage to the microbolometer and a second contact 310 may be used to provide a signal path from the microbolometer to the ROIC by which signals corresponding to infrared light absorbed by the microbolometer can be read out. Further descriptions of ROIC and microbolometer circuits may be found in U.S. Patent No.6,028,309, which is incorporated by reference in its entirety herein for all purposes. [0081] The sensor 304 may be arranged to convert incident light such as infrared light into detectable electrical signals based on changes in electrical properties of the sensor (e.g., changes in resistivity) due to changes in temperature of the sensor when the light is incident. According to an embodiment, the sensor 304 may include a resistive material, which may be formed of a high temperature coefficient of resistivity (TCR) material (e.g., vanadium oxide (VOx), titanium oxide (TiOx), or amorphous silicon). The resistive material may be suspended above the ROIC on the bridge 302 and coupled to its contacts 310 via the legs 308. Docket No.70052.2043WO01 [0082] According to various embodiments, each contact 310 may be attached to a portion of a leg 308 that bends downward toward the ROIC (e.g., contact 310 may be formed on a substrate such as the ROIC and the leg 308 may include a portion that runs at a non- perpendicular angle to the substrate from a first height above the substrate such as the height of the bridge downward to the substrate contact) and/or each contact 310 may include a portion that extends downward (e.g., in the negative z-direction of FIG.3) from the leg 308 to the surface of the ROIC. The legs 308 may be formed from one or more layers of conductive material such as, for example, titanium, nickel chromium, and/or other suitable conductive materials. [0083] In order to provide the legs 308 having a width and a length that is sufficient to provide suitable performance for microbolometer 300 without reducing the fill-factor of an array of microbolometers in which microbolometer 300 is included, legs 308 may be legs that run along paths in and/or parallel to the x-y plane of FIG.3 as shown and have an extended dimension that extends in a direction parallel to the z-direction of FIG.3. The legs 308 may include bend portions 312. The bend portions 312 may have additional electrical coupling and/or support structures as described in further detail hereinafter. [0084] A plane such as the x-y plane of FIG.3 may be defined by the bridge of the microbolometer (e.g., the bridge may include a planar sensor layer such as a resistive layer that defines a plane or a plane may be defined that passes through multiple bridges in a microbolometer array) or by the surface of a substrate (e.g., an ROIC substrate) to which the microbolometer array is coupled and disposed above. [0085] As shown, according to an embodiment, a leg may include a conductive (e.g., metal) portion and, if desired, insulating material on one or more sides of the conductive portion. However, this is merely illustrative. According to various embodiments, conductive portion may be partially or completely surrounded by dielectric material or may be free of dielectric material. Various examples of implementations of the legs 308 and processes to form the legs 308 and/or other structures (e.g., the bridge portion 302 and/or the contacts 310) are described hereinafter. [0086] FIGS.4A through 4T illustrate cross-sectional side views associated with an example process for forming a bolometer 500 in accordance with one or more embodiments of the present disclosure. FIG.5 illustrates a top-down view of the bolometer 500 corresponding to the cross-sectional side view of FIG.4T in accordance with one or more Docket No.70052.2043WO01 embodiments of the present disclosure. In an embodiment, the bolometer 500 is one of an array of bolometers of an infrared imaging device and may be referred to as a pixel. In FIG. 4A, a readout circuit wafer 400 (e.g., ROIC wafer) is provided. The readout circuit wafer 400 includes a substrate 401, an overglass layer 402, and a metal layer 403. Bolometer processing is performed on the readout circuit wafer 400 to form the bolometer 500 that is coupled to the readout circuit wafer 400. An example of bolometer processing is described with reference to FIGS.4B through 4T. In FIG.4B, pads 404 are disposed on the readout circuit wafer 400. The pads 404 may form part of one or more metal layers. In FIG.4C, a release layer 406 is disposed on the dielectric layer 402 and on the pads 404, and a protection layer 408 is disposed on the release layer 406. In some cases, one or more alignment marks may be etched in the protection layer 408 (e.g., to facilitate alignment for the bolometer processing using one or more masks). In FIG.4D, a metal layer 412 (e.g., metal absorber layer) is disposed on the protection layer 408, and a dielectric layer 414 (e.g., Si3N4/SiO2) is disposed on the metal layer 412. In FIG.4E, the protection layer 408, the metal layer 412, and the dielectric layer 414 are etched. Patterning may include depositing a photoresist layer and exposing the photoresist layer appropriate to define portions of the protection layer 408, the metal layer 412, and the dielectric layer 414 to be etched. A block 416 may identify a portion of the layers 408, 412, and 414 that remain after etching. In some cases, the block 416 may represent a mask material utilized to facilitate patterning and etching to obtain the layers 408, 412, and 414 as shown in FIG.4E. [0087] In FIG.4F, a dielectric layer 418 (e.g., thin film oxide layer) and a metal layer 420 are disposed, and the metal layer 420 is etched. Blocks 421 may identify portions of the metal layer 420 that remain after etching. In some cases, the blocks 421 may represent mask material utilized to facilitate patterning and etching to obtain the metal layer 420 as shown in FIG.4F. In FIG.4G, a dielectric layer 422 (e.g., thin film oxide layer), a resistive layer 424 (e.g., VOx layer), and a dielectric layer 426 are disposed. The dielectric layer 422 is in contact with the dielectric layer 418, the metal layer 420, and the resistive layer 424. The dielectric layer 426 is in contact with the resistive layer 424. In FIG.4H, the resistive layer 424 and the dielectric layer 426 are etched. Such an etch may help define a bridge portion of the bolometer 500 to be formed. A block 428 may identify portions of the resistive layer 424 and the dielectric layer 426 that remain after etching. In some cases, the block 428 may represent mask material utilized to facilitate patterning and etching to obtain the resistive layer 424 and the dielectric layer 426 as shown in FIG.4H. The block 428 may be Docket No.70052.2043WO01 considered as defining a sensing portion of a bridge and a non-sensing portion of the bridge. In FIG.4I, one or more patterning operations and etching operations are performed to remove (e.g., etch) the release layer 406, the dielectric layer 418, and the dielectric layer 422 to form a trench 432 down to the readout circuit wafer 400. In an aspect, a process of defining the trench 432 (and, in some cases, trenches associated with other pixels of the bolometer 500) may be referred to as a reticulation pattern. A block 430 may identify portions of the layers 422, 418, and 406 to be removed to form the trench 432. [0088] In FIG.4J, a contact metal layer 434 is disposed. The contact metal layer 434 is disposed on at least one of the pads 404 (e.g., left pad in FIG.4J) to couple the bridge portion of the bolometer 500 to the readout circuit wafer 400. The contact metal layer 434 is in contact with the release layer 406, the dielectric layer 418, the dielectric layer 422, and at least one of the pads 404. The contact metal layer 434 is utilized to form a contact basket. In FIG.4K, the contact metal layer 434 is etched to expose the dielectric layer 426 and 422. A block 436 may identify a portion of the contact metal layer 434 that is removed by etching. In some cases, the block 436 may represent mask material utilized to facilitate patterning and etching to obtain the contact metal layer 434 as shown in FIG.4K. In FIG.4L, a dielectric layer 438 is disposed. In FIG.4M, the dielectric layer 438 is etched. A block 440 may identify a portion of the dielectric layer 438 that remains after etching. In some cases, the block 440 may represent mask material utilized to facilitate patterning and etching to obtain the dielectric layer 438 as shown in FIG.4M. In FIG.4N, the contact metal layer 434 is etched. A block 442 may identify a portion of the contact metal layer 434 that remains after etching. In some cases, the block 442 may represent mask material utilized to facilitate patterning and etching to obtain the contact metal layer 434 as shown in FIG.4N. [0089] In FIG.4O, the dielectric layer 438, the dielectric layer 426, and the resistive layer 424 are etched to expose the resistive layer 424. A block 444 may identify a portion of the layers 438, 426, and 424 that is removed after etching. In some cases, the block 444 may represent mask material utilized to facilitate patterning and etching to obtain the layers 438, 426, and 424 as shown in FIG.4O. In FIG.4P, a leg metal layer 446 is disposed. In FIG. 4Q, the leg metal layer 446 is etched. Blocks 448 may identify portions of the leg metal layer 446 that remain after etching. In some cases, the blocks 448 may represent mask material utilized to facilitate patterning and etching to obtain the leg metal layer 446 as shown in FIG. 4Q. In FIG.4R, a dielectric layer 450 (e.g., thin film layer) is disposed. Docket No.70052.2043WO01 [0090] In FIG.4S, portions of the dielectric layer 412, the dielectric layer 414, the dielectric layer 418, the dielectric layer 422, the metal layer 420, the leg metal layer 446, and the dielectric layer 450 are removed, thus forming a bridge 453. Blocks 452 may identify portions of the layers 412, 414, 418, 422, 420, 446, and 450 that remain after etching. In some cases, the blocks 452 may represent mask material utilized to facilitate patterning and etching to obtain the layers 412, 414, 418, 422, 420, 446, and 450 as shown in FIG.4S. In FIGS.4T and 5, one or more patterning operations and etching operations are performed and the release layer 406 removed to form the bolometer 500. The bolometer 500 includes the bridge 453 and legs 460 and 461. Contacts 474 and 476 of the bolometer 500 extend to couple the legs 460 and 461, respectively, to the readout circuit wafer 400. The etching operations may cause a formation of tails 454, 456, and 458 and gaps 462, 464, and 466, respectively, above the tails 454, 456, and 458. In other cases of bolometer processing, tails are not formed (e.g., formation of tails may be avoided if desired). In FIGS.4T and 5, a sensing portion of the bridge 453 is associated with a region 470, and a non-sensing portion of the bridge 453 is associated with a region 472 surrounding the region 470. In some embodiments, the bridge 453 may include a metal layer (e.g., an absorber layer) disposed on the dielectric layer 426. A cap layer may be disposed on this metal layer. [0091] In one or more embodiments, leg structures for connecting a bridge (e.g., a microbolometer bridge) to a contact (e.g., an ROIC contact) and processes/flows for forming such leg structures are provided herein. In some embodiments, the leg structures have constructions having dimensions appropriate to provide lower thermal conductance. In some aspects, such leg structures have a conductor element (e.g., leg metal) that is thin (e.g., along a vertical z-direction) and narrow (e.g., along a horizontal x-direction). [0092] It is noted that structures and/or portions thereof (e.g., a layer(s) of material)) in the present disclosure may be described using terms such as flat, vertical, parallel, perpendicular, and so forth. Due to tolerances associated with dimensional aspects and/or fabrication processes/flows, such terms generally describe the structures and/or portions thereof in a nominal/substantial sense. As one example, a layer described as being a flat layer may correspond to a nominally/substantially flat layer. As another example, a layer described as being vertical and thus parallel to the z-direction may correspond to a nominally/substantially vertical layer that is nominally/substantially parallel to the z-direction. Although various openings are shown as being circular or elliptical, the openings may be of other shapes such as square, rectangular, trapezoidal, etc. Furthermore, in any implementation, what is depicted Docket No.70052.2043WO01 as one layer of material (e.g., dielectric layer, conductive layer, etc.) may be realized with multiple layers of materials, where each layer may be of a thickness and/or a material that is the same or different from an adjacent layer. As examples, a dielectric layer may refer to and/or be realized as a single dielectric layer or multiple dielectric layers formed by multi- layer deposition of mixed dielectrics, and, similarly, a metal layer may refer to and/or be realized as a single metal layer or multiple metal layers of mixed metals. [0093] FIGS.6A through 6J illustrate leg structures 605, 610, 615, 620, 625, 630, 635, 640, 645, and 650 in accordance with one or more embodiments of the present disclosure. The leg structures 605, 610, 615, 620, 625, 630, 635, 640, 645, and 650 are described further herein in relation to example processes/flows and/or variations thereto. The leg structures 605, 610, 615, 620, 625, 630, 635, 640, 645, and 650 extend along three directions (e.g., three orthogonal directions) x, y, and z, as shown by the coordinate system in FIGS.6A through 6J. [0094] The leg structure 605 of FIG.6A includes a dielectric layer 704, a conductive layer 710, a dielectric layer 712, and a dielectric layer 714. The conductive layer 710 is disposed on the dielectric layer 704. The dielectric layer 712 is disposed on the conductive layer 710. The dielectric layer 714 is disposed on the dielectric layer 704, the conductive layer 710, and the dielectric layer 712. In this regard, the dielectric layer 714 is disposed along sidewalls of the conductive layer 710 and along sidewalls and angled edge of the dielectric layer 712. A height (e.g., vertical z-direction) of the conductive layer 710 is less than a height of the dielectric layer 714. In an aspect, the dielectric layer 704, the conductive layer 710, the dielectric layer 712, and the dielectric layer 714 may be referred to as an L1 dielectric layer, a leg metal layer, an L₂ dielectric layer, and an L₃ dielectric layer, respectively. In some embodiments, for explanatory purposes, the leg structure 605 may be formed using an example process/flow shown in FIGS.7A through 7C. [0095] The leg structure 610 of FIG.6B includes a dielectric layer 804, a conductive layer 806, a dielectric layer 812, and a dielectric layer 814. The conductive layer 806 is disposed on the dielectric layer 804. The dielectric layer 812 is disposed on the conductive layer 806. The dielectric layer 814 is disposed on the dielectric layer 804, the conductive layer 806, and the dielectric layer 812. In this regard, the dielectric layer 814 is disposed along sidewalls of the conductive layer 806 and along sidewalls and arc of the dielectric layer 812. A height (e.g., vertical z-direction) of the conductive layer 806 is less than a height of the dielectric layer 814. In an aspect, the dielectric layer 804, the conductive layer 806, the dielectric layer Docket No.70052.2043WO01 812, and the dielectric layer 814 may be referred to as an L1 dielectric layer, a leg metal layer, an L₂ dielectric layer, and an L₃ dielectric layer, respectively. In some embodiments, for explanatory purposes, the leg structure 610 may be formed using an example process/flow shown in FIGS.8A through 8C. [0096] The leg structure 615 of FIG.6C may illustrate a variation of the leg structures 605 and 610 without the dielectric layer 712 or 812, respectively. The leg structure 615 includes the dielectric layer 804, the conductive layer 806, and the dielectric layer 814. The conductive layer 806 is disposed on the dielectric layer 804. The dielectric layer 814 is disposed on the dielectric layer 804 and the conductive layer 806. In this regard, the dielectric layer 814 is disposed along sidewalls of the conductive layer 806 and around the conductive layer 806. A height (e.g., vertical z-direction) of the conductive layer 806 is less than a height of the dielectric layer 814. [0097] The leg structure 620 of FIG.6D includes a dielectric layer 906, a conductive layer 908, and a dielectric layer 910. The conductive layer 908 is disposed on the dielectric layer 906 and along a sidewall of the dielectric layer 906. The dielectric layer 910 is disposed on the dielectric layer 906 and the conductive layer 908. A height (e.g., vertical z-direction) of the conductive layer 908 is less than a height of the dielectric layer 910. In an aspect, the dielectric layer 906, the conductive layer 908, and the dielectric layer 910 may be referred to as an L1 dielectric layer, a leg metal layer, and an L2 dielectric layer, respectively. In some embodiments, for explanatory purposes, the leg structure 620 may be formed using an example process/flow shown in FIGS.9A and 9B. [0098] The leg structure 625 of FIG.6E may illustrate a variation of the leg structure 620 in which the leg structure 625 is characterized as being thinner (e.g., dimension along vertical z- direction) and narrower (e.g., dimension along horizontal x-direction) than the leg structure 620 due to the thinner and narrower dimensions of the conductive layer 908 of the leg structure 625 compared to dimensions of the conductive layer 908 of the leg structure 620, as further described herein. [0099] The leg structure 630 of FIG.6F includes a dielectric layer 1006, a conductive layer 1008, and a dielectric layer 1010. The conductive layer 1008 is disposed on the dielectric layer 1006. The dielectric layer 1010 is disposed on the conductive layer 1008. The leg structure 630 and each of the layers 1006, 1008, and 1010 may be considered as having a z- shaped or s-shaped cross section. In some embodiments, for explanatory purposes, the leg Docket No.70052.2043WO01 structure 630 may be formed using an example process/flow shown in FIGS.10A and 10B. In some cases, rather than the leg structure 630 as shown in FIG.6F, the leg structure 630 may have a tail 655 (e.g., also referred to as a residual tab or simply a residual) that is formed due to etching operation(s) performed to form the leg structure 630, thus resulting in the leg structure 635 of FIG.6G. The tail 655 may be a portion of the dielectric layer 1006. A gap 660 is between the tail 655 and a side of the dielectric layer 1006 such that the tail 655 faces the side of the dielectric layer 1006. [0100] The leg structure 640 of FIG.6H includes a dielectric layer 665, a conductive layer 670, and a dielectric layer 675. The conductive layer 670 is disposed on the dielectric layer 665. The dielectric layer 675 is disposed on the conductive layer 670 and the dielectric layer 665. In this regard, the dielectric layer 675 is disposed along a sidewall of the conductive layer 670. A height (e.g., vertical z-direction) of the conductive layer 670 is less than a height of the dielectric layer 675. Example dimensions and other aspects of the leg structure 640 are described further herein. [0101] The leg structure 645 of FIG.6I may illustrate a variation of the leg structure 640 with an additional dielectric layer 680. The conductive layer 670 is disposed on the dielectric layer 665. The dielectric layer 675 is disposed on the conductive layer 670, the dielectric layer 680, and the dielectric layer 665. In this regard, the dielectric layer 675 is disposed along a sidewall of the conductive layer 670 and along sidewalls and arc of the dielectric layer 680. A height (e.g., vertical z-direction) of the conductive layer 670 is less than a height of the dielectric layer 675. Example dimensions and other aspects of the leg structure 645 are described further herein. [0102] The leg structure 650 of FIG.6J may illustrate a variation of the leg structures 640 and 645 with additional layers. The leg structure 650 includes a dielectric layer 1310, a dielectric layer 1312, a dielectric layer 1318, a conductive layer(s) 1320, a dielectric layer 1322, a dielectric layer 1328, and a dielectric layer 1332. The dielectric layer 1312 is disposed on the dielectric layer 1310. The dielectric layer 1318 is disposed on the dielectric layer 1312. The conductive layer(s) 1320 is disposed on the dielectric layer 1318. The dielectric layer 1322 is disposed on the conductive layer(s) 1320. The dielectric layer 1328 is disposed on the dielectric layer 1322. The dielectric layer 1332 is disposed on the dielectric layer 1322, disposed on and around the dielectric layer 1328, disposed along a sidewall of the layers 1322, 1320, 1318, and 1312, and disposed on the dielectric layer 1310. In an aspect, Docket No.70052.2043WO01 the dielectric layer 1310, the dielectric layer 1312, the dielectric layer 1318, the conductive layer(s) 1320, the dielectric layer 1322, the dielectric layer 1328, and the dielectric layer 1332 may be referred to as a poly cap, an L1a dielectric, an L1b dielectric, a leg metal, a leg metal cap, an L₂ dielectric, and/or an L₃ dielectric, respectively. In an embodiment, the dielectric layer 1310, the conductive layer 1320, the dielectric layer 1328, and the dielectric layer 1332 may correspond to the dielectric layer 665, the conductive layer 670, the dielectric layer 680, and the dielectric layer 675, respectively. In some embodiments, for explanatory purposes, the leg structure 650 may be formed using an example process/flow shown in FIGS.13A through 13E. [0103] Example processes/flows and/or associated description for forming the leg structures 605, 610, 615, 620, 625, 630, 635, 640, 645, and 650 are provided in accordance with one or more embodiments of the present disclosure. It is noted that other processes/flows may be utilized to form each of these leg structures. Based on preferences and/or specifications (e.g., available resources, performance specifications), it is understood that the specific order of steps in the processes/flows may be rearranged and/or adjusted and that some steps may be removed while others may be added. In any implementation, what is depicted as one layer of material (e.g., dielectric layer, conductive layer, etc.) may be realized with multiple layers of materials, where each layer may be of a thickness and/or a material that is the same or different from an adjacent layer. Structures shown in the figures may extend along three directions (e.g., three orthogonal directions) x, y, and z. [0104] FIGS.7A through 7C illustrate cross-sectional side views associated with an example process/flow for forming the leg structure 605 of FIG.6A in accordance with one or more embodiments of the present disclosure. It is noted that other processes/flows may be utilized to form the leg structure 605. Based on preferences and/or specifications (e.g., available resources, performance specifications), it is understood that the specific order of steps in the process/flow shown in FIGS.7A through 7C may be rearranged and/or adjusted and that some steps may be removed while others may be added. In any implementation, what is depicted as one layer of material (e.g., dielectric layer, conductive layer, etc.) may be realized with multiple layers of materials, where each layer may be of a thickness and/or a material that is the same or different from an adjacent layer. Structures shown in FIGS.7A through 7C extend along three directions (e.g., three orthogonal directions) x, y, and z. Docket No.70052.2043WO01 [0105] Turning first to FIG.7A, structures S701 through S704 are shown. To arrive at the structure S701, a sacrificial layer 702 (e.g., also referred to as a release layer) is formed. The sacrificial layer 702 may be or may include a polyimide layer. To arrive at the structure S702, a dielectric layer 704 (e.g., a conformal dielectric layer) is formed (e.g., disposed, deposited) on the sacrificial layer 702. An example thickness of the sacrificial layer 702 may be between approximately 3,500 Å and approximately 4,500 Å. As non-limiting examples, the dielectric layer 704 may include an aluminum oxide (Al2O3) layer, a silicon dioxide (SiO₂) layer, and/or a silicon nitride layer. In an aspect, the dielectric layer 704 may be referred to as an L1 dielectric layer or simply an L1 dielectric. The dielectric layer 704 is a flat layer (e.g., a substantially/nominally flat layer) on a top surface of the sacrificial layer 702 and parallel (e.g., substantially/nominally parallel) to the x-y plane (e.g., the x-direction and the y-direction). The dielectric layer 704 has a substantially/nominally uniform thickness. An example thickness tL1 of the dielectric layer 704 may be between approximately 100 Å and approximately 200 Å. [0106] To arrive at the structure S703, a sacrificial layer 706 is formed on the dielectric layer 704. The sacrificial layer 706 may be or may include a polyimide layer. An example thickness t_sac of the sacrificial layer 706 may be between approximately 800 Å and approximately 1,500 Å. To arrive at the structure S704, a portion of the sacrificial layer 706 is removed. For example, a portion of the sacrificial layer 706 may be removed by patterning the sacrificial layer 706. Patterning may include depositing a photoresist layer and exposing the photoresist layer appropriate to define the portion of the sacrificial layer 706 to be removed (e.g., to be etched). In the structure S704, with the removal of a portion of the sacrificial layer 706, a vertical edge 708 of the sacrificial layer 706 is defined. In other cases, a portion of the sacrificial layer 706 may be removed such that the remaining sacrificial layer 706 is a right trapezoidal shape having an angled edge in place of the vertical edge 708 shown in the structure S704. [0107] As shown in FIG.7B, to arrive at a structure S705 from the structure S704, a conductive layer 710 is formed on the structure S704. In this regard, the conductive layer 710 is formed on the sacrificial layer 702 and the dielectric layer 704. The conductive layer 710 has a substantially/nominally uniform height/thickness. An example thickness tLM of the conductive layer 710 may be between approximately 100 Å and approximately 500 Å. The conductive layer 710 may be a metal layer or a metallic layer. As non-limiting examples, the conductive layer 710 may include a titanium (Ti) layer, a nickel-chromium (Ni-Cr) alloy, Docket No.70052.2043WO01 and/or titanium nitride (TiN) layer. For the structure S705, the vertical edge 708 may correspond to and/or be referred to as a vertical edge of the sacrificial layer 706, a vertical edge of the conductive layer 710, and/or a vertical edge of the structure S705. The conductive layer 710 may be considered as having three sections: a first section that is a flat section disposed on a top surface of the sacrificial layer 706 and parallel to the x-direction and the y-direction; a second section that is a flat section disposed on a top surface of the dielectric layer 704 and parallel to the x-direction (e.g., and thus parallel to the first section); and a third section joining the first section and the second section. In the structure S705, the third section includes a vertical section along the vertical edge 708 (e.g., a sidewall) of the sacrificial layer 702 and parallel to the z-direction (e.g., and thus perpendicular to the first and second sections and the x- and y-directions). In other cases, the vertical edge 708 may instead be an angled edge in which case the third section is at an angle relative to the first and second sections. [0108] To arrive at a structure S706, a dielectric layer 712 is formed on the structure S705. In this regard, the dielectric layer 712 is formed on the conductive layer 710. In an aspect, the dielectric layer 712 may be referred to as an L2 dielectric layer or simply an L2 dielectric. The dielectric layer 712 has a substantially/nominally uniform thickness. As non-limiting examples, the dielectric layer 712 may include an SiO2 layer, an Al2O3 layer, and/or a silicon nitride layer. An example thickness tL2p of the dielectric layer 712 may be between approximately 120 Å and approximately 180 Å. For the structure S706, the vertical edge 708 may correspond to and/or be referred to as a vertical edge of the sacrificial layer 706, a vertical edge of the conductive layer 710, a vertical edge of the dielectric layer 712, and/or a vertical edge of the structure S706. Similar to the conductive layer 710, the dielectric layer 712 may be considered as having three sections: a first section that is a flat section disposed on a top surface of the a corresponding flat section of the conductive layer 710 and parallel to the x-direction and the y-direction; a second section that is a flat section disposed on a top surface of a corresponding flat section of the dielectric layer 704 and parallel to the x- direction and the y-direction; and a third section joining the first section and the second section and disposed on a corresponding section of the conductive layer 710 along the vertical edge 708. [0109] To arrive at a structure S707, a portion of the dielectric layer 712 is removed from the structure S706. For example, the structure S706 may be patterned and etched to remove the portion of the dielectric layer 712 to arrive at the structure S707. Patterning may include Docket No.70052.2043WO01 depositing a photoresist layer and exposing the photoresist layer appropriate to define the portion of the dielectric layer 712 to be removed (e.g., to be etched). As shown by the structure S707, the remaining portion of the dielectric layer 712 may be along the vertical edge 708 (e.g., along a vertical sidewall of the conductive layer 710). [0110] As shown in FIG.7C, to arrive at a structure S708 from the structure S707, a portion of the conductive layer 710 is removed (e.g., via patterning) from the structure S707. As an example and for explanatory purposes, the structure S707 may be patterned and etched to remove a portion of the conductive layer 710. As shown in the structure S708, the dielectric layer 712 may be used as a hard mask that protects a portion of the conductive layer 710 under the dielectric layer 712 from removal (e.g., being etched). Furthermore, as also shown in the structure S708, although one or more operations (e.g., etching operations) may be performed primarily to remove the conductive layer 710, the operation(s) may remove some of the dielectric layer 712 of the structure S707. An example largest thickness t_L2 of the dielectric layer 712 may be between approximately 800 Å and approximately 1,500 Å. Although in the structure S707 the dielectric layer 712 has a right trapezoidal shape with sidewalls joined by an angled edge, the operation(s) may result in sidewalls joined by an arc. In the structure S708, a thickness t_sac of the sacrificial layer 706 is approximately a sum of t_LM of the conductive layer 710 and tL2 of the dielectric layer 712 after etching. In other cases (e.g., dependent on etching operation(s) and/or other removal operation(s) performed on the structure S707), the sum of tLM and tL2 may be less than or greater than tsac. It is noted that the thickness tLM of the conductive layer 710 as first shown in the structure S705 is nominally/substantially maintained (e.g., through operations performed to arrive at the structures S706 and S707) and may be considered or otherwise referred to as a height of the remaining portion of the conductive layer 710 as shown in the structure S708. Similarly, t_L2 may be considered or otherwise referred to as a thickness or a height of the dielectric layer 712 after etching. As t_L2 is at a highest point of the dielectric layer 712, t_L2 may be referred to as the largest thickness/height of the dielectric layer 712. A width wLM of the conductive layer 710 may be nominally/substantially equal to a largest width w_L2 of the dielectric layer 712. An example width wLM may be between approximately 100 Å and approximately 300 Å. Examples of the heights t_sac and t_LM are described above. It is noted that in some cases the dielectric layer 712 is optional. As one example, the structure S708 may be processed (e.g., etched and/or other removal process) such that the conductive layer 710 as shown in the structure S708 remains. As another example, the dielectric layer 712 may be disposed on the Docket No.70052.2043WO01 conductive layer 710 to protect the conductive layer 710, and then the dielectric layer 712 may be removed. [0111] To arrive at a structure S709, the sacrificial layer 706 is removed (e.g., via one or more etching operations). To arrive at a structure S710, a dielectric layer 714 is formed on the structure S709. In this regard, the dielectric layer 714 is formed on the dielectric layer 704, the conductive layer 710, and the dielectric layer 712. In an aspect, the dielectric layer 714 may be referred to as an L₃ dielectric layer or simply an L₃ dielectric. The dielectric layer 714 has a substantially/nominally uniform thickness tL3. As a non-limiting example, the dielectric layer 714 may include an Al₂O₃ layer, an SiO₂ layer, and/or a silicon nitride layer. An example thickness tL3 of the dielectric layer 714 may be between approximately 80 Å and approximately 150 Å. The dielectric layer 714 is disposed around and surrounds the dielectric layer 712 and the conductive layer 710. [0112] To arrive at the leg structure 605 from the structure S710, a portion of the dielectric layer 704 and a portion of the dielectric layer 714 are removed (e.g., etched to remove), and then the leg structure 605 released by removing the sacrificial layer 702. In some cases, a photoresist may be formed on the structure S710, appropriately patterned to define the leg structure 605 that would result from one or more etching operations, and removed after the etching operation(s) to obtain the leg structure 605 disposed on the remaining sacrificial layer 702, and then the remaining sacrificial layer 702 removed to release the leg structure 605. The leg structure 605 has a height t_leg (e.g., also referred to as a thickness) extending along the z-direction and a width wleg extending along the x-direction. The height tleg may be or may be around a sum of t_L1, t_LM, t_L2, and t_L3. An example width w_leg of the leg structure 605 may be between approximately 150 nm and approximately 300 nm. [0113] The leg structure 605 may be considered as having three sections. Sections 716 and 718 may be flat sections parallel to a horizontal direction (e.g., the x-direction, the y- direction) and include a respective portion of the dielectric layer 704 and a respective portion of the dielectric layer 714 on the respective portion of the dielectric layer 704. A section 720 is adjacent to and joins the sections 716 and 718. The section 720 may include a portion of the dielectric layer 704, the conductive layer 710, and a portion of the dielectric layer 714. The conductive layer 710 is disposed on the portion of the dielectric layer 704. The portion of the dielectric layer 714 extends along the horizontal direction (e.g., the x-direction) and a vertical direction (e.g., the z-direction) and may be disposed on portions of the dielectric Docket No.70052.2043WO01 layer 704, disposed along sidewalls of the conductive layer 710 (e.g., a first sidewall and a second sidewall opposite the first sidewall of the conductive layer 710), and disposed around the dielectric layer 712 (e.g., along sidewalls and angled edge of the dielectric layer 712). It is noted that such a separation of the leg structure 605 into three sections is arbitrary and made for explanatory purposes to describe the leg structure 605. The leg structure 605 may be arbitrarily separated into fewer or more than three sections. In an aspect, the leg structure 605 may be referred to as having a T-shape (or an inverted T-shape). In some embodiments, the leg structure 605 may be characterized as being a thin (e.g., dimension along the z- direction) and narrow (e.g., dimension along the x-direction) leg structure due to the thickness t_LM and the width w_LM of the conductive layer 710. [0114] FIGS.8A through 8C illustrate cross-sectional side views associated with an example process/flow for forming the leg structure 610 of FIG.6B in accordance with one or more embodiments of the present disclosure. Turning first to FIG.8A, structures S801 through S804 are shown. To arrive at the structure S801, a sacrificial layer 802 is formed. The sacrificial layer 802 may be or may include a polyimide layer. An example thickness of the sacrificial layer 802 may be between approximately 3,500 Å and approximately 4,500 Å. To arrive at the structure S802, a dielectric layer 804 (e.g., a conformal dielectric layer) is formed on the sacrificial layer 802. In an aspect, the dielectric layer 804 may be referred to as an L1 dielectric layer or simply an L1 dielectric. The dielectric layer 804 is a flat layer on a top surface of the sacrificial layer 802 and parallel to the x-direction and the y-direction. The dielectric layer 804 has a substantially/nominally uniform thickness. As non-limiting examples, the dielectric layer 804 may include an Al₂O₃ layer, an SiO₂ layer, and/or a silicon nitride layer. An example thickness tL1 of the dielectric layer 804 may be between approximately 100 Å and approximately 200 Å. [0115] To arrive at the structure S803, a conductive layer 806 is formed on the dielectric layer 804. The conductive layer 806 has a substantially/nominally uniform height/thickness. The conductive layer 806 is a flat layer on a top surface of the dielectric layer 804 and parallel to the x-direction and the y-direction. The conductive layer 806 may be a metal layer or a metallic layer. As non-limiting examples, the conductive layer 806 may include a Ti layer and/or TiN layer. An example height/thickness tLM of the conductive layer 806 may be between approximately 100 Å and approximately 500 Å. To arrive at the structure S804, a sacrificial layer 808 is formed on the conductive layer 806. The sacrificial layer 808 may be Docket No.70052.2043WO01 or may include a polyimide layer. An example thickness tsac of the sacrificial layer 808 may be between approximately 800 Å and approximately 1,500 Å. [0116] As shown in FIG.8B, to arrive at a structure S805 from the structure S804, a portion of the sacrificial layer 808 is removed. For example, a portion of the sacrificial layer 808 may be removed via one or more etching operations. In the structure S805, with the removal of a portion of the sacrificial layer 808, a vertical edge 810 of the sacrificial layer 808 is defined. In other cases, a portion of the sacrificial layer 808 may be removed such that the remaining sacrificial layer 808 is a right trapezoidal shape having an angled edge in place of the vertical edge 810 shown in the structure S805. To arrive at a structure S806, a dielectric layer 812 is formed on the structure S805. In this regard, the dielectric layer 812 is formed on the sacrificial layer 808 and the conductive layer 806. The dielectric layer 812 has a substantially/nominally uniform thickness. In an aspect, the dielectric layer 812 may be referred to as an L₂ dielectric layer or simply an L₂ dielectric. As non-limiting examples, the dielectric layer 812 may include an SiO2 layer, an Al2O3 layer, and/or a silicon nitride layer. An example thickness t_L2p of the dielectric layer 812 may be between approximately 120 Å and approximately 180 Å. For the structure S806, the vertical edge 810 may correspond to and/or be referred to as a vertical edge of the sacrificial layer 808, a vertical edge of the dielectric layer 812, and/or a vertical edge of the structure S806. [0117] The dielectric layer 812 may be considered as having three sections: a first section that is a flat section disposed on a top surface of the sacrificial layer 808 and parallel to the x- direction and the y-direction; a second section that is a flat section disposed on a top surface of the conductive layer 806 and parallel to the x-direction and the y-direction (e.g., and thus parallel to the first section); and a third section joining the first section and the second section. In the structure S806, the third section is a vertical section along the vertical edge 810 (e.g., a sidewall) of the sacrificial layer 808 and parallel to the z-direction (e.g., and thus perpendicular to the first and second sections and the x- and y-directions). In other cases, the vertical edge 810 may instead be an angled edge in which case the third section is at an angle relative to the first and second sections. [0118] To arrive at a structure S807, a portion of the dielectric layer 812 is removed from the structure S806. For example, the structure S806 may be etched (e.g., via one or more etching operations) to remove a portion of the dielectric layer 812 to arrive at the structure S807. As shown by the structure S807, the remaining portion of the dielectric layer 812 may Docket No.70052.2043WO01 be along the vertical edge 810 (e.g., along a vertical sidewall of the sacrificial layer 808). The remaining portion of the dielectric layer 812 may have a left sidewall, a right sidewall opposite the left sidewall (e.g., opposing sidewalls), and an arc from the right sidewall to the left sidewall. In some cases, rather than an arc, the remaining portion of the dielectric layer 812 may have an angled edge from the right sidewall to the left sidewall. An example height/thickness t_L2 of the dielectric layer 812 may be between approximately 800 Å and approximately 1,500 Å. A largest width wL2 of the dielectric layer 812 (e.g., the largest width extending from the left sidewall to the right sidewall of the dielectric layer 812 as shown in the structure S807) may be around the width wLM of the conductive layer 806. To arrive at a structure S808, the sacrificial layer 808 is removed (e.g., via one or more etching operations). [0119] As shown in FIG.8C, to arrive at a structure S809 from the structure S808, a portion of the conductive layer 806 is removed from the structure S808. As an example and for explanatory purposes, the structure S808 may be etched (e.g., via one or more etching operations) to remove a portion of the conductive layer 806. As shown in the structure S809, the dielectric layer 812 may be used as a hard mask that protects a portion of the conductive layer 806 under the dielectric layer 812 from removal (e.g., being etched). It is noted that the thickness t_LM of the conductive layer 806 as first shown in the structure S803 (e.g., when the conductive layer 806 is deposited) is nominally/substantially maintained (e.g., through operations performed to arrive at the structures S804 through S809) and may be considered or otherwise referred to as a height of the remaining portion of the conductive layer 806 as shown in the structure S809. Similarly, tL2 may be considered or otherwise referred to as a thickness or a height of the dielectric layer 812 after etching to arrive at S807 and nominally/substantially maintained (e.g., through operations performed to arrive at the structures S808 and S809). As t_L2 is at a highest point of the dielectric layer 812, t_L2 may be referred to as the largest thickness/height of the dielectric layer 812. A width wLM of the conductive layer 806 may be nominally/substantially equal to the width w_L2 of the dielectric layer 812. In this regard, an example width wLM may be between approximately 80 Å and approximately 300 Å. [0120] To arrive at a structure S810, a dielectric layer 814 is formed on the structure S809. In this regard, the dielectric layer 814 is formed on the dielectric layer 804, the conductive layer 806, and the dielectric layer 812. In an aspect, the dielectric layer 814 may be referred to as an L3 dielectric layer or simply an L3 dielectric. The dielectric layer 814 has a substantially/nominally uniform thickness t_L3. An example thickness t_L3 of the dielectric Docket No.70052.2043WO01 layer 814 may be between approximately 90 Å and approximately 130 Å. As a non-limiting example, the dielectric layer 814 may include an Al₂O₃ layer, an SiO₂ layer, and/or a silicon nitride layer. The dielectric layer 814 is disposed around and surrounds the dielectric layer 812 and the conductive layer 806. [0121] To arrive at the leg structure 610 from the structure S810, a portion of the dielectric layer 804 and a portion of the dielectric layer 814 are removed (e.g., via etching), and then the leg structure 610 released by removing the sacrificial layer 802. In some cases, a photoresist may be formed on the structure S810, appropriately patterned to define the leg structure 610 that would result from one or more etching operations, and removed after the etching operation(s) to obtain the leg structure 610 disposed on the remaining sacrificial layer 802, and then the remaining sacrificial layer 802 removed to release the leg structure 610. The leg structure 610 has a height tleg (e.g., also referred to as a thickness) extending along the z-direction and a width w_leg extending along the x-direction. The height t_leg may be or may be around a sum of tL1, tLM, tL2, and tL3. An example width wleg of the leg structure 610 may be between approximately 150 nm and approximately 300 nm. In an aspect, the leg structure 605 and the leg structure 610 may have similar heights and/or widths. [0122] The leg structure 610 may be considered as having three sections. Sections 816 and 818 may be flat sections parallel to a horizontal direction (e.g., the x-direction, the y- direction) and include a respective portion of the dielectric layer 804 and a respective portion of the dielectric layer 814 on the respective portion of the dielectric layer 814. A section 820 is adjacent to and joins the sections 816 and 818. The section 820 may include a portion of the dielectric layer 804, the conductive layer 806, the dielectric layer 812, and a portion of the dielectric layer 814. The conductive layer 806 is disposed on the portion of the dielectric layer 804. The dielectric layer 812 is disposed on the conductive layer 806. The portion of the dielectric layer 814 extends along the horizontal direction (e.g., the x-direction, the y- direction) and a vertical direction (e.g., the z-direction) and may be disposed on portions of the dielectric layer 804, disposed along sidewalls of the conductive layer 806 (e.g., a first sidewall and a second sidewall opposite the first sidewall of the conductive layer 806), and disposed around the dielectric layer 814 (e.g., along sidewalls and arc of the dielectric layer 812). It is noted that such a separation of the leg structure 610 into three sections is arbitrary and made for explanatory purposes to describe the leg structure 610. The leg structure 610 may be arbitrarily separated into fewer or more than three sections. In an aspect, the leg structure 610 may be referred to as having a T-shape (or an inverted T-shape). In some Docket No.70052.2043WO01 embodiments, the leg structure 610 may be characterized as being a thin (e.g., dimension along the z-direction) and narrow (e.g., dimension along the x-direction) leg structure due to the thickness tLM and the width wLM of the conductive layer 806. In some cases, the leg structure 610 may include a poly cap layer, such as shown in a leg structure 1122 of FIGS. 11C and 11D. In this regard, the poly cap layer may be considered a part of the dielectric layer 804 (e.g., the dielectric layer 804 is formed by a multi-layer deposition of dielectrics) or the poly cap layer may be considered a separate layer (e.g., separate dielectric layer) on which the dielectric layer 804 is formed. As provided above and applicable throughout the present disclosure, a dielectric layer may refer to and/or be realized as a single dielectric layer or multiple dielectric layers formed by multi-layer deposition of dielectrics, and, similarly, a conductive layer may refer to and/or be realized as a single conductive layer or multiple conductive layers of metal and/or metallic materials. [0123] It is noted that in some embodiments the dielectric layer 712 of the leg structure 605 or the dielectric layer 812 of the leg structure 610 is optional. The leg structure 615 of FIG. 6C may be an end result of a process/flow in which the dielectric layer 712 or the dielectric layer 812 is not in the resulting leg structure. As one example, with reference to the process/flow shown in FIGS.7A through 7C, the structure S708 of FIG.7C may be processed (e.g., etched and/or other removal process) such that the conductive layer 710 as shown in the structure S708 remains but without the dielectric layer 712. As another example, the dielectric layer 712 may be disposed on the conductive layer 710 to protect the conductive layer 710, and then the dielectric layer 712 may be removed before forming of the dielectric layer 714. Similarly, as one example, with reference to the process/flow shown in FIGS.8A through 8C, the structure S809 of FIG.8C may be processed such that the conductive layer 806 shown in the structure S809 remains but without the dielectric layer 812. As another example, the dielectric layer 812 may be disposed on the conductive layer 806 to protect the conductive layer 806, and then the dielectric layer 812 may be removed before forming of the dielectric layer 814. [0124] FIGS.9A and 9B illustrate cross-sectional side views associated with an example process/flow for forming the leg structure 620 of FIG.6D in accordance with one or more embodiments of the present disclosure. Turning first to FIG.9A, structures S901 through S904 are shown. To arrive at the structure S901, a sacrificial layer 902 is formed. The sacrificial layer 902 may be or may include a polyimide layer. To arrive at the structure S902, a portion of the sacrificial layer 902 is removed and then a dielectric layer 906 (e.g., a Docket No.70052.2043WO01 conformal dielectric layer) formed on the sacrificial layer 902. Removal of the portion of the sacrificial layer 902 defines a vertical edge 904. An example height t_PI of the vertical edge 904 may be between approximately 800 Å and approximately 1,500 Å. In an aspect, the dielectric layer 906 may be referred to as an L₁ dielectric layer or simply an L₁ dielectric. The dielectric layer 906 has a substantially/nominally uniform thickness. An example thickness t_L1 of the dielectric layer 906 may be between approximately 100 Å and approximately 200 Å. The dielectric layer 906 may be considered as having three sections: a first section that is a flat section disposed on an upper top surface of the sacrificial layer 902 at a top of the vertical edge 904 and parallel to the x-direction and the y-direction; a second section that is a flat section disposed on a lower top surface of the sacrificial layer 902 at a bottom of the vertical edge 904 and parallel to the x-direction and the y-direction (e.g., and thus parallel to the first section); and a third section joining the first section and the second section. In the structure S902, the third section is a vertical section along the vertical edge 904 (e.g., a sidewall) of the sacrificial layer 902 and parallel to the z-direction (e.g., and thus perpendicular to the first and second sections and the x- and y-directions), In other cases, the vertical edge 904 may instead be an angled edge in which case the third section is at an angle relative to the first and second sections. [0125] To arrive at the structure S903, a conductive layer 908 is formed on the dielectric layer 906. The conductive layer 908 may be a metal layer or a metallic layer. In some cases, a height of the conductive layer 908 does not reach a top of the vertical edge 904 of the dielectric layer 906. In some cases, as shown in the structure S904, a height of the conductive layer 908 does not reach a top of the vertical edge 904 of the sacrificial layer 902. The conductive layer 908 may be considered as having three sections: a first section that is a flat section (e.g., of nominally/substantially uniform thickness) disposed on an upper top surface of the dielectric layer 906 at a top of the vertical edge 904 and parallel to the x- direction and the y-direction; a second section (e.g., of nominally/substantially uniform thickness) that is a flat section disposed on a lower top surface of the dielectric layer 906 at a bottom of the vertical edge 904 and parallel to the x-direction and the y-direction (e.g., and thus parallel to the first section); and a third section joining the first section and the second section. In the structure S903, the third section is a vertical section along the vertical edge 904 (e.g., a sidewall) of the dielectric layer 906 and parallel to the z-direction (e.g., and thus perpendicular to the first and second sections and the x- and y-directions). In other cases, the vertical edge 904 may instead be an angled edge in which case the third section is at an angle Docket No.70052.2043WO01 relative to the first and second sections. In some aspects, the first and second sections of the conductive layer 908 may have around the same thickness, while at least a portion of the third section of the conductive layer 908 may be thicker than the first and second sections. [0126] To arrive at a structure S904, a portion of the conductive layer 908 is removed from the structure S903. The portion of the conductive layer 908 may include at least the first and second sections of the conductive layer 908. For example, the structure S903 may be etched (e.g., via one or more etching operations) to remove at least the first and second sections of the conductive layer 908 to arrive at the structure S904. In this regard, as shown by the structure S904, the remaining portion of the conductive layer 908 may be along the vertical edge 904 (e.g., along a vertical sidewall of the dielectric layer 906). The remaining portion of the conductive layer 908 may have a left sidewall and a right sidewall opposite the left sidewall (e.g., opposing sidewalls) and an arc from the right sidewall to the left sidewall. In some cases, rather than an arc, the remaining portion of the conductive layer 908 may have an angled edge from the right sidewall to the left sidewall. An example height/thickness tLM of the conductive layer 908 may be between approximately 100 Å and approximately 500 Å. An example width wLM of the conductive layer 908 (e.g., a largest width extending from the left sidewall to the right sidewall of the conductive layer 908 as shown in the structure S904) may be between approximately 80 Å and approximately 300 Å. [0127] As shown in FIG.9B, to arrive at a structure S905 from the structure S904, a dielectric layer 910 (e.g., a conformal dielectric layer) is formed on the structure S905. In this regard, the dielectric layer 910 is formed on the dielectric layer 906 and the conductive layer 908. In an aspect, the dielectric layer 910 may be referred to as an L₂ dielectric layer or simply an L2 dielectric. The dielectric layer 910 has a substantially/nominally uniform thickness. An example thickness t_L2 of the dielectric layer 910 may be between approximately 80 Å and approximately 300 Å. The dielectric layer 910 may be considered as having three sections: a first section that is a flat section disposed on an upper top surface of the dielectric layer 906 and parallel to the x-direction and the y-direction; a second section that is a flat section disposed on a lower top surface of the dielectric layer 906 and parallel to the x-direction and the y-direction (e.g., and thus parallel to the first section); and a third section joining the first section and the second section. In the structure S905, the third section extends along the vertical edge 904 (e.g., a sidewall) of the dielectric layer 906 and the arc and the right sidewall of the conductive layer 908. Docket No.70052.2043WO01 [0128] To arrive at a structure S906, the structure S905 is processed (e.g., etched) to define the leg structure 620. In this regard, portions of each of the dielectric layers 910 and 906, the conductive layer 908, and the sacrificial layer 902 are removed (e.g., using one or more etching operations). In some cases, a photoresist may be formed on the structure S905, appropriately patterned to define the leg structure 620 that would result from one or more etching operations, and removed after the etching operation(s) to obtain the leg structure 620 disposed on the remaining sacrificial layer 902. The leg structure 620 is formed along and around the vertical edge 904 defined in the structure S902. [0129] To arrive at the leg structure 620 from the structure S906, the sacrificial layer 902 is removed to release the leg structure 620. An example height tleg of the leg structure 620 may be between approximately 800 Å and approximately 1,500 Å. An example width w_leg of the leg structure 620 may be between approximately 150 nm and approximately 300 nm. A height of the dielectric layer 906 and/or a height of the dielectric layer 910 are greater than the height tLM of the conductive layer 908. In the leg structure 620, each of the height of the dielectric layer 906 and the height of the dielectric layer 910 are greater than the height t_LM of the conductive layer 908. [0130] The leg structure 620 may be considered as having three sections. Sections 912 and 914 may be flat sections parallel to a horizontal direction (e.g., the x-direction, the y- direction) and include a respective portion of the dielectric layer 906 and a respective portion of the dielectric layer 910 on the respective portion of the dielectric layer 906. A section 916 is adjacent to and joins the sections 912 and 914. The section 916 may include a portion of the dielectric layer 906, the conductive layer 908, and a portion of the dielectric layer 910. The conductive layer 908 is disposed on the portion of the dielectric layer 906. The dielectric layer 906 may be referred to as having an s-shape or a z-shape. The portion of the dielectric layer 910 extends along the horizontal direction (e.g., the x-direction) and a vertical direction (e.g., the z-direction) and may be disposed on a sidewall of the dielectric layer 906 and disposed around the arc and the right sidewall of the conductive layer 908. It is noted that such a separation of the leg structure 620 into three sections is arbitrary and made for explanatory purposes to describe the leg structure 620. The leg structure 620 may be separated into three sections in a different manner or separated into fewer or more than three sections. In some embodiments, the leg structure 620 may be characterized as being a thin (e.g., dimension along the z-direction) and narrow (e.g., dimension along the x-direction) leg structure due to the thickness t_LM and the width w_LM of the conductive layer 908. The leg Docket No.70052.2043WO01 structure 620 may have a size and shape to limit heat transmission between an infrared sensing element and a readout wafer. [0131] With reference to the leg structure 625 of FIG.6E, the leg structure 625 may be formed using the same or similar process/flow as that shown in FIGS.9A and 9B to arrive at the leg structure 620, except that removal of the conductive layer 908 of the structure S703 is performed such that a height tLM of the leg structure 625 is less than the height tLM of the leg structure 620. [0132] FIG.10A and 10B illustrate cross-sectional side views associated with an example process/flow for forming the leg structure 610 of FIG.6B in accordance with one or more embodiments of the present disclosure. Turning first to FIG.10A, structures S1001 through S1003 are shown. To arrive at the structure S1001, a sacrificial layer 1002 is formed. The sacrificial layer 1002 may be or may include a polyimide layer. To arrive at the structure S1002, a portion of the sacrificial layer 1002 is removed and then a dielectric layer 1006 (e.g., a conformal dielectric layer) formed on the sacrificial layer 1002. Removal of the portion of the sacrificial layer 1002 defines a vertical edge 1004. In an aspect, the dielectric layer 1006 may be referred to as an L₁ dielectric layer or simply an L₁ dielectric. The dielectric layer 1006 has a substantially/nominally uniform thickness. An example thickness t_L1 of the dielectric layer 1006 may be between approximately 80 Å and approximately 300 Å. The dielectric layer 1006 may be considered as having three sections: a first section that is a flat section disposed on an upper top surface of the sacrificial layer 1002 at a top of the vertical edge 1004 and parallel to the x-direction and y-direction; a second section that is a flat section disposed on a lower top surface of the sacrificial layer 1002 at a bottom of the vertical edge 1004 and parallel to the x-direction and the y-direction (e.g., and thus parallel to the first section); and a third section joining the first section and the second section. In the structure S1002, the third section is a vertical section along the vertical edge 1004 (e.g., a sidewall) of the dielectric layer 1006 and parallel to the z-direction (e.g., and thus perpendicular to the first and second sections and the x- and y-directions). Around the vertical edge 1004, The sidewall of the dielectric layer 1006 is in contact with a left sidewall of the conductive layer 1008. In other cases, the vertical edge 1004 may instead be an angled edge in which case the third section is at an angle relative to the first and second sections. [0133] To arrive at the structure S1003, a conductive layer 1008 is formed on the dielectric layer 1006. The conductive layer 1008 has a substantially/nominally uniform Docket No.70052.2043WO01 height/thickness. An example height/thickness tLM of the conductive layer 1008 may be between approximately 100 Å and approximately 500 Å. The conductive layer 1008 may be a metal layer or a metallic layer. The conductive layer 1008 may be considered as having three sections: a first section that is a flat section disposed on an upper top surface of the dielectric layer 1006 at a top of the vertical edge 1004 and parallel to the x-direction and the y-direction; a second section that is a flat section disposed on a lower top surface of the dielectric layer 1006 at a bottom of the vertical edge 1004 and parallel to the x-direction and the y-direction (e.g., and thus parallel to the first section); and a third section joining the first section and the second section. In the structure S1003, the third section is a vertical section along the vertical edge 1004 (e.g., a sidewall) of the dielectric layer 1006 and parallel to the z-direction (e.g., and thus perpendicular to the first and second sections and the x- and y- directions). [0134] As shown in FIG.10B, to arrive at a structure S1004 from the structure S1003, a dielectric layer 1010 (e.g., a conformal dielectric layer) is formed on the conductive layer 1008. In an aspect, the dielectric layer 1010 may be referred to as an L₂ dielectric layer or simply an L2 dielectric. The dielectric layer 1010 has a substantially/nominally uniform thickness. An example thickness t_L2 of the dielectric layer 1010 may be between approximately 80 Å and approximately 300 Å. The dielectric layer 1010 may be considered as having three sections: a first section that is a flat section disposed on an upper top surface of the dielectric layer 1006 and parallel to the x-direction and the y-direction; a second section that is a flat section disposed on a lower top surface of the dielectric layer 1006 and parallel to the x-direction (e.g., and thus parallel to the first section); and a third section joining the first section and the second section. The third section extends along an arc and a right sidewall of the conductive layer 1008. [0135] To arrive at a structure S1005, the structure S1004 is processed (e.g., patterned) to define the leg structure 630. In this regard, portions of each of the dielectric layers 1010 and 1006, the conductive layer 1008, and the sacrificial layer 1002 are removed (e.g., using one or more etching operations). In some cases, a photoresist may be formed on the structure S1005, appropriately patterned to define the leg structure 630 that would result from one or more etching operations, and removed after the etching operation(s) to obtain the leg structure 630 disposed on the remaining sacrificial layer 1002. The leg structure 630 is formed along and around the vertical edge 1004 defined in the structure S1002. Docket No.70052.2043WO01 [0136] To arrive at the leg structure 630 from the structure S1005, the sacrificial layer 1002 is removed to release the leg structure 630. An example height t_leg of the leg structure 630 may be between approximately 800 Å and approximately 1,500 Å. An example width wleg of the leg structure 630 may be between approximately 150 nm and approximately 300 nm. [0137] The leg structure 630 may be considered as having three sections. Sections 1012 and 1014 may be flat sections parallel to a horizontal direction (e.g., the x-direction, the y- direction) and include a respective portion of the dielectric layer 1006 and a respective portion of the dielectric layer 1010 on the respective portion of the dielectric layer 1006. A section 1016 is adjacent to and joins the sections 1012 and 1014. The section 1016 may include a portion of the dielectric layer 1006, the conductive layer 1008, and a portion of the dielectric layer 1010. The conductive layer 1008 is disposed on the portion of the dielectric layer 1006. The leg structure 630 and components thereof (e.g., the dielectric layers 1006 and 1010 and the conductive layer 1008) may be referred to as having an s-shape or a z- shape. The portion of the dielectric layer 1010 is disposed around the arc and the right sidewall of the conductive layer 1008. It is noted that such a separation of the leg structure 630 into three sections is arbitrary and made for explanatory purposes to describe the leg structure 630. The leg structure 630 may be separated into three sections in a different manner or separated into fewer or more than three sections. [0138] FIGS.11A through 11D illustrate perspective views associated with an example process/flow for forming a leg structure in accordance with one or more embodiments. In this regard, the perspective views may be associated with a process/flow similar to the process/flow shown in FIGS.7A through 7C and/or FIGS.8A and 8B. [0139] Turning first to FIG.11A, structures S1101 through S1106 are shown. To arrive at the structure S1101, a sacrificial layer 1102 is formed. The sacrificial layer 1102 may be or may include a polyimide layer. An example thickness of the sacrificial layer 1102 may be between approximately 3,500 Å and approximately 4,500 Å, such as 4,000 Å. In an aspect, the sacrificial layer 1102 may be cured at around 350°C. In an aspect, the sacrificial layer 1102 may be formed on a substrate or an overglass layer (e.g., an overglass layer disposed on a substrate). In an embodiment, the structure S1101 may correspond to (e.g., similar to or same as) a zoomed-in view of a portion of the structure S701 of FIG.7A or S801 of FIG.8A, in which the sacrificial layer 1102 may correspond to the sacrificial layer 702 or 802, respectively. Docket No.70052.2043WO01 [0140] To arrive at the structure S1102, a dielectric layer 1104 is formed on the sacrificial layer 1102. As an example, the dielectric layer 1104 may be an Al₂O₃ layer, an SiO₂ layer, and/or a silicon nitride layer. In some cases, the dielectric layer 1104 may be referred to as a poly cap layer. An example thickness of the dielectric layer 1104 may be between approximately 30 Å and approximately 50 Å. In some aspects, the dielectric layer 1104 may be formed using an atomic layer deposition (ALD) operation. ALD may facilitate control of film quality at the angstrom scale. In some cases, a temperature associated with the ALD operation may be around 200°C. [0141] To arrive at the structure S1103, a dielectric layer 1106 is formed on the dielectric layer 1104. As an example, the dielectric layer 1106 may be an Al2O3 layer, an SiO2 layer, and/or a silicon nitride layer. An example thickness of the dielectric layer 1106 may be between approximately 30 Å and approximately 50 Å. In some aspects, the dielectric layer 1104 may be formed using ALD. In some cases, the dielectric layer 1106 may act as a hard mask for one or more upcoming reticulation etches (e.g., for defining one or more trenches). In an embodiment, the structure S1103 may correspond to a zoomed-in view of a portion of the structure S702 of FIG.7A or S802 of FIG.8A, in which the dielectric layer 1104 and/or 1106 may individually or collectively correspond to the dielectric layer 704 or 804, respectively. [0142] To arrive at a structure S1104, a dielectric layer 1108 is formed on the dielectric layer 1106. As an example, the dielectric layer 1108 may be an Al₂O₃ layer, an SiO₂ layer, and/or a silicon nitride layer. An example thickness of the dielectric layer 1108 may be between approximately 80 Å and approximately around 120 Å. In some aspects, the dielectric layer 1108 may be formed using ALD. In an embodiment, the structure S1104 may correspond to a zoomed-in view of a portion of the structure S702 of FIG.7A or S802 of FIG.8A, in which the dielectric layer 1104, 1106, and/or 1108 may individually or collectively correspond to the dielectric layer 704 or 804, respectively. For example, in one embodiment, the dielectric layer 1106 and 1108 may collectively form the dielectric layer 704 or 804, in which the dielectric layer 1106 may be referred to as an L1a dielectric layer, the dielectric layer 1108 may be referred to as an L_1b dielectric layer, and the dielectric layers 1106 and 1108 may collectively be referred to as an L1 dielectric layer. [0143] To arrive at the structure S1105, a conductive layer 1110 is formed on the dielectric layer 1108. As a non-limiting example, the conductive layer 1110 may be or may include Ti. Docket No.70052.2043WO01 An example thickness of the conductive layer 1110 may be between approximately 200 Å and approximately 300 Å. In some aspects, the conductive layer 1110 may be referred to as a leg metal layer, as the conductive layer 1110 of the structure S1105 will be processed (e.g., appropriately etched) to form legs of a bolometer as further described herein. In some aspects, a pre-sputtering process (e.g., in-situ pre-sputtering process) may be performed (e.g., to remove impurities from a target material used to form the conductive layer 1110) before leg metal deposition and then a sputtering process performed to deposit the conductive layer 1110 on the structure S1104 to arrive at the structure S1105. In an embodiment, the structure S1105 may correspond to a zoomed-in view of a portion of the structure S1103, in which the conductive layer 806 may correspond to the conductive layer 1110. In some cases, such as shown in a structure S1240 of FIG.12G for example, another metal layer (e.g., a TiN layer) may be disposed on the metal layer 1110, with the metal layer 1110 and this other metal layer collectively referred to as leg metal layers or leg metal. [0144] To arrive at the structure S1106, a sacrificial layer 1112 is formed on (e.g., spin coated on) the conductive layer 1110. The sacrificial layer 1112 may be or may include a polyimide layer. An example thickness of the sacrificial layer 1112 may be between approximately 800 Å and 1,500 Å, such as 1,000 Å. In an embodiment, the structure S1106 may correspond to a zoomed-in view of a portion of the structure S804 of FIG.8A, in which the sacrificial layer 1112 may correspond to the sacrificial layer 808. [0145] As shown in FIG.11B, to arrive at a structure S1107 from the structure S1106, a photoresist layer 1114 is formed on (e.g., spin coated on) the sacrificial layer 1112. To arrive at a structure S1108, a portion of the photoresist layer 1114 is removed (e.g., via patterning involving using mask material, UV light, and developer) such that a portion of the sacrificial layer 1112 is exposed and another portion of the sacrificial layer 1112 is covered by the photoresist layer 1114. For example, mask material may be applied on (e.g., placed over) the photoresist layer 1114 of the structure S1107 and a light (e.g., UV light) may be applied to expose, to the light, a portion(s) of the photoresist layer 1114 not blocked by the mask material. In this regard, the mask material may have a design/pattern appropriate to expose the portion(s) of the photoresist layer 1114. A photoresist developer may then be applied to remove the portion of the photoresist layer 1114 that was exposed to the light. [0146] It is noted that such patterning of the photoresist layer 1114 may define sub-micron features. To arrive at a structure S1109, the portion of the sacrificial layer 1114 not covered Docket No.70052.2043WO01 by the photoresist layer 1114 is removed (e.g., via one or more etching operations). As shown by the structure S1109, the removal operation may be designed and performed such that a sidewall of the sacrificial layer 1112 is substantially/nominally 90º. This sidewall may provide a vertical edge 1116 of the sacrificial layer 1112. To arrive at a structure S1110, the remaining photoresist layer 1114 of the structure S1109 is removed such that the sacrificial layer 1112 covered by the photoresist layer 1114 in the structure S1109 is exposed. In an embodiment, the structure S1110 may correspond to a zoomed-in view of the structure S805 of FIG.8B, in which the vertical edge 1116 may correspond to the vertical edge 810. [0147] To arrive at a structure S1111, a dielectric layer 1118 is formed on the structure S1110. In this regard, the dielectric layer 1118 is disposed on the conductive layer 1110 and the sacrificial layer 1112. In an aspect, the dielectric layer 1118 may be referred to as an L₂ dielectric layer or simply an L2 dielectric. In some aspects, the dielectric layer 1118 may be formed using ALD. In some cases, the ALD may be a plasma-enhanced/assisted ALD process. As an example, the dielectric layer 1118 may be an Al2O3 layer, an SiO2 layer, and/or a silicon nitride layer. The dielectric layer 1118 may be an SiO₂ layer deposited using ALD at a process temperature as low as around 100°C. An example thickness of the SiO2 layer may be between approximately 120 Å and approximately 180 Å. In an embodiment, the structure S1111 may correspond to a zoomed-in view of a portion of the structure S806 of FIG.8B, in which the dielectric layer 1118 may correspond to the dielectric layer 812. [0148] As shown in FIG.11C, to arrive at a structure S1112 from the structure S1111, the structure S1111 is etched such that a portion of the dielectric layer 1118 remains on the sidewall of the sacrificial layer 1112 (e.g., along the vertical edge 1116). In an embodiment, the structure S1112 may correspond to a zoomed-in view of a portion of the structure S807. To arrive at a structure S1113, the structure S1112 is etched (e.g., via an O₂ etch operation) to remove the sacrificial layer 1112. The dielectric layer 1118 previously along the sidewall of the sacrificial layer 1112 of the structure S1112 remains on the conductive layer 1110. In an embodiment, the structure S1113 may correspond to a zoomed-in view of a portion of the structure S808 of FIG.8B. [0149] To arrive at a structure S1114, the structure S1113 is etched such that portions of the conductive layer 1110 not covered by the dielectric layer 1118. In this regard, the dielectric layer 1118 may be used as a hard mask for the conductive layer 1110. The dielectric layer 1118 previously along the sidewall of the sacrificial layer 1112 of the Docket No.70052.2043WO01 structure S1112 remains on the metal layer 1110. In an embodiment, the structure S1114 may correspond to a zoomed-in view of a portion of the structure S809 of FIG.8C. It is noted that while not shown by the structure S1114, photoresist may be included on other portions of the structure and may be removed after etching of the conductive layer 1110, such as shown by a structure S1263 of FIG.12L. [0150] To arrive at a structure S1115, a dielectric layer 1120 is formed on the structure S1114. In this regard, the dielectric layer 1120 is formed on the dielectric layer 1108, the dielectric layer 1118, and the conductive layer 1110. The dielectric layer 1120 surrounds (e.g., is disposed on and around) the dielectric layer 1118 and the conductive layer 1110. In an aspect, the dielectric layer 1120 may be referred to as an L3 dielectric layer or simply an L₃ dielectric. In some aspects, the dielectric layer 1120 may be formed using ALD. As an example, the dielectric layer 1120 may be an Al2O3 layer, an SiO2 layer, and/or a silicon nitride layer. As an example, the dielectric layer 1120 may be an Al₂O₃ layer deposited using ALD at a process temperature range of around 200°C. An example thickness of the Al2O3 layer may be between approximately 90 Å and approximately 130 Å. In an embodiment, the structure S1115 may correspond to a zoomed-in view of a portion of the structure S810 of FIG.8C, in which the dielectric layer 1120 may correspond to the dielectric layer 814. [0151] To arrive at a structure S1116, the structure S1115 is etched to expose a portion of the sacrificial layer 1102. In this regard, one or more etching operations may be performed to etch down to the sacrificial layer 1102 by removing a portion of the dielectric layers 1104, 1106, 1108, and 1120. In an aspect, the dielectric layers 1104, 1106, 1108, 1118, and 1120 and the conductive layer 1110 of the structure S1116 collectively form a leg structure 1122. In an embodiment, the structure S1116 may correspond to a zoomed-in view of a portion of the structure S810 of FIG.8C. [0152] To arrive at the leg structure 1122, the structure S1116 is etched (e.g., release etched) to remove the sacrificial layer 1102. As such, the leg structure 1122 previously disposed on the sacrificial layer 1102 in the structure S1116 is released, and the sacrificial layer 1102 may be referred to as a release layer. The leg structure 1122 has a height tleg extending along the z-direction, a width w_leg extending along the x-direction, and a length extending along the y-direction. The leg structure 1122 runs along the x-y plane. [0153] When viewed in a direction along the length of the leg structure 1122 (e.g., the y- direction), the leg structure 1122 may be considered as having three sections. Sections 1124 Docket No.70052.2043WO01 and 1126 may be flat sections parallel to a horizontal direction (e.g., the x-direction) and include a respective portion of each of the dielectric layer 1104, 1106, 1108, and 1120. A section 1128 is adjacent to and joins the sections 1124 and 1126. The section 1128 may include a portion of each of the dielectric layers 1104, 1106, 1108, and 1120; the conductive layer 1110; and the dielectric layer 1118. The conductive layer 1110 is disposed on the portion of the dielectric layer 1108. The portion of the dielectric layer 1120 extends along the horizontal direction (e.g., the x-direction) and a vertical direction (e.g., the z-direction) and may be disposed on portions of the dielectric layer 1108, disposed along sidewalls of the conductive layer 1110 (e.g., a first sidewall and a second sidewall opposite the first sidewall of the conductive layer 1110), and disposed around the dielectric layer 1118 (e.g., along sidewalls and arc of the dielectric layer 1118). It is noted that such a separation of the leg structure 1122 into three sections is arbitrary and made for explanatory purposes to describe the leg structure 1122. The leg structure 1122 may be arbitrarily separated into fewer or more than three sections. In an aspect, the leg structure 1122 may be referred to as having a T-shape (or an inverted T-shape). [0154] In some embodiments, the leg structure 1122 may be characterized as being a thin (e.g., dimension along the z-direction) and narrow (e.g., dimension along the x-direction) leg structure due to the thickness tLM and the width wLM of the conductive layer 1110. In an embodiment, the leg structure 1122 may correspond to the leg structure 610 of FIGS.6B and 8C. The sections 1124, 1126, and 1128 of the leg structure 1122 may correspond to the sections 816, 818, and 820, respectively, of the leg structure 610. [0155] FIGS.12A through 12Q illustrate perspective views associated with an example process/flow for forming a pixel (e.g., a bolometer) of an infrared imaging device in accordance with one or more embodiments of the present disclosure. The pixel may include a bridge (e.g., that includes an infrared sensing portion/element), leg structures, and ROIC contacts. In an embodiment, FIG.12A shows the process for forming the pixel after a readout circuit wafer (e.g., the readout circuit wafer 400 of FIG.4A) has been formed. [0156] Turning first to FIG.12A, structures S1201 through S1206 are shown. To arrive at the structure S1201, a wafer 1202 is provided. In some cases, the wafer 1202 may include a substrate (e.g., silicon substrate) and an overglass layer (e.g., SiO2) disposed on the substrate. A top surface of the wafer 1202 may include a top surface of the overglass layer. Although not shown in the structure S1201, one or more contacts (e.g., referred to as vias) may have Docket No.70052.2043WO01 been formed. In an aspect, the wafer 1202 is a readout circuit wafer and the contact(s) may be referred to as an ROIC via(s). As an example, the wafer 1202 may include, or may include components corresponding to, the substrate 401, the overglass layer 402, and the metal layer 403 shown in FIGS.4A through 4T. It is noted that the structure S1201 may show only a portion of the wafer 1202. [0157] To arrive at the structure S1202, a conductive layer 1204 is formed on the wafer 1202 (e.g., the overglass layer of the wafer 1202). As non-limiting examples, the conductive layer 1204 may be or may include titanium (Ti) or aluminum (Al). An example thickness of the conductive layer 1204 may be between approximately 1,200 Å and approximately 1,800 Å. The conductive layer 1204 is a metal layer or a metallic layer. In some aspects, the conductive layer 1204 may be referred to as a reflective metal layer and used to reflect infrared radiation to a resistive material of the infrared sensor (e.g., the bolometer) for facilitating infrared detection by the infrared sensor. In some aspects, a pre-sputtering process (e.g., in-situ pre-sputtering process) may be performed (e.g., to remove impurities from a target material used to form the conductive layer 1204) and then a sputtering process performed to deposit the conductive layer 1204 on the wafer 1202 to arrive at the structure S1202. [0158] To arrive at the structure S1203, a photoresist layer 1206 is formed on the conductive layer 1204. For example, the photoresist layer 1206 may be spin coated on the structure S1202 (e.g., on the conductive layer 1204 of the structure S1202). An example thickness of the photoresist layer may be approximately 1.5 m. [0159] To arrive at the structure S1204, portions of the photoresist layer 1206 are removed to define openings 1208A and 1208B (e.g., also referred to as trenches or perforations). The conductive layer 1204 is the top layer (e.g., the exposed layer) within the openings 1208A and 1208B. For example, mask material may be applied on (e.g., placed over) the photoresist layer 1206 of the structure S1203 and a light (e.g., UV light) may be applied to expose, to the light, a portion(s) of the photoresist layer 1206 not blocked by the mask material. In this regard, the mask material may have a design/pattern appropriate to expose the portion(s) of the photoresist layer 1206 so as to define the openings 1208A and 1208B (e.g., and other openings not shown in the structure S1204). A photoresist developer may then be applied to remove the portion of the photoresist layer 1206 to define the openings 1208A and 1208B as shown in the structure S1204. Docket No.70052.2043WO01 [0160] To arrive at the structure S1205, the conductive layer 1204 is etched to remove a portion of the conductive layer 1204 within the openings 1208A and 1208B such that the dielectric layer 1202 within the openings 1208A and 1208B is exposed. To arrive at the structure S1206, the photoresist layer 1206 is removed (e.g., via a resist strip operation). In some cases, after the photoresist layer 1206 is removed, a cleaning operation may be performed to remove any remaining residue associated with the photoresist layer 1206. With the photoresist layer 1206 removed, the conductive layer 1204 is exposed. Within the openings 1208A and 1208B, the dielectric layer 402 remain exposed. [0161] As shown in FIG.12B, to arrive at a structure S1207 from the structure S1206, a sacrificial layer 1210 is formed/applied on the structure S1206 (e.g., on the dielectric layer 1202 and the conductive layer 1204 of the structure S1206). For example, the sacrificial layer 1210 may be spin coated on the structure S1206. The sacrificial layer 1210 may be or may include a polyimide layer. An example thickness of the sacrificial layer 1210 may be between approximately 3,500 Å and approximately 4,500 Å. In an embodiment, the structure S1207 may correspond to (e.g., similar to or same as) a zoomed-out view of the structure S1101 of FIG.11A, in which the sacrificial layer 1210 may correspond to the sacrificial layer 1102. Further in this regard, the sacrificial layer 1210 may correspond to the sacrificial layer 702 of FIG.7A or the sacrificial layer 802 of FIG.8A. [0162] To arrive at a structure S1208, a dielectric layer 1212 is formed on the sacrificial layer 1210 of the structure S1207. In some aspects, the dielectric layer 1212 may be formed using ALD. ALD may facilitate control of film quality at the angstrom scale. In some cases, the ALD may be a thermal ALD process. As an example, the dielectric layer 1212 may include an SiO2 layer, an Al2O3 layer, and/or a silicon nitride layer. As an example, the dielectric layer 1212 may be an Al₂O₃ layer deposited using ALD at a process temperature range of around 120°C. An example thickness of the Al2O3 layer may be between approximately 40 Å and approximately 60 Å. In an aspect, the dielectric layer 1212 may be referred to as a poly cap layer or simply a poly cap. In an embodiment, the structure S1208 may correspond to a zoomed-out view of the structure S1102 of FIG.11A, in which the dielectric layer 1212 may correspond to the dielectric layer 1104. [0163] To arrive at a structure S1209, a dielectric layer 1214 is formed on the dielectric layer 1212 of the structure S1208. In some aspects, the dielectric layer 1214 may be formed using ALD. In some cases, the ALD may be a plasma-enhanced/assisted ALD process. As Docket No.70052.2043WO01 an example, the dielectric layer 1214 may be an SiO2 layer deposited using ALD at a process temperature range of around 120°C. An example thickness of the SiO₂ layer may be between approximately 30 Å and approximately 50 Å. [0164] To arrive at a structure S1210, a dielectric layer 1216 is formed on the dielectric layer 1214 of the structure S1209. As an example, the dielectric layer 1216 may be a titanium oxide (TiOx) layer. In some cases, such deposition may be performed using ion beam deposition (IBD). An example thickness of the titanium oxide layer may be between approximately 550 Å and approximately 650 Å. To arrive at a structure S1211, a cap layer 1218 is formed on the dielectric layer 1216 of the structure S1210. The cap layer 1218 may be an in-situ cap of the dielectric layer 1216. In some aspects, the cap layer 1218 may be formed by performing a sputtering operation. As an example, the cap layer 1218 may be SiO2 layer. An example thickness of the SiO2 layer may be between approximately 40 Å and approximately 60 Å. [0165] As shown in FIG.12C, to arrive at a structure S1212 from the structure S1211, a photoresist layer 1220 is formed (e.g., spin coated) on the structure S1211 (e.g., on the cap layer 1218 of the structure S1211). To arrive at a structure S1213, a portion of the photoresist layer 1220 is removed (e.g., using mask material, UV light, and developer) such that a portion of the cap layer 1218 is exposed and another portion of the cap layer 1218 remains covered by the photoresist layer 1220. [0166] To arrive at a structure S1214, the structure S1213 is etched such that the dielectric layer 1214 is exposed at a portion of the structure S1214 not covered/protected by the photoresist layer 1220. In this regard, one or more etching operations may be performed to remove a portion of the dielectric layer 1216 and a portion of the cap layer 1218 of the structure S1213 that are not covered/protected by the photoresist layer 1220. To arrive at a structure S1215, the photoresist layer 1220 is removed. With the photoresist layer 1220 removed, the cap layer 1218 previously covered by the photoresist layer 1220 is exposed. In some cases, a plasma ashing operation may be performed to remove the photoresist layer 1220. As shown in the structures S1214 and 1215, the dielectric layer 1216 has a sidewall and is between the dielectric layer 1214 and the cap layer 1218. [0167] To arrive at a structure S1216, a dielectric layer 1222 is formed on the structure S1215. In this regard, the dielectric layer 1222 is formed on the dielectric layer 1214, the dielectric layer 1216, and the cap layer 1218 of the structure S1215. In some aspects, the Docket No.70052.2043WO01 dielectric layer 1222 may be formed using ALD. In some cases, the ALD may be a plasma- enhanced/assisted ALD process. As an example, the dielectric layer 1222 may be an SiO₂ layer, an Al2O3 layer, and/or a silicon nitride layer. As an example, the dielectric layer 1222 may be an SiO₂ layer deposited using ALD at a process temperature range of around 200°C. An example thickness of the SiO2 layer may be between approximately 30 Å and approximately 50 Å. In an aspect, the dielectric layer 1222 may be referred to as an L_1a dielectric layer or L1a dielectric. In some cases, the dielectric layer 1222 may be used to protect the dielectric layer 1216 (e.g., protect the sidewall of the dielectric layer 1216). In some cases, the dielectric layer 1222 may provide some hard mask functionality for upcoming etches (e.g., upcoming reticulation etches), such as etches performed to arrive at structures S1219, S1220, and/or S1221 for example. In an embodiment, the structure S1216 may correspond to a zoomed-out view of the structure S1103 of FIG.11A, in which the dielectric layer 1222 may correspond to the dielectric layer 1106. [0168] As shown in FIG.12D, to arrive at a structure S1217 from the structure S1216, a photoresist layer 1224 is formed (e.g., spin coated) on the structure S1216 (e.g., on the dielectric layer 1222 of the structure S1216). To arrive at a structure S1218, a portion of the photoresist layer 1224 is removed to define an opening 1226. As further described herein, the opening 1226 may be used to help define a contact (e.g., a basket contact) between a leg structure and the wafer 1202 (e.g., that includes the ROIC). A portion of the dielectric layer 1222 within the opening 1226 is exposed. A remaining portion of the dielectric layer 1222 is covered by the photoresist layer 1224. The opening 1226 is defined by sidewalls formed of the photoresist layer 1224 and a bottom of the opening 1226 formed by a top surface of the dielectric layer 1222. [0169] To arrive at a structure S1219, the structure S1218 is etched such that a portion of the sacrificial layer 1210 within the opening 1226 is exposed. In this regard, one or more etching operations may be performed to etch down to the sacrificial layer 1210 by removing a portion of each of the dielectric layer 1222, the cap layer 1218, the dielectric layer 1216, the dielectric layer 1214, and the dielectric layer 1212. The remaining portion of the structure S1218 is protected from the etching operation(s) by the photoresist layer 1224. The opening 1226 is defined by sidewalls formed of the photoresist layer 1224, the dielectric layer 1222, the cap layer 1218, the dielectric layer 1216, the dielectric layer 1214, and the dielectric layer 1212; and a bottom of the opening 1226 formed by a top surface of the sacrificial layer 1210. Docket No.70052.2043WO01 [0170] To arrive at a structure S1220, the structure S1219 is etched to remove the portion of the sacrificial layer 1210 within the opening 1226 such that a portion of the metal layer 1204 under the opening 1226 is exposed. The remaining portion of the structure S1219 is protected from the etching operation by the photoresist layer 1224. The opening 1226 is defined by sidewalls formed of the photoresist layer 1224, the dielectric layer 1222, the cap layer 1218, the dielectric layer 1216, the dielectric layer 1214, the dielectric layer 1212, and the sacrificial layer 1210; and a bottom of the opening 1226 formed by a top surface of the metal layer 1204 (e.g., as better shown in a structure S1221 that follows). [0171] To arrive at a structure S1221, the photoresist layer 1224 is removed (e.g., using mask material, UV light, and developer) such that the dielectric layer 1222 is exposed. The dielectric layer 1222 has the opening 1226 defined therein. The opening 1226 is defined by sidewalls formed of the dielectric layer 1222, the cap layer 1218, the dielectric layer 1216, the dielectric layer 1214, the dielectric layer 1212, and the sacrificial layer 1210, and a bottom of the opening 1226 formed by the top surface of the metal layer 1204. [0172] As shown in FIG.12E, to arrive at a structure S1222 from the structure S1221, a photoresist layer 1228 is formed (e.g., spin coated) on the structure S1221. In this regard, the opening 1226 of the structure S1221 is filled by the photoresist layer 1228. To arrive at a structure S1223, a photoresist layer 1230 is formed (e.g., spin coated) on the structure S1222. In this regard, the photoresist layer 1230 is disposed directly on the photoresist layer 1228. In some cases, as shown in the structure S1223, the photoresist layer 1230 may be thicker than the photoresist layer 1228. In some cases, the photoresist layer 1228 may be referred to as a bottom photoresist later or a bottom lift-off layer and/or the photoresist layer 1230 may be referred to as a top photoresist layer or a top lift-off layer. Although the photoresist layers 1228 and 1230 are formed as two separate layers, the photoresist layers 1228 and 1230 may be deposited as a single photoresist layer or as more than two photoresist layers in other manufacturing processes. [0173] To arrive at a structure S1224, a portion of the photoresist layer 1230 is removed to define an opening 1232. A portion of the photoresist layer 1228 within the opening 1232 is exposed. To arrive at a structure S1225, a portion of the photoresist layer 1228 is removed to extend the opening 1232. The photoresist layer 1228 may be removed through appropriate exposing/undercutting. Docket No.70052.2043WO01 [0174] To arrive at a structure S1226, metal material 1234 is formed on the structure S1225. As a non-limiting example, the metal material 1234 may be or may include nickel chromium (NiCr) or Cr. As shown in the structure S1226, the metal material 1234 covers the photoresist layer 1230 and a portion of the dielectric layer 1222 that is within the opening 1232 and under the photoresist layer 1230. In some aspects, the metal material 1234 may provide a metal liner since it lines the sidewalls of the openings 1226 and 1232. In some aspects, a pre-sputtering process (e.g., in-situ pre-sputtering process) may be performed prior to disposing of the metal material 1234. [0175] As shown in FIG.12F, to arrive at a structure S1227 from the structure S1226, the photoresist layer 1230 and the metal material 1234 thereon are removed. In some cases, a portion of the photoresist layer 1228 may be removed as well. In an aspect, the metal material 1234, the photoresist layer 1230, and, in some cases, the portion of the photoresist layer 1228 may be removed using a polishing operation, such as a chemical mechanical polishing (CMP) operation. The removal of the photoresist layer 1230 and the metal material 1234 thereon leaves the metal material 1234 on the dielectric layer 1222 exposed. [0176] To arrive at a structure S1228, the photoresist layer 1228 is removed. To arrive at a structure S1229, metal stringers associated with the metal material 1234 are removed (e.g., via one or more etching operations). In some cases, such stringers are generally small but may cause shorts if not removed. [0177] To arrive at a structure S1230, a dielectric layer 1236 is formed on the structure S1229. In this regard, the dielectric layer 1236 is formed on a top surface of the dielectric layer 1222 and the metal material 1234 and along sidewalls of the opening 1226. In some aspects, the dielectric layer 1236 may be formed using ALD. In some cases, the ALD may be a plasma-enhanced/assisted ALD process. As an example, the dielectric layer 1236 may include an SiO₂ layer, an Al₂O₃ layer, and/or a silicon nitride layer. As an example, the dielectric layer 1236 may be an Al2O3 layer deposited using ALD at a process temperature range of around 200°C. An example thickness of the Al₂O₃ layer may be between approximately 80 Å and approximately 120 Å. In an aspect, the dielectric layer 1236 may be referred to as an L_1b dielectric layer or L_1b dielectric. In an embodiment, the structure S1230 may correspond to a zoomed-out view of the structure S1104 of FIG.11A, in which the dielectric layer 1236 may correspond to the dielectric layer 1108. To arrive at a structure S1231, a photoresist layer 1238 is disposed (e.g., spin coated) on the structure S1230. Docket No.70052.2043WO01 [0178] As shown in FIG.12G, to arrive at a structure S1232 from the structure S1231, a portion of the photoresist layer 1238 is removed to define an opening 1240. A portion of the dielectric layer 1236 is exposed due to the opening 1240. A remaining portion of the dielectric layer 1236 is covered by the photoresist layer 1238. To arrive at a structure S1233, the structure S1232 is etched such that a portion of the metal material 1234 within the opening 1240 is exposed, as shown more clearly with respect to a structure S1234 that follows. In this regard, one or more etching operations may be performed to etch down to the metal material 1234 by removing the dielectric layer 1236. The remaining portion of the structure S1233 is protected from the etching operation(s) by the photoresist layer 1238. [0179] To arrive at the structure S1234, the photoresist layer 1238 is removed such that the metal material 1234 within the opening 1240 is exposed. As shown for example by the structure S1234, the opening 1240 is smaller than the opening 1226. The metal material 1234 may form and/or be referred to as a via. In an embodiment, for the pixel that results from the process/flow of FIGS.12A through 12Q, the metal material 1234 may be used (e.g., together with additional conductive material coupled to the metal material 1234 in some cases) to provide electrical contact between the bridge of the pixel and circuitry (e.g., ROIC circuitry) disposed on the wafer 1202. In some cases, in the pixel, the bridge may be coupled to the metal material 1234 via a leg structure. [0180] To arrive at a structure S1235, a photoresist layer 1242 is formed (e.g., spin coated) on the structure S1234. In this regard, the photoresist layer 1242 is formed on the dielectric layer 1236 and within the opening 1226. To arrive at a structure S1236, portions of the photoresist layer 1242 are removed (e.g., using mask material, UV light, and developer) to define openings 1243A and 1243B. With these portions of the photoresist layer 1242, portions of the dielectric layer 1236 within the openings 1243A and 1243B are exposed. [0181] As shown in FIG.12H, to arrive at a structure S1237 from the structure S1236, the structure S1236 is etched such that portions of the dielectric layer 1216 with the openings 1243A and 1243B are exposed. In this regard, one or more etching operations may be performed to etch down to the dielectric layer 1216 by removing portions of each of the dielectric layer 1236, the dielectric layer 1222, and the cap layer 1218. The remaining portion of the structure S1236 is protected from the etching operation(s) by the photoresist layer 1242. To arrive at a structure S1238, the photoresist layer 1242 is removed. Docket No.70052.2043WO01 [0182] To arrive at a structure S1239, a conductive layer 1244 is formed on the structure S1238. In this regard, the conductive layer 1244 is disposed on the dielectric layers 1216 and 1236. The metal layer 1244 also fills the opening 1226 such that the metal layer 1244 is disposed on the metal material 1234 and lines sidewalls of the opening 1226. In some cases, the conductive layer 1244 in the opening 1226 may form part of a contact (e.g., a basket contact) that connects to the wafer 1202. As a non-limiting example, the conductive layer 1244 may be or may include Ti. An example thickness of the conductive layer 1244 may be between approximately 100 Å and approximately 500 Å. In some embodiments, the conductive layer 1244 may be referred to as a leg metal layer, as the conductive layer 1244 of the structure S1239 may be processed (e.g., appropriately etched) to form legs of a bolometer as previously described and also as further described herein. In some aspects, a pre- sputtering process (e.g., in-situ pre-sputtering process) may be performed (e.g., to remove impurities from a target material used to form the conductive layer 1244) before the leg metal deposition and then a sputtering process performed to deposit the conductive layer 1244 on the structure S1238. [0183] To arrive at a structure S1240, a conductive layer 1246 is formed on the structure S1239. In this regard, the conductive layer 1246 is formed on the conductive layer 1244 and also fills and lines the opening 1226. In some cases, the conductive layer 1246 in the opening 1226 may form part of a contact (e.g., a basket contact) that connects to the wafer 1202. As a non-limiting example, the conductive layer 1246 may be or may include titanium nitride (TiN). In some embodiments, the conductive layer 1246 may be referred to as another leg metal layer, as the conductive layer 1246 of the structure S1240 may be processed (e.g., appropriately etched) along with the conductive layer 1244 to form legs of a bolometer as previously described and also as further described herein. In an embodiment, the structure S1239 and/or S1240 may correspond to a zoomed-out view of the structure S1105 of FIG. 11A, in which the conductive layer 1244 and/or 1246 may correspond to the conductive layer 1110. [0184] To arrive at a structure S1240, a dielectric layer 1248 is formed on the conductive layer 1246. In this regard, the dielectric layer 1248 is formed on the conductive layer 1246 and fills and lines the opening 1226. In some cases, the dielectric layer 1248 in the opening 1226 may form part of a contact (e.g., a basket contact) that connects to the wafer 1202. As an example, the dielectric layer 1248 may include an SiO2 layer, an Al2O3 layer, and/or a silicon nitride layer. As a non-limiting example, the dielectric layer 1248 may be or may Docket No.70052.2043WO01 include SiO2. An example thickness of the dielectric layer 1248 may be between approximately 40 Å and approximately 60 Å. In some aspects, the dielectric layer 1248 may be referred to as a leg metal cap layer. In some cases, the dielectric layer 1248 may be deposited via sputtering. [0185] As shown in FIG.12I, to arrive at a structure S1242 from the structure S1241, a photoresist layer 1250 is formed (e.g., spin coated) on the structure S1242. In this regard, the photoresist layer 1250 is formed on the dielectric layer 1248 and within the opening 1226. To arrive at a structure S1243, portions of the photoresist layer 1250 are removed, thus exposing portions of the dielectric layer 1248 (e.g., exposing the leg metal cap) corresponding to the removed portions of the photoresist layer 1250. It is noted that, although portions of the dielectric layer 1248 may appear discontinuous in the structure S1243, the structure S1243 may represent only a portion of a larger structure in which one or more of these portions may be continuous with each other. It is further noted that sub-micron features may be defined through appropriate patterning. [0186] To arrive at a structure S1244, the structure S1243 is etched to remove the exposed dielectric layer 1248 of the structure S1243, thus exposing portions of the conductive layer 1246 corresponding to the removed portions of the dielectric layer 1248. The remaining portion of the structure S1244 is protected from etching operation(s) by the photoresist layer 1250. To arrive at a structure S1245, the structure S1244 is etched to expose the dielectric layer 1236. In this regard, one or more etching operations may be performed to remove the exposed conductive layer 1246 of the structure S1244 and the conductive layer 1244 below the conductive layer 1246. The remaining portion of the structure S1245 is protected from the etching operation(s) by the photoresist layer 1250. To arrive at a structure S1246, the photoresist layer 1250 is removed. A top surface of the structure S1246 includes the dielectric layers 1236 (e.g., the L1b dielectric) and 1248 (e.g., the leg metal cap) and has the opening 1226 defined therein that is filled and has its sidewalls lined with the dielectric layer 1248. [0187] As shown in FIG.12J, to arrive at a structure S1247 from the structure S1246, a photoresist layer 1252 is formed (e.g., spin coated) on the structure S1247. In this regard, the photoresist layer 1252 is formed on the dielectric layers 1236 and 1248 and within the opening 1226. In an aspect, the photoresist layer 1252 may be referred to as a stop gap photoresist layer. To arrive at a structure S1248, a portion of the photoresist layer 1252 is Docket No.70052.2043WO01 removed to define openings 1254A and 1254B. A portion of the dielectric layer 1236 is exposed within the openings 1254A and 1254B. A remaining portion of the dielectric layer 1236 is covered by the photoresist layer 1252. [0188] To arrive at a structure S1249, the structure S1248 is etched such that a portion of the dielectric layer 1216 within and under the openings 1254A and 1254B is exposed. In this regard, one or more etching operations may be performed to etch down to the dielectric layer 1216 (e.g., by removing portions of the dielectric layers 1236, 1222, and/or 1214 and/or the cap layer 1218). The remaining portion of the structure S1248 is substantially/nominally protected from the etching operation(s) by the photoresist layer 1252. In some cases, relative to the structure S1248, the etching operation(s) may remove a portion of the photoresist layer 1252 and enlarge the openings 1254A and 1254B of the structure S1248. [0189] To arrive at a structure S1250, the photoresist layer 1252 is removed. A surface of the structure S1250 includes the dielectric layers 1216, 1236, and 1248 and has the opening 1226 defined therein. To arrive at a structure S1251, a sacrificial layer 1256 is formed (e.g., spin coated) on the structure S1250. The sacrificial layer 1256 may be or may include a polyimide layer. An example thickness of the sacrificial layer 1256 may be approximately 1,000 Å. In an embodiment, the structure S1251 may correspond to a zoomed-out view of the structure S1106 of FIG.11A, in which the sacrificial layer 1256 may correspond to the sacrificial layer 1112. [0190] As shown in FIG.12K, to arrive at a structure S1252 from the structure S1251, a photoresist layer 1258 is formed (e.g., spin coated) on the structure S1251. In an embodiment, the structure S1252 may correspond to a zoomed-out view of the structure S1107of FIG.11B, in which the photoresist layer 1258 may correspond to the photoresist layer 1114. To arrive at a structure S1253, a portion of the photoresist layer 1258 is removed (e.g., using mask material, UV light, and developer) such that a portion of the sacrificial layer 1256 is exposed and another portion of the sacrificial layer 1256 is covered by the photoresist layer 1258. The photoresist layer 1258 in the structure S1253 covers the opening 1226 and helps define a shape of a leg structure, as shown in further structures formed by the manufacturing/bolometer process. In an embodiment, the structure S1253 may correspond to a zoomed-out view of the structure S1108 of FIG.11B. [0191] To arrive at a structure S1254, the structure S1253 is etched to remove a portion of the sacrificial layer 1256 of the structure S1252 not covered by the photoresist layer 1258. In Docket No.70052.2043WO01 an embodiment, the structure S1254 may correspond to a zoomed-out view of the structure S1109 of FIG.11B. To arrive at a structure S1255, the remaining photoresist layer 1258 of the structure S1254 is removed such that the sacrificial layer 1256 covered by the photoresist layer 1258 of the structure S1254 is exposed. In an embodiment, the structure S1255 may correspond to a zoomed-out view of the structure S1110 of FIG.11B. [0192] To arrive at a structure S1256, a dielectric layer 1260 is formed on the structure S1255. As an example, the dielectric layer 1222 may include an SiO₂ layer, an Al₂O₃ layer, and/or a silicon nitride layer. An example thickness of the dielectric layer 1260 may be between approximately 40 Å and approximately 60 Å. In some aspects, the dielectric layer 1260 may be deposited by a sputtering process. In an aspect, the dielectric layer 1260 may be referred to as an L₂ dielectric layer or L₂ dielectric. In an embodiment, the structure S1256 may correspond to a zoomed-out view of the structure S1111 of FIG.11B, in which the dielectric layer 1260 may correspond to the dielectric layer 1118. [0193] As shown in FIG.12L, to arrive at a structure S1257 from the structure S1256, a dielectric layer 1262 is formed on the structure S1256. In this regard, the dielectric layer 1262 is formed on a top surface of the dielectric layer 1260 and within the opening 1226. In some aspects, the dielectric layer 1262 may be formed using ALD. In some cases, the ALD may be a plasma-enhanced/assisted ALD process. As an example, the dielectric layer 1262 may be an SiO2 layer, an Al2O3 layer, and/or a silicon nitride layer. As an example, the dielectric layer 1262 may be an SiO₂ layer deposited using ALD at a process temperature range of around 200°C. An example thickness of the SiO2 layer may be between approximately 160 Å and approximately 240 Å. In an aspect, the dielectric layer 1262 and/or 1260 may be referred to individually or collectively as an L2 dielectric layer or L2 dielectric. For example, the dielectric layer 1260 and 1262 may be referred to as an L_2a dielectric layer and an L2b dielectric layer, respectively. In an embodiment, the structure S1257 may correspond to a zoomed-out view of the structure S1111 of FIG.11B, in which the dielectric layers 1260 and/or 1262 may correspond to the dielectric layer 1118. [0194] To arrive at a structure S1258, a photoresist layer 1264 is formed (e.g., spin coated) on the structure S1257. To arrive at a structure S1259, a portion of the photoresist layer 1264 is removed (e.g., using mask material, UV light, and developer) such that a portion of the dielectric layer 1262 is exposed and another portion of the dielectric layer 1262 (e.g., including a portion of the dielectric layer 1262 within the opening 1226) is covered by the Docket No.70052.2043WO01 photoresist layer 1264. In this regard, the photoresist layer 1264 remains in a region associated with the opening 1226 (e.g., associated with a contact to the wafer 1202) and a region associated with the bridge. [0195] To arrive at a structure S1260, the structure S1259 is etched to remove a portion of the dielectric layers 1260 and 1262 that is exposed (e.g., not covered by the photoresist layer 1264) while leaving a portion of the dielectric layers 1260 and 1262 along a sidewall of the sacrificial layer 1256. In some cases, a portion of the dielectric layer 1248 may also be removed. As shown in the structure S1260, various layers such as the dielectric layer 1236, the conductive layer 1246, and the sacrificial layer 1256 are exposed. In an embodiment, the structure S1260 may correspond to a zoomed-out view of the structure S1112 of FIG.11C. [0196] To arrive at a structure S1261, the structure S1260 is etched (e.g., O2 etch highly selective to polyimide and lowly selective to other material) to remove the sacrificial layer 1256. With the sacrificial layer 1256 removed, the dielectric layer 1248 (previously under the sacrificial layer 1256 in the structure S1260) is exposed. In the structure S1261, portions 1266 and 1268 (demarcated with dashed boxes) show two portions of the structure S1261 at which a leg structure has been defined and will continue to be further defined as shown in subsequent structures. In the portion 1266, the dielectric layer 1262 is disposed on the dielectric layer 1260, and the dielectric layer 1260 is disposed on the conductive layer 1246. In some cases, the dielectric layer 1260 and 1262 may form a sidewall around the dielectric layer 1248. A similar sidewall is formed by the dielectric layers 1260 and 1262 in the portion 1268. Other portions of the structure S1261 not explicitly identified with a dashed box may also include a similar sidewall associated with a leg structure. In an embodiment, the structure S1261 may correspond to (e.g., similar to) a zoomed-out view of the structure S1113 of FIG.11C. [0197] As shown in FIG.12M, to arrive at a structure S1262 from the structure S1261, the structure S1261 is etched to remove a portion of the conductive layers 1244 and 1246 such that the dielectric layer 1236 is exposed. Portions of the conductive layers 1244 and 1246 under the dielectric layers 1260 and 1262 may be protected by the dielectric layers 1260 and 1262. In this regard, the dielectric layers 1260 and 1262 may be considered as hard masks for the conductive layers 1244 and 1246. In an aspect, the conductive layers 1244 and 1246 may be, or may be considered, leg metal layers, and a leg metal etch performed on the structure S1261 to arrive at the structure S1262. As such, the portions 1266 and 1268 (as Docket No.70052.2043WO01 identified in the structure S1261) include a leg-like structure (e.g., an in progress leg structure) formed of the conductive layer 1244, the conductive layer 1246 disposed on the conductive layer 1244, the dielectric layer 1260 disposed on the conductive layer 1246, and the dielectric layer 1262 disposed on the dielectric layer 1260. In an embodiment, the structure S1262 may correspond to a zoomed-out view of the structure S1114 of FIG.11C. [0198] To arrive at a structure S1263, the photoresist layer 1264 is removed. The dielectric layer 1262 under the photoresist layer 1264 is exposed. In the structure S1263, a portion 1270 is associated with the bridge and a portion 1272 is associated with the contact to the ROIC wafer 1202, with the portions 1266 and 1268 each being associated with a respective leg structure between the portion 1270 and the portion 1272. The leg structure of the portion 1268 may be removed in subsequent processing operations. It is noted that the dashed boxes that define the portions 1266, 1268, 1270, and 1272 are provided for illustration purposes to facilitate describing of general associations of these portions with their functionality as a pixel of an infrared imaging device. Additional, fewer, and/or different portions may be defined in the structure 1263 (and other structures). [0199] To arrive at a structure S1264, a dielectric layer 1274 is formed on the structure S1263. In some aspects, the dielectric layer 1274 may be formed using ALD. In some cases, the ALD may be a plasma-enhanced/assisted ALD process. As an example, the dielectric layer 1274 may include an SiO2 layer, an Al2O3 layer, and/or a silicon nitride layer. As an example, the dielectric layer 1274 may be an Al₂O₃ layer deposited using ALD at a process temperature range of around 200°C. The dielectric layer 1274 may help protect the bridge, the leg structure, and the ROIC contact as well as any signals propagating between the bridge, the leg structure, and the ROIC contact. An example thickness of the Al2O3 layer may be between approximately 100 Å and approximately 140 Å. In an aspect, the dielectric layer 1274 may be referred to as L3 dielectric layer or L3 dielectric. In an aspect, such as shown in the structure S1263, a residual portion of the sacrificial layer 1256 may remain. This residual portion of the sacrificial layer 1256 may be removed (e.g., through ashing) prior to forming the dielectric layer 1274. In an embodiment, the structure S1264 may correspond to a zoomed-out view of the structure S1115 of FIG.11C, in which the dielectric layer 1274 may correspond to the dielectric layer 1120. [0200] To arrive at a structure S1265, a photoresist layer 1276 is formed (e.g., spin coated) on the structure S1257. To arrive at a structure S1266, a portion of the photoresist layer 1276 Docket No.70052.2043WO01 is removed (e.g., using mask material, UV light, and developer) such that a portion of the dielectric layer 1274 is exposed and another portion of the dielectric layer 1274 is covered by the photoresist layer 1276. The photoresist layer 1276 generally covers the portion 1266, 1270, and 1272 identified in the structure S1263 associated with the leg structure, the bridge, and the ROIC contact portion, respectively. In an embodiment, a structure S1323 of FIG. 13E corresponds to a cross-sectional view along a line A-A’ indicated in the structure S1266. [0201] As shown in FIG.12N, to arrive at a structure S1267 from the structure S1266, the structure S1266 is etched such that the sacrificial layer 1210 is exposed in portions of the structure S1266 not covered/protected by the photoresist layer 1276. In this regard, the dielectric layers 1212, 1214, 1222, 1236, and 1274 are removed via one or more etching operations. In an embodiment, a structure S1324 of FIG.13E corresponds to a cross- sectional view along a line B-B’ indicated in the structure S1267. [0202] To arrive at a structure S1268, the photoresist layer 1276 is removed. As more clearly shown in the structure S1268 and with reference to the portions 1266, 1268, 1270, and 1272 identified in the structure S1263 of FIG.12L, a stringer 1278 within the portion 1268 is disposed between (e.g., and may electrically connect) the portion 1270 associated with the bridge and the portion 1272 associated with the ROIC contact portion. The stringer 1278 may be considered to form a residual/stray leg structure formed as a byproduct of the processing operations of the manufacturing process and is removed in subsequent processing operations as further described herein. The stringer 1278 may be formed of the conductive layer 1244, the conductive layer 1246 disposed on the conductive layer 1244, the dielectric layer 1260 disposed on the conductive layer 1246, and the dielectric layer 1262 disposed on the dielectric layer 1260. In an embodiment, a structure S1325 of FIG.13E corresponds to a cross-sectional view along a line C-C’ indicated in the structure S1268. [0203] As shown in structures S1269, S1270, and S1271, processing operations are performed to remove the stringer 1278. To arrive at the structure S1269, a photoresist layer 1276 is formed (e.g., spin coated) on the structure S1268. To arrive at the structure S1270, a portion of the photoresist layer 1280 is removed to define an opening 1282 at a position that encompasses at least a portion of the stringer 1278. In an aspect, the photoresist layer 1280 may be referred to as a stop gap photoresist layer. To arrive at the structure S1271, the structure S1270 is etched to remove the portion of the stringer 1278 within the opening 1282. Docket No.70052.2043WO01 [0204] As shown in FIG.12O, to arrive at a structure S1272 from the structure S1271, the photoresist layer 1280 is removed. As shown by the structure S1272, the stringer 1278 has been removed, thus breaking a connection between the portion 1270 associated with the bridge and the portion 1272 associated with the ROIC contact. Each of the leg structure, the bridge, and the ROIC contact associated with the portion 1266, 1270, and 1272 is covered by the dielectric layer 1274 (e.g., the L₃ dielectric). The sacrificial layer 1210 is disposed around and/or below the leg structure, the bridge, and the ROIC contact and disposed around and/or on the ROIC wafer 1202 and the conductive layer 1204. In an embodiment, a structure S1325 of FIG.13E corresponds to a cross-sectional view along a line D-D’ indicated in the structure S1272. [0205] It is noted that the structures S1201 through S1272 shown in FIGS.12A through 12O may show a portion of a larger structure. In this regard, as processing operations are performed to form the structures S1202 through S1272, one or more of these processing operations may also be forming other portions of the larger structure. FIG.12P illustrates structures S1273 and S1274. The structure S1273 includes a portion 1284 that may correspond to (e.g., be similar to or the same as) the structure S1272, in which the portion 1284 may include the portion 1266, 1270, and 1272 associated with the leg structure, the bridge, and the ROIC contact, respectively. Furthermore, operations to form the portion 1284 (e.g., by performing operations to arrive at some or all of the structures S1201 through S1272) may simultaneously form a portion 1286. In an aspect, the portion 1284 and 1286 may collectively form a single pixel of an infrared sensor (e.g., a bolometer). In an embodiment, as labeled in the structure S1273, the pixel includes a bridge 1288, leg structures 1290A and 1290B, and ROIC contacts 1292A and 1292B. It is further noted that performing these operations may also form other pixels around the pixel formed by the portions 1284 and 1286 as shown by portions of various leg structures, ROIC contacts, and bridge around the portions 1284 and 1286, and as such the structure S1273 is also a portion of an even larger structure that may be formed to form an array of infrared sensors (e.g., an array of microbolometers). The dielectric layer 1274 covers the bridge, the leg structures, and the ROIC contacts of each pixel. The sacrificial layer 1210 is disposed around and/or below the leg structures, the bridge, and the ROIC contacts of each pixel and disposed around and/or on the ROIC wafer 1202 and the conductive layer 1204. [0206] To arrive at a structure S1274, a sacrificial layer 1293 is formed (e.g., spin coated) on the structure S1273. The sacrificial layer 1293 may be or may include a polyimide layer. Docket No.70052.2043WO01 An example thickness of the sacrificial layer 1293 may be approximately 1.5 m and 2.5 m. As shown in FIG.12Q, to arrive at a structure S1275 from the structure S1274, a photoresist layer 1294 is formed (e.g., spin coated) on the structure S1274 and then a portion of the photoresist layer 1294 is removed to define an opening 1295. [0207] To arrive at a structure S1276, the photoresist layer 1294 may be removed and then layers 1296 formed on the sacrificial layer 1293 and lining the opening 1295. In some cases, the opening 1295 extends through an entirety of the thickness of the sacrificial layer 1293 such that a top surface of the bridge 1288 is exposed. In such cases, the layers 1296 provide a thermal connection to the bridge 1288 to transfer heat to the bridge 1288 to facilitate infrared sensing. The layers 1296 may include a first dielectric layer, a conductive layer formed on the first dielectric layer, and a second dielectric layer formed on the conductive layer. The conductive layer may be used as an absorbing layer. The first dielectric layer may be the same or different material and the same or different size from the second dielectric layer. In an aspect, the first and second dielectric layers may each be an Al2O3 layer deposited using ALD and having a thickness of approximately 150 Å, and/or the conductive layer may be a Ti layer formed by sputtering and having a thickness of approximately 150 Å. [0208] As shown in FIG.12R, to arrive at a structure S1277 from the structure S1276, a photoresist layer is formed (e.g., spin coated) on the structure S1276 (e.g., on the layers 1296 and within the opening 1290), a portion of the photoresist layer removed to define portions of the layers 1296 to be removed, and the portions of the layers 1292 not covered by the photoresist layer removed (e.g., one or more etching operations). In this regard, each photoresist portion 1297A-H of the photoresist layer is disposed on a corresponding portion of the layers 1296 and may be associated with an absorber structure of a pixel. In some cases, the opening 1295 extends through an entirety of the thickness of the sacrificial layer 1293 such that a top surface of the bridge 1288 is exposed. In such cases, the layers 1296 provide a thermal connection to the bridge 1288 to transfer heat to the bridge 1288 to facilitate infrared sensing. It is noted that while the structures S1275 through S1278 only show the opening 1290, each pixel may have an absorber structure formed of the layers 1292 and having an opening. In this regard, although only the single opening 1290 is shown as being formed in the structures S1275 through 1278, multiple openings may be formed and/or processed prior to, concurrently with, or after the opening 1290 is formed and/or processed. Docket No.70052.2043WO01 [0209] To arrive at a structure S1278, a release etch operation is performed to remove any exposed polymers, polyimide, and resist, including the sacrificial layers 1210 and 1293 and the photoresist portions 1297A-H. The release etch operation may include one or more etch operations. The release etch operation suspends each pixel’s leg structure and bridge from the wafer 1202. In some cases, as shown in the structure S1278, each pixel may have an absorber structure disposed thereon and thermally connected to the bridge of the pixel. The structure S1278 shows the absorber structure 1298 and the bridge 1288 of one pixel of an infrared sensor array (e.g., bolometer array) and a portion of additional pixels. For example, each portion 1299A-G of the layers 1296 may correspond to an absorber structure of a pixel. [0210] FIGS.13A through 13E illustrate perspective views associated with an example process for forming leg structures of a pixel (e.g., a bolometer) of an infrared imaging device in accordance with one or more embodiments of the present disclosure. The pixel may include a bridge (e.g., including an infrared sensing portion/element), leg structures, and ROIC contacts. An axes denoting an x-direction, a y-direction, and a z-direction and a scale are provided in FIGS.13A through 13E. In an embodiment, FIG.12A shows the process for forming the leg structures of the pixel after a readout circuit wafer (e.g., the readout circuit wafer 400 of FIG.4A) has been formed. In some embodiments, other portions of the bridge may be formed while the leg structures of the pixel are being formed. In some embodiments, multiple pixels are formed along with the pixel during the process/flow. [0211] Turning first to FIG.13A, structures S1301 through S1306 are shown. To arrive at the structure S1301, a wafer 1302 is provided. The wafer 1302 may include a substrate (e.g., silicon substrate) and an overglass layer (e.g., SiO₂) disposed on the substrate. A top surface of the wafer 1302 may include a top surface of the overglass layer. Although not shown in the structure S1301, one or more contacts (e.g., referred to as vias) may have been formed. In an aspect, the wafer 1302 is a readout circuit wafer and the contact(s) may be referred to as an ROIC via(s). As an example, the wafer 1302 may include, or may include components corresponding to (e.g., similar to or the same as), the substrate 401, the overglass layer 402, and the metal layer 403 shown in FIGS.4A through 4T. It is noted that the structure S1301 may show only a portion of the wafer 1302. In an embodiment, the structure S1301 may correspond to a zoomed-in and rotated view of the structure S1201 of FIG.12A, in which the wafer 1302 may correspond to the wafer 1202. Docket No.70052.2043WO01 [0212] To arrive at the structure S1302, a conductive layer 1304 is formed on the wafer 1302 and an opening 1306 (e.g., a trench) is defined in the wafer 1302. In some aspects, the conductive layer 1304 may be formed of a metal layer, a metallic layer, or generally any sufficiently conductive material dependent on application and may be referred to as a reflective conductive layer, a reflective metal layer (RML), or simply reflector and used to reflect infrared radiation to a resistive material of the pixel for facilitating infrared detection by the bridge of the pixel. For example, infrared radiation that is incident upon the infrared sensing element of the bridge may pass through the infrared sensing element and not be absorbed by the infrared sensing element. The conductive layer 1304 may reflect this unabsorbed infrared radiation back towards the infrared sensing element for potential absorption by the infrared sensing element. As a non-limiting example, the conductive layer 1304 may be or may include Ti. [0213] In an embodiment, the structure S1302 may correspond to a zoomed-in and rotated view of the structure S1206 of FIG.12A, in which the conductive layer 1304 may correspond to the conductive layer 1204 and the opening 1306 may correspond to the opening 1208A. In this regard, in some cases, to form the conductive layer 1304, a conductive material (e.g., a metal) may be formed on the wafer layer 1302 (e.g., shown in the structure S1202), a photoresist layer formed on the conductive material (e.g., shown in the structure S1203) and patterned to define the opening 1306 (e.g., shown in the structure S1204), the conductive material etched to provide the conductive layer 1304 and expose the wafer 1302 within the opening 1306 (e.g., shown in the structure S1205), and the photoresist removed (e.g., shown in the structure S1206). [0214] To arrive at the structure S1303, a sacrificial layer 1308 is formed (e.g., spin coated) on the structure S1302. The sacrificial layer 1308 may be or may include a polyimide layer. An example thickness of the sacrificial layer 1308 may be between approximately 3,500 Å and approximately 4,500 Å. In an embodiment, the structure S1303 may correspond to a zoomed-in and rotated view of the structure S1207 of FIG.12B, in which the sacrificial layer 1308 may correspond to the sacrificial layer 1210. [0215] To arrive at the structure S1304, one or more dielectric layers are formed on the structure S1303. For example, as shown in the structure S1304, a dielectric layer 1310 is formed on the sacrificial layer 1308 and a dielectric layer 1312 is formed on the dielectric layer 1310. In some cases, the dielectric layer 1312 may protect sidewalls associated with a Docket No.70052.2043WO01 leg structure oxide and may be used as a hard mask for an upcoming reticulation etch. In an aspect, the dielectric layer 1310 may be a cap layer (e.g., a poly cap layer). In an aspect, the dielectric layer 1312 may be referred to as an L1a dielectric layer or an L1a dielectric. As an example, the dielectric layer 1310 and/or the dielectric layer 1312 may include an SiO₂ layer, an Al2O3 layer, and/or a silicon nitride layer. As a non-limiting example, the dielectric layer 1312 may be or may include an Al₂O₃ layer deposited using ALD. An example thickness of the Al2O3 may be between approximately 30 Å and approximately 50 Å. In an embodiment, the structure S1304 may correspond to a zoomed-in and rotated view of the structure S1216 of FIG.12C, in which the dielectric layer 1310 may correspond the dielectric layer 1212 (e.g., the poly cap layer) and the dielectric layer 1312 may correspond to the dielectric layer 1222 (e.g., the L1a dielectric). [0216] To arrive at the structure S1305, an opening 1314 is formed in the structure S1304. The opening 1314 may be lined by the dielectric layers 1310 and 1312 and the sacrificial layer 1308. In an embodiment, the structure S1305 may correspond to a zoomed-in and rotated view of the structure S1221 of FIG.12D, in which the opening 1314 may correspond to the opening 1226 of the structure S1305. In an aspect, a reticulation loop may be performed on the structure S1304 to arrive at the structure S1305. In some cases, to form the opening 1314, a photoresist layer may be formed on the structure S1304 (e.g., shown in the structure S1217), the photoresist layer patterned to define the opening 1226 (e.g., shown in the structure S1218), the dielectric layers 1310 and 1312 (e.g., oxides) and the sacrificial layer 1308 within the opening 1314 etched (e.g., shown in the structures S1219 and S1220), and the photoresist layer removed (e.g., shown in the structure S1221). In some cases, the sacrificial layer 1308 within the opening 1314 may be etched to expose the conductive layer 1304 within the opening 1314 and then the photoresist layer removed. In this regard, the opening 1314 may extend through the sacrificial layer 1308 down to the conductive layer 1304. [0217] To arrive at the structure S1306, a conductive material 1316 is formed in the opening 1314. The conductive material 1316 may be in contact with the conductive layer 1304 (e.g., to form a basket contact layer to the wafer 1302). As a non-limiting example, the conductive material 1316 may be or may include NiCr. In an embodiment, the structure S1306 may correspond to a zoomed-in and rotated view of the structure S1228 or S1229 (e.g., if a conductive stringer(s) is present and removed) of FIG.12F, in which the conductive material 1316 may correspond to the conductive material 1234 of the structure S1228 or Docket No.70052.2043WO01 S1229. In an aspect, a reticuliner loop may be performed on the structure S1305 to arrive at the structure S1306. Appropriate disposing and patterning of photoresist may be performed (e.g., operations performed to arrive at the structure S1222 through the structure S1229) such that the conductive material 1316 is in and around the opening 1314 as shown by the structure S1306. In some cases, etching may be performed to remove any conductive stringers associated with the conductive material 1316. [0218] As shown in FIG.13B, to arrive at a structure S1307 from the structure S1306, a dielectric layer 1318 is formed on the structure S1306. In this regard, the dielectric layer 1318 is formed on a top surface of the dielectric layer 1312 and the conductive material 1316 within and around the opening 1314. In some aspects, the dielectric layer 1318 may be formed using ALD. As non-limiting examples, the dielectric layer 1318 may include an SiO₂ layer, an Al2O3 layer, and/or a silicon nitride layer. As an example, the dielectric layer 1318 may be an Al₂O₃ layer deposited using ALD. An example thickness of the Al₂O₃ layer may be between approximately 80 Å and approximately 120 Å, such as approximately 100 Å. In an aspect, the dielectric layer 1318 may be referred to as an L_1b dielectric layer or L_1b dielectric. In an embodiment, the structure S1307 may correspond to a zoomed-in and rotated view of the structure S1230 of FIG.12F, in which the dielectric layer 1318 may correspond to the dielectric layer 1236 (e.g., the L1b dielectric) of the structure S1230. [0219] Following the structure S1307, one or more processing operations (e.g., patterning, etching, etc.) may be performed to arrive at structures corresponding to the structures S1231 through the structure S1238. Among other features, similar to that shown in the structure S1238 of FIG.12G, an opening may be formed in the opening 1314 to expose the conductive material 1316. To then arrive at a structure S1308, one or more conductive layers (e.g., leg metal layer(s)) may be formed and one or more dielectric layers (e.g., leg metal cap layer(s)) may be formed on the conductive layer(s). For example, as shown in the structure S1308, a conductive layer(s) 1320 is formed on the dielectric layer 1318 and within the opening 1314 and a dielectric layer(s) 1322 is formed on the conductive layer(s) 1320 and within the opening 1314. In an embodiment, the structure S1308 may correspond to a zoomed-in and rotated view of any one of the structures S1241 of FIG.12G through S1250 of FIG.12I, in which the conductive layer(s) 1320 may correspond to the conductive layers 1244 and/or 1246 and/or the dielectric layer(s) 1322 may correspond to the dielectric layer 1248. In an aspect, a leg metal loop may be performed starting from the structure S1306 to arrive at the structure S1307. In some cases, for the leg metal loop, operations may be performed Docket No.70052.2043WO01 corresponding to (e.g., similar to or the same as) those described with respect to the structures S1239 through up to S1250. [0220] To arrive at a structure S1309, a sacrificial layer 1324 is formed (e.g., spin coated) on the structure S1308. The sacrificial layer 1324 may be or may include a polyimide layer. In this regard, the sacrificial layer 1324 is formed on a top surface of the structure S1308, including the dielectric layer(s) 1322 within and around the opening 1314. An example thickness of the sacrificial layer 1324 may be between approximately 800 Å and approximately 1,200 Å. In an embodiment, the structure S1309 may correspond to a zoomed-in and rotated view of the structure S1251 of FIG.12I, in which the sacrificial layer 1324 may correspond to the sacrificial layer 1256. [0221] To arrive at a structure S1310, a photoresist layer 1326 is formed (e.g., spin coated) on the structure S1309. In this regard, the photoresist layer 1326 is formed on a top surface of the structure S1309, including the sacrificial layer 1324 within and around the opening 1314. In an embodiment, the structure S1310 may correspond to a zoomed-in and rotated view of a portion of the structure S1252 of FIG.12J, in which the photoresist layer 1326 may correspond to the photoresist layer 1258. [0222] To arrive at a structure S1311, a portion of the photoresist layer 1326 is removed (e.g., using mask material, UV light, and developer) such that a portion of the sacrificial layer 1324 is exposed and another portion of the sacrificial layer 1324 is covered by the photoresist layer 1326. In an embodiment, the structure S1311 may correspond to a zoomed-in and rotated view of a portion of the structure S1253 of FIG.12J, in which the sacrificial layer 1324 and the photoresist layer 1326 may correspond to the sacrificial layer 1256 and the photoresist layer 1258, respectively. [0223] As shown in FIG.13C, to arrive at a structure S1312 from the structure S1311, the structure S1312 is etched to remove the sacrificial layer 1324 not covered/protected by the photoresist layer 1326. In an embodiment, the structure S1312 may correspond to a zoomed- in and rotated view of a portion of the structure S1254 of FIG.12J, in which the sacrificial layer 1324, the photoresist layer 1326, and the dielectric layer 1322 may correspond to the sacrificial layer 1256, the photoresist layer 1258, and the dielectric layer 1248, respectively. [0224] To arrive at a structure S1313, the remaining photoresist layer 1326 of the structure S1312 is removed such that the sacrificial layer 1324 covered by the photoresist layer 1326 in Docket No.70052.2043WO01 the structure S1312 is exposed. In an embodiment, the structure S1313 may correspond to a zoomed-in and rotated view of a portion of the structure S1255 of FIG.12J. [0225] To arrive at a structure S1314, one or more dielectric layers may be disposed on the structure S1313. For example, as shown in the structure S1314, a dielectric layer 1328 is disposed on a top surface of the dielectric layer 1322 and a top surface and sidewalls of the sacrificial layer 1324. In some cases, the dielectric layer 1328 may be formed using ALD and/or sputtering. As non-limiting examples, the dielectric layer 1328 may include an SiO₂ layer, an Al2O3 layer, and/or a silicon nitride layer. As one example, the dielectric layer 1328 may be an SiO₂ layer deposited using ALD (e.g., plasma-enhanced/assisted ALD process) at a process temperature range of around 100°C. An example thickness of the SiO2 layer may be approximately 150 Å. As another example, the dielectric layer 1328 may be a layer formed using multi-layer deposition, in which the dielectric layer 1328 may include a first SiO₂ layer (e.g., approximately 50 Å) deposited using sputtering and then a second SiO₂ layer (e.g., approximately 200 Å) deposited using ALD on the first SiO2 layer. In an aspect, the dielectric layer 1328 may be referred to as an L₂ dielectric layer or L₂ dielectric. In an embodiment, the structure S1314 may correspond to a zoomed-in and rotated view of a portion of the structure S1256 of FIG.12J or the structure S1257 of FIG.12K, in which the dielectric layer 1328 may include the dielectric layer 1260 and/or 1262. [0226] To arrive at a structure S1315, a photoresist layer 1330 is formed (e.g., spin coated) on the structure S1314. In an embodiment, the structure S1315 may correspond to a zoomed- in and rotated view of a portion of the structure S1258 of FIG.12K, in which the photoresist layer 1330 may include the photoresist layer 1264. [0227] To arrive at a structure S1316, a portion of the photoresist layer 1330 is removed (e.g., using mask material, UV light, and developer) such that a portion of the dielectric layer 1328 is exposed and another portion of the dielectric layer 1328 is covered by the photoresist layer 1330. In an embodiment, the structure S1316 may correspond to a zoomed-in and rotated view of a portion of the structure S1259 of FIG.12K. [0228] As shown in FIG.13D, to arrive at a structure S1317 from the structure S1316, the structure S1316 is etched to remove a portion of the dielectric layer 1328. As shown by the structure S1317, such removal of the dielectric layer 1328 exposes the sacrificial layer 1324 and the dielectric layer 1322. The remaining dielectric layer 1328 is disposed along the Docket No.70052.2043WO01 sidewalls of the sacrificial layer 1324. In some cases, the dielectric layer 1328 along the sidewalls of the sacrificial layer 1324 may be considered a demarcation of a leg structure. [0229] To arrive at a structure S1318, the structure S1317 is etched to remove the dielectric layer 1322, the conductive layer(s) 1320, the dielectric layer 1318, and the dielectric layer 1312 such that the dielectric layer 1310 is exposed. As shown around a central region of the structure S1318, the dielectric layer 1328 is disposed along the sidewalls of the sacrificial layer 1324 and on the dielectric layer 1322. The sacrificial layer 1324 is disposed on the dielectric layer 1322. The dielectric layer 1322 is disposed on the conductive layer(s) 1320. The conductive layer(s) 1320 is disposed on the dielectric layer 1318. The dielectric layer 1318 is disposed on the dielectric layer 1312. The dielectric layer 1312 is disposed on the dielectric layer 1310. In an embodiment, the structure S1317 or S1318 may correspond to a zoomed-in and rotated view of a portion of the structure S1260 of FIG.12K. [0230] To arrive at a structure S1319, the structure S1318 is etched to remove a portion of the sacrificial layer 1324 to expose the dielectric layer 1322. A remaining portion of the sacrificial layer 1324 is covered/protected by the photoresist layer 1330. In an embodiment, the structure S1319 may correspond to a zoomed-in and rotated view of a portion of the structure S1262 of FIG.12L. [0231] To arrive at a structure S1320, the photoresist layer 1330 is removed. In an embodiment, the structure S1320 may correspond to a zoomed-in and rotated view of a portion of the structure S1263 of FIG.12L. In some cases, after the photoresist layer 1330 is removed, one or more additional operations (e.g., etching and/or ashing operations) may be performed to remove any remaining exposed portion of the sacrificial layer 1324, such as the remaining sacrificial layer 1324 shown in the structure S1320. [0232] To arrive at a structure S1321, one or more dielectric layers may be formed on the structure S1320. For example, as shown in the structure S1321, a dielectric layer 1332 is formed over an entire top surface of the structure S1321. In this regard, among being in contact with other layers/regions of the structure S1320, the dielectric layer 1332 may cover the exposed dielectric layer 1310 and the sidewalls formed of the dielectric layer 1328 and be disposed along sidewalls of the dielectric layers 1310, 1312, 1318, and 1322 and the conductive layer 1322. As non-limiting examples, the dielectric layer 1332 may include an Al2O3 layer, an SiO2 layer, and/or a silicon nitride layer. In some cases, the dielectric layer 1332 may be formed using ALD. As one example, the dielectric layer 1332 may be an Al₂O₃ Docket No.70052.2043WO01 layer deposited using ALD (e.g., plasma-enhanced/assisted ALD process) at a process temperature range of around 200°C. An example thickness of the dielectric layer 1332 may be between approximately 80 Å and approximately 150 Å. In an aspect, the dielectric layer 1332 may be referred to as an L₃ dielectric layer or L₃ dielectric. In an embodiment, the structure S1321 may correspond to a zoomed-in and rotated view of a portion of the structure S1264 of FIG.12L, in which the dielectric layer 1332 may include the dielectric layer 1274. [0233] As shown in FIG.13E, to arrive at a structure S1322 from the structure S1321, a photoresist layer 1334 is formed (e.g., spin coated) on the structure S1321. In an embodiment, the structure S1322 may correspond to a zoomed-in and rotated view of a portion of the structure S1265 of FIG.12L, in which the photoresist layer 1334 may include the photoresist layer 1276. [0234] To arrive at a structure S1323, a portion of the photoresist layer 1334 is removed (e.g., using mask material, UV light, and developer) such that a portion of the dielectric layer 1332 is exposed and another portion of the dielectric layer 1332 is covered by the photoresist layer 1334. In an embodiment, the structure S1323 may correspond to a zoomed-in and rotated view of a portion of the structure S1266 of FIG.12L. In this regard, in an embodiment, the structure S1323 may correspond to a cross-sectional view along the line A- A’ indicated in the structure S1266 of FIG.12L. [0235] To arrive at a structure S1324, the structure S1323 is etched such that the sacrificial layer 1308 is exposed in portions of the structure S1323 not covered by the photoresist layer 1334. In this regard, one or more etching operations may be used to etch down to the sacrificial layer 1308 by removing the layers 1310, 1312, 1318, 1320, and 1322. In an embodiment, the structure S1324 may correspond to a zoomed-in and rotated view of a portion of the structure S1267 of FIG.12M. In this regard, in an embodiment, the structure S1324 may correspond to a cross-sectional view along the line B-B’ indicated in the structure S1267 of FIG.12M. [0236] To arrive at a structure S1325, the photoresist layer 1334 is removed. The structure S1325 may be roughly demarcated into portions 1336, 1338, and 1340 associated with a leg structure, a bridge, and an ROIC contact, respectively. It is noted that while the structure S1325 appears to show disjointed leg structure portions, the disjoint appearance is due to the cross-sectional view provided of the structure S1325. The leg structure is continuous between the bridge and the ROIC contact. Portions 1342 and 1344 (e.g., cross-sections) of Docket No.70052.2043WO01 the leg structure are identified in the structure S1325. In an embodiment, the structure S1325 may correspond to a zoomed-in and rotated view of a portion of the structure S1268 of FIG. 12M. In this regard, in an embodiment, the structure S1325 may correspond to a cross- sectional view along the line C-C’ indicated in the structure S1268. The portions 1336, 1338, and 1340 of the structure S1325 may correspond to the portions 1266, 1270, and 1272 (identified in the structure S1263 of FIG.12L), respectively. In some embodiments, additional processing operations may be performed starting from the structure S1325 to arrive at a pixel of an infrared imaging device, such as operations to arrive at one or more of the structures S1269 through S1278. [0237] The leg structure 650 of FIG.6J may correspond to the portion 1342. The portion 1342 may correspond to a flipped version (e.g., flipped about the z-axis) of the leg structure 650. FIG.13F illustrates the leg structure 650 that may correspond to the portion 1342 in accordance with one or more embodiments. The leg structure 650 includes a dielectric layer 1310, a dielectric layer 1312, a dielectric layer 1318, a conductive layer(s) 1320, the dielectric layer 1322, the dielectric layer 1328, and the dielectric layer 1332. The dielectric layer 1312 is disposed on the dielectric layer 1310. The dielectric layer 1318 is disposed on the dielectric layer 1312. The conductive layer(s) 1320 is disposed on the dielectric layer 1318. The dielectric layer 1322 is disposed on the conductive layer(s) 1320. The dielectric layer 1328 is disposed on the dielectric layer 1322. The dielectric layer 1332 is disposed on the dielectric layer 1322, disposed on and around the dielectric layer 1328, disposed along a sidewall of the layers 1322, 1320, 1318, and 1312, and disposed on the dielectric layer 1310. In an aspect, the dielectric layer 1310, the dielectric layer 1312, the dielectric layer 1318, the conductive layer(s) 1320, the dielectric layer 1322, the dielectric layer 1328, and the dielectric layer 1332 may be referred to as a poly cap, an L_1a dielectric, an L_1b dielectric, a leg metal, a leg metal cap, an L2 dielectric, and/or an L3 dielectric, respectively. An example thickness t_LM of the conductive layer 1320 may be between approximately 100 Å and approximately 500 Å. An example width wLM of the conductive layer 1320 may be between approximately 80 Å and approximately 300 Å. An example leg height t_leg of the leg structure 650 may be between approximately 800 Å and approximately 1,500 Å. An example leg width w_leg of the leg structure 650 may be between approximately 150 nm and approximately 300 nm. [0238] The leg structure 650 may be considered as having three sections. Sections 1352 and 1354 may be flat sections parallel to a horizontal direction (e.g., the x-direction). The Docket No.70052.2043WO01 section 1352 includes a portion of each of the layers 1310, 1312, 1318, 1320, 1322, and 1332. The section 1354 includes a portion of the layers 1310 and 1332. A section 1356 is adjacent to and joins the sections 1352 and 1354. The section 1356 may include the dielectric layer 1328 and a portion of each of the layers 1310, 1312, 1318, 1320, 1322, and 1332. The portion of the dielectric layer 1332 of the portion 1356 is disposed along and around sidewalls and an arc joining the sidewalls of the dielectric layer 1328. It is noted that such a separation of the leg structure 650 into three sections is arbitrary and made for explanatory purposes to describe the leg structure 650. The leg structure 650 may be arbitrarily separated into fewer or more than three sections. [0239] It is noted that in some embodiments various layers of the leg structure 650 may be optional. The leg structure 640 of FIG.6H includes the dielectric layer 665, the conductive layer 670, and the dielectric layer 675. As non-limiting examples, each of the dielectric layers 665 and 675 may include an Al₂O₃ layer, an SiO₂ layer, and/or a silicon nitride layer. As non-limiting examples, the conductive layer 710 may include a titanium layer, a nickel- chromium alloy, and/or titanium nitride layer. The leg structure 640 may be considered as having three sections. Sections 682 and 684 may be flat sections parallel to a horizontal direction (e.g., the x-direction). The section 682 includes the conductive layer 670 and a portion of the dielectric layers 665 and 675. The section 684 includes a portion of the dielectric layers 665 and 675. A section 686 is adjacent to and joins the sections 682 and 684. The section 686 includes a portion of the dielectric layers 665 and 675. The portion of the dielectric layer 675 of the section 686 is disposed along a sidewall of the conductive layer 670. In FIG.6H, the section 686 is a vertical section along a vertical edge of the conductive layer 670 and parallel to the z-direction (e.g., and thus perpendicular to the sections 682 and 684 and the x- and y-directions). In other cases, the vertical edge of the conductive layer 670 may instead be an angled edge in which case the section 686 is at an angle relative to the sections 682 and 684. It is noted that such a separation of the leg structure 640 into three sections is arbitrary and made for explanatory purposes to describe the leg structure 640. The leg structure 640 may be arbitrarily separated into fewer or more than three sections. [0240] An example height/thickness t_LM of the conductive layer 670 may be between approximately 100 Å and approximately 500 Å. An example width wLM of the conductive layer 670 may be between approximately 80 Å and approximately 300 Å. An example thickness t1 of the dielectric layer 665 may be between approximately 100 Å and approximately 200 Å. An example thickness t₂ of the dielectric layer 675 may be between Docket No.70052.2043WO01 approximately 80 Å and approximately 150 Å. An example leg width wleg of the leg structure 640 may be between approximately 150 nm and approximately 300 nm. Along the vertical edge of the leg structure 640, the height/thickness tLM of the conductive layer 670 is less than a height of the dielectric layer 675 which may be or may be around a sum of t_LM and t2 as shown in FIG.6H. A height tleg of the leg structure 640 may be or may be around a sum of t₁, t_LM, and t₂. In some embodiments, the leg structures 640 may be characterized as being a thin (e.g., dimension along the z-direction) and narrow (e.g., dimension along the x- direction) leg structure due to the thickness t_LM and the width w_LM of the conductive layer 670. [0241] The leg structure 645 of FIG.6I may illustrate a variation of the leg structure 640 with the dielectric layer 680. The leg structure 645 includes the dielectric layer 665, the conductive layer 670, the dielectric layer 675, and the dielectric layer 680. The conductive layer 670 is disposed on the dielectric layer 665. The dielectric layer 675 is disposed on the conductive layer 670, the dielectric layer 680, and the dielectric layer 665. In this regard, the dielectric layer 675 is disposed along a sidewall of the conductive layer 670 and along sidewalls and arc of the dielectric layer 680. As non-limiting examples, dielectric layer 680 may include an Al₂O₃ layer, an SiO₂ layer, and/or a silicon nitride layer. The leg structure 645 may be considered as having three sections. A section 690 may be a flat section parallel to a horizontal direction (e.g., the x-direction, the y-direction) and include a portion of each of the dielectric layer 665, the conductive layer 670, and the dielectric layer 675. A section 692 may be a flat section parallel to a horizontal direction and include a portion of each of the dielectric layer 665 and the dielectric layer 675. A section 694 is adjacent to and joins the sections 690 and 692. The section 694 may include the dielectric layer 680 and a portion of each of the dielectric layer 665, the conductive layer 670, the dielectric layer 675. In the section 694, the conductive layer 670 is disposed on the portion of the dielectric layer 665 and the dielectric layer 680 is disposed on the conductive layer 670. The portion of the dielectric layer 675 of the section 694 extends along the horizontal direction (e.g., the x- direction, the y-direction) and a vertical direction (e.g., the z-direction) and may be disposed on and along a sidewall of the conductive layer 670 and disposed around the dielectric layer 680 (e.g., along sidewalls and arc of the dielectric layer 680). It is noted that such a separation of the leg structure 645 into three sections is arbitrary and made for explanatory purposes to describe the leg structure 645. The leg structure 645 may be arbitrarily separated into fewer or more than three sections. Docket No.70052.2043WO01 [0242] An example height/thickness tLM of the conductive layer 670 may be between approximately 100 Å and approximately 500 Å. An example width w_LM of the conductive layer 670 may be between approximately 80 Å and approximately 300 Å. An example thickness t₁ of the dielectric layer 665 may be between approximately 100 Å and approximately 200 Å. An example thickness t2 of the dielectric layer 675 may be between approximately 80 Å and approximately 150 Å. An example thickness t₃ of the dielectric layer 680 may be between approximately 800 Å and approximately 1,500 Å. An example leg width w_leg of the leg structure 645 may be between approximately 150 nm and approximately 300 nm. Along the vertical edge of the leg structure 645, the height/thickness tLM of the conductive layer 670 is less than a height of the dielectric layer 675 which may be or may be around a sum of tLM and t2 as shown in FIG.6I. A height tleg of the leg structure 645 may be or may be around a sum of t₁, t_LM, t₂, and t₃. In some embodiments, the leg structures 640, 645, and 650 of FIGS.6H, 6I, and 6J may be characterized as being a thin (e.g., dimension along the z-direction) and narrow (e.g., dimension along the x-direction) leg structure due to the thickness tLM and the width wLM of the conductive layer 670 or 1320. [0243] In one or more embodiments, leg structures of a given pixel (e.g., bolometer) may be mechanically stiffened through use of one or more layers having (e.g., appropriately manufactured to have) a respective desired stress. In this regard, during a process to design and simulate a bolometer, one or more stress layers may be added to a bolometer design, a stress of one or more constituent layers of a bolometer design may be tuned, and/or dimensions (e.g., thickness) of one or more constituent layers of the bolometer design may be tuned. In some aspects, such stiffening may correspond to and/or otherwise be associated with an increase in a resonant frequency (e.g., a lowest resonant frequency) associated with the bolometers. A desired resonant frequency associated with the bolometer may be a resonant frequency (e.g., a lowest resonant frequency) higher than environmental shock and vibration to increase a robustness of the bolometer to such environmental shock and vibration. [0244] As provided above, a bolometer may be fabricated by deposition and patterning of layers on a sacrificial material (e.g., polyimide). Narrow, meandering legs are often used to thermally isolate a thermistor/resistive element of the bolometer while maintaining mechanical and electrical connectivity to an ROIC (e.g., via an ROIC contact such as the contact 310). The legs are made up of dielectric/supporting layers and conductive layers (e.g., metal layers). The bolometer and the layers of the legs may be flat when deposited. Docket No.70052.2043WO01 When the sacrificial material is removed (e.g., to release the legs and the bolometer), the layers of the legs may deform according to an intrinsic stress in the dielectric layers and the conductive layers. For a given layer, an intrinsic stress may depend on a material or materials that form the layer, a deposition method (e.g., ALD, chemical vapor deposition (CVD), sputtering) used to deposit the layer, and deposition parameters associated with the deposition method, such as temperature and bias voltage for some deposition methods. For some deposition methods, a stress of a layer may be adjusted by tuning one or more of these deposition parameters. [0245] To be robust to environmental shock and vibration, the bolometer is nominally/substantially insensitive to environmental shock and vibration, which may stem from, by way of non-limiting examples, ultrasonic wirebond or weapons shock. A response (and possible mechanical failure) of the bolometer depends in part on the resonant frequency of the bolometer compared to frequencies of the environmental vibration or shock. Increasing the resonant frequency of the bolometer to be higher than expected environmental frequencies robustifies the bolometer. Such robustification may be especially important when performance considerations may push the design in a direction associated with lower robustness, such as, for example, thinner legs (e.g., to reduce fill factor and/or affect other characteristics). In some embodiments/applications, the desired resonant frequency (e.g., the desired lowest resonant frequency) associated with the bolometer array may be a frequency greater than approximately 120 kHz. In some embodiments/applications, the desired resonant frequency (e.g., the desired lowest resonant frequency) associated with the bolometer array may be a frequency between approximately 120 kHz and approximately 1 MHz. [0246] During a process to design and simulate a bolometer, one or more stress layers may be added to a bolometer design, an intrinsic stress of one or more existing layers of a bolometer design may be tuned, and/or dimensions (e.g., thickness) of one or more existing layers (e.g., such as one or more existing stress layers) of a bolometer design may be tuned. Tuning of an intrinsic stress of a layer may be referred to as pre-stressing the layer. Such adding of stress layers (e.g., high stress layers), adjusting of intrinsic stress of one or more existing layers, and/or adjustment of dimensions of one or more existing layers may be asymmetric or symmetric. In a case of asymmetric stress, pre-stress is asymmetric about a neutral axis (e.g., the bending mid-plane), for example by adding a highly compressive layer on a bottom of the bolometer leg. When the bolometer is released, the legs bow up, which Docket No.70052.2043WO01 somewhat relaxes the stress condition. This bowed shape, combined with a residual stress, causes an increase in resonant frequency. In a case of symmetric stress, pre-stress is symmetric about the neutral axis, for example by adding high stress layers on both a bottom and a top of the bolometer leg. Then, due to the symmetry, there is no significant leg bow upon release. The resonant frequency will rise, although in general more moderately relative to the asymmetric case. In both asymmetric and symmetric stress modification, adding one or more stress layers to the bolometer legs can increase a lowest resonant frequency (denoted as f_n), which stiffens the bolometer and makes the bolometer less susceptible to environmental vibration and shock. [0247] FIG.14A illustrates a pixel 1400 in accordance with one or more embodiments of the present disclosure. The pixel 1400 includes a bolometer bridge 1405, bolometer legs 1410 and 1415, and contacts 1420 and 1425. The bolometer leg 1410 may couple the bolometer bridge 1405 to the contact 1420. The bolometer leg 1415 may couple the bolometer bridge 1405 to the contact 1425. The contacts 1420 and 1425 may be coupled to an ROIC, thus coupling the bolometer bridge 1405 to the ROIC. A coordinate system with x- , y-, and z-axes is shown. [0248] FIG.14B illustrates a cross-sectional view of the bolometer leg 1410 along a line E- E’ indicated in FIG.14A. The bolometer leg 1415 may have the same cross-sectional view. The bolometer leg 1410 includes a cap layer 1450, a dielectric layer 1455 disposed on the cap layer 1450, a conductive layer 1460 disposed on the dielectric layer 1455, a dielectric layer 1465 disposed on the conductive layer 1460, and a cap layer 1470 disposed on the dielectric layer 1465. In an aspect, the dielectric layer 1455 may be referred to as an L₁ dielectric layer, the dielectric layer 1465 may be referred to as an L2 dielectric layer, and/or the conductive layer 1460 may be referred to as a leg metal layer. [0249] A stress profile (e.g., stress as a function of z) associated with the cross section of FIG.14B of the bolometer leg 1410 may be symmetric or asymmetric. In one case, to achieve a symmetric stress profile, a thickness of and a stress of with the cap layers 1450 and 1470 may be the same (e.g., nominally/substantially the same) and a thickness and a stress of the dielectric layers 1455 and 1465 may be the same. In this case, the bolometer leg 1410 may be referred to as being associated with and/or having a symmetric stress profile that is symmetric about an axis (e.g., a neutral axis). As an example, FIG.14C illustrates an example symmetric stress profile associated with the bolometer leg 1410 in accordance with Docket No.70052.2043WO01 one or more embodiments of the present disclosure. An example stress of the cap layers 1450 and 1470 is -600 MPa (e.g., +600 MPa compressive stress), a stress of the dielectric layers 1455 and 1465 is -60 MPa, and a stress of the conductive layer 1460 is 100 MPa. The bolometer leg 1410 has a symmetric stress profile that is symmetric about an axis 1475 (e.g., neutral axis) at z = 0.1 m. As shown in FIG.14C, an example thickness of the cap layers 1450 and 1470 is approximately 0.02 m, an example thickness of the dielectric layers 1455 and 1465 is approximately 0.06 m, and an example thickness of the metal layer 1460 is approximately 0.04 m. [0250] In some embodiments, an effect of the stress of the cap layers 1450 and 1470 on the lowest resonant frequency of the bolometer legs 1410 and 1415 may be determined (e.g., during a design of the bolometer leg) by tuning the stress of the cap layers 1450 and 1470. The cap layers 1450 and 1470 may then be manufactured with the appropriate stress to obtain a bolometer leg having a desired resonant frequency. In this regard, an appropriate deposition process (e.g., sputtering or ALD or CVD) may be selected and appropriate deposition parameters (e.g., temperature, bias voltage, etc.) associated with the deposition process may be determined. Tunability of the stress of the cap layers 1450 and 1470 are indicated by the double ended arrows in FIG.14C. [0251] FIG.14D illustrates a graph of an example relationship between the stress of the cap layers 1450 and 1470 and the lowest resonant frequency of the bolometer leg 1410 or the bolometer leg 1415 in accordance with one or more embodiments of the present disclosure. As the stress of the cap layers 1450 and 1470 increases, the lowest resonant frequency (e.g., also referred to as a lowest eigenfrequency or a lowest mode resonance) increases. The lowest resonant frequency increases less as a function of stress (e.g., a smaller slope at higher cap stress values). For the values of stress shown in the graph of FIG.14D, the cap layers 1450 and 1470 and a leg bow associated with the bolometer legs 1410 and 1415 has a small leg bow of between 0 nm to 4 nm. In some aspects, to provide an appropriately stiffened bolometer leg, the cap layers 1450 and 1470 may be designed to have a higher, in magnitude, stress than the dielectric layers 1455 and 1465 and the conductive layer 1460. [0252] It is noted that, while FIGS.14C and 14D provide the symmetric case in which the cap layers 1450 and 1470 have the same stress, the cap layers 1450 and 1470 may be tuned to have different stress to implement an asymmetric stress profile. In some embodiments, rather than tuning the stress of both the cap layers 1450 and 1470, the stress of only one of the cap Docket No.70052.2043WO01 layer 1450 or 1470 is tuned. In some aspects, relative to a symmetric stress profile, an asymmetric stress profile may be associated with a larger increase in the lowest resonant frequency of the bolometer leg but a larger leg bow, as further described herein. [0253] FIG.15A illustrates a pixel 1500 in accordance with one or more embodiments of the present disclosure. The pixel 1500 includes a bolometer bridge (not shown), an absorber structure 1505 disposed over the bolometer bridge (e.g., obscuring the bolometer bridge in FIG.15A), bolometer legs 1510 and 1515, a contact 1520, and a connection 1525. The bolometer leg 1515 may couple the bolometer bridge to the contact 1520 (e.g., a ROIC contact). The bolometer leg 1515 may couple the bolometer bridge to a contact (not shown) obscured by the absorber structure 1505. The connection 1525 connects the bolometer leg 1515 to the bolometer bridge. A coordinate system with x-, y-, and z-axes is shown. [0254] The leg structure 1510 has portions 1530 and 1535. The portion 1530 is associated with a low (or no) leg bow. The portion 1535 is associated with a higher leg bow than the portion 1530. The portion 1530 may be associated with a low (or no) leg bow due to the contact 1520 and the connection 1525 acting as anchor points for the leg structure 1510, whereas the portion 1535 may be associated with a higher leg bow due to being farther (e.g., along the y-direction) from the anchor points. Similarly, the leg structure 1515 has a portion 1540 associated with a higher leg bow and a portion (not shown) obscured by the absorber structure 1505 that corresponds to the portion 1530 and is associated with a low (or no) leg bow. In this regard, portions of the leg structure 1510 closer to the anchor points are generally associated with lower leg bow compared to portions of the leg structure 1510 farther from the anchor points. [0255] FIG.15B illustrates a cross-sectional view of the bolometer leg 1510 along a line F- F’ indicated in FIG.15A. The bolometer leg 1515 may have the same cross-sectional view. The bolometer leg 1515 includes a cap layer 1550, a dielectric layer 1555 disposed on the cap layer 1550, a conductive layer 1560 disposed on the dielectric layer 1555, a dielectric layer 1565 disposed on the dielectric layer 1555 and disposed on and around the conductive layer 1560. In an aspect, the dielectric layer 1555 may be referred to as an L1 dielectric layer, the dielectric layer 1565 may be referred to as an L₂ dielectric layer, and/or the conductive layer 1560 may be referred to as a leg metal layer. [0256] FIG.15C illustrates an example asymmetric stress profile associated with the bolometer leg 1510 along a line G-G’ indicated in FIG.15B in accordance with one or more Docket No.70052.2043WO01 embodiments of the present disclosure. An example stress of the dielectric layer 1555 is -0.2 GPa and of the dielectric layer 1565 is 0. A stress of the cap layer 1550 is tuned between 0 and -0.25 GPa. As shown in FIG.15C, an example thickness of the cap layer 1550 is approximately 0.005 m, an example thickness of the dielectric layer 1555 is approximately 0.01 m, and an example thickness of the dielectric layer 1565 is approximately 0.012 m. [0257] FIG.15D illustrates a graph of an example relationship between the stress of the cap layer 1550 and the lowest resonant frequency of the bolometer leg 1510 or 1515 in accordance with one or more embodiments of the present disclosure. As the stress of the cap layer 1550 increases, the lowest resonant frequency increases. In some aspects, to provide an appropriately stiffened bolometer leg, the cap layer 1550 may be designed to have a higher, in magnitude, stress than the dielectric layers 1555 and 1565 and the conductive layer 1560. FIG.15E illustrates a graph of an example relationship between the stress of the cap layer 1550 and a leg bow of the bolometer leg 1510 or 1515. In some cases, the leg bow of the bolometer leg 1510 or 1515 may refer to a largest leg bow (e.g., largest displacement) of the bolometer leg 1510 or 1515. For a given leg structure, this largest leg bow is generally associated with portions of the leg structure farthest from anchor points for the leg structure. As the stress of the cap layer 1550 increases, the leg bow increases. As such, for asymmetric stress, a tradeoff exists between a lowest resonant frequency and a leg bow, which both increase with the stress of the cap layer 1550. [0258] In an embodiment, the bolometer leg 1510 may correspond to the leg structure 1122 of FIG.11D without the dielectric layer 1118. The cap layer 1550, the dielectric layer 1555, the conductive layer 1560, and the dielectric layer 1565 may correspond to the dielectric layer 1104, the dielectric layer 1106 and/or 1108, the conductive layer 1110, and the dielectric layer 1120, respectively. In this regard, the cap layer 1550 may be a high stress layer. In some cases, the bolometer leg 1510 may include a dielectric layer on the conductively layer 1560 that is similar to the dielectric layer 1118. [0259] FIGS.16A through 16F collectively illustrate a comparison between symmetric stress and asymmetric stress. FIG.16A illustrates a cross section of a simplified bolometer leg 1600. While in general a bolometer leg has several layers with different stress (e.g., due to different material systems, deposition methods, and deposition parameters), FIG.16A illustrates a leg structure associated with a single stress (e.g., regardless of whether it is a Docket No.70052.2043WO01 single layer with a single stress or multiple layers having the same stress) for explanatory purposes. [0260] FIG.16B illustrates a bolometer leg formed by the bolometer leg 1600 of FIG.16A with high stress layers 1605 and 1610 of equal stress (e.g., nominally/substantially equal stress) added (e.g., above and below the bolometer leg 1600). In this regard, a symmetric stress modification (e.g., symmetric about a midplane) is made to the bolometer leg 1600 through the addition of the two high stress layers 1605 and 1610 of equal stress (e.g., nominally/substantially equal stress). FIG.16C illustrates a bolometer leg formed by the bolometer leg 1600 of FIG.16A with only a single high stress layer 1615 added. In this regard, an asymmetric stress modification is made to the bolometer leg 1600. [0261] FIG.16D illustrates a graph depicting an example relationship between a lowest resonant frequency of the bolometer leg of FIG.16B (i.e., the bolometer leg 1600 with symmetric stress modification) and a stress of the layers 1605 and 1610. FIG.16E illustrates a graph depicting an example relationship between a lowest resonant frequency of the bolometer leg of FIG.16C (i.e., the bolometer leg 1600 with asymmetric stress modification) and a stress of the layer 1615. In this regard, the graphs of FIG.16C and 16D depict an effect of the symmetric stress modification and asymmetric stress modification, respectively, on the lowest resonant frequency of the bolometer leg 1600. FIG.16F illustrates a graph depicting an example relationship between a leg bow (e.g., a largest leg bow) of the bolometer legs of FIG.16B and 16C and their respective stress modification. In this regard, a solid line 1620 shows a relationship between the leg bow of the bolometer leg of FIG.16B and the stress of the layers 1605 and 1610, and a dashed line 1625 shows a relationship between the leg bow of the bolometer leg of FIG.16C and the stress of the layer 1615. [0262] At around zero stress, which can be considered the case with the bolometer leg 1600 without stress modification, the lowest resonant frequency is around 117 kHz and the leg bow is zero as shown in FIGS.16D through 16F. At a stress of around 600 MPa, the lowest resonant frequency is around 133 kHz and the leg bow is substantially/nominally zero for the bolometer leg of FIG.16B, and the lowest resonant frequency is around 316 kHz and the leg bow is around 0.5 m for the bolometer leg of FIG.16C. [0263] With reference to FIG.16B, stress modification (e.g., asymmetric or symmetric) may be performed on the leg structure of FIG.16B. As one non-limiting example, a symmetric stress modification may include adjusting a thickness of the layer 1605 and 1610 Docket No.70052.2043WO01 such that, after performing the adjustment to both layers, the thickness of the layers 1605 and 1610 are the same. Alternatively or in addition, a symmetric stress modification may include adjusting a stress of the layer 1605 and 1610 such that, after performing the adjustment to both layers, the stress of the layers 1605 and 1610 are the same. As one non-limiting example, an asymmetric stress modification may include adjusting a thickness of the layer 1605 and/or 1610 such that, after performing the adjustment to one or both layers, the thickness of the layer 1605 is different from the thickness of the layer 1610. Alternatively or in addition, an asymmetric stress modification may include adjusting a stress of the layer 1605 and/or 1610 such that, after performing the adjustment to one or both layers, the stress of the layer 1605 is different from the stress of the layer 1610. In some aspects, one or more symmetric stress modifications may be performed on a leg structure along with one or more asymmetric stress modifications. [0264] Compared to symmetric stress modification of the bolometer leg, asymmetric stress modification of the bolometer leg may allow for a larger range of possible lowest resonant frequency exhibited by the bolometer leg while also having larger leg bow. As such, a bolometer leg may be designed to have a stress profile dependent on application and based on lowest resonant frequency requirements, leg bow requirements, and/or other requirements. In some cases, a combination of symmetric stress and asymmetric stress may be implemented in different portions of a device. In some cases, the bolometer leg may have a stress profile such that any leg bow exhibited by the bolometer leg bows upward (e.g., upwards in a direction away from the ROIC, such as upwards along a z-direction), such as a linear ramp upward, rather than the bolometer leg dipping (e.g., downwards in a direction toward the ROIC). [0265] Although the foregoing describes examples of symmetric and asymmetric profiles in which a bottommost layer and/or a topmost layer is a high stress layer, one or more layers between the bottommost layer and the topmost layer may be a high stress layer alternative to or in addition to the bottommost layer and/or the topmost layer being a high stress layer. In general, stress associated with the bottommost layer and the topmost layer (e.g., and thus tuning the stress of one or more of these layers) is associated with a larger effect on leg characteristics, such as a lowest resonant frequency of a leg, than the stress of layers between the bottommost and topmost layers. In some embodiments, a stress of one or more intermediate layers may be tuned along with or alternative to tuning a stress of the topmost and/or bottommost layer to determine a stress profile that achieves a desired characteristic(s) Docket No.70052.2043WO01 (e.g., a desired lowest resonant frequency and/or a leg bow below a maximum threshold leg bow) of the bolometer. In some embodiments, alternatively or in addition to tuning a stress, dimensions (e.g., thickness) of one or more intermediate layers may be tuned along with or alternative to tuning corresponding dimensions of the topmost and/or bottommost layer to achieve a desired characteristic(s) (e.g., a desired lowest resonant frequency and/or a leg bow below a maximum threshold leg bow) of the bolometer. [0266] FIG.17 is a flowchart of illustrative operations that may be performed for forming a pixel in accordance with one or more embodiments. In some embodiments, the pixel may have a leg structure according to any one of the leg structures 605, 610, 615, 620, 625, 630, 635, and 640. At block 1705, a bridge structure is formed on a sacrificial layer. For example, the bridge structure may include the bridge 1288 of FIG.12O and the sacrificial layer may include the sacrificial layer 1210. At block 1710, one or more openings are formed in the sacrificial layer. At block 1715, a contact metal layer is disposed on sidewalls of the opening(s). For example, the openings with the contact metal layer disposed therein may include the ROIC contacts 1292A and 1292B. At block 1720, one or more leg structures are formed. Each leg structure(s) may connect the bridge structure to an ROIC contact. For example, the leg structures 1290A and 1290B connect the bridge 1288 to the ROIC contacts 1292A and 1292B, respectively. As shown for example in FIGS.12A through 12Q, one or more operations associated with forming the bridge structure (e.g., the bridge 1288), forming the openings and disposing contact metals in the openings (e.g., the ROIC contacts 1292A and 1292B), and forming the leg structures (e.g., the leg structures 1290A and 1290B) may overlap and/or may be performed concurrently in some embodiments. For example, an operation performed to form the leg structures may also form the bridge structure and/or the ROIC contact. Example processes/flows for forming leg structures are described with respect to FIGS.7A through 11D and example processes/flows for forming a pixel including leg structures, ROIC contacts, and a bridge are described with respect to FIGS.12A through 13F. [0267] FIG.18 is a flowchart of illustrative operations that may be performed for bolometer stiffening in accordance with one or more embodiments. At block 1805, a leg structure having a stress profile is provided. In an aspect, this leg structure may form a part of a bolometer design. At block 1810, a resonant frequency associated with the leg structure is determined. At block 1815, a score associated with the leg structure is determined. The score is based at least in part on the resonant frequency. The score may be quantitative (e.g., a numerical score) and/or qualitative (e.g., leg structure is either a successful leg structure Docket No.70052.2043WO01 meeting all requirements or a failed leg structure). In some cases, the score may be further based on other characteristics associated with the leg structure or portion thereof such as, by way of non-limiting examples, a leg bow, a fill factor, an electrical conductivity, a thermal conductivity, and/or costs (e.g., material and/or manufacturing costs) associated with the leg structure or portion thereof. In an aspect, the score may be based in part on whether a lowest resonant frequency associated with the leg structure is above a threshold frequency. In this regard, dependent on application, if the lowest resonant frequency is not above the threshold frequency, the score may automatically be set to indicate the leg structure is a failed leg structure and must be adjusted. [0268] In some aspects, dependent on application, a desired range (e.g., design requirement and/or preference), a maximum threshold, or a minimum threshold may be associated with one or more characteristics associated with the leg structure or portion thereof. For example, for a given application, a leg structure may need to have a lowest resonant frequency within a desired lowest resonant frequency range. A leg structure having a lowest resonant frequency at around the middle of the desired lowest frequency range may be associated with a higher score than a leg structure having a lowest resonant frequency away from the middle of the desired lowest frequency range. As indicated above, in an aspect, if the lowest resonant frequency of a leg structure does not fall within this desired lowest resonant frequency range, the score may automatically be set to indicate (e.g., set to a value that indicates) the leg structure is a failed leg structure and must be adjusted. Other characteristics (e.g., leg bow, fill factor, electrical conductivity, thermal conductivity, costs) associated with a leg structure may similarly be within a range, above a threshold minimum value, and/or below a threshold maximum value, with a score associated with the leg structure being based on the leg structure’s characteristics relative to the corresponding range, threshold minimum value, and/or threshold maximum value. [0269] At block 1820, a determination is made as to whether the score is above a threshold score. If the determination at block 1820 is that the score is above the threshold score, the process 1800 continues to block 1825. In some cases, the score may be defined such that a lower score is associated with a more desirable leg structure than a higher score, in which cases the determination at block 1820 may be whether the score is below a threshold score. At block 1825, data indicative of manufacturing the leg structure is stored. If the determination at block 1820 is that the score is not above the threshold score, the process 1800 continues to block 1830. At block 1830, the leg structure is adjusted. Such adjustment Docket No.70052.2043WO01 may include adjusting a stress profile of the leg structure via a symmetric stress modification and/or an asymmetric stress modification. In this regard, such adjustment may include adding one or more stress layers to the bolometer design, tuning a stress of one or more constituent layers (e.g., one or more existing stress layers) of the bolometer design, and/or tuning one or more dimensions (e.g., thickness) of one or more constituent layers (e.g., one or more existing stress layers) of the bolometer design. In some cases, such adjustments may involve an adjustment to manufacturing processes associated with a leg structure, such as a deposition method used and/or deposition parameters associated with a deposition method (e.g., temperature, bias voltage, etc.). [0270] It is noted that dimensional aspects provided above are examples and that other values for the dimensions can be utilized in accordance with one or more implementations. Furthermore, the dimensional aspects provided above are generally nominal values. As would be appreciated by a person skilled in the art, each dimensional aspect has a tolerance associated with the dimensional aspect. Similarly, aspects related to distances between features provided above are also examples and also have associated tolerances, and aspects related to positions/orientations (e.g., above, below, top, bottom, above, below, vertical, horizontal, etc.) between features (e.g., different layers) may refer to an arbitrary frame of reference primarily to provide positions/orientations of features relative to one another (e.g., as shown in and described in relation to the various figures). [0271] Where applicable, various embodiments provided by the present disclosure can be implemented using hardware, software, or combinations of hardware and software. Also where applicable, the various hardware components and/or software components set forth herein can be combined into composite components comprising software, hardware, and/or both without departing from the spirit of the present disclosure. Where applicable, the various hardware components and/or software components set forth herein can be separated into sub-components comprising software, hardware, or both without departing from the spirit of the present disclosure. In addition, where applicable, it is contemplated that software components can be implemented as hardware components, and vice versa. [0272] Software in accordance with the present disclosure, such as non-transitory instructions, program code, and/or data, can be stored on one or more non-transitory machine readable mediums. It is also contemplated that software identified herein can be implemented using one or more general purpose or specific purpose computers and/or Docket No.70052.2043WO01 computer systems, networked and/or otherwise. Where applicable, the ordering of various steps described herein can be changed, combined into composite steps, and/or separated into sub-steps to provide features described herein. [0273] The foregoing description is not intended to limit the present disclosure to the precise forms or particular fields of use disclosed. Embodiments described above illustrate but do not limit the invention. It is contemplated that various alternate embodiments and/or modifications to the present invention, whether explicitly described or implied herein, are possible in light of the disclosure. Accordingly, the scope of the invention is defined only by the following claims.

Claims

Docket No.70052.2043WO01 CLAIMS 1. A method comprising: determining a resonant frequency associated with a leg structure; determining a score associated with the leg structure based at least on the resonant frequency; and adjusting the leg structure based on the score to obtain an adjusted leg structure, wherein the adjusting comprises adjusting a stress of one or more layers of the leg structure, adjusting one or more dimensions of one or more layers of the leg structure, and/or adding one or more layers to the leg structure to obtain an adjusted leg structure. 2. The method of claim 1, wherein the resonant frequency is a lowest resonant frequency associated with the leg structure, and wherein a lowest resonant frequency associated with the adjusted leg structure is higher than the lowest resonant frequency associated with the leg structure. 3. The method of claim 2, wherein the lowest resonant frequency associated with the adjusted leg structure is within a range between approximately 120 kHz and approximately 1 MHz. 4. The method of claim 1, wherein the score is further based on a leg bow, a fill factor, an electrical conductivity, and/or a thermal conductivity associated with at least a portion of the leg structure. 5. The method of claim 4, wherein the portion of the leg structure is associated with a larger leg bow than a corresponding portion of the adjusted leg structure. 6. The method of claim 4, wherein the portion of the leg structure is associated with a smaller leg bow than a corresponding portion of the adjusted leg structure. 7. The method of claim 1, wherein the adjusting the leg structure comprises performing an asymmetric stress modification on the leg structure to obtain the adjusted leg structure. Docket No.70052.2043WO01 8. The method of claim 7, wherein the asymmetric stress modification comprises increasing, in magnitude, a stress of one or more layers of the leg structure disposed on one side of an axis associated with the leg structure to obtain the adjusted leg structure. 9. The method of claim 8, wherein the increasing the stress of the one or more layers of the leg structure disposed on the one side of the axis comprises adjusting one or more deposition parameters associated with the one or more layers of the leg structure disposed on the one side of the axis. 10. The method of claim 7, wherein the asymmetric stress modification comprises adjusting a thickness of one or more layers of the leg structure disposed on one side of an axis associated with the leg structure to obtain the adjusted leg structure. 11. The method of claim 7, wherein the resonant frequency is a lowest resonant frequency associated with the leg structure, wherein the leg structure comprises a first side and a second side opposite the first side, wherein the asymmetric stress modification comprises adding a layer to one of the first side or the second side of the leg structure to obtain the adjusted leg structure, and wherein the layer has a stress such that a lowest resonant frequency associated with the adjusted leg structure is higher than the lowest resonant frequency associated with the leg structure. 12. The method of claim 1, wherein the adjusting the leg structure comprises performing a symmetric stress modification on the leg structure to obtain the adjusted leg structure. 13. The method of claim 12, wherein the symmetric stress modification comprises adjusting a stress of a first layer of the leg structure on a first side of an axis associated with the leg structure and a stress of a second layer of the leg structure on a second side of the axis opposite the first side to substantially the same stress to obtain the adjusted leg structure, and wherein the first layer and the second layer are substantially equidistant from the axis. Docket No.70052.2043WO01 14. The method of claim 12, wherein the symmetric stress modification comprises adjusting a thickness of a first layer of the leg structure on a first side of an axis associated with the leg structure and a stress of a second layer of the leg structure on a second side of the axis opposite the first side to substantially the same thickness to obtain the adjusted leg structure, and wherein the first layer and the second layer are substantially equidistant from the axis. 15. The method of claim 12, wherein the leg structure comprises a top side and a bottom side opposite the top side, wherein the symmetric stress modification comprises adding a first layer to the top side of the leg structure and a second layer to the bottom side of the leg structure to obtain the adjusted leg structure, and wherein the first and second layers have substantially the same stress and are substantially equidistant from an axis associated with the leg structure. 16. The method of claim 1, further comprising: determining a resonant frequency associated with the adjusted leg structure; determining a score associated with the adjusted leg structure based at least on the resonant frequency associated with the adjusted leg structure; and further adjusting the adjusted leg structure based on the score associated with the adjusted leg structure to obtain a further adjusted leg structure. 17. The method of claim 1, further comprising: forming a bridge on a first sacrificial layer; forming an opening in the first sacrificial layer; disposing a contact metal layer on sidewalls of the opening; forming the adjusted leg structure that couples to the bridge and the contact metal layer, wherein the adjusted leg structure comprises: a first dielectric layer; a conductive layer disposed on the first dielectric layer; and a second dielectric layer disposed on the conductive layer; and removing the first sacrificial layer to suspend the bridge and the adjusted leg structure above a substrate, wherein the contact metal layer is coupled to the substrate, and wherein at Docket No.70052.2043WO01 least a portion of the adjusted leg structure has a leg bow extending away from the substrate after the removing. 18. The method of claim 17, wherein the adjusted leg structure further comprises a cap layer, wherein the first dielectric layer is disposed on the cap layer, and wherein the adjusting the leg structure comprises adding the cap layer to the leg structure. 19. The method of claim 17, wherein: the leg structure comprises: a first cap layer associated with a first stress; the first dielectric layer disposed on the first cap layer; the conductive layer; and the second dielectric layer; and the adjusting the leg structure comprises adjusting a stress of the first cap layer from the first stress to a second stress; and the forming the adjusted leg structure further comprising forming the first cap layer according to predetermined deposition parameters such that the first cap layer of the adjusted leg structure is associated with the second stress. 20. The method of claim 19, wherein the forming the adjusted leg structure further comprises forming a second cap layer on the second dielectric layer according to predetermined deposition parameters such that the second cap layer of the adjusted leg structure is associated with the second stress. 21. The method of claim 1, further comprising providing an array of bolometers to form a focal plane array (FPA), wherein each bolometer of the array comprises the adjusted leg structure. 22. The method of claim 21, further comprising providing an infrared imaging device comprising the FPA. 23. A method of making a leg structure, the method comprising: Docket No.70052.2043WO01 forming a first cap layer based on predetermined deposition parameters such that the first cap layer is associated with a predetermined stress; forming a first dielectric layer on the first cap layer; forming a conductive layer on the first dielectric layer; and forming a second dielectric layer on the conductive layer, wherein the predetermined stress associated with the first cap layer is higher, in magnitude, than a stress associated with each of the first dielectric layer, the conductive layer, and the second dielectric layer, and wherein the leg structure has a lowest resonant frequency indicated by a stress profile of the leg structure. 24. The method of claim 23, wherein the lowest resonant frequency of the leg structure is within a range between approximately 120 kHz and approximately 1 MHz. 25. The method of claim 23, further comprising forming a second cap layer on the second dielectric layer based on predetermined deposition parameters such that the second cap layer is associated with the predetermined stress. 26. The method of claim 23, wherein the second dielectric layer is formed on the first dielectric layer and along a first sidewall of the conductive layer and a second sidewall of the conductive layer opposite the first sidewall, and wherein a height of the conductive layer is less than a height of the second dielectric layer. 27. An infrared imaging device comprising: a substrate comprising a plurality of contacts; a microbolometer array coupled to the substrate, wherein the microbolometer array comprises a plurality of microbolometers, and wherein each microbolometer comprises: a bridge; and a leg structure coupled to the bridge and to one of the plurality of contacts, wherein the leg structure comprises: a first cap layer; a first dielectric layer disposed on the first cap layer; a conductive layer disposed on the first dielectric layer; and Docket No.70052.2043WO01 a second dielectric layer disposed on the conductive layer, wherein a stress associated with the first cap layer is higher, in magnitude, than a stress associated with each of the first dielectric layer, the conductive layer, and the second dielectric layer, and wherein the leg structure has a lowest resonant frequency indicated by a stress profile of the leg structure. 28. The infrared imaging device of claim 27, wherein the lowest resonant frequency of the leg structure is within a range between approximately 120 kHz and approximately 1 MHz. 29. The infrared imaging device of claim 27, wherein the leg structure further comprises a second cap layer disposed on the second dielectric layer, and wherein a stress associated with the second cap layer is substantially the same as the stress associated with the first cap layer. 30. The infrared imaging device of claim 27, wherein the substrate further comprises a surface, wherein the surface defines a plane, wherein the second dielectric layer is disposed on the first dielectric layer and along a first sidewall of the conductive layer and a second sidewall of the conductive layer opposite the first sidewall, wherein a height of the conductive layer is less than a height of the second dielectric layer, and wherein the height of the conductive layer and the height of the second dielectric layer extend in a direction perpendicular to the plane. 31. The infrared imaging device of claim 27, wherein at least a portion of the leg structure has a leg bow extending away from the substrate. 32. The infrared imaging device of claim 27, wherein a leg bow of a first portion of the leg structure is smaller than a leg bow of a second portion of the leg structure, and wherein the first portion of the leg structure is closer to the one of the plurality of contacts than the second portion.