WO2025219844A1 - Storage device - Google Patents

Abstract

Provided is a storage device with a reduced occupied area. Provided is a storage device capable of accurately reading data. Provided is a storage device which can be easily manufactured. In this storage device, a first plurality of transistors have a portion positioned in a first opening of an insulating layer, a second plurality of transistors have a portion positioned in a second opening of the insulating layer, and a plate line of a first plurality of capacitive elements and a plate line of a second plurality of capacitive elements are spaced apart. The first plurality of capacitive elements and the second plurality of capacitive elements include a material capable of having ferroelectricity. One among the source and the drain of one of the first plurality of transistors is connected to one of the first plurality of capacitive elements, and the other is connected to a bit line. One among the source and the drain of one of the second plurality of transistors is connected to one of the second plurality of capacitive elements, and the other is connected to the bit line.

Description

storage device

One aspect of the present invention relates to a semiconductor device.

Note that one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed in this specification relates to an object, an operating method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices (including liquid crystal display devices), light-emitting devices, power storage devices, imaging devices, memory devices, processing devices, signal processing devices, sensors, arithmetic devices (including processors), electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof.

Research and development of ferroelectric memories is currently underway (Non-Patent Document 1). For next-generation ferroelectric memories, active research is also being conducted on hafnium oxide-related materials, including ferroelectric _HfO2 -based materials (Non-Patent Document 2), ferroelectric properties of _{Hf0.5Zr0.5O2 thin} films (Non-Patent Document 3), and ferroelectric properties of _HfO2 thin films (Non-Patent Document ₄ ). Furthermore, the integration of _{ferroelectric Hf0.5Zr0.5O2 -} based FeRAM (Ferroelectric Random Access Memory) with CMOS has been demonstrated (Non-Patent Document 5).

An example of a memory or circuit element that uses a ferroelectric substance is a ferroelectric capacitor. A ferroelectric capacitor is a type of capacitive element in which a ferroelectric insulating material is sandwiched between a pair of electrodes, and is able to retain data by utilizing the hysteresis characteristics of the remanent polarization of the ferroelectric insulating material. This allows data to be retained even without the application of voltage, and so there are high hopes for the realization of non-volatile memory (FeRAM) using ferroelectric capacitors.

In particular, Patent Documents 1 and 2 disclose a circuit configuration that retains data in a ferroelectric capacitor even when the power supply voltage to the flip-flop circuit is cut off. This circuit configuration makes it possible to back up the data retained by the flip-flop circuit to the ferroelectric capacitor, allowing the flip-flop circuit to be shut down.

Republished Publication No. 03-044953 JP 2013-124290 A

T. S. Boescke, et al. , “Ferroelectricity in hafnium oxide thin films”, APL99, 2011 Zhen Fan, et al. , “Ferroelectric HfO2-based materials for next-generation f "erroelectric memories", JOURNAL OF ADVANCED DIELECTRICS, Vol. 6, No. 2, 2016 Jun Okuno, et al. , “SoC compatible 1T1C FeRAM memory array based on ferroelectric Hf0.5Zr0.5O2”, VLSI 2020 Akira Toriumi, "Ferroelectricity of HfO2 Thin Films," The Japan Society of Applied Physics, Vol. 88, No. 9, 2019 T. Francois, et al. , “Demonstration of BEOL-compatible ferroelectric Hf0.5Zr0.5O2 scaled FeR AM co-integrated with 130nm CMOS for embedded NVM applications”, IEDM 2019 Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https://unit.aist.go.jp/rpd-envene/PV/ja/results/2019/oral/T13.pdf>

An object of one embodiment of the present invention is to provide a memory device with a reduced occupation area. Another object of one embodiment of the present invention is to provide a memory device from which data can be accurately read. Another object of one embodiment of the present invention is to provide a memory device that can be easily manufactured. Another object of one embodiment of the present invention is to provide a semiconductor device with a reduced occupation area. Another object of one embodiment of the present invention is to provide a semiconductor device from which data can be accurately read. Another object of one embodiment of the present invention is to provide a semiconductor device that can be easily manufactured. Another object of one embodiment of the present invention is to provide an electronic device including the above-described memory device. Another object of one embodiment of the present invention is to provide a novel memory device, a novel semiconductor device, or a novel electronic device.

Note that the problems of one embodiment of the present invention are not limited to the above-mentioned problems. The above-mentioned problems do not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, etc., and can be extracted as appropriate from these descriptions. Note that one embodiment of the present invention solves at least one of the above-mentioned problems and other problems. Therefore, one embodiment of the present invention does not necessarily solve all of the above-mentioned problems and other problems.

One aspect of the present invention is a transistor having a first transistor, a second transistor, a first capacitor, a second capacitor, a first insulating layer, a second insulating layer, a third insulating layer, and a bit line, wherein the first transistor, the second transistor, and the second insulating layer are each located on the first insulating layer, the third insulating layer is located on the first transistor and the second transistor, the first capacitor, the second capacitor, and the bit line are each located on the third insulating layer, the second insulating layer has a first opening reaching the first insulating layer and a second opening reaching the first insulating layer, the first transistor has a portion located within the first opening, the second transistor has a portion located within the second opening, and the first transistor has a first electrode functioning as one of a source electrode and a drain electrode, and a second electrode functioning as the other. The second transistor has a first electrode that functions as one of a source electrode and a drain electrode, and a third electrode that functions as the other, the first electrode being connected to a bit line; the first capacitor has a columnar fifth electrode, a fourth insulating layer that covers at least a portion of a columnar side surface of the fifth electrode, and a sixth electrode; the second capacitor has a columnar seventh electrode, a fifth insulating layer that covers at least a portion of a columnar side surface of the seventh electrode, and an eighth electrode; the fourth insulating layer has a portion located between the fifth electrode and the sixth electrode, and the fifth insulating layer has a portion located between the seventh electrode and the eighth electrode; the fourth insulating layer and the fifth insulating layer include a material that can have ferroelectricity; the second electrode is connected to the fifth electrode of the first capacitor, and the third electrode is connected to the seventh electrode of the second capacitor.

Furthermore, in the above aspect, it is preferable that the semiconductor device has a first plug, a second plug, and a third plug, the first plug to the third plug each having a portion provided in the third insulating layer, the first electrode to the third electrode each being located on the second insulating layer, the first electrode being connected to the bit line via the first plug, the second electrode being connected to the fifth electrode of the first capacitance element via the third plug, and the third electrode being connected to the seventh electrode of the second capacitance element via the third plug.

Furthermore, in the above aspect, there is provided a semiconductor layer shared by a first transistor and a second transistor, the first transistor having a first gate line, and the second transistor having a second gate line, and the semiconductor layer having a first portion in contact with a first side surface of the first opening, a second portion in contact with an upper surface of the first insulating layer within the first opening, a third portion in contact with a second side surface of the first opening, a fourth portion in contact with a third side surface of the second opening, a fifth portion in contact with an upper surface of the first insulating layer within the second opening, and a sixth portion in contact with a fourth side surface of the second opening, and the first and third portions are preferably arranged with the first gate line sandwiched therebetween, and the fourth and sixth portions are preferably arranged with the second gate line sandwiched therebetween.

Furthermore, in the above embodiment, it is preferable that the semiconductor layer has a metal oxide, and that the metal oxide contains indium.

Or one aspect of the present invention is a transistor having a first plurality of transistors, a second plurality of transistors, a first plurality of capacitance elements, a second plurality of capacitance elements, a first insulating layer, a second insulating layer, a third insulating layer, and a bit line, wherein the first plurality of transistors, the second plurality of transistors, and the second insulating layer are each located on the first insulating layer, the third insulating layer is located on the first plurality of transistors and the second plurality of transistors, the first plurality of capacitance elements, the second plurality of capacitance elements, and the bit line are each located on the third insulating layer, the second insulating layer has a first opening reaching the first insulating layer and a second opening reaching the first insulating layer, each of the first plurality of transistors has a portion located within the first opening, and each of the second plurality of transistors has a portion located within the second opening, the first plurality of capacitance elements have a first plate line shared by the first plurality of capacitance elements, and the second plurality of capacitance elements The memory device includes a second plate line shared by a second plurality of capacitance elements, and the first plate line and the second plate line are spaced apart. The first transistor is one of the first plurality of transistors, and one of its source and drain is connected to a bit line and the other is connected to one of the first plurality of capacitance elements. The second transistor is one of the second plurality of transistors, and one of its source and drain is connected to the bit line and the other is connected to one of the second plurality of capacitance elements. Each of the first plurality of capacitance elements has a fifth electrode having a columnar shape, and each of the second plurality of capacitance elements has a sixth electrode having a columnar shape. Each of the first plurality of capacitance elements has a fourth insulating layer sandwiched between the fifth electrode and the first plate line, and each of the second plurality of capacitance elements has a fifth insulating layer sandwiched between the sixth electrode and the second plate line. The fourth insulating layer and the fifth insulating layer include a material that may have ferroelectricity.

Furthermore, in the above aspect, it is preferable that each of the first plurality of transistors has a first semiconductor layer, and within the first opening, the first semiconductor layers of the first plurality of transistors are arranged in order along the first direction, each of the second plurality of transistors has a second semiconductor layer, and within the second opening, the second semiconductor layers of the second plurality of transistors are arranged in order along the second direction, and the bit line extends in a third direction, and the first direction and the second direction each intersect with the third direction.

Furthermore, in the above aspect, it is preferable that the first plurality of transistors have a first gate line shared by the first plurality of transistors, and in each of the first plurality of transistors, the first semiconductor layer has a first portion in contact with the first side surface of the first opening, a second portion in contact with the top surface of the first insulating layer within the first opening, and a third portion in contact with the second side surface of the first opening, with the first portion and the third portion being disposed with the first gate line sandwiched between them, and the second plurality of transistors have a second gate line shared by the second plurality of transistors, and in each of the second plurality of transistors, the second semiconductor layer has a fourth portion in contact with the third side surface of the second opening, a fifth portion in contact with the top surface of the first insulating layer within the second opening, and a sixth portion in contact with the fourth side surface of the second opening, with the fourth portion and the sixth portion being disposed with the second gate line sandwiched between them.

One embodiment of the present invention can provide a semiconductor device with a reduced occupation area. Alternatively, one embodiment of the present invention can provide a semiconductor device from which data can be accurately read. Alternatively, one embodiment of the present invention can provide a semiconductor device that can be easily manufactured. Alternatively, one embodiment of the present invention can provide a semiconductor device with a reduced occupation area. Alternatively, one embodiment of the present invention can provide a semiconductor device from which data can be accurately read. Alternatively, one embodiment of the present invention can provide a semiconductor device that can be easily manufactured. Alternatively, one embodiment of the present invention can provide an electronic device that includes the above-described memory device. Alternatively, one embodiment of the present invention can provide a novel memory device, a novel semiconductor device, or a novel electronic device.

Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. Note that the other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. Note that one embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above.

1A is a top view showing an example of the configuration of a storage device; FIG. 1B is a perspective view showing an example of the configuration of a storage device; FIG. 1C is a cross-sectional view showing an example of the configuration of a storage device; and FIG. 1D is a top view showing an example of the configuration of a storage device.
2A is a top view showing an example of the configuration of a storage device, FIG. 2B is a cross-sectional view showing an example of the configuration of a storage device, FIG. 2C is a perspective view showing an example of the configuration of a storage device, and FIG. 2D is a cross-sectional view showing an example of the configuration of a storage device.
3A is a top view showing an example of the configuration of a storage device, and FIGS. 3B and 3C are cross-sectional views showing the example of the configuration of a storage device.
Fig. 4A is a top view showing a configuration example of a memory device. Fig. 4B is a cross-sectional view showing a configuration example of a memory device. Fig. 4C is a top view showing a configuration example of a memory device. Figs. 4D and 4E are cross-sectional views showing configuration examples of a memory device. Figs. 5A to 5E are cross-sectional views showing examples of a method for manufacturing a memory device.
FIG. 6 is a cross-sectional view showing an example of the configuration of a storage device.
7A and 7B are cross-sectional and top views showing an example of the configuration of a storage device.
FIG. 8 is a cross-sectional view showing an example of the configuration of a storage device.
FIG. 9 is a cross-sectional view showing an example of the configuration of a storage device.
FIG. 10 is a cross-sectional view showing an example of the configuration of a storage device.
FIG. 11 is a cross-sectional view showing an example of the configuration of a storage device.
FIG. 12 is a block diagram showing an example of the configuration of a semiconductor device.
FIG. 13 is a diagram illustrating an example of a circuit configuration of a memory cell array and memory cells.
FIG. 14A is a graph showing an example of a hysteresis characteristic, and FIG. 14B is a timing chart showing an example of a method for driving a memory cell.
FIG. 15 is a conceptual diagram illustrating the hierarchy of a storage device.
FIG. 16A is a block diagram showing a configuration example of a semiconductor device, and FIG. 16B is a schematic perspective view showing the configuration example of the semiconductor device.
17A to 17E are diagrams illustrating an example of a storage device.
18A to 18D are diagrams showing an example of an electronic component.
19A and 19B are diagrams showing an example of an electronic device, and FIGS. 19C to 19E are diagrams showing an example of a mainframe computer.
Fig. 20A is a diagram illustrating an example of space equipment, and Fig. 20B is a diagram illustrating an example of a storage system applicable to a data center.
21A and 21B are diagrams illustrating the carrier concentration dependence of Hall mobility, and Fig. 21C is a cross-sectional view illustrating an indium oxide film.
22A1 to 22A7 and 22B1 to 22B6 are diagrams for explaining electrical connections.

(Notes regarding this specification)
In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (for example, a transistor, a diode, and a photodiode), or a device having such a circuit. A semiconductor device also refers to any device that can function by utilizing semiconductor characteristics. An example of a semiconductor device is an integrated circuit. Another example of a semiconductor device is a chip equipped with an integrated circuit. Another example of a semiconductor device is an electronic component in which a chip is housed in a package. For example, a memory device, a display device, a light-emitting device, a computing device, a lighting device, and an electronic device may themselves be a semiconductor device or may include a semiconductor device.

In this specification, "connection" includes, for example, "electrical connection." When using the term "electrical connection" to define the connection relationship between circuit elements as a physical entity, "electrical connection" includes, for example, "direct connection" and "indirect connection." "A and B are directly connected" refers to a connection between A and B without the intervention of a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" refers to a connection between A and B via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. In other words, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signals or potential interactions occur between A and B, then such a circuit can be defined as an entity, with "A and B being indirectly connected." Even if there is a time during the operation of the circuit when electrical signals or potential interactions do not occur between A and B, it can still be defined as "A and B being indirectly connected" if there is a time during the operation of the circuit when electrical signals or potential interactions occur between A and B. Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when no power supply voltage is supplied to a circuit and the circuit is not operating, the circuit can still be defined as "A and B being indirectly connected" (however, for example, this only applies when electrical signals or potential interactions occur between A and B during the operation of the circuit when power supply voltage is supplied to the circuit and the circuit is operating).

Below are specific examples of "indirect connection." First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in Figures 22A1 and 22A2. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," assuming that the circuit is operating, there is at least one time when a single transistor between A and B is in the on state, conducting, or allowing current to flow. Note that "A and B are indirectly connected" also includes times when a single transistor between A and B is in the off state or non-conducting. When "A and B are indirectly connected," if multiple transistors are connected between A and B, there is at least one time when each of the multiple transistors between A and B is in the on state, conducting, or allowing current to flow, assuming that the circuit is operating. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases where the multiple transistors between A and B are in an off state or non-conductive state at the same time or at different times. As another example, as shown in FIG. 22A3, when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply or GND, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

While we have provided examples of cases where an "indirect connection" can and cannot be established, here is another example of a case where an "indirect connection" cannot be established. Even if electrical signal transmission or potential interaction occurs between A and B during the circuit's operation, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in Figure 22A4. Another example of a case where A and B are connected via an insulator is when a transistor gate insulating film or the like is interposed between A and B, as shown in Figure 22A5. In this case, it cannot be said that "A (the transistor gate) and B (the transistor source or drain) are indirectly connected."

Another example of a case where it cannot be said that "A and B are indirectly connected" is when there is no timing when electrical signals are exchanged or potential interactions occur between A and B. An example of this is when, as shown in Figures 22A6 and 22A7, multiple transistors are connected via their sources and drains in the path from A to B, and a constant potential V is supplied to the node between the transistors from a power supply, GND, etc. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." In addition, in Figure 22A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, the connection relationship will be the same as in Figures 22A6 and 22A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected" or "B and C are indirectly connected."

Although we have given an example of "indirect connection," as an example, the provision for "indirect connection" is included in the provision for "electrical connection," so if "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

Next, specific examples of "direct connection" are shown. Examples of "A and B are directly connected" include cases where A and B are connected without any circuit elements between them, as shown in Figures 22B1, 22B2, and 22B3. Note that when A and B are connected to a power supply that supplies a constant potential V or to GND without any circuit elements between them, as shown in Figures 22B4 and 22B5, it is possible to say that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." Note that even when A (or B) is connected to a constant potential V via the source and drain of a transistor, as shown in Figure 22B6, it is still possible to say that "A and B are directly connected." Note that because A and V or B and V are connected via the source and drain of a transistor, they cannot be said to be directly connected; instead, it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected."

Although we have given an example of a "direct connection," the provision for a "direct connection" is included in the provision for an "electrical connection," so if "A and B are directly connected," it can also be said that "A and B are electrically connected."

Furthermore, in this specification, a "resistance element" can be, for example, a circuit element having a resistance value higher than 0 Ω, or a wiring having a resistance value higher than 0 Ω. Therefore, in this specification, a "resistance element" is intended to include a wiring having a resistance value, a transistor in which a current flows between a source and a drain, a diode, or a coil. The term "resistance element" can sometimes be replaced with the terms "resistance,""load," or "region having a resistance value." Conversely, the terms "resistance,""load," or "region having a resistance value" can sometimes be replaced with the term "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Alternatively, it may be, for example, 1 Ω or more and 1 x 10 ⁹ Ω or less.

In this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance greater than 0 F, a wiring region having a capacitance greater than 0 F, or the gate capacitance of a transistor. The terms "capacitive element" and "gate capacitance" can sometimes be replaced with "capacitance." Conversely, the term "capacitance" can sometimes be replaced with "capacitive element" or "gate capacitance." A "capacitive element" (including a "capacitive element" with three or more terminals) includes an insulator and a pair of conductors sandwiching the insulator. Therefore, the term "pair of conductors" in a "capacitive element" can be replaced with "pair of electrodes," "pair of conductive regions," "pair of regions," or "pair of terminals." The terms "one of the pair of terminals" and "the other of the pair of terminals" may be referred to as a first terminal and a second terminal, respectively. The capacitance value can be, for example, 0.05 fF to 10 pF. It may also be, for example, 1 pF to 10 μF.

In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input/output terminals of the transistor. One of the two input/output terminals serves as a source and the other as a drain depending on the transistor's conductivity type (n-channel or p-channel) and the level of the potential applied to the three terminals. For this reason, the terms "source" and "drain" are sometimes interchangeable. In this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" and "the other of the source or drain" are used. In addition, "one of the source or drain" may be interchangeable with "first terminal" or "first electrode," and "the other of the source or drain" may be interchangeable with "second terminal" or "second electrode." Note that, depending on the transistor structure, a backgate may be included in addition to the three terminals described above. In this specification, one of the gate or backgate of the transistor may be referred to as a first gate, and the other of the gate or backgate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "back gate" may be interchangeable. Also, if a transistor has three or more gates, the respective gates may be referred to as the first gate, second gate, third gate, etc. in this specification.

For example, in this specification, a transistor with a multi-gate structure having two or more gate electrodes can be used as an example of a transistor. With a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the transistor's breakdown voltage (improved reliability). Alternatively, with a multi-gate structure, when operating in the saturation region, even if the voltage between the drain and source changes, the current between the drain and source does not change much, resulting in a voltage-current characteristic with a flat slope. By utilizing voltage-current characteristics with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with good characteristics can be realized.

Furthermore, even when a circuit diagram shows a single circuit element, that circuit element may actually comprise multiple circuit elements. For example, when a circuit diagram shows one resistive element, this includes two or more resistive elements connected in series. For example, when a circuit diagram shows one capacitive element, this includes two or more capacitive elements connected in parallel. For example, when a circuit diagram shows one transistor, this includes two or more transistors connected in series, with the gates of the respective transistors connected to each other. Similarly, when a circuit diagram shows one switch, this includes two or more transistors connected in series or in parallel, with the gates of the respective transistors connected to each other.

Furthermore, in this specification, the term "node" can be referred to as a terminal, wiring, electrode, conductive layer, conductor, or impurity region, depending on the circuit configuration and device structure. Furthermore, terminals, wiring, etc. can also be referred to as nodes.

Furthermore, in this specification, the term "selector" may refer to, for example, a circuit having multiple input terminals and one output terminal, selecting one of the multiple input terminals, and establishing a state of conduction between the selected input terminal and the one output terminal. In other words, the term "selector" may refer to a circuit that selects one of the input signals input to each of the multiple input terminals and outputs the selected input signal to the output terminal. Alternatively, the term "selector" may refer to, for example, a circuit having multiple output terminals and one input terminal, selecting one of the multiple output terminals, and establishing a state of conduction between the selected output terminal and the one input terminal. In other words, the term "selector" may refer to a circuit that selects one of the multiple output terminals and outputs the input signal input to the input terminal to the selected output terminal. In other words, the term "selector" may refer to a multiplexer or demultiplexer. In particular, when inputting or outputting an analog potential or analog current, the selector may refer to an analog multiplexer or analog demultiplexer.

Furthermore, in this specification, "voltage" and "potential" can be used interchangeably as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is ground potential (earth potential), then "voltage" can be replaced with "potential." Note that ground potential does not necessarily mean 0V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to circuits, and the potential output from circuits also change.

Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not refer to specific potentials. For example, if two wirings are both described as "functioning as wirings that supply high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, if two wirings are both described as "functioning as wirings that supply low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

Furthermore, in this specification, the term "high potential" can be appropriately replaced with "high-level potential." Furthermore, in this specification, the term "low potential" can be appropriately replaced with "low-level potential."

Furthermore, "electric current" refers to the phenomenon of charge transfer (electrical conduction). For example, "electrical conduction of positively charged bodies is occurring" can be rephrased as "electrical conduction of negatively charged bodies is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) accompanying the movement of carriers. Examples of carriers here include electrons, holes, anions, cations, and complex ions. The carriers differ depending on the system through which the current flows (e.g., semiconductors, metals, electrolytes, and vacuums). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current flow and is expressed as a negative current amount. Therefore, in this specification, unless otherwise specified, the expression "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Additionally, the statement "current is input to element A" can be rephrased as "current is output from element A."

Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Also, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

Furthermore, in this specification, terms indicating position, such as "above" and "below," are sometimes used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, terms are not limited to those described in the specification, etc., and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing shown by 180 degrees.

Furthermore, the terms "above" and "below" do not limit the positional relationship between components to being directly above or below, and in direct contact. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B above insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B below insulating layer A" does not require that electrode B be formed in direct contact below insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

Furthermore, in this specification, terms such as "row" and "column" may be used to describe components arranged in a matrix and their relative positions. Furthermore, the relative positions of the components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, etc., and can be rephrased as appropriate depending on the situation. For example, the expression "row direction" can sometimes be rephrased as "column direction" by rotating the orientation of the drawing shown by 90 degrees.

Furthermore, in this specification, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film". Or, for example, the term "insulating film" can be changed to the term "insulating layer". Furthermore, in some cases or depending on the situation, the terms "film" and "layer" can be replaced with other terms without using them. For example, the terms "conductive layer" or "conductive film" can be changed to the term "conductor". Or, for example, the terms "insulating layer" or "insulating film" can be changed to the term "insulator".

Furthermore, the terms "electrode," "wiring," and "terminal" used in this specification do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are formed integrally. For example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where one or more selected from "electrode," "wiring," and "terminal" are formed integrally. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, the terms "electrode," "wiring," and "terminal" may be replaced with the term "region" in some cases.

Furthermore, in this specification, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the situation or circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to a term such as "power line." The reverse is also true: terms such as "signal line" or "power line" may be changed to the term "wiring." The term "power line" may be changed to the term "signal line." The reverse is also true: terms such as "signal line" may be changed to the term "power line." The term "potential" applied to wiring may be changed to the term "signal" depending on the situation or circumstances. The reverse is also true: the term "signal" may be changed to the term "potential."

Furthermore, this specification may use timing charts to explain the operation method of a semiconductor device. Furthermore, the timing charts used in this specification show ideal operation examples, and the periods, magnitudes, and timings of signals (e.g., potential or current) shown in the timing charts are not limited unless otherwise specified. The magnitudes and timings of signals (e.g., potential or current) input to each wiring (including a node) in the timing charts described in this specification may be changed depending on the situation. For example, even if two periods are shown at equal intervals in a timing chart, the lengths of the two periods may be different. For example, even if one period is shown as long and the other as short, the lengths of the two periods may be equal, or one period may be short and the other period may be long. To clearly illustrate the timing chart, for example, two or more overlapping signals may be intentionally shifted.

Furthermore, in this specification, semiconductor impurities refer to, for example, substances other than the main components that make up the semiconductor layer. For example, elements with a concentration of less than 0.1 atomic % are impurities. The presence of impurities may cause one or more of the following: an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity.

In this specification, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has the function of controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching the path through which a current flows. Therefore, a switch may have two or more terminals through which a current flows, in addition to a control terminal. As an example, an electrical switch, a mechanical switch, etc. can be used. In other words, a switch is not limited to a specific type as long as it has the function of controlling a current.

Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits that combine these. When a transistor is used as a switch, the "conductive state" of the transistor refers to, for example, a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited, or a state in which current can flow between the source electrode and drain electrode. Furthermore, the "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

One example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. Such a switch has an electrode that can be mechanically moved, and the movement of this electrode controls whether the switch is conductive or non-conductive.

In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases where the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases where the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

Furthermore, in this specification, the configurations shown in each embodiment can be combined as appropriate with the configurations shown in other embodiments to form one aspect of the present invention. Furthermore, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined with each other as appropriate.

Furthermore, the content (part or all of the content) described in one embodiment may be applied to, combined with, or substituted for at least one of the other content (part or all of the content) described in that embodiment and the content (part or all of the content) described in one or more other embodiments.

Note that the content described in the embodiments refers to the content described in each embodiment using various figures or the content described using text in the specification.

Furthermore, a figure (in whole or in part) described in one embodiment can be combined with at least one of another portion of that figure, another figure (in whole or in part) described in that embodiment, and one or more figures (in whole or in part) described in another embodiment, to form even more figures.

The embodiments described in this specification are explained with reference to the drawings. However, the embodiments can be implemented in many different ways, and those skilled in the art will readily understand that the form and details can be modified in various ways without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations may be omitted. Also, in perspective views, etc., the description of some components may be omitted to ensure clarity of the drawings.

In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", or "[m,n]" may be added to the reference numeral. Also, when an identification symbol such as "_1", "[n]", or "[m,n]" is added to a reference numeral in drawings, etc., the identification symbol may not be added if there is no need to distinguish between them in this specification.

Furthermore, in the drawings in this specification, sizes, layer thicknesses, or regions may be exaggerated for clarity. Therefore, they are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences, etc. may be included.

(Embodiment 1)
In this embodiment, a memory device which is a semiconductor device of one embodiment of the present invention will be described.

[Configuration Example 1]
Fig. 1A shows a schematic top view of a memory device having two memory cells 15. Fig. 1B shows a perspective view corresponding to the schematic top view of Fig. 1A, Fig. 1C shows schematic cross-sectional views taken along lines A1-A2, A2-A3, and A3-A4 shown in Fig. 1A, and Fig. 1D shows a schematic top view taken along chain double-dashed line B1-B2 shown in Fig. 1C.

In FIG. 1A, two memory cells 15 are arranged side by side along the direction in which the semiconductor layer 21 extends. The semiconductor layer 21 is provided across the two memory cells 15.

The memory cell 15 includes a transistor 20 and a capacitor 30 thereon. The capacitor 30 can be provided overlapping the transistor 20.

Memory cell 15 is a memory circuit having one transistor and one capacitive element, and has a DRAM (Dynamic Random Access Memory) configuration. Furthermore, by using a material that can have ferroelectric properties as the dielectric of the capacitive element, the capacitive element can be made into a ferroelectric capacitor, and memory cell 15 can have an FeRAM (Ferroelectric Random Access Memory) configuration.

The transistor 20 and the capacitor 30 are provided on an insulating layer 11 provided on a substrate (not shown). The insulating layer 11 functions as a base insulating layer. The transistor 20 has a portion located within an opening provided in the insulating layer 43.

Transistor 20 has a semiconductor layer 21, an insulating layer 22 that functions as a gate insulating layer, a conductive layer 23 that functions as a gate electrode, and a conductive layer 25a that functions as one of a source electrode and a drain electrode, and a conductive layer 25b that functions as the other. Conductive layer 25a is connected to conductive layer 24, and conductive layer 25b is connected to a capacitor element 30. Conductive layer 25a can be shared by two adjacent memory cells 15.

The conductive layer 23 is disposed within the opening of the insulating layer 43. The semiconductor layer 21 has a portion located within the opening of the insulating layer 43, and this portion faces the conductive layer 23 with the insulating layer 22 sandwiched therebetween.

Conductive layer 25a and conductive layer 25b are located on insulating layer 43, with conductive layer 23 sandwiched between them in a planar view.

Two memory cells are provided in one island-shaped semiconductor layer 21, and the two memory cells are connected to the same conductive layer 24. Furthermore, the transistors 20 in each of the two memory cells share conductive layer 25a, but have separate conductive layers 25b. Two conductive layers 23 are arranged perpendicular to conductive layer 24, with one conductive layer 25a sandwiched between them. Two conductive layers 25b are also arranged, each sandwiching one of the conductive layers 23 between them.

By configuring two transistors 20 provided on one island-shaped semiconductor layer 21 to share the conductive layer 25a, the integration density of the memory device can be increased. On the other hand, in memory cells connected to different bit lines, the semiconductor layers 21 are provided separately. This reduces noise, leakage, etc. between memory cells and improves the reliability of the memory device.

The capacitance element 30 has a conductive layer 51 that functions as a lower electrode, a conductive layer 53 that functions as an upper electrode, and an insulating layer 52 that is disposed between them and functions as a dielectric. The conductive layer 51 has a columnar shape.

In this specification, a columnar body refers to a structure having a high aspect ratio in a cross-sectional view. For example, in the cross-sectional view of FIG. 1C , the aspect ratio of the conductive layer 51 refers to the ratio of the length M of the conductive layer 51 in the A2-A3 direction (which can also be referred to as the width M of the conductive layer 51) to the length K (which can also be referred to as the height of the conductive layer 51) in a direction perpendicular or approximately perpendicular to the surface on which it is formed (e.g., one or both of the conductive layer 46b and the insulating layer 46). The aspect ratio of the conductive layer 51 is preferably as large as possible without causing the conductive layer 51 to collapse during the manufacturing process of the capacitive element 30. In other words, the height K of the conductive layer 51 is preferably greater than the width M of the conductive layer 51, provided that the conductive layer 51 does not collapse. Note that while the cross-sectional view of FIG. 1C has been described above as an example, the height H of the conductive layer 51 is preferably greater than the width L of the conductive layer 51, provided that the conductive layer 51 does not collapse, even in cross-sectional views other than those of FIG. 1C .

Furthermore, in this specification, the term "columnar body" may be alternatively referred to as "pillar." Furthermore, the columnar body or pillar may have a tapered shape. Furthermore, in this specification, a columnar body or pillar having a tapered shape may be referred to as a truncated cone.

In this specification, a tapered shape refers to a shape in which at least a portion of the side of a structure is inclined with respect to the substrate surface. Alternatively, it refers to a shape in which at least a portion of the side of a structure is inclined with respect to the film surface underlying the structure. The angle between the inclined side and the substrate surface or film surface is referred to as the taper angle. In this specification, a tapered shape with a taper angle greater than 0 degrees and less than 90 degrees is referred to as a forward taper shape, and a tapered shape with a taper angle greater than 90 degrees and less than 180 degrees is referred to as a reverse taper shape.

As shown in Figures 1C and 1D, the insulating layer 52 covers the side surfaces of the columnar shape of the conductive layer 51. Furthermore, the conductive layer 53 has a portion that faces the side surface of the conductive layer 51, with the insulating layer 52 sandwiched between them. Figure 1D shows an example in which the conductive layer 51 is circular in plan view, the insulating layer 52 and the conductive layer 53 have highly uniform film thicknesses, and the outlines (also called perimeters) of each layer in plan view, more specifically, the outer outlines, are circular.

Figure 2A shows a schematic top view of the memory device 10. The memory device 10 shown in Figure 2A has a plurality of memory cells 15 shown in Figure 1A. In Figure 2A, the plurality of memory cells 15 are arranged in a matrix. Note that a conductive layer 53 overlaps the conductive layer 51, but here, to make the conductive layer 51 easier to see, the conductive layer 51 is shown with a solid line instead of a dotted line.

Figure 2B shows schematic cross-sectional views taken along the cutting lines A5-A6, A6-A7, and A7-A8 shown in Figure 2A, and Figure 2C shows a perspective view corresponding to a portion of Figure 2A.

The memory device 10 has a configuration in which multiple memory cells 15 are arranged along a line 99 that forms an angle θ with the X-axis and along a line that is perpendicular to the Z-axis and perpendicular to the line 99. In the plan view shown in FIG. 2A and other figures, the semiconductor layer 21 has a strip-like region extending along the line 99. In FIG. 2A, an example is shown in which θ is 27°. θ can be, for example, 30° or an angle close to that. Reducing θ can sometimes increase the integration density of the memory device. On the other hand, θ is preferably large enough so that the region where the conductive layer 51 of the capacitance element 30 is formed does not overlap with the conductive layer 24 functioning as the bit line. θ can be, for example, 10° to 35°. In the memory device 10, the conductive layer 24 functioning as the bit line and the conductive layer 23 functioning as the word line are preferably arranged to intersect. In the memory device 10, the conductive layer 24 functioning as the bit line extends in the X-direction, and the conductive layer 23 functioning as the word line extends in the Y-direction.

The conductive layer 23 can function as a gate line shared by multiple transistors 20 arranged in sequence in the Y direction. The conductive layer 23 can function as a gate electrode for each of the multiple shared transistors 20.

In addition, in FIG. 2A, in the region surrounded by a dashed square line, memory cells 15 are arranged in a matrix, and conductive layer 24 extends in the X direction to region 80 on the left side (the negative X coordinate side). In region 80 shown in FIG. 2A, conductive layer 24 may be connected to peripheral circuits of memory cells 15, for example. Region 80 will be described later in FIG. 12.

Memory cell 15, transistor 20, and capacitor 30 can be applied to memory cell MC or memory cell 1480, transistor M9, and capacitor Cfe, respectively, in embodiment 2 described below. Furthermore, conductive layer 24 and conductive layer 23 can be applied to wiring BL and wiring WL, respectively.

In a transistor according to one embodiment of the present invention, a semiconductor layer is formed along the side and bottom surfaces of a slit-shaped opening in an insulating layer, and a gate insulating layer and a gate electrode are formed in this order on the semiconductor layer. By deepening the opening, the channel length can be increased without increasing the area of the transistor in a planar view.

In the memory device shown in Figures 1A to 2C, a slit-shaped opening is provided in the insulating layer 43, and the longitudinal direction of the slit coincides with the Y direction. It can also be expressed as having a slit-shaped opening extending in the Y direction in the insulating layer 43. It can also be expressed as having a region that extends in a band shape in a plan view.

A plurality of semiconductor layers 21 are provided in the slit along the Y direction. For example, each of the plurality of semiconductor layers 21 is included in a different transistor 20. The plurality of semiconductor layers 21 are arranged in order along the Y direction.

The conductive layer 23 is provided extending in the Y direction within an opening extending in the Y direction. The slit-shaped opening in the insulating layer 43 has a first side surface and a second side surface facing each other with the conductive layer 23 sandwiched therebetween. The first side surface and the second side surface each extend in the Y direction.

By using a planarization process using polishing or an etch-back process using dry etching to make the upper surface of the conductive layer 23 lower than the upper surface of the insulating layer 22 outside the opening, the conductive layer 23 can be processed without using a photomask or the like. For example, the upper surface of the conductive layer 23 may be higher than the lower surfaces of the conductive layers 25a and 25b. The transistor 20 shown in Figure 1C and other figures shows an example in which the upper surface of the conductive layer 23 is lower than the upper surfaces of the conductive layers 25a and 25b.

In transistor 20, a current path is formed in semiconductor layer 21 in the following order: a portion in contact with one of conductive layer 25a and conductive layer 25b, a portion in contact with one of the first side surface and second side surface, a portion in contact with the top surface of insulating layer 11, a portion in contact with the other of the first side surface and second side surface, and a portion in contact with the other of conductive layer 25a and conductive layer 25b.

An insulating layer 44 is provided covering the transistor 20. An insulating layer 45 is provided on the insulating layer 44. An insulating layer 46 and a conductive layer 24 are provided on the insulating layer 45. An insulating layer 46 is provided on the insulating layer 45 and the conductive layer 24. An insulating layer 47 and an insulating layer 48 are provided in this order on the insulating layer 46.

Conductive layer 25a and conductive layer 24 are connected via conductive layer 88a. Conductive layer 88a is formed so as to be embedded in insulating layer 45, insulating layer 44, and semiconductor layer 21, and can function as a plug.

A capacitance element 30 is provided on the insulating layer 46.

The conductive layer 51 of the capacitor 30 is connected to the conductive layer 25b of the transistor 20 via the conductive layer 46b and the conductive layer 88b. The conductive layer 88b is formed so as to be embedded in the insulating layer 46, the insulating layer 45, the insulating layer 44, and the semiconductor layer 21, and can function as a plug. The conductive layer 46b is formed on the insulating layer 46 and the conductive layer 88b. The conductive layer 46b has a portion that overlaps with the conductive layer 51 and a portion that overlaps with the conductive layer 88b.

Note that in the configurations shown in Figures 1A to 1C and Figures 2A to 2D, the conductive layer 51 overlaps the conductive layer 23 in plan view. This allows for a configuration in which the direction in which the multiple capacitance elements 30 are provided and the direction in which the conductive layer 23 extends to coincide, as shown in Figures 2A to 2D.

The conductive layer 51 has a portion embedded in the insulating layer 47 and a portion embedded in the insulating layer 48. The conductive layer 51 also has a columnar portion protruding above the insulating layer 48. While Figures 1A to 2C and other figures show examples in which the conductive layer 51 has a columnar shape and the bottom shape of the column is circular, the bottom shape is not limited to a circle and can be an ellipse, a rectangle with rounded corners, or the like. The outline shape of the conductive layer 51 in a planar view may be a regular polygon such as an equilateral triangle, square, or regular pentagon, or a polygon other than a regular polygon. The channel width can be increased by using a concave polygon, such as a star-shaped polygon, which is a polygon with at least one interior angle exceeding 180°. Other shapes include a polygon with rounded corners and a closed curve combining straight lines and curves.

In the memory device 10 shown in Figures 2A to 2D, the conductive layer 53 may be shared between two adjacent capacitance elements 30.

Figure 2D is a modified example of the capacitance element shown in Figure 2B, in which conductive layer 53 is formed to fill the region between conductive layers 51, and the upper surface of conductive layer 53 is made approximately flat.

Furthermore, Figure 7A is a modified example of Figure 1C, showing an example in which the upper part of conductive layer 51 is rounded. In Figure 7A, conductive layer 51 has rounded upper corners in a cross-sectional view. By using a rounded shape, it is possible to alleviate electric field concentration between conductive layer 51 and conductive layer 53. Alleviating electric field concentration can suppress short circuits in capacitive element 30, thereby improving the reliability of memory device 10.

As shown in Figures 1D and 2A, the conductive layer 53 of the capacitance element 30 has a columnar appearance, with a conductive layer 51 and an insulating layer 52 disposed inside. As shown in Figure 2A, the conductive layer 53 has a shape in which adjacent circles overlap in a plan view. It can also be expressed as the conductive layers 53 of the two capacitance elements 30 overlapping and connected.

By connecting the conductive layers 53 of adjacent capacitance elements 30, multiple memory cells 15 can be arranged at high density. The conductive layers 53 can function as wiring. Since the length of the wiring can be shortened, wiring resistance can sometimes be reduced.

In plan view, the conductive layer 53 has a shape in which adjacent circles overlap each other, and the adjacent circles are aligned in the Y direction. In FIG. 2A, in the capacitive elements 30 aligned in the Y direction, one adjacent capacitive element is connected to the conductive layer 53, and the other adjacent capacitive element is separated by the conductive layer 53. Here, as shown in FIGS. 3A and 3B, by placing a dummy pattern capacitive element (hereinafter referred to as capacitive element dm) between the two separated conductive layers 53, the conductive layer 53 can be extended in the Y direction.

For example, the conductive layer 51 is provided separately for each of the multiple capacitance elements 30. The insulating layer 52 can be shared by the multiple capacitance elements 30. Alternatively, the insulating layer 52 can be provided separately for each of the multiple capacitance elements 30.

Figure 3A shows a schematic top view of the memory device 10, and Figure 3B shows a schematic cross-sectional view taken along the cutting line A9-A10. Note that conductive layer 53 overlaps conductive layer 51, but in Figure 3B, conductive layer 51 is shown with a solid line instead of a dotted line to make it easier to see.

In the plan view of Figure 3A, the conductive layer 53 has a shape in which adjacent circles overlap each other and multiple circles are arranged along the Y direction. For this reason, the conductive layer 53 is sometimes referred to as rosary-shaped wiring. The memory device 10 shown in Figure 3A has multiple rosary-shaped wiring that extends in the Y direction, and the multiple wirings are arranged in order in the X direction.

Furthermore, the conductive layer 53 has a region that functions as wiring. As an example, the conductive layer 53 has a region that functions as wiring PL, which will be described in embodiment 2 below.

In particular, when the capacitive element 30 of the memory device 10 is a ferroelectric capacitor, the conductive layer 53 (wiring PL) functions as a plate line for transmitting a predetermined signal when writing or reading data from the memory cell 15.

Note that if the memory device 10 is a DRAM rather than an FeRAM, the conductive layer 53 (wiring PL) preferably functions as wiring for applying a fixed potential.

By the way, since the conductive layer 53 functions as one of the multiple wirings PL, adjacent wirings need to be electrically isolated from each other. In the memory device 10 shown in Figure 3A, adjacent rosary-shaped wirings in the X direction are spaced apart, and can be suitably used as electrically isolated wirings.

Furthermore, the wiring is configured to connect the conductive layers 53 of adjacent capacitance elements 30, and in the region of the conductive layer 53 sandwiched between the conductive layers 51 between multiple capacitance elements 30, the conductive layer 53 is provided so as to fill the spaces between the conductive layers 51, allowing the thickness of the conductive layer 53 in the height direction (Z direction) to be increased. By making the conductive layer 53 thicker, the wiring resistance can be reduced.

Furthermore, since the conductive layer 53 can function as a plate line, the manufacturing process can be simplified compared to when a separate plate line is provided.

Furthermore, for example, if a plate line is provided separately in a layer above or below the capacitive element 30, the plate line and the conductive layer 53 of the capacitive element can be connected using a plug or the like. In this case, if the plug is provided on the top surface of the conductive layer 53, depending on the thickness of the conductive layer 53, there is a concern that the plug may penetrate the insulating layer 52 below the conductive layer 53, causing a short circuit between the plug and the conductive layer 51. If the plug is positioned so that it does not overlap the conductive layer 51 in a plan view in order to avoid a short circuit, there is a concern that this will result in an increase in the circuit area.

In the memory device 10 shown in Figures 3A and 3B, the conductive layer 53 functions as a plate line, which enables circuit integration and improved reliability of the memory device.

Furthermore, Figure 3C shows a modified example of Figure 3B. In the configuration shown in Figure 3C, conductive layer 53 has a portion that faces the side of conductive layer 51 with insulating layer 52 sandwiched therebetween, and does not cover the top surface of conductive layer 51. If a planarization process using a polishing method is used to form conductive layer 53, the configuration shown in Figure 3C may be obtained.

By using a low-resistance material for the conductive layer 53, the wiring resistance can be reduced.

The capacitance element dm, which functions as a dummy pattern, has a conductive layer 51, similar to the capacitance element 30. An insulating layer 52 is provided on the conductive layer 51 of the capacitance element dm, and a conductive layer 53 is provided on the insulating layer 52. In the capacitance element dm, similar to the capacitance element 30, the conductive layer 53 has a portion facing the side of the conductive layer 51 and a portion facing the top surface of the conductive layer 51, with the insulating layer 52 sandwiched between them.

Furthermore, in the capacitor dm, the conductive layer 51 is not connected to the conductive layer 25b of the transistor 20 and is in a floating state. Therefore, a plug for connecting to the conductive layer 25b does not need to be provided below the conductive layer 51. Because one of the pair of electrodes of the capacitor dm is in a floating state, it does not retain data, unlike the capacitor 30.

In Figure 7B, to make it easier to see the memory cells 15 corresponding to each conductive layer 23 and conductive layer 24 in the top view shown in Figure 2A, the conductive layers 23, 24, and memory cells 15 are numbered and represented as conductive layer 23[x], conductive layer 24[y], and memory cell 15[y,x]. Memory cell 15[y,x] is the memory cell 15 connected to conductive layer 23[x] and conductive layer 24[y]. x and y are each positive integers.

Figure 7B shows four conductive layers 23 arranged in order: conductive layer 23[1], conductive layer 23[2], conductive layer 23[3], and conductive layer 23[4]; and three conductive layers 24 arranged in order: conductive layer 24[1], conductive layer 24[2], and conductive layer 24[3]. Figure 7B also shows memory cells 15[y, x] where x = 1 to 4 and y = 1 to 3.

Figure 7B shows memory cell 15[1,2], memory cell 15[2,2], and memory cell 15[3,2] as memory cells 15 connected to conductive layer 23[2]. By providing a capacitance element dm between the capacitance element 30 of memory cell 15[2,2] and the capacitance element 30 of memory cell 15[3,2], the conductive layers 53 in memory cell 15[1,2], memory cell 15[2,2], and memory cell 15[3,2] can be connected in a rosary pattern and used as a common plate line.

Furthermore, in memory cell 15[1,1], memory cell 15[2,1], and memory cell 15[3,1] connected to conductive layer 23[1], by providing capacitance element dm between capacitance element 30 of memory cell 15[1,1] and capacitance element 30 of memory cell 15[2,1], the conductive layers 53 in memory cell 15[1,1], memory cell 15[2,1], and memory cell 15[3,1] can be connected in a rosary shape and used as a common plate line.

Furthermore, in memory cell 15[1,3], memory cell 15[2,3], and memory cell 15[3,3] connected to conductive layer 23[3], by providing capacitance element dm between capacitance element 30 of memory cell 15[1,3] and capacitance element 30 of memory cell 15[2,3], the conductive layers 53 in memory cell 15[1,3], memory cell 15[2,3], and memory cell 15[3,3] can be connected in a rosary shape and used as a common plate line.

Furthermore, in memory cell 15[1,4], memory cell 15[2,4], and memory cell 15[3,4] connected to conductive layer 23[4], by providing capacitance element dm between capacitance element 30 of memory cell 15[2,4] and capacitance element 30 of memory cell 15[3,4], the conductive layers 53 in memory cell 15[1,4], memory cell 15[2,4], and memory cell 15[3,4] can be connected in a rosary shape and used as a common plate line.

In the memory device 10 shown in Figures 1A to 2C and Figure 7B, etc., in the transistors 20 of two memory cells 15 (e.g., memory cell 15[1,1] and memory cell 15[1,2] shown in Figure 7B) that share a semiconductor layer 21, as shown in Figure 1C, conductive layer 25a connected to conductive layer 24 via conductive layer 88a is shared. On the other hand, conductive layer 25b is provided separately in each.

In the transistor 20, the semiconductor layer 21 has a portion that contacts the side of the insulating layer 43 and a portion that contacts the top surface of the insulating layer 11. The side of the insulating layer 43 is preferably perpendicular to the top surface of the insulating layer 11. Note that the side of the insulating layer 43 does not necessarily have to be strictly perpendicular to the top surface of the insulating layer 11. If the side of the insulating layer 43 is inclined with respect to the Z direction, the semiconductor layer 21 is also inclined along the side. The semiconductor layer 21 also has portions that contact the side of the conductive layer 25a and the side of the conductive layer 25b, and these portions can function as one and the other of the source and drain regions of the transistor. Furthermore, the vicinity of the portion of the semiconductor layer 21 that contacts the side of the conductive layer 25a may also function as one of the source and drain regions. Similarly, the vicinity of the portion that contacts the side of the conductive layer 25b may also function as the other of the source and drain regions. In the semiconductor layer 21, the region sandwiched between the source and drain regions functions as a channel formation region. For example, in the semiconductor layer 21, at least a portion of the region in contact with the side surface of the insulating layer 43 functions as a channel formation region.

The semiconductor layer 21 has a portion that is provided along the side of the insulating layer 43 and whose surface (either or both of the surface of the semiconductor layer 21 facing the insulating layer 43 or the surface of the insulating layer 22) is perpendicular or approximately perpendicular to the top surface of the insulating layer 11, and a portion that is provided along the top surface of the insulating layer 11 and whose surface (the surface of the semiconductor layer 21 facing the insulating layer 11 or the surface of the insulating layer 22) is parallel or approximately parallel to the top surface of the insulating layer 11.

In the memory device 10, the insulating layer 43 has two side surfaces (hereinafter referred to as the first side surface and the second side surface) that face each other with the conductive layer 23 sandwiched therebetween. The semiconductor layer 21 has a portion that contacts the first side surface and a portion that contacts the second side surface. The portion that contacts the first side surface and the portion that contacts the second side surface are arranged with the gate electrode sandwiched between them.

The channel formation region of transistor 20 is provided along the side of an opening provided in insulating layer 43. In the cross-sectional view shown in Figure 1C, etc., semiconductor layer 21 can also be described as having a U-shape. Current flows through semiconductor layer 21 along the U-shape. In transistor 20, the channel length direction has not only a horizontal portion but also a vertical portion. Therefore, the occupied area can be reduced compared to so-called planar transistors in which semiconductors are arranged on a flat surface.

Furthermore, in transistor 20, conductive layers 25a and 25b can be formed at different heights from the channel formation region. That is, the source and drain electrodes can be formed at different heights from the channel formation region. This can be considered a configuration that makes it easier to suppress the short channel effect. Furthermore, even when the channel length is increased to a level that sufficiently suppresses the short channel effect, an increase in the area occupied by transistor 20 can be suppressed.

When a metal oxide is used for the semiconductor layer 21, the semiconductor layer 21 can be easily formed on the side surface of the opening provided in the insulating layer 43 using a thin-film method. By configuring the semiconductor layers of adjacent transistors to be insulated by the insulating layer 43, noise, leakage, and the like between adjacent transistors can be minimized. Therefore, a highly reliable memory device can be realized even when miniaturization is performed and integration is increased.

Furthermore, the channel length of the transistor 20 can be precisely controlled by the thickness of the insulating layer 43, which functions as a spacer. Therefore, the variation in channel length can be significantly reduced compared to planar transistors. Furthermore, by thinning the insulating layer 43, transistors with extremely short channel lengths can be fabricated. For example, transistors with channel lengths of 10 nm to 2 μm, 10 nm to 1 μm, 10 nm to 500 nm, 10 nm to 300 nm, 10 nm to 200 nm, 10 nm to 100 nm, 15 nm to 100 nm, 20 nm to 100 nm, or 20 nm to 50 nm can be fabricated. Therefore, transistors with extremely short channel lengths that could not be achieved using mass-production exposure equipment can be fabricated. Furthermore, transistors with channel lengths of less than 20 nm can be fabricated without using the extremely expensive exposure equipment used in cutting-edge LSI technology.

Conductive layers 25a1 and 25b1 of transistor 20 are preferably made of a conductive material with lower resistance than conductive layers 25a2 and 25b2. In particular, they preferably contain a metal material. Conductive layers 25a2 and 25b2 are preferably made of a conductive metal oxide (oxide conductor).

Using a conductive metal oxide for conductive layer 25a2 and conductive layer 25b2, which are in contact with semiconductor layer 21 containing a metal oxide, is preferable because it reduces the contact resistance between them and reduces the load on the wiring. In particular, it is preferable for conductive layer 25a2 and conductive layer 25b2 to contain the same metal element as the metal element contained in semiconductor layer 21, as this further reduces the contact resistance. Furthermore, using a metal material with lower resistance than conductive layer 25a2 and conductive layer 25b2 for conductive layer 25a1 and conductive layer 25b1 makes it possible to reduce both the contact resistance and the wiring resistance, thereby further reducing the load on the wiring.

In the memory device 10, insulating layers 44, 46, and 47 function as interlayer insulating films. Insulating layers 44, 46, and 47 can be made of inorganic insulating materials such as silicon oxide and silicon oxynitride. For insulating layers 45 and 48, it is preferable to use an insulating film that has barrier properties against hydrogen. This prevents hydrogen from diffusing from above insulating layers 45 and 48 toward the semiconductor layer 21. For insulating layers 45 and 48, it is preferable to use a silicon nitride film, silicon nitride oxide film, aluminum oxide film, magnesium oxide film, hafnium oxide film, gallium oxide film, or the like. It is particularly preferable to use a silicon nitride film or a silicon nitride oxide film.

[Configuration Example 2]
4A shows a schematic top view of the storage device 10, and FIG. 4B shows a schematic cross-sectional view taken along the cutting lines A11-A12 and A12-A13 shown in FIG. 4A.

In the memory device 10 shown in FIG. 4A, compared to FIG. 2A, adjacent capacitance elements 30 in the Y direction are arranged with a gap between them. Furthermore, adjacent capacitance elements 30 in the X direction with a single conductive layer 23 sandwiched between them are arranged so that their Y coordinates are offset. Therefore, the configuration shown in FIG. 4A can increase the packing rate of capacitance elements 30. This may enable an increase in the integration density of the memory device 10.

Also, in FIG. 4A, the conductive layer 51 of the capacitance element 30 is shifted closer to the conductive layer 24 than the position of the conductive layer 25b. As a result, the conductive layer 51 may have a portion that overlaps with the conductive layer 24 in a planar view.

Figure 4C shows a configuration in which the conductive layers 53 that were spaced apart in multiple capacitance elements 30 arranged side by side in the Y direction in Figure 4A are connected. The conductive layers 53 are shared by multiple capacitance elements 30 arranged side by side in the Y direction and can function as wiring extending in the Y direction.

Figure 4D shows a schematic cross-sectional view taken along the cutting line A14-A15 shown in Figure 4C. Note that Figure 4C omits the configuration below the insulating layer 46. The conductive layer 53 is shared by multiple capacitive elements 30 arranged in the Y direction.

Figure 4E also shows a modified example of Figure 4D. Figure 4D shows an example in which the thickness of conductive layer 53 is roughly the same in the portion covering the side surface of conductive layer 51 and the portion covering the top surface, whereas Figure 4E shows an example in which conductive layer 53 is formed so as to be embedded in the region between conductive layers 51, and the top end is roughly flat.

In the configuration shown in Figure 4D, for example, when removing portions of conductive layer 53 between patterns, the conductive film in the portions to be removed is thin, which may make it easier to remove. On the other hand, in the configuration shown in Figure 4E, for example, the conductive layer 53 is thick, which may make it possible to reduce the wiring resistance of conductive layer 53.

[Example of manufacturing method]
An example of a method for manufacturing a memory device of one embodiment of the present invention will be described below, taking the memory device 10 illustrated in FIG. 2B as an example.

The thin films (insulating films, semiconductor films, conductive films, etc.) that make up memory devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), and atomic layer deposition (ALD). CVD methods include plasma enhanced chemical vapor deposition (PECVD) and thermal CVD (TCVD). One type of thermal CVD method is metal organic chemical vapor deposition (MOCVD).

Furthermore, the thin films (insulating films, semiconductor films, conductive films, etc.) that make up the memory device can be formed by methods such as spin coating, dipping, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

Sputtering methods include RF sputtering, which uses a high-frequency power source as the sputtering power source; DC sputtering, which uses a direct-current power source; and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is suitable for film deposition using insulating targets. DC sputtering is primarily used for depositing metal conductive films. In addition to forming conductive films, DC sputtering can also be used to form insulating films through reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used to deposit films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

CVD methods can be classified into PECVD, TCVD, and photo-CVD (photo-CVD) methods, which use light. They can also be further divided into metal CVD (MCVD) and MOCVD methods depending on the source gas used.

Plasma CVD can produce high-quality films at relatively low temperatures. Furthermore, because thermal CVD does not use plasma, it is possible to minimize plasma damage to the workpiece. Furthermore, because thermal CVD does not cause plasma damage during film formation, it produces films with fewer defects.

ALD methods that can be used include thermal ALD, in which the reaction between the precursor and reactant is carried out using only thermal energy, and PEALD, which uses plasma-excited reactants.

Unlike sputtering, CVD and ALD are film formation methods that are less affected by the shape of the workpiece and have good step coverage. ALD, in particular, has excellent step coverage and thickness uniformity, making it suitable for coating the surfaces of openings with high aspect ratios. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which have a faster film formation rate.

CVD methods allow for the deposition of films of any composition by adjusting the flow rate ratio of the source gases. For example, CVD methods allow for the deposition of films with continuously changing compositions by changing the flow rate ratio of the source gases while the film is being deposited. When depositing a film while changing the flow rate ratio of the source gases, the time required for film deposition can be shortened compared to when multiple deposition chambers are used, as no time is required for transport or pressure adjustment. This can potentially increase the productivity of memory devices.

With the ALD method, films of any desired composition can be deposited by simultaneously introducing multiple different precursors. Alternatively, when multiple different precursors are introduced, films of any desired composition can be deposited by controlling the number of cycles of each precursor. Also, as with the CVD method, films with continuously changing compositions can be deposited.

Furthermore, the thin films that make up the memory device can be processed using methods such as photolithography. Alternatively, the thin films may be processed using methods such as nanoimprinting, sandblasting, and lift-off. Furthermore, island-shaped thin films may be directly formed using a film-forming method that uses a shielding mask such as a metal mask.

There are two typical photolithography methods. One is to form a resist mask on the thin film to be processed, process the thin film by etching or other methods, and then remove the resist mask. The other is to form a photosensitive thin film, then expose and develop it to process it into the desired shape.

In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed using immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as light for exposure. Electron beams can also be used instead of light for exposure. Extreme ultraviolet light, X-rays, or electron beams are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

Thin film etching can be performed using methods such as dry etching, wet etching, and sandblasting.

First, a substrate (not shown) is prepared, and an insulating layer 11 is formed on the substrate.

The substrate can be one that is heat-resistant enough to withstand at least the subsequent heat treatment.

The insulating layer 11 can be an inorganic insulating film such as a silicon oxide film or a silicon oxynitride film. The insulating layer 11 can be formed by sputtering, CVD, MBE, PLD, ALD, or other methods. If the surface on which the insulating layer 11 is to be formed is not flat, a planarization process may be performed after the insulating layer 11 is formed to make the upper surface of the insulating layer 11 flat.

Next, an insulating film that will become insulating layer 43 is formed on insulating layer 11. It is preferable to use an oxide film for this insulating film that contains enough oxygen to release oxygen when heated, and has a low hydrogen content.

Next, heat treatment may be performed. The heat treatment may be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be approximately 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to replenish desorbed oxygen. By performing the above heat treatment, impurities such as water and hydrogen contained in the insulating film can be reduced before the formation of an oxide semiconductor film that serves as a semiconductor layer.

Next, a conductive film that will become conductive layer 25a and conductive layer 25b is formed on the insulating film that will become insulating layer 43.

Next, slit-shaped openings are formed in the conductive film that will become conductive layers 25a and 25b. Subsequently, using the conductive layer with the openings as a mask, slit-shaped openings are formed in the insulating film that will become insulating layer 43, thereby forming insulating layer 43.

When processing the insulating layer 43, it is preferable to use anisotropic dry etching so that the side surfaces are approximately vertical. However, depending on the processing conditions, the side surfaces of the insulating layer 43 may be inclined relative to the direction perpendicular to the surface on which they are formed, resulting in a tapered shape.

Next, a semiconductor film that will become the semiconductor layer 21 is deposited, covering the conductive layer with the slit-shaped openings and the insulating layer 43.

The semiconductor film can be a metal oxide (oxide semiconductor) film with semiconductor properties. The metal oxide film can be formed by a sputtering method, CVD method, MBE method, PLD method, ALD method, or the like, as appropriate.

Next, unnecessary portions of the semiconductor film that will become semiconductor layer 21 are removed by etching, forming semiconductor layer 21. Subsequently, unnecessary portions of the conductive layer below semiconductor layer 21 are removed by etching, forming conductive layer 25a and conductive layer 25b (Figure 5A). Note that while conductive layer 25a is not shown in the cross sections shown in Figures 5A to 5E, conductive layer 25a can be fabricated by referring to the fabrication method for conductive layer 25b.

Next, an insulating layer 22 is formed. Subsequently, a conductive layer 23 is formed to fill the slit-shaped openings in the insulating layer 43 (Figure 5B).

Next, insulating layer 44 and insulating layer 45 are formed in this order on conductive layer 23 and insulating layer 22. Openings are then formed in insulating layer 45, insulating layer 44, and semiconductor layer 21, and conductive layer 88a is formed to fill the openings. Note that conductive layer 88a is not shown here.

Next, the conductive layer 24 is formed on the insulating layer 45. Subsequently, the insulating layer 46 is formed on the insulating layer 45 and the conductive layer 24.

Next, openings are formed in insulating layer 46, insulating layer 45, insulating layer 44, and semiconductor layer 21, and conductive layer 88b is formed to fill the openings.

Next, conductive layer 46b is formed on insulating layer 46 and conductive layer 88b. Subsequently, insulating layer 47, insulating layer 48, and insulating layer 79 are formed in this order on conductive layer 46b and insulating layer 46. Here, insulating layer 79 is an insulating layer that is removed after conductive layer 51 is formed. Therefore, insulating layer 79 is sometimes called a sacrificial layer.

Next, openings are formed in insulating layer 79, insulating layer 48, and insulating layer 47, reaching conductive layer 46b. Subsequently, conductive layer 51 is formed by filling the openings with a conductive layer (Figure 5C).

Next, insulating layer 79 is removed by etching. By using an insulating layer with a relatively low etching rate under the etching conditions for insulating layer 79 as insulating layer 48, insulating layer 48 can function as an etching stopper for insulating layer 79.

Next, an insulating layer 52 is formed to cover the side and top surfaces of the conductive layer 51 and the top surface of the insulating layer 48. Next, a conductive film 53f, which will become the conductive layer 53, is formed on the insulating layer 52 (Figure 5D).

Next, a conductive layer 53 is formed by removing part of the conductive film 53f, and a memory device of one embodiment of the present invention can be manufactured (Figure 5E).

[Configuration Example 3]
In the memory device 10, a layer in which functional circuits are provided can be stacked on a layer in which memory cells 15 are provided. The functional circuits can include, for example, a driver circuit for driving the memory cells 15, as well as an arithmetic circuit and a power supply circuit. The driver circuit can include, for example, one or more of a row decoder, a column decoder, a row driver, a column driver, an input circuit, an output circuit, a sense amplifier, etc. This can reduce the footprint of the semiconductor chip including the memory device 10 and can shorten the wiring length compared to when the functional circuits and the memory cells 15 are arranged side by side, thereby achieving high-speed operation and low power consumption.

Figure 6 shows an example in which a transistor 90 constituting a functional circuit is arranged below the insulating layer 11. Here, one of the source electrode and drain electrode of the transistor 90 is connected to a conductive layer 24 that functions as a bit line. Figure 6 corresponds to region 80 shown in Figure 2A and is a schematic cross-sectional view taken along line C1-C2.

Transistor 90 is a transistor in which a channel is formed in a portion of substrate 91, which is a single-crystal semiconductor substrate. Substrate 91 can typically be made of single-crystal silicon. Substrate 91 can also be made of a semiconductor composed of a single element such as germanium, or a compound semiconductor composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or gallium nitride. Alternatively, substrate 91 can be a semiconductor substrate having an insulator region within the aforementioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate.

Transistor 90 is provided on substrate 91 and has a conductive layer 94 that functions as a gate, an insulating layer 93 that functions as a gate insulating layer, a semiconductor region 92 made of part of the substrate 91, and low-resistance regions 95a and 95b that function as source and drain regions. Transistor 90 may be either a p-channel or n-channel type. An element isolation layer 98 is provided on substrate 91 between two adjacent transistors 90.

Transistor 90 has a semiconductor region 92 in which a channel is formed that has a convex shape (fin shape). Although not shown in FIG. 6 , a conductive layer 94 is provided to cover the side and top surfaces of semiconductor region 92 in the X direction, with an insulating layer 93 interposed between them. Such a transistor 90 is also called a FIN-type transistor.

An insulating layer 85 is provided covering the transistor 90, an insulating layer 86 is provided on the insulating layer 85, and an insulating layer 87 is provided on the insulating layer 86. A conductive layer 81 is provided so as to be embedded in the insulating layer 87. An insulating layer 11 is provided covering the conductive layer 81 and the insulating layer 87. A plug 82 is provided inside an opening provided in the insulating layer 85 and the insulating layer 86, and the plug 82 connects the conductive layer 81 to the low-resistance region 95b. A plug 83 is provided inside an opening provided in the insulating layer 43 and the insulating layer 11, and the plug 83 connects the conductive layer 25c to the conductive layer 81. A conductive layer 88c is provided inside an opening provided in the insulating layer 44 and the insulating layer 45. The conductive layer 25c is connected to the conductive layer 24 via the conductive layer 88c.

Conductive layer 25c includes conductive layer 25c1 and conductive layer 25c2 on conductive layer 25c1. For materials, structures, etc. that can be used for conductive layer 25c1 and conductive layer 25c2, refer to those for conductive layer 25a1 and conductive layer 25a2, respectively.

Note that although an example in which a conductive layer 81 is provided as a wiring layer has been shown here, a structure in which interlayer insulating layers and wiring layers are alternately stacked (also referred to as a multilayer wiring layer) can also be used between the layer in which the transistor 90 is provided and the layer in which the memory cell 15 is provided.

The above is an explanation of an example configuration of a storage device.

[About the components]
<Substrate>
Substrates on which transistors are formed may be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride. Examples of semiconductor substrates having an insulating region within the aforementioned semiconductor substrate include silicon-on-insulator (SOI) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Substrates containing metal nitrides and substrates containing metal oxides can also be used. Examples of substrates include an insulating substrate having a conductive layer or semiconductor layer provided thereon, a semiconductor substrate having a conductive layer or insulating layer provided thereon, and a conductive substrate having a semiconductor layer or insulating layer provided thereon. Alternatively, a substrate provided with elements may be used, such as a capacitor, a resistor, a switch (including a transistor), a light-emitting element, a memory element, or the like.

<Insulating layer>
For example, the insulating layer 52 can be made of a material that functions as a dielectric. For example, a high-dielectric-constant (high-k) material is preferably used as the dielectric. Specifically, for example, a high-dielectric-constant material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, or hafnium zirconium oxide can be used for the insulating layer 52. Alternatively, as another example, an oxide containing one or both of aluminum and hafnium is preferably used, more preferably an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and even more preferably hafnium oxide having an amorphous structure. As another example, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), or (Ba,Sr)TiO ₃ (BST) can be used. Using a high-dielectric-constant material for the dielectric of the capacitive element 30 can increase the capacitance value and enable the voltage written to the capacitive element 30 to be retained for a long period of time.

Furthermore, a material capable of exhibiting ferroelectricity can be used for the insulating layer 52. Furthermore, by using a material capable of exhibiting ferroelectricity for the insulating layer 52, the capacitive element 30 can be made into a ferroelectric capacitor.

Examples of materials that can have ferroelectricity include hafnium oxide, zirconium oxide, zirconium hafnium oxide (sometimes referred to as HfZrO _X (X is a real number greater than 0)), a material in which element J ₁ is added to hafnium oxide (here, element J ₁ refers to one or more elements selected from zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), and strontium (Sr)), and a material in which element J ₂ is added to zirconium oxide (here, element J ₂ refers to one or more elements selected from hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), and strontium (Sr)). Furthermore, piezoelectric ceramics having a perovskite structure, such as lead titanate (sometimes referred to as PbTiO _X ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used as materials capable of exhibiting ferroelectricity. Furthermore, for example, a mixture or compound composed of multiple materials selected from the materials listed above may be used as materials capable of exhibiting ferroelectricity. Incidentally, the crystal structure (characteristics) of hafnium oxide, zirconium oxide, zirconium hafnium oxide, and materials obtained by adding element _J1 to hafnium oxide may change depending not only on the film formation conditions but also on various processes. Therefore, in this specification, materials that exhibit ferroelectricity are referred to not only as ferroelectrics but also as materials capable of exhibiting ferroelectricity.

Among the materials that can exhibit ferroelectricity, materials containing hafnium oxide or materials containing hafnium oxide and zirconium oxide are preferred because they can exhibit ferroelectricity even in thin films of only a few nanometers. This allows the process of fabricating ferroelectric capacitors to be shortened. Note that in this specification, a layer of a material that can exhibit ferroelectricity may be referred to as a ferroelectric layer or metal oxide film.

When the insulating layer 52 is formed by the ALD method using a material containing hafnium oxide and zirconium oxide, for example, tetrakis(ethylmethylamido)hafnium (TEMAHf) or hafnium tetrachloride can be used as a precursor containing hafnium. Furthermore, tetrakis(ethylmethylamido)zirconium (TEMAZr) or zirconium tetrachloride can be used as a precursor containing zirconium. Furthermore, one or both of _H2O and _O3 can be used as an oxidizing agent. However, the oxidizing agent is not limited to these. For example, the oxidizing agent can include one or more selected from _O2 , _O3 , _N2O , _NO2 , _H2O , and _{H2O2 .}

Furthermore, the insulating layer 52 can have a single-layer structure or a laminated structure. In particular, when the insulating layer 52 has a laminated structure, each insulating layer included in the insulating layer 52 can be made of, for example, one or both of the above-mentioned high-k material and the above-mentioned material that can have ferroelectricity.

Furthermore, the film thickness of the insulating layer 52 is preferably 1 nm or more and 30 nm or less, more preferably 2 nm or more and 20 nm or less, and even more preferably 3 nm or more and 15 nm or less.

Furthermore, unlike paraelectric materials, ferroelectric materials maintain their internal dielectric polarization even when no voltage is applied (sometimes called remanent polarization). Because the dielectric polarization is maintained, using a ferroelectric capacitor for the capacitive element 30 suppresses degradation of the data stored in the memory cells 15. This makes it possible to reduce refresh operations for the memory cells 15, thereby reducing the power consumption of the storage device 10.

The insulating layer 22 functions as the gate insulating layer of the transistor. The insulating layer 22 can be made of an insulating material that is a high-k material.

It is also preferable to use a laminated insulating material made of a high-k material as the insulating layer 22, and it is preferable to use a laminated structure of a high-k material and a material with a higher dielectric strength than the high-k material.

Furthermore, a material exhibiting ferroelectricity may be used for the insulating layer 22.

The insulating layer 22 can have an insulating film that has the function of capturing or fixing hydrogen. The insulating layer 22 can also have an insulating film that has barrier properties against hydrogen. By suppressing the diffusion of hydrogen from the conductive layer 23 side to the semiconductor layer 21, a highly reliable transistor can be realized.

Insulating film materials capable of capturing or adhering hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may also contain zirconium, such as oxides containing hafnium and zirconium. Metal oxides with an amorphous structure have dangling bonds in some oxygen atoms, which enhance their ability to capture or adhering hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure may be achieved by including silicon in these oxides. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate). Metal oxides may have crystalline regions and/or grain boundaries.

Furthermore, as an insulating film having barrier properties against hydrogen, it is preferable to use a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, a gallium oxide film, or the like.

Furthermore, the insulating layer 22 may have an insulating film that releases oxygen when heated.

Furthermore, the insulating layer 22 can have an insulating film that has a barrier property against oxygen. As an insulating film that has a barrier property against oxygen, it is preferable to use an aluminum oxide film, a silicon nitride film, a hafnium oxide film, a hafnium silicate film, or the like. As an insulating film that has a barrier property against oxygen and hydrogen, it is preferable to use an aluminum oxide film, a silicon nitride film, a hafnium oxide film, or the like.

Furthermore, the insulating layer 22 may have an insulating film that has barrier properties against hydrogen.

Aluminum oxide not only acts as a barrier against oxygen, but also has the ability to capture or fix hydrogen, thereby preventing hydrogen from diffusing into the semiconductor layer 21.

When the insulating layer 22 has a stacked structure, each insulating film is preferably a thin film. For example, by making the thickness of the insulating layer 22 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also referred to as the S value) of the transistor can be reduced. Furthermore, the thickness of each insulating film is preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5 nm or less, more preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and less than 5 nm, and even more preferably 1 nm or more and 3 nm or less.

In this specification and the like, the term "barrier property" refers to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). When hydrogen is described as a corresponding substance, it refers to at least one of, for example, a hydrogen atom, a hydrogen molecule, and a substance bonded to hydrogen, such as a water molecule or OH ⁻ . Furthermore, when impurities are described as a corresponding substance, unless otherwise specified, they refer to impurities in a channel formation region or a semiconductor layer, and refer to at least one of, for example, a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (such as N ₂ O, NO, or NO ₂ ), a copper atom, and the like. Furthermore, when oxygen is described as a corresponding substance, it refers to at least one of, for example, an oxygen atom, an oxygen molecule, and the like.

Here, the electrical characteristics of a transistor using a metal oxide film can be stabilized by surrounding it with an insulating film that has the function of suppressing the permeation of impurities and oxygen. The insulating film that has the function of suppressing the permeation of impurities and oxygen can be, for example, an insulating film containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, the insulating film that has the function of suppressing the permeation of impurities and oxygen can be made of oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, or nitrides such as aluminum nitride, silicon nitride oxide, or silicon nitride.

Specific examples of insulating film materials that function to suppress the permeation of impurities such as water and hydrogen, and oxygen include oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Furthermore, examples of insulating film materials that function to suppress the permeation of impurities such as water and hydrogen, and oxygen include hafnium aluminate. Furthermore, examples of insulating film materials that function to suppress the permeation of impurities such as water and hydrogen, and oxygen include nitrides such as aluminum nitride, aluminum titanium nitride, silicon nitride oxide, and silicon nitride.

Insulating layer 11, insulating layer 43, insulating layer 46, and insulating layer 47 can be used as interlayer insulating films. For example, they are preferably formed by a film formation method such as sputtering or plasma CVD. In particular, when sputtering is used, hydrogen gas does not need to be used as the film formation gas, and therefore a film with an extremely low hydrogen content can be obtained. This prevents hydrogen from being supplied to semiconductor layer 21, stabilizing the electrical characteristics of transistor 20.

The insulating layer 43 is preferably an oxide insulating film because it is in contact with the channel formation region of the semiconductor layer 21. In particular, it is preferable to use an oxide insulating film that releases oxygen when heated. The oxide insulating film that can be used for the gate insulating layer described above can be used as the insulating layer 43.

Insulating layer 45 and insulating layer 48 can be, for example, an insulating film that has barrier properties against hydrogen, or an insulating film that has the function of capturing or fixing hydrogen. This makes it possible to prevent hydrogen from diffusing from above insulating layer 45 or insulating layer 48 toward semiconductor layer 21.

<Conductive layer>
The conductive layer is preferably made of, for example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, palladium, iridium, strontium, and lanthanum, or an alloy containing two or more of the above metal elements, or an alloy combining two or more of the above metal elements. The conductive layer is preferably made of, for example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel. Tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are also preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. The conductive layer may be made of a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element (for example, phosphorus), or silicide (for example, nickel silicide).

Using a material with high electrical conductivity (a material with low electrical resistance) can reduce the power consumption of the memory device 10. Furthermore, using a material with high electrical conductivity (a material with low electrical resistance) can reduce the amount of electric heat generated, thereby reducing the thermal impact on the transistor 20.

Multiple conductive layers formed from the above materials may be stacked. For example, a layered structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing oxygen. Also, a layered structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing nitrogen. Also, a layered structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing oxygen and a conductive material containing nitrogen.

Conductive layer 25a and conductive layer 25b are in contact with semiconductor layer 21. Here, when an oxide semiconductor is used as semiconductor layer 21, if an easily oxidized metal such as aluminum is used in the portion of conductive layer 25a or conductive layer 25b in contact with semiconductor layer 21, an insulating oxide (e.g., aluminum oxide) may be formed between conductive layer 25a or conductive layer 25b and semiconductor layer 21, preventing electrical conduction therebetween. Therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide material for at least the portion of conductive layer 25a and conductive layer 25b in contact with semiconductor layer 21.

For conductive layer 25a2 and conductive layer 25b2 in contact with semiconductor layer 21, it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. These are preferable because they are conductive materials that are resistant to oxidation or materials that maintain their conductivity even when oxidized.

Alternatively, conductive oxides such as indium oxide, zinc oxide, In-Sn oxide, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide, and Ga-Zn oxide can be used. Conductive oxides containing indium are particularly preferred due to their high conductivity. Alternatively, oxide materials such as In-Ga-Zn oxide that can be used for the semiconductor layer 21 can also be used as a conductive layer by increasing the carrier concentration.

For example, conductive layer 25a2 and conductive layer 25b2 can each be a single-layer structure of the above-mentioned conductive oxide film, a three-layer structure in which a titanium nitride film, a tungsten film, and a titanium nitride film are stacked in this order, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on tungsten, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on the above-mentioned conductive oxide film, or a two-layer structure in which the above-mentioned conductive oxide film is stacked on a ruthenium film or a ruthenium oxide film.

The conductive layer 23 functions as a gate electrode and can be made of a variety of conductive materials. For the conductive layer 23, it is preferable to use a metal element selected from the group consisting of aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing such a metal element. Nitrides of the above metals or alloys, or oxides of the above metals or alloys, may also be used. For example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferable. Semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide may also be used.

In addition, the conductive layer 23 may be made of nitrides and oxides that can be used for the conductive layers 25a and 25b.

The conductive layer 51 functions as one electrode of the capacitance element 30, and the conductive layer 53 functions as the other electrode of the capacitance element 30.

Various conductive materials can be used for conductive layer 51 and conductive layer 53. For example, the materials listed above that can be used as conductive layers can be used.

Furthermore, each of conductive layer 51 and conductive layer 53 may be a single layer or may have a laminated structure.

The conductive layer 51 has, for example, a columnar shape. Therefore, when a layered structure is applied to the conductive layer 51, it can have, for example, a configuration having a first layer that forms the core and second and subsequent layers that surround the core.

It is preferable to use, for example, titanium nitride for conductive layers 51 and 53. Furthermore, if the conductive layer has a laminated structure, for example, using titanium nitride for the layer in contact with insulating layer 52 may make it easier for the ferroelectricity of insulating layer 52 to be expressed.

It is also preferable to use a material that can be formed using the ALD method for the conductive layer 51. The ALD method has high coverage and is suitable as a method for forming conductive films in fine openings with high aspect ratios.

The conductive layer 53 can also function as a wiring layer. Therefore, by using a low-resistance material for the conductive layer 53, the wiring resistance can be reduced and the operating speed of the memory device can be increased.

By using a metal such as tungsten or ruthenium as the conductive layer 53, the resistance of the conductive layer 53 can be suitably reduced. It is also possible to stack these metals with titanium nitride, for example. As an example, titanium nitride can be used as the first layer (here, the layer in contact with the insulating layer 52), and tungsten can be used as the second layer on the titanium nitride.

Because conductive layer 53, conductive layer 23, conductive layer 25a, and conductive layer 25b also function as wiring, it is preferable to use a laminate of low-resistance conductive materials. For example, the upper layer of conductive layer 25a and conductive layer 25b can also be made of a low-resistance conductive material that can be used for conductive layer 23 described above.

The conductive layer 24 can function as wiring. The conductive material that can be used for the conductive layer 23, the conductive layer 25a, and the conductive layer 25b described above can be used for the conductive layer 24. It is particularly preferable to use a low-resistance conductive material.

<Semiconductor layer>
The semiconductor layer 21 preferably contains a metal oxide (oxide semiconductor).

In oxide is preferably used as the metal oxide that can be used for the semiconductor layer 21. Examples of metal oxides that can be used for the semiconductor layer 21 include Ga oxide and Zn oxide. The metal oxide preferably contains at least In or Zn. The metal oxide preferably contains two or three elements selected from In, element M, and Zn. The element M is a metal element or semimetal element with a high bond energy with oxygen, such as a metal element or semimetal element with a bond energy with oxygen higher than that of indium. Specific examples of the element M include Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb. The element M contained in the metal oxide is preferably one or more of the above elements, and is particularly preferably one or more selected from Al, Ga, Y, and Sn, with Ga being more preferred.

Indium oxide is preferably used for the semiconductor layer. The higher the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the higher the field-effect mobility of the transistor. Therefore, by using indium oxide for the semiconductor layer, the transistor can achieve a large on-state current and high frequency characteristics.

In this specification and the like, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). For example, examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be described below. Fig. 21A is a schematic diagram showing the carrier concentration dependence of the Hall mobility for silicon (Si) and indium oxide (InO _x ), and Fig. 21B is a schematic diagram showing the carrier concentration dependence of the Hall mobility for IGZO.

First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as indicated by the arrows in Figure 21B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as indicated by the arrows in Figure 21A (see Non-Patent Document 6). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic the indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties closer to silicon. Note that the characteristics of indium oxide shown in Figure 21A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 21A.

21A , the low carrier concentration range R1 has extremely high hole mobility, and can therefore be considered a carrier concentration range suitable for, for example, a transistor channel formation region. For example, in the case of indium oxide, range R1 is a range including a carrier concentration value of 1×10 ¹⁵ cm ⁻³ , for example, a range of 1×10 ¹⁴ cm ⁻³ or more and 1×10 ¹⁸ cm ⁻³ or less. By sufficiently reducing the carrier concentration, it is expected that the hole mobility value can be increased to approximately 270 cm ² /(V·s).

In addition, in indium oxide, the region where the carrier concentration is in range R1 can contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. Range R2 is a range in which the carrier concentration value includes 1×10 ²⁰ cm ⁻³ , for example, a range of 1×10 ¹⁹ cm ⁻³ or more and 1×10 ²² cm ⁻³ or less. By sufficiently increasing the carrier concentration, it is expected that the resistivity can be reduced to 1×10 ⁻⁴ Ω·cm or less.

Indium oxide, the region with a carrier concentration in range R2 can contain an element that increases the carrier concentration. For example, it is preferable that the region contains the same element as the source electrode and drain electrode of the transistor. Examples of such elements include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. It is particularly preferable to use an element whose oxide has conductive or semiconducting properties. The element that increases the carrier concentration can be supplied by forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment. Unless otherwise specified, the present specification does not limit the use of mass separation. For example, the present specification refers to a method of supplying ions after mass separation as the ion implantation method, and a method of supplying ions without mass separation as the ion doping method.

In this way, indium oxide uses a region with a low carrier concentration for the channel formation region of a transistor, and a region with a high carrier concentration for the source and drain regions of the transistor. In other words, indium oxide can be considered an oxide capable of valence electron control. Note that with IGZO, strain can form in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide allows for valence electron control, so strain does not need to be formed in the film as with IGZO. Minimizing strain in the film is expected to improve reliability. For example, by creating regions within the indium oxide film with carrier concentrations in range R1 and range R2 shown in Figure 21A, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in silicon-based transistors is generally known. However, valence electron control in indium oxide-based transistors is a novel technological concept that would not normally be conceived.

By using the above technical concept, the transistor containing indium oxide in this specification has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) A high on-state current (in other words, high mobility). (2) A low off-state current. (3) Normally-off operation is possible. (4) High reliability. (5) A high cutoff frequency (fT). For example, the transistor containing indium oxide in this specification has high mobility, a low off-state current, and is normally-off operation. This transistor has high mobility and is different from a normally-on transistor.

Note that a semiconductor being i-type can be said to have the same Fermi level (Ef) and intrinsic Fermi level (Ei) (Ef = Ei). As shown in Figure 21B, in IGZO, the lower the carrier concentration, the lower the hole mobility. Therefore, when Ef = Ei is finally achieved, there is a possibility that the carriers will disappear (in other words, the physical properties will be similar to those of an insulator), and the transistor will no longer function. On the other hand, in indium oxide, as shown in Figure 21A, the lower the carrier concentration, the higher the hole mobility. When Ef = Ei is finally achieved, the hole mobility will be maximized. In other words, a transistor containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Note that a transistor containing indium oxide is likely to be normally-off due to its low carrier concentration. Therefore, a transistor containing indium oxide can be normally-off and achieve high field-effect mobility.

Note that normally-off refers to a state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0 V. Furthermore, normally-off can be evaluated by the threshold voltage (Vth) or shift value (Vsh) of the transistor. Unless otherwise specified, Vth is calculated by a constant current method. More specifically, Vth is defined as the gate voltage (Vg) when the value of drain current (Id) × channel length (L) ÷ channel width (W) in the Id-Vg characteristics of the transistor is 1 nA (1 × 10 ⁻⁹ A). Furthermore, Vsh is the gate voltage (Vg) at the intersection between the tangent to the maximum slope when the drain current (Id) in the Id-Vg characteristics of the transistor is expressed logarithmically and the line of Id = 1 pA (1 × 10 ^-12 A), or the Vg at the intersection between the line extrapolated from between two points where the slope when Id in the Id-Vg characteristics of the transistor is expressed logarithmically and the line of Id = 1 pA. For example, if either one or both of Vth and Vsh are zero or a positive value, the transistor can be considered to be normally off.

Furthermore, in a transistor containing indium oxide, the film structure in contact with the indium oxide film is important for making the semiconductor i-type, i.e., achieving Ef = Ei. For example, in a transistor containing indium oxide, a film structure in which a silicon oxide film in contact with the indium oxide film, a hafnium oxide film, and a silicon nitride film are stacked is one example. With this film structure, a highly reliable semiconductor device with Ef = Ei can be obtained.

In the above film configuration, instead of the silicon oxide film, a film containing oxygen, such as a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a gallium oxide film, can also be used. Also, in the above film configuration, instead of the silicon nitride film, a silicon nitride oxide film, a silicon oxynitride film, or the like can also be used. Furthermore, the hafnium oxide film, which is located closer to the indium oxide film than the silicon nitride film, functions as a gettering site for hydrogen.

The above film configuration can also be considered as a stacked structure of a film capable of supplying oxygen to the indium oxide film from the indium oxide film side (e.g., a silicon oxide film), a film capable of gettering hydrogen (e.g., a hafnium oxide film), and a film that suppresses the penetration of oxygen and hydrogen (e.g., a silicon nitride film). With this configuration, oxygen vacancies in the indium oxide film are filled with oxygen in the silicon oxide film. Furthermore, hydrogen in the indium oxide film is captured by the hafnium oxide film by heat treatment or the like. Furthermore, the provision of a silicon nitride film results in a film configuration that reduces the penetration of oxygen and hydrogen from the outside. In other words, the above film configuration allows the indium oxide film to become closer to i-type. Therefore, a transistor having the above-described indium oxide film has high field-effect mobility and high reliability.

Next, we will explain indium oxide films used in transistors. It is preferable that the indium oxide film be crystalline (i.e., have crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also known as microcrystalline films). In particular, polycrystalline indium oxide films are preferred, and single-crystal films are even more preferred. Single-crystal films do not have grain boundaries. Impurities that impede carrier flow (typically, insulating impurities, insulating oxides, etc.) tend to segregate at grain boundaries. Using a single-crystal film can suppress carrier scattering at grain boundaries, resulting in a transistor with high field-effect mobility. It also offers the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and as few crystal grain boundaries as possible. Note that in a transistor using a polycrystalline film of indium oxide, if there are no crystal grain boundaries in the channel formation region or no crystal grain boundaries are observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to use single-crystal indium oxide.

The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, analysis may be performed by combining multiple of these techniques.

Furthermore, in this specification, a semiconductor layer in which no crystal grain boundaries are observed in the channel formation region, a semiconductor layer in which the channel formation region is contained in a single crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions within the channel formation region can be referred to as a single crystal film. Furthermore, a semiconductor layer in which, within a single crystal grain in the channel formation region, the direction of the other crystal axis changes continuously around a certain crystal axis or a certain crystal orientation as the axis of rotation can be referred to as a single crystal film.

The channel formation region refers to the region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, source electrode, and drain electrode.

The lower the impurity concentration in the indium oxide film in the channel formation region, the better. Impurities in the indium oxide film in the channel formation region can act as a source of carrier scattering, which can reduce field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Impurities in the indium oxide film include boron and silicon. The indium oxide film preferably has a concentration of these impurities of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Note that carbon, hydrogen, and other elements can be contained in the film formation gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above impurities.

Note that the indium oxide film in the channel formation region can contain elements that can maintain a low carrier concentration, as long as the crystals maintain a cubic crystal structure (bixbyite type). Examples of such elements include gallium, aluminum, scandium, yttrium, and lanthanides (lanthanum, neodymium, samarium, erbium, ytterbium, etc.). These elements exist primarily as trivalent cations in the oxide, allowing the carrier concentration of the indium oxide to be maintained low.

By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm ² /(V·s) or more, preferably 100 cm ² /(V·s) or more, more preferably 150 cm ² /(V·s) or more, even more preferably 200 cm ² /(V·s) or more, and still more preferably 250 cm ² /(V·s) or more.

One of the features of an indium oxide film is its high oxygen permeability (diffusibility) compared to an IGZO film. As shown in FIG. 21C, oxygen (O) diffusing into an indium oxide film (denoted as _InOX ) passes through the indium oxide film and is released as oxygen molecules (O ₂ ). It may also react with hydrogen contained in the film and be released as water molecules (H ₂ O). Furthermore, if oxygen vacancies ( _VO ) exist in the film, the diffusing oxygen atoms compensate for the oxygen vacancies. Since oxygen easily diffuses into an indium oxide film, it can also be said that oxygen vacancies are more easily compensated for compared to an IGZO film.

As such, indium oxide films are easier to reduce oxygen vacancies in than IGZO films, and by applying such indium oxide films to transistors, it is possible to create transistors that exhibit extremely high reliability.

21C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and is released as hydrogen molecules (H ₂ ). Alternatively, hydrogen reacts with oxygen contained in the film and is released as water molecules.

Transistors using indium oxide film are accumulation-type transistors that use electrons as majority carriers. Assuming that the carrier relaxation time is a constant value, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, using indium oxide, which has a small effective electron mass, in a transistor can increase the transistor's on-current or field-effect mobility.

Table 1 shows the effective masses of single-crystal indium oxide (here, In ₂ O ₃ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Furthermore, the effective mass of electrons in indium oxide is characterized by being almost independent of the crystal orientation. Therefore, by using crystalline indium oxide for a transistor, a transistor with high field-effect mobility and high frequency characteristics (also referred to as f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely low off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-state current per 1 μm of channel width can be 1 fA (1×10 ⁻¹⁵ A) or less or 1 aA (1×10 ⁻¹⁸ A) or less in an environment of 125° C., and 1 aA (1×10 ⁻¹⁸ A) or less or 1 zA (1×10 ⁻²¹ A) or less in an environment of room temperature (25° C.). Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

For the layer (hereinafter referred to as the seed layer) that comes into contact with at least a portion of the crystalline indium oxide film, it is preferable to use a material containing crystals with a small difference in lattice constant from indium oxide (also referred to as lattice mismatch). This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may also be used as one of the layers that come into contact with at least a portion of the crystalline indium oxide film.

One method for evaluating the degree of lattice mismatch is to use the lattice mismatch value shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, an indium oxide film) with respect to the crystals of the seed layer is calculated by Δa = (( _L1 - _L2 ) / _L2 ) × 100, where _L1 is the length or lattice constant of the unit lattice vector of the crystals of the formed film, and _L2 is the length or lattice constant of the unit lattice vector of the crystals of the seed layer.

The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the better, with 0 being most preferable. For example, Δa can be set to between -5% and 5%, preferably between -4% and 4%, more preferably between -3% and 3%, and even more preferably between -2% and 2%.

Here, the indium oxide crystals have a cubic crystal structure (bixbyite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystals with the cubic YSZ crystals is within the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

The crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having hexagonal or trigonal crystal structure can be used under an indium oxide film having cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to [001] and the crystal orientation of the underside of the indium oxide film to [111], the requirements regarding _the crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or _trigonal crystals include _wurtzite structure, _YbFe2O4 structure, _Yb2Fe3O7 structure, and modified structures thereof _{. An example of a crystal having a YbFe2O4 structure or a Yb2Fe3O7 structure is IGZO .} Note that a single crystal film of indium oxide can be formed not only on a YSZ substrate but also on an insulating film. On the other hand, it is difficult to form a single crystal film of silicon on an insulating film. Silicon crystals have a diamond structure. As such, indium oxide and silicon have similar properties in terms of single crystals. However, when comparing indium oxide and silicon from the perspective of whether they can form single crystals on an insulating film, they have different properties.

In crystalline films, for example, crystal grains can be seen in high-resolution transmission electron microscope (TEM) images. Furthermore, in crystalline films, for example, crystal grain boundaries can sometimes be seen in high-resolution TEM images. In other words, crystal grains and crystal grain boundaries can sometimes be observed in high-resolution TEM images of crystalline films.

The content of the first element in the semiconductor layer is preferably low. Furthermore, the concentration of the first element in the semiconductor layer is preferably low. In particular, the concentration of the first element in the channel formation region is preferably low. Here, the first element is at least one of boron, carbon, aluminum, silicon, zinc, and gallium. The concentration of the first element in the semiconductor layer is preferably, for example, 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less.

Furthermore, by using a precursor that has been distilled one or more times during deposition of the semiconductor layer, it is possible to set the concentration of the first element in the semiconductor layer to 0.01 atomic% (100 ppm) or less, 0.0001% (1 ppm) or less, or 0.00001% (0.1 ppm or 100 ppb) or less. In other words, the indium content (purity) excluding oxygen in the semiconductor layer can be 99.99 atomic% or more (4N), 99.9999 atomic% or more (6N), or 99.99999 atomic% or more (7N).

By lowering the concentrations of boron, carbon, aluminum, and silicon in the semiconductor layer, the crystallinity of the semiconductor layer can be improved.

When a semiconductor layer contains gallium atoms, the gallium atoms bond with excess oxygen atoms to form a Ga-O structure. The Ga-O structure functions as an acceptor that traps electrons. Therefore, in a transistor having a semiconductor layer containing gallium atoms and excess oxygen atoms, the amount of variation in threshold voltage during PBTS (Positive Bias Temperature Stress) testing increases. Therefore, by lowering the gallium concentration in the semiconductor layer, the amount of variation in threshold voltage during PBTS testing can be reduced. This results in a transistor with high reliability when a positive bias is applied. Note that the same phenomenon as when gallium atoms are included can occur when the semiconductor layer contains zinc atoms.

The concentration of the first element can be measured using, for example, inductively coupled plasma mass spectrometry (ICP-MS), XPS, SIMS, time-of-flight secondary ion mass spectrometry (ToF-SIMS), Auger electron spectroscopy (AES), and other methods. Evaluation can be performed using techniques such as ion beam electron spectroscopy (ELC), energy dispersive X-ray spectroscopy (EDX), or inductively coupled plasma atomic emission spectroscopy (ICP-AES).

Metal oxides that function as semiconductors preferably have a band gap of 2.0 eV or more, and more preferably 2.5 eV or more. By using a metal oxide with a wide band gap for the semiconductor layer, the off-state current of the transistor can be reduced, and the power consumption of the semiconductor device can be significantly reduced.

In a transistor using a metal oxide for a semiconductor layer, the off-state current per μm of channel width at room temperature can be 1×10 ⁻¹⁷ A/μm or less, preferably 1×10 ⁻¹⁸ A/μm or less, more preferably 1×10 ⁻¹⁹ A/μm or less. The off-state current per μm of channel width at 85° C. can be 1×10 ⁻¹⁶ A/μm or less, preferably 1×10 ⁻¹⁷ A/μm or less, more preferably 1×10 ⁻¹⁸ A/μm or less.

Furthermore, miniaturization of an OS transistor can improve the high-frequency characteristics of the transistor. For example, the cutoff frequency of the transistor can be improved. Specifically, the cutoff frequency of the transistor can be set to 50 GHz or higher, preferably 100 GHz or higher, and more preferably 150 GHz or higher at room temperature.

The semiconductor layer may be a single layer or a laminated structure of two or more layers. For example, when the semiconductor layer has a two-layer structure consisting of a first semiconductor layer and a second semiconductor layer on the first semiconductor layer, it is preferable to use a metal oxide (typically indium oxide) applicable to the semiconductor layer described above as the first semiconductor layer, and a metal oxide whose conduction band minimum is located closer to the vacuum level than the conduction band minimum of the first semiconductor layer as the second semiconductor layer. In this case, the first semiconductor layer can function mainly as a current path (channel). In other words, the first semiconductor layer has a channel formation region on the surface facing the second semiconductor layer and in its vicinity.

By using the above-described structure, it is possible to reduce the number of carriers trapped at the interface of the first semiconductor layer and its vicinity. Furthermore, it is possible to move the channel away from the surface of the gate insulating layer, thereby reducing the effects of surface scattering. This increases the field-effect mobility of the transistor.

Examples of metal oxides that can be used for the second semiconductor layer include In-Ga oxide, In-Zn oxide, ITO, indium titanium oxide (In-Ti oxide), In-Al-Zn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, indium titanium zinc oxide (In-Ti-Zn oxide), and ITSO. Alternatively, zinc oxide, aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), and aluminum tin oxide (Al-Sn oxide) can also be used.

Specific examples of the In-Zn oxide used in the second semiconductor layer include an In:Zn=1:1 (atomic ratio) or a composition thereabout, an In:Zn=2:1 (atomic ratio) or a composition thereabout, or an In:Zn=4:1 (atomic ratio) or a composition thereabout. Specific examples of the IGZO used in the second semiconductor layer include an In:Ga:Zn=1:1:1 (atomic ratio) or a composition thereabout, an In:Ga:Zn=1:3:2 (atomic ratio) or a composition thereabout, or an In:Ga:Zn=1:3:4 (atomic ratio) or a composition thereabout.

The crystallinity of the metal oxide contained in the second semiconductor layer is not particularly limited. For example, the second semiconductor layer may contain one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part).

Note that the semiconductor material that can be used for the semiconductor layer 21 is not limited to oxide semiconductors. For example, semiconductors made of single elements or compound semiconductors can be used. Examples of semiconductors made of single elements include silicon (including single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon) and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors. Note that these semiconductor materials may contain impurities as dopants.

Alternatively, the semiconductor layer 21 may include a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a single layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as the semiconductor layer of a transistor include molybdenum sulfide (typically MoS ₂ ), molybdenum selenide (typically MoSe ₂ ), molybdenum tellurium (typically MoTe ₂ ), tungsten sulfide (typically WS ₂ ), tungsten selenide (typically WSe ₂ ), tungsten tellurium (typically WTe ₂ ), hafnium sulfide (typically HfS ₂ ), hafnium selenide (typically HfSe ₂ ), zirconium sulfide (typically ZrS ₂ ), and zirconium selenide (typically ZrSe ₂ ).

The crystallinity of the semiconductor material used for the semiconductor layer 21 is not particularly limited, and any of an amorphous semiconductor, a single-crystal semiconductor, or a semiconductor having crystallinity other than single crystal (a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Using a crystalline semiconductor is preferable because it can suppress deterioration of the transistor characteristics.

This concludes the explanation of the components.

[Configuration Example 4]
A configuration example of a storage device of one embodiment of the present invention will be described with reference to FIGS.

The transistor 20 used in the memory cell 15 can be formed using a thin-film method. Therefore, the memory cell 15 including the transistor 20 can be stacked on another functional layer, such as a layer in which a memory cell array is formed or a layer in which a functional circuit is formed. For example, as shown in Figure 6 above, a layer including a memory cell array having multiple memory cells 15 can be stacked on a functional circuit provided on a substrate 91. By providing a layer including a memory cell array on a functional circuit, circuit integration can be achieved. Furthermore, by providing a layer including a memory cell array on a functional circuit, the wiring length between the functional circuit and the layer can be shortened, thereby improving data accessibility and reducing power consumption.

In addition, memory cell arrays can be stacked. By stacking memory cell arrays, the memory density per chip can be increased.

Figure 8 shows an example of stacking a layer 77 in which a memory cell array is provided. Layer 77 is provided with a plurality of memory cells 15, which are arranged, for example, in a matrix in plan view.

As shown in Figure 8, layers 77 can be stacked. Note that Figure 8 shows an example in which two layers 77 are stacked, but three or more layers 77 can also be stacked.

As shown in Figures 9 and 10, a layer 77_S can be formed using transistor 90 formed on substrate 91 instead of transistor 20, and layer 77 can be stacked on layer 77_S.

The layer 77_S shown in FIG. 9 has multiple memory cells 15. Note that each memory cell 15 has a transistor 90 and a capacitor 30 provided over the transistor 90. The transistor 90 shown in FIG. 6 can be used as the transistor 90.

Note that while Figure 8 shows an example in which one layer 77 is stacked on top of layer 77_S, two or more layers 77 can also be stacked.

Figure 10 shows an example in which the configuration of transistor 90 is different from that of Figure 9.

The transistor 90 shown in Figure 10 has a configuration in which an insulating layer 93 functioning as a gate insulating layer and a conductive layer 94 functioning as a gate electrode are provided in a trench portion formed in a substrate 91. Furthermore, an insulating layer UI1 is formed on the conductive layer 94 within the trench.

In the substrate 91, a semiconductor region 92 is formed in the region corresponding to the side and bottom of the trench portion. Low-resistance regions 95a and 95b are formed above the semiconductor region 92.

The transistor 20 shown in Figure 10 has a semiconductor region 92 that is U-shaped in cross section, and low-resistance regions 95a and 95b that face each other across a trench portion in plan or cross section.

The insulating layer UI1 functions as an insulating layer to prevent direct contact between the low resistance regions 95a and 95b.

In the memory device of one embodiment of the present invention, by using a ferroelectric insulating layer for the insulating layer 52, the capacitor 30 can be made nonvolatile. This allows data to be retained in the memory cell 15 for a long time. Furthermore, by using a ferroelectric insulating layer for the insulating layer 52, the reliability of the memory cell 15 may be improved.

Furthermore, in a storage device of one embodiment of the present invention, by using an OS transistor as the transistor of the memory cell 15, leakage of charge held in the capacitor 30 can be extremely reduced. As a result, data can be held in the memory cell 15 for a long time.

In Figure 11, the configuration of the capacitance elements 30 in layer 77 differs from that in Figure 10. In Figure 11, the conductive layers 53 of the capacitance elements 30 in layer 77 are not provided separately for each capacitance element 30 or for each series of capacitance elements 30 arranged in one direction (for example, the Y direction shown in Figure 3A, etc.), but rather, for example, the conductive layers 53 of the capacitance elements 30 in an entire block of layer 77 are provided in common. If, for example, a ferroelectric insulating layer is not used as the insulating layer 52 of the capacitance element 30, the configuration shown in Figure 11 can also be used.

When a non-ferroelectric insulating layer is used for the insulating layer 52, the manufacturing process of the memory cell 15 and the peripheral circuits can be simplified in some cases. Furthermore, the material used for the insulating layer 52 can be selected appropriately according to the operating speed, process temperature, etc. required for the memory cell 15.

In a memory device of one embodiment of the present invention, for example, a ferroelectric insulating layer can be used for the insulating layer 52 of the capacitor used in layer 77_S, and an insulating layer that is less ferroelectric than layer 77_S can be used for the insulating layer 52 of the capacitor used in layer 77. Alternatively, a ferroelectric insulating layer can be used for layer 77_S, and an OS transistor can be used as the transistor in layer 77.

Multiple layers 77 can be stacked, allowing for increased memory capacity. This makes it suitable for use as a large-capacity memory.

This embodiment can be implemented by appropriately combining at least a portion of it with other embodiments described in this specification.

(Embodiment 2)
In this embodiment, configuration examples of a memory device which is a semiconductor device of one embodiment of the present invention and a peripheral circuit included in the memory device will be described with reference to FIGS. 12 to 14B.

<Configuration example of storage device>
12 shows an example of the configuration of a memory device. The memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, and a write circuit. The precharge circuit has the function of precharging the wiring. The sense amplifier has the function of amplifying the data signal read from the memory cell. Note that the above wiring is connected to the memory cell in the memory cell array 1470. The amplified data signal is output to the outside of the memory device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 also includes, for example, a row decoder, a word line driver circuit, a plate line driver circuit, and the like, and can select the row to access.

The memory device 1400 is supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 from the outside. Control signals (CE, WEN, RES), an address signal ADDR, and a data signal WDATA are also input to the memory device 1400 from the outside. The address signal ADDR is input to the row decoder and column decoder, and the data signal WDATA is input to the write circuit.

The control logic circuit 1460 processes control signals (CE, WEN, RES) input from the outside to generate control signals for the row decoder and column decoder. The control signal CE is a chip enable signal, the control signal WEN is a write enable signal, and the control signal RES is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals can be input as needed.

The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. The number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in a column, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in a row, etc.

Note that the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are not limited to those described above. The arrangement or functions of these circuits, and the wirings, circuit elements, and the like connected to the circuits may be changed, deleted, or added as necessary. The memory device of one embodiment of the present invention has high operating speed and can retain data for a long period of time.

Figure 13 shows an example configuration of the memory cell array 1470 and memory cells MC described above.

The memory cell array 1470 shown in FIG. 13 has memory cells 1480 arranged in a matrix of m/2 rows and n columns (m is an even number greater than or equal to 1, and n is an integer greater than or equal to 1). The memory cell 1480 shown in FIG. 13 is a memory circuit applicable to the memory cell MC described above, and is an example of the circuit configuration of a memory cell using a ferroelectric capacitor. Also shown in FIG. 13 are a row circuit 1420 and a column circuit 1430.

In FIG. 13, memory cell 1480 has transistor M9 and capacitance element Cfe. Here, in memory cell 1480, transistor M9 can correspond to transistor 20 described in embodiment 1, and capacitance element Cfe can correspond to capacitance element 30 described in embodiment 1.

Furthermore, in the memory cell array 1470 of Figure 13, m memory cells 1480 are connected to one wiring BL.

Note that the following description focuses on one of the multiple memory cells 1480 shown in Figure 13.

One of the source and drain of transistor M9 is connected to wiring BL (e.g., one of wirings BL[1] to BL[n]). The other of the source and drain of transistor M9 is connected to one of a pair of electrodes of capacitor Cfe. The gate of transistor M9 is connected to wiring WL (e.g., one of wirings WL[1] to WL[m]). The other of the pair of electrodes of capacitor Cfe is connected to wiring PL (e.g., one of wirings PL[1] to PL[m]).

The wiring WL functions as a word line, and can control the on/off switching of the transistor M9 by applying a potential to the wiring WL as a selection signal or non-selection signal. For example, the transistor M9 can be turned on by setting the selection signal applied to the wiring WL to a high potential (H), and the transistor M9 can be turned off by setting the non-selection signal applied to the wiring WL to a low potential (L). The wiring WL is connected to a word line driver circuit included in the row circuit 1420, and the word line driver circuit can apply a selection signal or non-selection signal to the wiring WL.

The wiring BL functions as a bit line, and when the transistor M9 is on, a potential corresponding to a data signal applied to the wiring BL is applied to one of a pair of electrodes of the capacitor Cfe. The wiring BL is connected to a bit line driver circuit included in the column circuit 1430. The bit line driver circuit has a function of generating a data signal to be written to the memory cell MC. The bit line driver circuit also has a function of reading data output from the memory cell MC. Specifically, the bit line driver circuit is provided with a sense amplifier, and the data output from the memory cell MC can be read using the sense amplifier.

The wiring PL functions as a plate line. A predetermined potential is applied to the wiring PL and is supplied to the other of the pair of electrodes of the capacitance element Cfe. The wiring PL is connected to a plate line driver circuit included in the row circuit 1420, and the plate line driver circuit is a circuit that can apply the potential to the wiring PL, for example, during a write operation or a read operation.

The capacitance element Cfe has a dielectric layer between two electrodes made of a material that can have ferroelectric properties. By using a ferroelectric layer that can be thinned as the dielectric layer of the capacitance element and combining it with miniaturized transistors, a highly integrated memory device can be created. Hereinafter, the dielectric layer of the capacitance element Cfe will be referred to as the ferroelectric layer.

The ferroelectric layer of the capacitance element Cfe has a hysteresis characteristic. Figure 14A is a graph showing an example of this hysteresis characteristic. In Figure 14A, the horizontal axis represents the voltage applied to the ferroelectric layer. This voltage can be, for example, the difference between the potential of one of the pair of electrodes of the capacitance element Cfe and the potential of the other of the pair of electrodes of the capacitance element Cfe.

In addition, in Figure 14A, the vertical axis represents the polarization of the ferroelectric layer, and a positive value indicates that positive charges are biased toward one side of the pair of electrodes of the capacitance element Cfe, and negative charges are biased toward the other side of the pair of electrodes of the capacitance element Cfe. On the other hand, a negative value for polarization indicates that positive charges are biased toward the other side of the pair of electrodes of the capacitance element Cfe, and negative charges are biased toward one side of the pair of electrodes of the capacitance element Cfe.

The voltage shown on the horizontal axis of the graph in FIG. 14A may be the difference between the potential of the other of the pair of electrodes of the capacitance element Cfe and the potential of one of the pair of electrodes of the capacitance element Cfe. Furthermore, the polarization shown on the vertical axis of the graph in FIG. 14A may be a positive value when positive charges are biased toward the other of the pair of electrodes of the capacitance element Cfe and negative charges are biased toward one of the pair of electrodes of the capacitance element Cfe, and a negative value when positive charges are biased toward one of the pair of electrodes of the capacitance element Cfe and negative charges are biased toward the other of the pair of electrodes of the capacitance element Cfe.

As shown in Figure 14A, the hysteresis characteristics of the ferroelectric layer can be represented by curve 61 and curve 62. The voltages at the intersections of curve 61 and curve 62 are VSP and -VSP. VSP and -VSP can be said to have opposite polarities.

After applying a voltage equal to or less than -VSP to the ferroelectric layer, if the voltage applied to the ferroelectric layer is increased, the polarization of the ferroelectric layer increases according to curve 61. On the other hand, after applying a voltage equal to or greater than VSP to the ferroelectric layer, if the voltage applied to the ferroelectric layer is decreased, the polarization of the ferroelectric layer decreases according to curve 62. Therefore, VSP and -VSP can each be referred to as saturation polarization voltages. Note that, for example, VSP may be referred to as the first saturation polarization voltage, and -VSP may be referred to as the second saturation polarization voltage. Furthermore, while Figure 14A shows a case where the absolute values of the first and second saturation polarization voltages are equal, the absolute values of the two may be different.

Here, Vc denotes the voltage applied to the ferroelectric layer when the polarization of the ferroelectric layer changes according to curve 61 and the polarization of the ferroelectric layer is 0. Furthermore, -Vc denotes the voltage applied to the ferroelectric layer when the polarization of the ferroelectric layer changes according to curve 62 and the polarization of the ferroelectric layer is 0. Vc and -Vc can each be referred to as coercive voltages. The values of Vc and -Vc can be said to be values between -VSP and VSP. For example, Vc may be referred to as the first coercive voltage, and -Vc may be referred to as the second coercive voltage. Furthermore, although Figure 14A shows that the absolute values of the first coercive voltage and the second coercive voltage are equal, their absolute values may be different.

Furthermore, when no voltage is applied to the ferroelectric layer, the maximum value of polarization is called the "remanent polarization Pr" and the minimum value is called the "remanent polarization -Pr." Furthermore, the difference between the remanent polarization Pr and the remanent polarization -Pr is called the "remanent polarization 2Pr."

As described above, the voltage applied to the ferroelectric layer of the capacitance element Cfe can be expressed as the difference between the potential of one of the pair of electrodes of the capacitance element Cfe and the potential of the other of the pair of electrodes of the capacitance element Cfe. Also, as described above, the other of the pair of electrodes of the capacitance element Cfe is connected to the wiring PL. Therefore, by controlling the potential of the wiring PL, it is possible to control the voltage applied to the ferroelectric layer of the capacitance element Cfe.

An example of a method for driving the memory cell 1480 shown in Figure 13 will be described. In the following description, the voltage applied to the ferroelectric layer of the capacitance element Cfe is the difference (potential difference) between the potential of one of the pair of electrodes of the capacitance element Cfe and the potential of the other of the pair of electrodes of the capacitance element Cfe (wiring PL). Furthermore, the transistor M9 is an n-channel transistor.

Figure 14B is a timing chart showing an example of a method for driving memory cell 1480. Figure 14B shows an example of writing and reading binary digital data to memory cell 1480. Specifically, Figure 14B shows an example in which data "1" is written to memory cell 1480 from time T01 to time T02, read and rewrite are performed from time T03 to time T05, read and write data "0" to memory cell 1480 from time T11 to time T13, read and rewrite are performed from time T14 to time T16, and read and write data "1" to memory cell 1480 from time T17 to time T19.

The sense amplifier electrically connected to the wiring BL is supplied with Vref as a reference potential. In the read operation shown in Figure 14B, if the potential of the wiring BL is higher than Vref, data "1" is read by the bit line driver circuit. On the other hand, if the potential of the wiring BL is lower than Vref, data "0" is read by the bit line driver circuit.

From time T01 to time T02, the word line driver circuit applies a high potential to the wiring WL as a selection signal. This turns on transistor M9. The potential of the wiring BL is also set to Vw. Because transistor M9 is on, the potential of one of the pair of electrodes of capacitance element Cfe becomes Vw. Furthermore, GND is applied to the wiring PL by the plate line driver circuit. As a result, the voltage applied to the ferroelectric layer of capacitance element Cfe becomes "Vw-GND." This allows data "1" to be written to memory cell 1480. Therefore, the period from time T01 to time T02 can be said to be the period during which the write operation is performed.

Here, Vw is preferably equal to or greater than VSP, for example, and is preferably equal to VSP. Furthermore, in this specification, GND is the ground potential, but it does not necessarily have to be the ground potential as long as the memory cell 1480 can be driven in a manner that satisfies the spirit of one aspect of the present invention. For example, if the absolute value of the first saturation polarization voltage is different from the absolute value of the second saturation polarization voltage, and the absolute value of the first coercive voltage is different from the absolute value of the second coercive voltage, GND can be a potential other than ground.

From time T02 to time T03, the bit line driver circuit applies GND to the line BL, and the plate line driver circuit applies GND to the line PL. As a result, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes 0V. From time T01 to time T02, the voltage "Vw-GND" applied to the ferroelectric layer of the capacitance element Cfe can be set to VSP or higher, so from time T02 to time T03, the polarization amount of the ferroelectric layer of the capacitance element Cfe changes according to curve 62 shown in FIG. 14A. As a result, from time T02 to time T03, no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe.

After applying GND to both the wiring BL and the wiring PL, the word line driver circuit applies a low potential to the wiring WL as a non-selection signal. This turns off transistor M9. This completes the write operation, and data "1" is stored in memory cell 1480. Note that the potentials of the wiring BL and the wiring PL can be set to any potential as long as no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe, i.e., as long as the voltage applied to the ferroelectric layer of the capacitance element Cfe is equal to or greater than the second coercive voltage, -Vc.

From time T03 to time T04, the word line driver circuit applies a high potential to the line WL as a selection signal. This turns on transistor M9. Furthermore, the plate line driver circuit applies Vw to the line PL. By setting the potential of line PL to Vw, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes "GND-Vw." As described above, the voltage applied to the ferroelectric layer of the capacitance element Cfe is "Vw-GND" from time T01 to time T02. Therefore, polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe. During polarization reversal, current flows through the line BL, and the potential of the line BL becomes higher than Vref. This allows the bit line driver circuit to read the data "1" stored in memory cell 1480. Therefore, the period from time T03 to time T04 can be considered a period during which a read operation is performed. Note that although Vref is higher than GND and lower than Vw, it may also be higher than Vw, for example.

Because the above read is a destructive read, the data "1" held in memory cell 1480 is lost. Therefore, from time T04 to time T05, the bit line driver circuit applies Vw to the wiring BL, and the plate line driver circuit applies GND to the wiring PL. This rewrites the data "1" to memory cell 1480. Therefore, the period from time T04 to time T05 can be said to be the period during which the rewrite operation is performed.

From time T05 to time T11, the bit line driver circuit applies GND to the wiring BL, and the plate line driver circuit applies GND to the wiring PL. Then, the word line driver circuit applies a low potential to the wiring WL as a non-selection signal. This completes the rewrite operation, and data "1" is retained in memory cell 1480.

From time T11 to time T12, the word line driver circuit applies a high potential to the wiring WL as a selection signal. Furthermore, the plate line driver circuit applies a potential Vw to the wiring PL. Because data "1" is stored in memory cell 1480, the potential of wiring BL becomes higher than Vref, and the data "1" stored in memory cell 1480 is read out. Therefore, the period from time T11 to time T12 can be considered a period during which a read operation is performed.

From time T12 to time T13, the bit line driver circuit applies GND to the wiring BL. Because transistor M9 is on, the potential of one of the pair of electrodes of the capacitance element Cfe becomes GND. In addition, the plate line driver circuit applies a potential Vw to the wiring PL. As a result, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes "GND-Vw". This allows data "0" to be written to memory cell 1480. Therefore, the period from time T12 to time T13 can be said to be the period during which the write operation is performed.

From time T13 to time T14, the bit line driver circuit applies GND to the line BL, and the plate line driver circuit applies GND to the line PL. As a result, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes 0V. Since the voltage "GND-Vw" applied to the ferroelectric layer of the capacitance element Cfe from time T12 to time T13 can be set to -VSP or less, the polarization amount of the ferroelectric layer of the capacitance element Cfe changes according to curve 61 shown in FIG. 14A from time T13 to time T14. As a result, no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe from time T13 to time T14.

After applying GND to both the wiring BL and the wiring PL, the word line driver circuit applies a low potential to the wiring WL as a non-selection signal. This turns off transistor M9. This completes the write operation, and data "0" is stored in memory cell 1480. Note that the potentials of the wiring BL and the wiring PL can be set to any potential as long as no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe, i.e., as long as the voltage applied to the ferroelectric layer of the capacitance element Cfe is equal to or lower than the first coercive voltage Vc.

From time T14 to time T15, the word line driver circuit applies a high potential to the line WL as a selection signal. This turns on transistor M9. Furthermore, the plate line driver circuit applies a potential Vw to the line PL. By setting the potential of line PL to Vw, the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes "GND-Vw." As described above, the voltage applied to the ferroelectric layer of the capacitance element Cfe is "GND-Vw" from time T12 to time T13. Therefore, no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe. Therefore, the amount of current flowing through the line BL is smaller than when polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe. As a result, the increase in the potential of the line BL is smaller than when polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe; specifically, the potential of the line BL becomes Vref or lower. Therefore, the bit line driver circuit can read the data "0" stored in memory cell 1480. Therefore, the period from time T14 to time T15 can be said to be the period during which the read operation is performed.

From time T15 to time T16, the bit line driver circuit applies GND to the wiring BL, and the plate line driver circuit applies potential Vw to the wiring PL. This rewrites data "0" to memory cell 1480. Therefore, the period from time T15 to time T16 can be considered the period during which the rewrite operation is performed.

Between time T16 and time T17, the bit line driver circuit applies GND to the line BL, and the plate line driver circuit applies GND to the line PL. Then, the word line driver circuit applies a low potential to the line WL as a non-select signal. This completes the rewrite operation, and data "0" is retained in memory cell 1480.

From time T17 to time T18, the word line driver circuit applies a high potential to the wiring WL as a selection signal. Furthermore, the plate line driver circuit applies a potential Vw to the wiring PL. Because data "0" is stored in memory cell 1480, the potential of wiring BL becomes lower than Vref, and the data "0" stored in memory cell 1480 is read out. Therefore, the period from time T17 to time T18 can be considered a period during which a read operation is performed.

From time T18 to time T19, the bit line driver circuit applies a potential Vw to the wiring BL. Because transistor M9 is on, the potential of one electrode of capacitance element Cfe becomes Vw. In addition, the plate line driver circuit applies a potential GND to the wiring PL. As a result, the voltage applied to the ferroelectric layer of capacitance element Cfe becomes "Vw-GND." This allows data "1" to be written to memory cell 1480. Therefore, the period from time T18 to time T19 can be said to be the period during which the write operation is performed.

From time T19 onwards, the bit line driver circuit applies GND to the line BL, and the plate line driver circuit applies GND to the line PL. Then, the word line driver circuit applies a low potential to the line WL as a non-select signal. This completes the write operation, and data "1" is stored in memory cell 1480.

A semiconductor device that uses a ferroelectric layer for the capacitance element Cfe functions as a non-volatile memory element that can retain written information even when the power supply is interrupted.

Furthermore, DRAM requires periodic refresh operations, which increases power consumption. A semiconductor device that uses a ferroelectric layer for the capacitance element Cfe does not require refresh operations, thereby reducing power consumption.

In this specification and the like, a memory element or a memory circuit including a ferroelectric layer may be referred to as a "ferroelectric memory" or an "FE memory." Therefore, a semiconductor device according to one embodiment of the present invention is both a ferroelectric memory and an FE memory. The FE memory can be expected to achieve an rewrite count of 1×10 ¹⁰ or more, preferably 1×10 ¹² or more, and more preferably 1×10 ¹⁵ or more. Furthermore, the FE memory can be expected to achieve an operating frequency of 10 MHz or more, preferably 1 GHz or more.

Furthermore, in FE memory, there is a correlation between the remnant polarization 2Pr and data retention capacity, and as the remnant polarization 2Pr decreases, the data retention capacity decreases. In this specification, the period until the remnant polarization 2Pr decreases by 5% (the data retention capacity decreases by 5%) is referred to as the "memory retention period." FE memory can be expected to achieve a memory retention period of one day or more, preferably ten days or more, more preferably one year or more, and even more preferably ten years or more in a temperature environment of 150°C or 200°C.

FE memory can also be applied to cache memory and registers of CPUs (Central Processing Units) and GPUs (Graphics Processing Units). By combining FE memory with CPU cache memory and registers, a normally-off CPU (NoffCPU (registered trademark)) can be realized. By combining FE memory with GPU cache memory and registers, a normally-off GPU (NoffGPU (registered trademark)) can be realized.

Note that this embodiment can be combined as appropriate with the same or other embodiments described in this specification. For example, the configuration, structure, method, etc. described in this embodiment can be used in appropriate combination with another configuration, structure, method, etc. described in this embodiment. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment can be used in appropriate combination with another configuration, structure, method, etc. described in another embodiment, etc.

(Embodiment 3)
In this embodiment, an example of the applicability of a semiconductor device of one embodiment of the present invention will be described with reference to FIG. 15 A transistor including an oxide as a semiconductor (hereinafter also referred to as an OS transistor) and a capacitor are used in a memory device of one embodiment of the present invention. Because the off-state current of an OS transistor is extremely small, a memory device including an OS transistor has excellent data retention characteristics and can function as a nonvolatile memory.

Semiconductor devices such as computers use a variety of memory devices depending on the application. Figure 15 shows a conceptual diagram explaining the hierarchy of memory devices used in semiconductor devices. In Figure 15, the conceptual diagram explaining the hierarchy of memory devices is represented by a triangle, with memory devices located higher in the triangle requiring faster operating speeds, and memory devices located lower in the triangle requiring larger memory capacities and higher recording densities.

In Figure 15, from the top layer of the triangle, there are memories integrated as registers into the CPU, GPU, and NPU (Neural Processing Unit) processing units, cache memory (sometimes simply referred to as cache, and typically L1, L2, and L3 caches), main memory such as DRAM, and storage memory such as 3D NAND and hard disks (also known as HDDs: hard disk drives).

Memory integrated as registers into arithmetic processing units such as CPUs, GPUs, and NPUs is used for temporary storage of calculation results, and is therefore frequently accessed by the arithmetic processing unit. Therefore, fast operating speeds are required rather than large storage capacities. Registers also have the function of storing setting information for the arithmetic processing unit.

Cache memory has the function of duplicating and storing a portion of the data stored in DRAM. By duplicating frequently used data and storing it in cache memory, it is possible to increase the speed of access to the data. Cache memory requires less storage capacity than DRAM, but is required to operate at a faster speed than DRAM. In addition, data rewritten in cache memory is duplicated and supplied to DRAM.

A memory device according to one embodiment of the present invention can be used as a DRAM.

Note that in Figure 15, the cache memory is illustrated only up to the L3 cache, but this is not limited to this. For example, a storage device according to one embodiment of the present invention can be used as the LLC (Last Level cache) or FLC (Final Level cache), which are the lowest level caches.

DRAM has the function of storing programs, data, etc. read from 3D NAND.

3D NAND has the ability to store data that requires long-term storage, various programs used in computing devices (for example, artificial neural network models), and more. Therefore, 3D NAND requires large storage capacity and high recording density rather than fast operating speeds.

Hard disks have large storage capacity and are non-volatile. Alternatively, solid-state drives (SSDs) can be used instead of hard disks.

By using OS transistors, the memory device of one embodiment of the present invention can be monolithically structured with peripheral circuits. Furthermore, by using OS transistors, the memory device can be monolithically stacked with the peripheral circuits. This is advantageous in terms of data access with the peripheral circuits. Furthermore, since the memory device can be stacked with the peripheral circuits, the degree of integration can be increased. Furthermore, by using OS transistors, the memory device of one embodiment of the present invention can retain data for a long period of time. Therefore, when used as a DRAM, the frequency of refresh can be reduced.

Furthermore, the storage device of one embodiment of the present invention can reduce leakage current by using an OS transistor. Therefore, for example, data can be sufficiently stored even if the capacitance value of a capacitor is small. Therefore, for example, by using the storage device of one embodiment of the present invention as a DRAM, the operation speed of the DRAM, for example, the speed at which data is rewritten, can be increased in some cases.

Furthermore, the memory device of one embodiment of the present invention can retain data for a long time by including a capacitor element containing a ferroelectric material. Therefore, when used as a DRAM, the frequency of refresh can be reduced. Furthermore, the reliability of the memory device can be improved.

A storage device of one embodiment of the present invention can be used for the Target2 area and the Target1 area shown in FIG. 15. In particular, it can be suitably used for the Target1 area.

As shown by the diagonal hatching in Figure 15, Target1 includes the boundary area (Target1_1) between DRAM and 3D NAND, and the boundary area (Target1_2) between DRAM and cache (L1, L2, L3). Examples of Target1_2 include the LLC and FLC mentioned above.

By replacing the storage device of one embodiment of the present invention with a DRAM, power consumption can be reduced. With this configuration, power consumption can be reduced to half or less, preferably one-tenth or less, more preferably one-hundredth, and even more preferably one-thousandth or less, compared to a configuration using DRAM. Therefore, the storage device of one embodiment of the present invention can be suitably used for Target 1.

Furthermore, the storage device of one embodiment of the present invention can retain data for a long time and has advantages in terms of data access. Therefore, the storage device of one embodiment of the present invention can be suitably used for Target1_1, which is a region of Target1 that is rewritten relatively infrequently. By applying the storage device of one embodiment of the present invention to Target1_1, the reliability of the storage device can be improved. Furthermore, the degree of integration of the storage device can be increased. Furthermore, the power consumption of the storage device can be reduced.

Furthermore, the storage device of one embodiment of the present invention has high operating speed and is advantageous in terms of data access, and therefore can be suitably used for Target1_2, which is a part of Target1 that is rewritten more frequently. By applying the storage device of one embodiment of the present invention to Target1_2, the computational efficiency of the storage device can be improved and its power consumption can be reduced.

Another means for reducing power consumption is a configuration in which a memory device such as a DRAM or FeRAM (including a semiconductor device according to one embodiment of the present invention) is stacked on a processor such as a CPU, GPU, or NPU. A configuration in which a processor and a memory device are stacked is called a monolithic stack. By configuring the processor and the memory device as a monolithic stack, it is possible to significantly reduce the power consumption required for data access between the processor and the memory device, for example. Therefore, by deploying information processing devices including supercomputers (also called HPCs (High Performance Computers)), computers, servers, etc. that employ such a configuration worldwide, it is possible to mitigate global warming.

In this way, a memory device using an oxide semiconductor according to one embodiment of the present invention can be applied to a wide range of memories, from memories integrated as registers in arithmetic processing units such as CPUs, GPUs, and NPUs, to memories located in the boundary area between DRAM and 3D NAND.

Note that this embodiment can be combined as appropriate with the same or other embodiments described in this specification. For example, the configuration, structure, method, etc. described in this embodiment can be used in appropriate combination with another configuration, structure, method, etc. described in this embodiment. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment can be used in appropriate combination with another configuration, structure, method, etc. described in another embodiment, etc.

(Embodiment 4)
16A and 16B show an example of a chip 1200 on which a semiconductor device of the present invention is mounted. A plurality of circuits (systems) are mounted on the chip 1200. A technology for integrating a plurality of circuits (systems) on a single chip in this manner is sometimes called a system on chip (SoC).

As shown in FIG. 16A, the chip 1200 has a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, and one or more network circuits 1216.

Bumps (not shown) are provided on the chip 1200, which connect to the first surface of the package substrate 1201, as shown in FIG. 16B. Furthermore, multiple bumps 1202 are provided on the back surface opposite the first surface of the package substrate 1201, which connects to the motherboard 1203.

The motherboard 1203 may be provided with storage devices such as DRAM 1221 and flash memory 1222. For example, the storage device 10 described in the first embodiment can be used instead of the DRAM 1221 and flash memory 1222.

It is preferable that the CPU 1211 has multiple CPU cores. It is also preferable that the GPU 1212 has multiple GPU cores. The CPU 1211 and GPU 1212 may each have memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and GPU 1212 may be provided on the chip 1200. The memory can be the storage device 10 described above. The GPU 1212 is also suitable for parallel calculation of a large amount of data, and can be used for image processing or multiply-and-accumulate operations.

Furthermore, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, enabling high-speed data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212.

The analog calculation unit 1213 has either an AD (analog-digital) conversion circuit or a DA (digital-analog) conversion circuit, or both. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222.

Interface 1215 has interface circuits with externally connected devices such as a display device, speaker, microphone, camera, and controller. Controllers include mice, keyboards, and game controllers. Examples of such interfaces that can be used include USB (Universal Serial Bus) and HDMI (High-Definition Multimedia Interface, registered trademark).

Network circuit 1216 includes a network circuit such as a LAN (Local Area Network). It may also include a circuit for network security.

The above circuits (systems) can be formed on chip 1200 using the same manufacturing process. Therefore, even if the number of circuits required for chip 1200 increases, there is no need to increase the manufacturing process, and chip 1200 can be manufactured at low cost.

The package substrate 1201 on which the chip 1200 having the GPU 1212 is mounted, the motherboard 1203 on which the DRAM 1221 and the flash memory 1222 are mounted can be called the GPU module 1204.

GPU module 1204 includes chip 1200 using SoC technology, allowing for a small size. Furthermore, due to its superior image processing capabilities, it is suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable (portable) game consoles. Furthermore, the product-sum operation circuit included in GPU 1212 allows for calculations such as deep neural networks (DNNs), which are AI models. Representative examples of AI models include convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs). Therefore, chip 1200 can be used as an AI chip, and GPU module 1204 can be used as an AI system module.

Note that this embodiment can be combined as appropriate with the same or other embodiments described in this specification. For example, the configuration, structure, method, etc. described in this embodiment can be used in appropriate combination with another configuration, structure, method, etc. described in this embodiment. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment can be used in appropriate combination with another configuration, structure, method, etc. described in another embodiment, etc.

Fifth Embodiment
In this embodiment, an application example of a semiconductor device using a storage device of one embodiment of the present invention will be described. The storage device 10 described in the above embodiment can be applied to various removable storage devices such as a memory card (e.g., an SD card), a USB memory, and an SSD (solid-state drive) as a cache memory or a main memory. Several configuration examples of removable storage devices are schematically shown in FIGS. 17A to 17E . The semiconductor device of one embodiment of the present invention is processed into a packaged memory chip and used in various storage devices and removable memories.

Figure 17A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the board 1104. A semiconductor device of one embodiment of the present invention can be incorporated into the memory chip 1105 or the like.

Figure 17B is a schematic diagram of the appearance of an SD card, and Figure 17C is a schematic diagram of the internal structure of an SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. By providing a memory chip 1114 on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. A wireless chip with wireless communication function may also be provided on the substrate 1113. This enables data to be read from and written to the memory chip 1114 through wireless communication between a host device and the SD card 1110. A semiconductor device of one embodiment of the present invention can be incorporated into the memory chip 1114 or the like.

Figure 17D is a schematic diagram of the appearance of an SSD, and Figure 17E is a schematic diagram of the internal structure of the SSD. SSD 1150 has a housing 1151, a connector 1152, and a board 1153. Board 1153 is housed in housing 1151. For example, memory chip 1154, memory chip 1155, and controller chip 1156 are attached to board 1153. Memory chip 1155 is a work memory for controller chip 1156, and may be, for example, a DOSRAM chip. By providing memory chip 1154 on the back side of board 1153 as well, the capacity of SSD 1150 can be increased. A semiconductor device of one embodiment of the present invention can be incorporated into memory chip 1154 or the like.

Note that this embodiment can be combined as appropriate with the same or other embodiments described in this specification. For example, the configuration, structure, method, etc. described in this embodiment can be used in appropriate combination with another configuration, structure, method, etc. described in this embodiment. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment can be used in appropriate combination with another configuration, structure, method, etc. described in another embodiment, etc.

(Embodiment 6)
This embodiment will describe electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)) that can use the semiconductor device described in the above embodiment. The electronic components, electronic devices, mainframes, space equipment, and data centers that use the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[Electronic Components]
Fig. 18A shows a perspective view of electronic component 700. Electronic component 700 shown in Fig. 18A has a substrate 701, a semiconductor device 710 on substrate 701, and a mold 711. In particular, semiconductor device 710 is sealed by mold 711. Note that Fig. 18A omits some parts in order to show the inside of electronic component 700.

The substrate 701 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate.

Electronic component 700 is provided with, for example, a lead frame 712. A portion of lead frame 712 located on substrate 701 is covered by mold 711, and another portion of lead frame 712 is exposed outside mold 711. In particular, the lead frame 712 exposed outside mold 711 functions as, for example, a terminal for mounting electronic component 700 to a printed circuit board.

In the mold 711, electrode pads 713 are provided on a lead frame 712, and the electrode pads 713 are connected to the semiconductor device 710 via wires 714. The electronic component 700 is mounted on a printed circuit board, for example, by contacting the lead frame 712 with wiring on the printed circuit board. In this way, a mounted board is completed by combining multiple electronic components and connecting them on the printed circuit board.

Next, the semiconductor device 710 will be described. For example, as shown in FIG. 18B, the semiconductor device 710 has a drive circuit layer 715 and a memory layer 716. The memory layer 716 can be configured with multiple memory cell arrays stacked together. The stacked drive circuit layer 715 and memory layer 716 can be configured as a monolithic stack. Configurations other than monolithic stacks include stacking multiple memory layers 716 using through-electrode technology (e.g., TSV (Through Silicon Via)) and Cu-Cu direct bonding. By stacking the drive circuit layer 715 and memory layer 716, for example, a so-called on-chip memory configuration can be achieved, in which the memory is formed directly on the processor. Using an on-chip memory configuration enables faster operation of the interface between the processor and memory.

Furthermore, the semiconductor device 710 has a configuration in which multiple memory cell arrays are stacked, which can improve either or both the memory bandwidth and memory access latency. Note that bandwidth refers to the amount of data transferred per unit time, and access latency refers to the time from access to the start of data exchange.

The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained during the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

Next, a modified example of electronic component 700 is shown in Figure 18C. Electronic component 700A shown in Figure 18C differs from electronic component 700 in that it does not use lead frame 712, but has electrodes 733 provided on the bottom of substrate 701. Electrodes 733 function as connection terminals for mounting electronic component 700A on a printed circuit board.

Figure 18C shows an example in which electrodes 733 are formed using solder balls. By arranging solder balls in a matrix on the bottom of substrate 701, BGA (Ball Grid Array) mounting can be achieved. For this purpose, substrate 701 is provided with through-hole vias, and these vias are provided with conductive layers 732 that function as wiring. Electrode pads 713 are provided above conductive layer 732 on substrate 701 so as to be in contact with them, and electrodes 733 are provided below conductive layer 732 below substrate 701 so as to be in contact with them.

Also, the electrodes 733 may be formed using conductive pins instead of solder balls. By arranging conductive pins in a matrix on the bottom of the substrate 701, PGA (Pin Grid Array) mounting can be achieved.

Furthermore, the electronic component 700A can be mounted on other substrates using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

Furthermore, an electronic component according to one embodiment of the present invention may be in the form of a SiP (System in Package) or an MCM (Multi-Chip Module). For example, an electronic component 700C shown in FIG. 18D has an interposer 731 provided on a package substrate 734 (printed circuit board), and a semiconductor device 735 and multiple semiconductor devices 710 provided on the interposer 731.

In the electronic component 700C of Figure 18D, as an example, the semiconductor device 710 is used as a high bandwidth memory (HBM). For example, the semiconductor device 735 can be used as an arithmetic circuit in an integrated circuit such as a CPU, GPU, or FPGA (Field Programmable Gate Array).

Similar to the substrate 701, the package substrate 734 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 can be, for example, a silicon interposer or a resin interposer.

The interposer 731 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 734. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 731, and the integrated circuits and package substrate 734 are connected using these through electrodes. In addition, with silicon interposers, TSVs can also be used as through electrodes.

HBM requires the connection of many wires to achieve a wide memory bandwidth. For this reason, the interposer on which the HBM is mounted must have fine, high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

Furthermore, SiP and MCM using silicon interposers are less likely to experience a decrease in reliability due to differences in the expansion coefficient between the integrated circuit and the interposer. Furthermore, because silicon interposers have a highly flat surface, poor connections between the integrated circuit mounted on the silicon interposer and the silicon interposer are less likely to occur. It is particularly preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging), in which multiple integrated circuits are arranged horizontally on an interposer.

Furthermore, if the temperature of the electronic component 700C increases due to heat generated by electric current or the like, the characteristics of the circuit elements (e.g., transistors) included in the electronic component 700C may deteriorate. Therefore, it is preferable to provide a heat sink (heat sink) on top of the electronic component 700C. When providing a heat sink, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 700C shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the semiconductor device 735.

[Electronic equipment]
Next, a perspective view of an electronic device 6500 is shown in FIG. 19A . The electronic device 6500 shown in FIG. 19A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory circuit. The semiconductor device of one embodiment of the present invention can be included in the electronic device 6500 as a main memory. The semiconductor device of one embodiment of the present invention can also be included in, for example, the display portion 6502, the control device 6509, or the like.

The electronic device 6600 shown in FIG. 19B is an information terminal that can be used as a notebook computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, and a control device 6616. Note that the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a memory circuit. The semiconductor device of one embodiment of the present invention can be included in the electronic device 6600 as a main memory. The semiconductor device of one embodiment of the present invention can also be included in the display portion 6615, the control device 6616, etc.

By including a semiconductor device of one embodiment of the present invention in the electronic devices 6500 and 6600, power consumption can be reduced, which is preferable.

[Large computer]
Next, Fig. 19C shows a perspective view of the mainframe 5600. The mainframe 5600 shown in Fig. 19C has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe 5600 may also be called a supercomputer.

The computer 5620 can have the configuration shown in the perspective view in Figure 19D, for example. In Figure 19D, the computer 5620 has a motherboard 5630, which has multiple slots 5631 and multiple connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

PC card 5621 shown in Figure 19E is an example of a processing board equipped with a CPU, GPU, memory device, etc. PC card 5621 has board 5622. Board 5622 also has connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that Figure 19E illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for these semiconductor devices, please refer to the descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 described below.

The connection terminal 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. The connection terminal 5629 may conform to, for example, PCIe.

Connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to PC card 5621, inputting signals, etc. They can also be, for example, interfaces for outputting signals calculated by PC card 5621. Examples of standards for connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Also, when outputting video signals from connection terminals 5623, 5624, and 5625, examples of standards for each include HDMI (registered trademark).

The semiconductor device 5626 has terminals (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting these terminals into sockets (not shown) provided on the board 5622.

The semiconductor device 5627 has multiple terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring on the board 5622. Examples of the semiconductor device 5627 include FPGAs, GPUs, and CPUs. For example, the electronic component 700 can be used as the semiconductor device 5627.

The semiconductor device 5628 has multiple terminals, and the semiconductor device 5628 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring on the board 5622. The semiconductor device 5628 can be, for example, a memory device that is a semiconductor device of one embodiment of the present invention. The semiconductor device 5628 can be, for example, the electronic component 700 described above.

The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, artificial intelligence learning and inference.

[Space equipment]
The semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as equipment for processing and storing information.

Figure 20A shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Figure 20A also shows a planet 6804 in outer space. Note that outer space refers to, for example, an altitude of 100 km or higher, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

Furthermore, although not shown in Figure 20A, the secondary battery 6805 may be provided with a battery management system (also known as BMS) or a battery control circuit.

In addition, outer space is an environment with radiation levels more than 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

When sunlight is irradiated onto the solar panel 6802, the power required for the satellite 6800 to operate is generated. However, for example, in situations where sunlight is not irradiated onto the solar panel, or where the amount of sunlight irradiating the solar panel is low, the amount of power generated is small. Therefore, there is a possibility that the power required for the satellite 6800 to operate will not be generated. In order to operate the satellite 6800 even in situations where the amount of power generated is low, it is recommended that a secondary battery 6805 be provided on the satellite 6800. Note that the solar panel is sometimes called a solar cell module.

Satellite 6800 can generate a signal. The signal is transmitted via antenna 6803, and can be received, for example, by a receiver located on the ground or by another satellite. By receiving the signal transmitted by satellite 6800, the position of the receiver that received the signal can be determined. As described above, satellite 6800 can constitute a satellite positioning system.

The control device 6807 also has a function of controlling the satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the control device 6807 is preferably configured using a semiconductor device according to one embodiment of the present invention.

Furthermore, the artificial satellite 6800 can be configured to include a sensor. For example, by configuring the artificial satellite 6800 with a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected off an object on the ground. Or, by configuring the artificial satellite 6800 with a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an Earth observation satellite.

Note that although an artificial satellite is used as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, a semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[Data Center]
The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term data management, such as ensuring data immutability. To manage long-term data, the building must be large enough to accommodate the installation of storage devices and servers for storing a huge amount of data, a stable power source for storing the data, or cooling equipment required for storing the data.

By using a semiconductor device according to one embodiment of the present invention in a storage system applied to a data center, the power required to store data can be reduced and the semiconductor device that stores data can be made smaller. This allows for the storage system to be made smaller, the power supply for storing data to be made smaller, and the cooling equipment to be made smaller. This allows for space savings in the data center.

Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows for reduced heat generation from the circuit. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

Figure 20B shows a storage system applicable to a data center. The storage system 7000 shown in Figure 20B has multiple servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has multiple storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

Storage 7003 uses flash memory to reduce data access speed, i.e., the time required to store and output data, but this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the slow access speed of storage 7003, storage systems typically provide cache memory within the storage to reduce the time required to store and output data.

The above-mentioned cache memory is used in the storage control circuit 7002 and storage 7003. Data exchanged between the host 7001 and storage 7003 is stored in the cache memory in the storage control circuit 7002 and storage 7003, and then output to the host 7001 or storage 7003.

By using OS transistors as transistors for storing data in the cache memory and maintaining a potential corresponding to the data, the frequency of refreshes can be reduced, and power consumption can be lowered. Furthermore, by stacking the memory cell array, miniaturization is possible.

Note that by applying the semiconductor device of one embodiment of the present invention to one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers, it is expected that power consumption can be reduced. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can also reduce emissions of greenhouse gases, typified by carbon dioxide (CO ₂ ). Furthermore, the semiconductor device of one embodiment of the present invention is effective as a measure against global warming due to its low power consumption.

Note that this embodiment can be combined as appropriate with the same or other embodiments described in this specification. For example, the configuration, structure, method, etc. described in this embodiment can be used in appropriate combination with another configuration, structure, method, etc. described in this embodiment. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment can be used in appropriate combination with another configuration, structure, method, etc. described in another embodiment, etc.

ADDR: address signal, BL[1]: wiring, BL[n]: wiring, BL: wiring, CE: control signal, Cfe: capacitance element, dm: capacitance element, GND: potential, MC: memory cell, PL: wiring, Pr: remnant polarization, RDATA: data signal, RES: control signal, TrP: transistor, TrQ: transistor, Vw: potential, WDATA: data signal, WEN: control signal, WL: wiring, 10: memory device, 11: insulating layer, 15: memory cell, 20: transistor , 21: semiconductor layer, 22: insulating layer, 23: conductive layer, 24: conductive layer, 25a: conductive layer, 25b: conductive layer, 25c: conductive layer, 30: capacitance element, 43: insulating layer, 44: insulating layer, 45: insulating layer, 46: insulating layer, 46b: conductive layer, 47: insulating layer, 48: insulating layer, 51: conductive layer, 52: insulating layer, 53: conductive layer, 53f: conductive film, 61: curve, 62: curve, 79: insulating layer, 80: region, 81: conductive layer, 82: plug, 83: plug, 85: insulating layer, 86: insulation layer, 87: insulating layer, 88a: conductive layer, 88b: conductive layer, 88c: conductive layer, 90: transistor, 91: substrate, 92: semiconductor region, 93: insulating layer, 94: conductive layer, 95a: low resistance region, 95b: low resistance region, 98: element isolation layer, 99: line, 700: electronic component, 700A: electronic component, 700C: electronic component, 701: substrate, 710: semiconductor device, 711: mold, 712: lead frame, 713: electrode pad, 714: wire, 715: drive circuit path layer, 716: memory layer, 731: interposer, 732: conductive layer, 733: electrode, 734: package substrate, 735: semiconductor device, 1100: USB memory, 1101: housing, 1102: cap, 1103: USB connector, 1104: substrate, 1105: memory chip, 1106: controller chip, 1110: SD card, 1111: housing, 1112: connector, 1113: substrate, 1114: memory chip, 1115: controller chip 1150: SSD, 1151: housing, 1152: connector, 1153: substrate, 1154: memory chip, 1155: memory chip, 1156: controller chip, 1200: chip, 1201: package substrate, 1202: bump, 1203: motherboard, 1204: GPU module, 1211: CPU, 1212: GPU, 1213: analog calculation unit, 1214: memory controller, 1215: interface, 1216: network circuit, 1221: DRAM, 1222: flash memory, 1400: storage device, 1411: peripheral circuit, 1420: row circuit, 1430: column circuit, 1440: output circuit, 1460: control logic circuit, 1470: memory cell array, 1480: memory cell, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection end child, 5626: semiconductor device, 5627: semiconductor device, 5628: semiconductor device, 5629: connection terminal, 5630: motherboard, 5631: slot, 6500: electronic device, 6501: housing, 6502: display unit, 6503: power button, 6504: button, 6505: speaker, 6506: microphone, 6507: camera, 6508: light source, 6509: control device, 6600: electronic device, 6611: housing, 6612: keyboard, 6613: pointing Device, 6614: External connection port, 6615: Display unit, 6616: Control unit, 6800: Satellite, 6801: Airframe, 6802: Solar panel, 6803: Antenna, 6804: Planet, 6805: Secondary battery, 6807: Control unit, 7000: Storage system, 7001: Host, 7001sb: Server, 7002: Storage control circuit, 7003: Storage, 7003md: Storage device, 7004: Storage area network

Claims (7)

a first transistor, a second transistor, a first capacitance element, a second capacitance element, a first insulating layer, a second insulating layer, a third insulating layer, and a bit line;
the first transistor, the second transistor, and the second insulating layer are each located on the first insulating layer;
the third insulating layer is located on the first transistor and the second transistor;
the first capacitance element, the second capacitance element, and the bit line are each located on the third insulating layer;
the second insulating layer has a first opening reaching the first insulating layer and a second opening reaching the first insulating layer;
the first transistor has a portion located within the first opening;
the second transistor has a portion located within the second opening;
the first transistor has a first electrode functioning as one of a source electrode and a drain electrode, and a second electrode functioning as the other of the source electrode and the drain electrode;
the second transistor has the first electrode functioning as one of a source electrode and a drain electrode, and a third electrode functioning as the other of the first electrode and the drain electrode;
the first electrode is connected to the bit line;
the first capacitance element includes a fifth electrode having a columnar shape, a fourth insulating layer covering at least a part of a side surface of the columnar shape of the fifth electrode, and a sixth electrode;
the second capacitance element includes a seventh electrode having a columnar shape, a fifth insulating layer covering at least a part of a side surface of the columnar shape of the seventh electrode, and an eighth electrode;
the fourth insulating layer has a portion located between the fifth electrode and the sixth electrode,
the fifth insulating layer has a portion located between the seventh electrode and the eighth electrode,
the fourth insulating layer and the fifth insulating layer contain a material that may have ferroelectric properties,
the second electrode is connected to the fifth electrode of the first capacitance element;
The third electrode is connected to the seventh electrode of the second capacitance element. In claim 1,
a first plug, a second plug, and a third plug;
each of the first plug to the third plug has a portion provided in the third insulating layer;
the first electrode to the third electrode are each located on the second insulating layer;
the first electrode is connected to the bit line via the first plug;
the second electrode is connected to the fifth electrode of the first capacitance element via the third plug;
the third electrode is connected to the seventh electrode of the second capacitive element via the third plug. In claim 2,
a semiconductor layer shared by the first transistor and the second transistor;
the first transistor has a first gate line;
the second transistor has a second gate line;
the semiconductor layer has a first portion in contact with a first side surface of the first opening, a second portion in contact with an upper surface of the first insulating layer within the first opening, a third portion in contact with the second side surface of the first opening, a fourth portion in contact with the third side surface of the second opening, a fifth portion in contact with the upper surface of the first insulating layer within the second opening, and a sixth portion in contact with the fourth side surface of the second opening;
the first portion and the third portion are disposed with the first gate line interposed therebetween,
The fourth portion and the sixth portion are disposed with the second gate line interposed therebetween. In claim 3,
the semiconductor layer comprises a metal oxide;
The memory device, wherein the metal oxide includes indium. a first plurality of transistors, a second plurality of transistors, a first plurality of capacitance elements, a second plurality of capacitance elements, a first insulating layer, a second insulating layer, a third insulating layer, and a bit line;
the first plurality of transistors, the second plurality of transistors, and the second insulating layer are each located on the first insulating layer;
the third insulating layer is located on the first plurality of transistors and on the second plurality of transistors;
the first plurality of capacitive elements, the second plurality of capacitive elements, and the bit lines are each located on the third insulating layer;
the second insulating layer has a first opening reaching the first insulating layer and a second opening reaching the first insulating layer;
each of the first plurality of transistors has a portion located within the first opening;
each of the second plurality of transistors has a portion located within the second opening;
the first plurality of capacitive elements have a first plate line provided in common to the first plurality of capacitive elements;
the second plurality of capacitive elements have a second plate line provided in common to the second plurality of capacitive elements;
the first plate line and the second plate line are spaced apart from each other,
a first transistor, which is one of the first plurality of transistors, has one of a source and a drain connected to the bit line and the other connected to one of the first plurality of capacitance elements;
a second transistor, which is one of the second plurality of transistors, has one of a source and a drain connected to the bit line and the other connected to one of the second plurality of capacitance elements;
each of the first plurality of capacitance elements has a fifth electrode having a columnar shape;
each of the second plurality of capacitance elements has a sixth electrode having a columnar shape;
each of the first plurality of capacitive elements has a fourth insulating layer sandwiched between the fifth electrode and the first plate line;
each of the second plurality of capacitive elements has a fifth insulating layer sandwiched between the sixth electrode and the second plate line;
The fourth insulating layer and the fifth insulating layer include a material that can have ferroelectric properties. In claim 5,
each of the first plurality of transistors has a first semiconductor layer;
In the first opening, the first semiconductor layers of the first plurality of transistors are arranged in order along a first direction,
each of the second plurality of transistors has a second semiconductor layer;
In the second opening, the second semiconductor layers of the second plurality of transistors are arranged in order along a second direction,
the bit lines extend in a third direction;
The storage device, wherein the first direction and the second direction each intersect with the third direction. In claim 6,
the first plurality of transistors have a first gate line shared by the first plurality of transistors;
In each of the first plurality of transistors, the first semiconductor layer has a first portion in contact with a first side surface of the first opening, a second portion in contact with an upper surface of the first insulating layer within the first opening, and a third portion in contact with a second side surface of the first opening;
the first portion and the third portion are disposed with the first gate line interposed therebetween,
the second plurality of transistors have a second gate line provided in common with the second plurality of transistors;
In each of the second plurality of transistors, the second semiconductor layer has a fourth portion in contact with a third side surface of the second opening, a fifth portion in contact with an upper surface of the first insulating layer within the second opening, and a sixth portion in contact with the fourth side surface of the second opening;
The fourth portion and the sixth portion are disposed with the second gate line interposed therebetween.