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WO2025215955A1 - Circuit de commutation optique - Google Patents

Circuit de commutation optique

Info

Publication number
WO2025215955A1
WO2025215955A1 PCT/JP2025/006491 JP2025006491W WO2025215955A1 WO 2025215955 A1 WO2025215955 A1 WO 2025215955A1 JP 2025006491 W JP2025006491 W JP 2025006491W WO 2025215955 A1 WO2025215955 A1 WO 2025215955A1
Authority
WO
WIPO (PCT)
Prior art keywords
optical switch
unit optical
group
port
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/JP2025/006491
Other languages
English (en)
Japanese (ja)
Inventor
和浩 池田
遼太郎 鴻池
恵治郎 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
National Institute of Advanced Industrial Science and Technology AIST
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Institute of Advanced Industrial Science and Technology AIST filed Critical National Institute of Advanced Industrial Science and Technology AIST
Publication of WO2025215955A1 publication Critical patent/WO2025215955A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/29—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the position or the direction of light beams, i.e. deflection
    • G02F1/31—Digital deflection, i.e. optical switching
    • G02F1/313—Digital deflection, i.e. optical switching in an optical waveguide structure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/27—Arrangements for networking

Definitions

  • the present invention relates to an optical switch circuit.
  • a typical conventional optical switch had a circuit configuration that connected any input port in the input port array on the left side to any output port in the output port array on the right side.
  • Wiring to nodes outside the input and output port arrays was assumed to use optical fiber, as shown schematically in Figure 2, and was based on the assumption that it could be done with unlimited low loss. Note that in a communications network, both input and output ports of each node are not necessarily connected to the same optical switch.
  • optical switches to perform advanced calculations
  • semiconductor chips including CPUs (Central Processing Units), GPUs (Graphics Processing Units), and memory
  • optical switches to perform advanced calculations
  • semiconductor chips photoelectric conversion chips, optical switch chips, etc. all onto a single board or package, thereby increasing efficiency and density.
  • optical fiber cannot be used, and connections are made using optical waveguides made of organic materials, glass, silicon, etc.
  • optical waveguides have greater loss than optical fiber, and there is also the problem of significant loss occurring when the paths cross multiple times.
  • an input/output port array with input ports and output ports arranged alternately, on both sides of the optical switch, as shown schematically in Figure 3.
  • the arrangement of the input/output ports of the optical switch and the input/output ports of the small devices will match, allowing for connection over a short distance without crossing.
  • Patent Document 1 Such a configuration in which input and output ports are arranged alternately in an optical switch is disclosed, for example, in Patent Document 1.
  • Patent Document 1 aims to suppress degradation of crosstalk characteristics, and does not adopt a PILOSS (Path-Independent Insertion Loss) topology, which results in problems such as high power consumption due to the large number of unit optical switches that need to be turned ON, and loss that is path-dependent.
  • PILOSS Pulth-Independent Insertion Loss
  • Patent Document 2 discloses a technology that reduces the number of intersections of planar optical waveguides by arranging inputs and outputs next to each other, thereby reducing optical waveguide crossing loss.
  • the topology is Switch & Select, and there are problems with the large number of switches that need to be turned ON, resulting in high power consumption and path-dependent loss.
  • Non-Patent Document 1 discloses technology that can be applied to shuffle wiring. Specifically, it discloses a two-layer crosspoint optical switch, both of which have Si optical waveguides formed on them, and it discloses that the interlayer connection at the crosspoint is not fixed, but can be made variable by moving the optical waveguide using MEMS (Micro Electro Mechanical Systems). The technology disclosed in this document is characterized by the variable interlayer connection.
  • MEMS Micro Electro Mechanical Systems
  • an object of the present invention in one aspect, is to provide an optical switch circuit with lower loss and in which input ports and output ports are alternately adjacent to each other.
  • An optical switch circuit has N ⁇ N unit optical switches, each having two input ports and two output ports.
  • the first to N/2th columns of unit optical switches are arranged from the inside to the outside, with either the input port or the output port of each unit optical switch facing inward.
  • the inward-facing port of the unit optical switch in the first column of the pth group is connected to the closer port of the unit optical switch in the first column of the p-1th and p+1th groups, and the inward-facing port of the unit optical switch in the qth column (q is an integer between 2 and N/2) of the pth group is connected to the closer port of the outward-facing port of the unit optical switch in the q-1th column of the p-1th and p+1th groups.
  • an optical switch circuit comprises (A) M optical switch circuits each including N ⁇ N unit optical switches, each having two input ports and two output ports, and (B) N ⁇ M input/output ports of N/2 destinations, each having 2 ⁇ M input/output ports, and two shuffle circuits that respectively connect the N ⁇ M input/output ports out of the total 2 ⁇ M ⁇ N input/output ports of the M optical switch circuits to satisfy a desired connection relationship.
  • the M optical switch circuits are arranged in a row, with one of the two shuffle circuits located on the left side of the row and the other on the right side of the row.
  • the inward-facing port of the unit optical switch in the first column of the pth group is connected to the closer port of the unit optical switch in the first column in the p ⁇ 1th and p+1th groups, and the inward-facing port of the unit optical switch in the qth (q is an integer between 2 and N/2) column of the pth group is connected to the closer port of the outward-facing port of the unit optical switch in the q ⁇ 1th column in the p ⁇ 1th and p+1th groups.
  • each of the unit optical switches in the N/2th column a specific one of the outward-facing ports is used for either input or output, with adjacent groups having different types of ports, with the first through Nth groups arranged leftward and the (N+1)th through (2xN)th groups arranged rightward.
  • each of the two shuffle circuits includes a first optical circuit layer on which MxN first optical waveguides are formed, and a second optical circuit layer on which MxN second optical waveguides are formed, and any one of the first optical waveguides and any one of the second optical waveguides is connected via a single interlayer connection structure to satisfy the desired connection relationship.
  • FIG. 1 is a diagram for explaining the problems of the prior art.
  • FIG. 2 is a diagram for explaining the problems of the prior art.
  • FIG. 3 is a diagram for explaining the problems of the prior art.
  • FIG. 4 is a diagram for explaining the problems of the prior art.
  • FIG. 5 is a diagram showing an example of the arrangement of unit optical switches in a PILOSS topology.
  • FIG. 6 is a diagram showing a Mach-Zehnder interferometer switch.
  • FIG. 7 is a diagram for explaining the operation of the Mach-Zehnder interference switch.
  • FIG. 8 is a diagram showing a process of modifying the optical switch circuit according to the first embodiment.
  • FIG. 9 is a diagram showing a process of modifying the optical switch circuit according to the first embodiment.
  • FIG. 10 is a diagram showing a process of modifying the optical switch circuit according to the first embodiment.
  • FIG. 11 is a diagram showing the configuration of the optical switch circuit according to the first embodiment.
  • FIG. 12 is a diagram showing a configuration of another example of the optical switch circuit according to the first embodiment.
  • FIG. 13 is a diagram illustrating an example of paths in another example of the optical switch circuit according to the first embodiment.
  • FIG. 14 is a diagram showing the configuration of an optical switch circuit according to a modification of the first embodiment.
  • FIG. 15 is a diagram showing an example in which a chip is connected to an optical switch circuit according to a modification of the first embodiment.
  • FIG. 16 is a diagram for explaining an application example 1 of the optical switch circuit according to the first embodiment.
  • FIG. 11 is a diagram showing the configuration of the optical switch circuit according to the first embodiment.
  • FIG. 12 is a diagram showing a configuration of another example of the optical switch circuit according to the first embodiment.
  • FIG. 13 is a diagram illustrating an example of
  • FIG. 17 is a diagram for explaining an application example 1 of the optical switch circuit according to the first embodiment.
  • FIG. 18 is a diagram for explaining application example 1 of the optical switch circuit according to the first embodiment.
  • FIG. 19 is a diagram for explaining an application example 2 of the optical switch circuit according to the first embodiment.
  • FIG. 20 is a diagram for explaining an application example 2 of the optical switch circuit according to the first embodiment.
  • FIG. 21 is a diagram for explaining an optical switch circuit according to the second embodiment.
  • FIG. 22 is a diagram illustrating an optical switch circuit according to the second embodiment.
  • FIG. 23 is a diagram illustrating an example of the configuration of a shuffle circuit according to the second embodiment.
  • FIG. 24 is a diagram illustrating an example of the configuration of a shuffle circuit according to the second embodiment.
  • FIG. 25 is a diagram for explaining a modification of the shuffle circuit according to the second embodiment.
  • FIG. 26 is a diagram for explaining a modification of the shuffle circuit according to the second embodiment.
  • the embodiment of the present invention is based on the PILOSS topology.
  • the PILOSS topology is completely non-blocking, and the number of unit optical switches that are turned on is small, at one per path, which saves power.
  • the number of switches and the number of wiring intersections per path are uniform (N and N-1, respectively), so loss is path-independent.
  • N is the number of input ports.
  • Figure 5 shows an example of a PILOSS topology circuit in which inputs 1 to 4 and outputs 1' to 4' are normally arranged.
  • the optical switch circuit shown in Figure 5 is a PILOSS topology optical switch circuit also shown in Patent Document 3, and includes N x N unit optical switches, each with two inputs and two outputs and represented by a square.
  • a two-input, two-output unit optical switch is, for example, a Mach-Zehnder interferometer switch.
  • a specific optical circuit structure includes phase shifters 10 and 20, with optical couplers 30 and 40 before and after them.
  • the solid lines in Figure 6(b) represent optical waveguides.
  • the refractive index of phase shifters 10 and 20 is electrically changed to switch between the bar state shown in Figure 7(a) and the cross state shown in Figure 7(b). More specifically, when power is supplied and turned ON, the switch enters the bar state, and when power is stopped and turned OFF, the switch enters the cross state. Note that in such a unit optical switch, the input and output are interchangeable.
  • 16 unit optical switches are arranged in four rows and four columns, with one port of each of the four unit optical switches in the leftmost column being an input port, and one port of each of the four unit optical switches in the rightmost column being an output port.
  • the unit optical switches are connected as shown in Figure 5.
  • the board is first folded to the left in the middle, as shown in Figure 8, so that the input and output ports are lined up on the left side.
  • the ports are lined up from top to bottom in the order of (1,1'), (2',2), (3,3'), and (4',4).
  • it would be best to arrange them for example, as (1',2) and (3',4) on the left side and (1,2') and (3,4') on the right side.
  • optical switch circuit with the layout shown in Figure 10 is different from that shown in Figure 5, but it retains the same PILOSS characteristics of being completely non-blocking, power-saving, and path-independent in loss. Furthermore, because the input and output ports are arranged alternately next to each other, it allows for short-distance connections to the outside world without crossings. Furthermore, the number of crossings within the optical switch circuit is reduced by one to N-2 for each path. This means that losses due to wiring crossings can be suppressed.
  • FIG 11 shows a circuit layout in which the arrangement and wiring of the unit optical switches in the optical switch circuit shown in Figure 10 are arranged neatly.
  • This optical switch circuit includes unit optical switches S11 to S82. These unit optical switches are divided into a first group including unit optical switches S11 and S12, a second group including unit optical switches S21 and S22, a third group including unit optical switches S31 and S32, a fourth group including unit optical switches S41 and S42, a fifth group including unit optical switches S51 and S52, a sixth group including unit optical switches S61 and S62, a seventh group including unit optical switches S71 and S72, and an eighth group including unit optical switches S81 and S82.
  • the groups are arranged adjacent to each other in numerical order.
  • the first and eighth groups are also arranged adjacent to each other.
  • Each group includes a first row of unit optical switches and a second row of unit optical switches, arranged from the inside to the outside.
  • the first row of unit optical switches S11 and the second row of unit optical switches S12 are arranged from the inside to the outside.
  • the first row of unit optical switches S21 and the second row of unit optical switches S22 are arranged from the inside to the outside.
  • the first row of unit optical switches S31 and the second row of unit optical switches S32 are arranged from the inside to the outside.
  • the first row of unit optical switches S41 and the second row of unit optical switches S42 are arranged from the inside to the outside.
  • the first row of unit optical switches S81 and the second row of unit optical switches S82 are arranged from the inside to the outside.
  • the input port or the output port faces inward in order to connect the first columns with each other, and for the second and subsequent columns with the columns before and after, either the input port or the output port faces inward.
  • unit optical switch S11 is connected to unit optical switch S21 and unit optical switch S81
  • unit optical switch S21 is connected to unit optical switch S11 and unit optical switch S31
  • unit optical switch S31 is connected to unit optical switch S21 and unit optical switch S41
  • unit optical switch S41 is connected to unit optical switch S31 and unit optical switch S51
  • unit optical switch S51 is connected to unit optical switch S41 and unit optical switch S61
  • unit optical switch S61 is connected to unit optical switch S51 and unit optical switch S71
  • unit optical switch S71 is connected to unit optical switch S61 and unit optical switch S81
  • unit optical switch S81 is connected to unit optical switch S71 and unit optical switch S11.
  • the inward-facing port of the unit optical switch in the second column of each group is connected to the nearest outward-facing port of the unit optical switch in the first column of the adjacent group. That is, unit optical switch S12 is connected to the nearest outward-facing port of unit optical switch S21 in the first column of the adjacent second group, and to the nearest outward-facing port (marked with a circle) of unit optical switch S81 in the first column of the adjacent eighth group.
  • Unit optical switch S22 is connected to the nearest outward-facing port of unit optical switch S11 in the first column of the adjacent first group, and to the nearest outward-facing port of unit optical switch S31 in the first column of the adjacent third group.
  • Unit optical switch S32 is connected to the nearest outward-facing port of unit optical switch S21 and to the nearest outward-facing port of unit optical switch S41.
  • Unit optical switch S42 is connected to the nearest outward facing port of unit optical switch S31 and to the nearest outward facing port (marked with a circle) of unit optical switch S51.
  • Unit optical switch S52 is connected to the nearest outward facing port (marked with a circle) of the unit optical switch S41 and to the nearest outward facing port of the unit optical switch S61.
  • Unit optical switch S62 is connected to the nearest outward facing port of the unit optical switch S51 and to the nearest outward facing port of the unit optical switch S71.
  • Unit optical switch S72 is connected to the nearest outward facing port of the unit optical switch S61 and to the nearest outward facing port of the unit optical switch S81.
  • Unit optical switch S82 is connected to the nearest outward facing port of the unit optical switch S71 and to the nearest outward facing port of the unit optical switch S11 (marked with a circle).
  • a specific port facing outward is used as a port of a different type (i.e., input or output) than the port type of the unit optical switch in the last column of the adjacent group, so that the input and output ports are arranged alternately next to each other. If there is a last column + 1 column, this specific port is the port connected to the (last column + 1 column) unit optical switch in the (own group number + 1) group.
  • the lower of the outward facing ports of unit optical switch S12 is used as input port 1
  • the lower of the outward facing ports of unit optical switch S22 is used as output port 1'
  • the lower of the outward facing ports of unit optical switch S32 is used as input port 2
  • the upper of the outward facing ports of unit optical switch S52 is used as input port 4
  • the upper of the outward facing ports of unit optical switch S62 is used as output port 4'
  • the upper of the outward facing ports of unit optical switch S72 is used as input port 3
  • the upper of the outward facing ports of unit optical switch S82 is used as output port 3'.
  • Each group is arranged adjacent to the other in numerical order.
  • the first and sixteenth groups are also arranged adjacent to each other.
  • the unit optical switch S11 in the first column, the unit optical switch S12 in the second column, the unit optical switch S13 in the third column, and the unit optical switch S14 in the fourth column are arranged in this order from the inside to the outside.
  • the unit optical switch S81 in the first column, the unit optical switch S82 in the second column, the unit optical switch S83 in the third column, and the fourth unit optical switch S84 are arranged in this order from the inside to the outside.
  • the unit optical switch S91 in the first column, the unit optical switch S92 in the second column, the unit optical switch S93 in the third column, and the fourth unit optical switch S94 are arranged in this order from the inside to the outside.
  • the unit optical switches S161 in the first column, the unit optical switch S162 in the second column, the unit optical switch S163 in the third column, and the fourth unit optical switch S164 are arranged from the inside to the outside in that order.
  • either the input port or the output port is arranged facing inward, and the other is arranged facing outward.
  • the inward-facing port of the unit optical switch in the first column in each group is connected to the closer port of the unit optical switch in the first column in the adjacent group.
  • unit optical switch S11 in the first group is connected to unit optical switch S161 and unit optical switch S21
  • unit optical switch S21 in the second group is connected to unit optical switch S11 and unit optical switch S31.
  • unit optical switch S81 in the eighth group is connected to unit optical switch S71 and unit optical switch S91.
  • Unit optical switch S161 in the sixteenth group is connected to unit optical switch S11 and unit optical switch S151.
  • unit optical switch S12 is connected to unit optical switch S161 and unit optical switch S21.
  • Unit optical switch S23 is connected to unit optical switch S12 and unit optical switch S32.
  • Unit optical switch S34 is connected to unit optical switch S23 and unit optical switch S43.
  • unit optical switch S13 is connected to unit optical switch S162 and unit optical switch S22.
  • Unit optical switch S14 is connected to unit optical switch S163 and unit optical switch S23.
  • unit optical switch S82 is connected to unit optical switch S71 and unit optical switch S91.
  • Unit optical switch S83 is connected to unit optical switch S72 and unit optical switch S92.
  • Unit optical switch S84 is connected to unit optical switch S73 and unit optical switch S93.
  • unit optical switch S92 is connected to unit optical switch S81 and unit optical switch S101.
  • Unit optical switch S93 is connected to unit optical switch S82 and unit optical switch S102.
  • Unit optical switch S94 is connected to unit optical switch S83 and unit optical switch S103.
  • unit optical switch S162 is connected to unit optical switch S151 and unit optical switch S11.
  • Unit optical switch S163 is connected to unit optical switch S152 and unit optical switch S12.
  • Unit optical switch S164 is connected to unit optical switch S153 and unit optical switch S13.
  • a specific port facing outward i.e., if there is an (N/2+1) column, the port connected to the unit optical switch in the (N/2+1) column in the p+1 group, is used as a port of a different type from the port type of the unit optical switch in the N/2 column in the adjacent group, so that the input and output ports are arranged alternately next to each other.
  • output and input ports appear in pairs in order, such as (1', 1), (2', 2), ..., (8', 8).
  • each unit optical switch The bar state and cross state of each unit optical switch are controlled by the control unit 100 to an appropriate state according to the path to be set.
  • Figure 13 shows three example paths in the optical switch circuit shown in Figure 12.
  • Figure 13 illustrates path R1 from input port 1 of unit optical switch S24 to output port 6' of unit optical switch S114, path R2 from input port 8 of unit optical switch S164 to output port 5' of unit optical switch S94, and path R3 from input port 7 of unit optical switch S144 to output port 4' of unit optical switch S74.
  • These paths are merely examples, and in these paths R1 to R3, the control unit 100 turns ON (bar state) only the last unit optical switch that is passed through.
  • an optical switch circuit such as that shown in Figure 12 is preferable, but in some cases, unit optical switches may be arranged as in the optical switch circuit shown in Figure 14.
  • This optical switch circuit includes 64 unit optical switches, just like in Figure 12, and four unit optical switches located on a half line from the center of the circle belong to one group. For example, if the group at 12 o'clock is designated as the first group and group numbers are assigned in counterclockwise order at equal angular intervals, the group at 9 o'clock is the fifth group, the group at 6 o'clock is the ninth group, and the group at 3 o'clock is the thirteenth group.
  • unit optical switches that are the same distance from the center of the circle, i.e., arranged on a circumference of the same radius, are unit optical switches in the same row, and are arranged in rows 1 to 4 from the center of the circle (i.e., the inside) to the outside.
  • semiconductor chips can be placed not only on the left and right but also on the top and bottom, as shown schematically in Figure 15.
  • the unit optical switches are arranged based on a circle, but it is also possible to arrange the unit optical switches based on a polygon instead of a circle.
  • K polygons can be arranged in N/2 rows concentrically, with 2 x N/K groups on each side.
  • the optical switch circuit according to the first embodiment has unused idle ports, similar to PILOSS, which can be used as another independent and synchronized switch circuit. This is the same feature as that of PILOSS described in Patent Document 3.
  • the input and output ports are named as shown in Figure 16. That is, the first set of input/output ports includes the lower output port B1 of unit optical switch S12, the lower input port A2 of unit optical switch S22, the lower output port B3 of unit optical switch S32, the lower input port A4 of unit optical switch S42, the upper output port B4 of unit optical switch S52, the upper input port A3 of unit optical switch S62, the upper output port B2 of unit optical switch S72, and the upper input port A1 of unit optical switch S82.
  • the second set of input/output ports includes the upper input port K4 of the unit optical switch S12, the upper output port L4 of the unit optical switch S22, the upper input port K3 of the unit optical switch S32, the upper output port L2 of the unit optical switch S42, the lower input port K1 of the unit optical switch S52, the lower output port L1 of the unit optical switch S62, the lower input port K2 of the unit optical switch S72, and the lower output port L3 of the unit optical switch S82. Switching from the input ports A1 to A4 to the output ports B1 to B4 and switching from the input ports K1 to K4 to the output ports L1 to L4 are performed independently and synchronously.
  • each path for the first set such as input port A1 to output port B4, input port A2 to output port B2, input port A3 to output port B3, and input port A4 to output port B1
  • each path for the second set such as input port K1 to output port L4, input port K2 to output port L2, input port K3 to output port L3, and input port K4 to output port L1
  • unit optical switch S12, unit optical switch S32, unit optical switch S52, and unit optical switch S72 are turned ON (bar state).
  • each path for the first set such as input port A1 to output port B2, input port A2 to output port B1, input port A3 to output port B4, and input port A4 to output port B3, and each path for the second set, such as input port K1 to output port L2, input port K2 to output port L1, input port K3 to output port L4, and input port K4 to output port L3, can be realized independently and synchronously, as shown schematically in FIG. 18.
  • unit optical switch S21, unit optical switch S41, unit optical switch S61, and unit optical switch S81 are turned ON (bar state).
  • FIG. 19 shows an example of a circuit for selecting a signal of each wavelength from a wavelength division multiplexed signal of four wavelengths ⁇ 1 to ⁇ 4 .
  • a wavelength selective coupler 201 for selecting light of wavelength ⁇ 1 a wavelength selective coupler 301 for selecting light of wavelength ⁇ 2 , a wavelength selective coupler 401 for selecting light of wavelength ⁇ 3 , and a wavelength selective coupler 501 for selecting light of wavelength ⁇ 4 are formed in series in an optical waveguide 601.
  • a wavelength selective coupler 202 for selecting light of wavelength ⁇ 1 a wavelength selective coupler 302 for selecting light of wavelength ⁇ 2 , a wavelength selective coupler 402 for selecting light of wavelength ⁇ 3 , and a wavelength selective coupler 502 for selecting light of wavelength ⁇ 4 are formed in series in an optical waveguide 602.
  • a wavelength selective coupler 204 for selecting light of wavelength ⁇ 1 a wavelength selective coupler 304 for selecting light of wavelength ⁇ 2 , a wavelength selective coupler 404 for selecting light of wavelength ⁇ 3 , and a wavelength selective coupler 504 for selecting light of wavelength ⁇ 4 are formed in series in the optical waveguide 603.
  • a wavelength selective coupler 205 for selecting light of wavelength ⁇ 1 a wavelength selective coupler 305 for selecting light of wavelength ⁇ 2 , a wavelength selective coupler 405 for selecting light of wavelength ⁇ 3 , and a wavelength selective coupler 505 for selecting light of wavelength ⁇ 4 are formed in series in the optical waveguide 604.
  • Such wavelength selective switches are not limited to four wavelengths and can be modified for wavelength division multiplexed signals with other numbers of wavelengths.
  • the optical switch circuit described in the first embodiment is used for the N-input, N-output optical switch, and M of these optical switch circuits are arranged vertically. Then, on the left and right of the row of these optical switch circuits, shuffle circuits with N x M port inputs and N x M port outputs are placed. These shuffle circuits use a two-layer optical waveguide structure to prevent crossings within the same circuit plane.
  • the shuffle circuit according to this embodiment employs a cross-point topology, as shown in FIG. 23. That is, for example, W first-layer optical waveguides 1000 made of Si are formed in the east-west direction (left-right direction), and W second-layer optical waveguides 1100 made of SiN are formed in the north-south direction (up-down direction). Note that the materials used for the first-layer optical waveguides 1000 and the second-layer optical waveguides 1100 are different from each other. That is, Si may be replaced with SiN and SiN may be replaced with Si.
  • an interlayer connection structure is formed between the second layer optical waveguide 1100 and the optical waveguide of the input/output port 1200.
  • an optical waveguide array or the like is directly connected to the second layer optical waveguide 1100 and an optical switch circuit is arranged on the same plane as the second layer optical waveguide 1100, the interlayer connection structure of the input/output port 1200 is not necessary.
  • 16 optical waveguides are arranged in the east-west and north-south directions, and an interlayer connection structure is formed at the intersections of the optical waveguides based on the required connection relationship.
  • Figure 25 shows the first stage of modification. That is, the first through eighth lines of the second-layer optical waveguide 1100 are moved to the upper side and their order is changed. If the interlayer connection structure is not changed, the connection relationship will be maintained even if this rearrangement is made. Furthermore, as shown in Figure 26, the shuffle circuit can be properly formed by removing unnecessary portions of the optical waveguide and adjusting the extraction direction of the second-layer optical waveguide so that the distance to the port of the connected chip is the shortest.
  • circuits according to the above-described embodiments are preferably implemented as optical integrated circuits made of Si optical waveguides or SiN optical waveguides manufactured by silicon photonics technology.
  • Silicon photonics relies on advanced silicon technology developed through electronics, resulting in highly stable and reproducible material properties. Furthermore, because it can be manufactured in semiconductor manufacturing plants, it offers excellent mass productivity, precision, and long-term reliability.
  • the unit optical switches included in the optical switch circuit typically use a 2x2 Mach-Zehnder interference switch that integrates a Si optical waveguide and a microheater (when using the thermo-optic effect) or a pin structure (when using the carrier plasma effect).
  • a 2x2 Mach-Zehnder interference switch that integrates a Si optical waveguide and a microheater (when using the thermo-optic effect) or a pin structure (when using the carrier plasma effect).
  • the switch disclosed in Non-Patent Document 1 or the ring-type optical switch disclosed in Non-Patent Document 2 may also be used.
  • the SiN optical waveguide layer is formed on top of the Si optical waveguide layer and the SiO2 cladding layer, sandwiched between them, and is formed with a sufficient vertical separation of, for example, 1 ⁇ m or more so that loss and crosstalk do not occur even when they intersect three-dimensionally.
  • a directional coupler or the like is used to connect the Si optical waveguide and the SiN optical waveguide to each other, achieving a highly efficient connection with a loss of less than 1 dB.
  • the shuffle wiring between each optical switch circuit and each chip does not cross on the same plane, allowing for low-loss connections.
  • the Si optical waveguide crossing loss is 0.02 dB per layer.
  • this loss can be improved.
  • the optical switch circuit has N ⁇ N unit optical switches, each having two input ports and two output ports.
  • the first to N/2th columns of unit optical switches are arranged from the inside to the outside, with either the input port or the output port of each unit optical switch facing inward.
  • the inward-facing port of the unit optical switch in the first column of the pth group is connected to the closer port of the unit optical switch in the first column of the p-1th and p+1th groups, and the inward-facing port of the unit optical switch in the qth column (q is an integer between 2 and N/2) of the pth group is connected to the closer port of the outward-facing port of the unit optical switch in the q-1th column of the p-1th and p+1th groups.
  • the input and output ports are arranged side by side. Furthermore, crossing of the wiring is suppressed, which helps to reduce losses due to crossing.
  • a specific one of the outward-facing ports may be used as either an input or output port in an adjacent group. For example, if the port of the unit optical switch in the N/2th column in an adjacent group is an input port, a specific one of the ports of this unit optical switch will be an output port.
  • groups 1 through N may be arranged facing left, and groups N+1 through 2xN may be arranged facing right. This allows for connection without crossing wires, even when destination chips are arranged on the left and right.
  • Groups 1 through 2xN may also be divided by the number of sides of the polygon, and 2xN/(number of sides) groups may be arranged in directions perpendicular to each side.
  • the optical switch circuit comprises (A) M optical switch circuits each including N ⁇ N unit optical switches, each having two input ports and two output ports; (B) N ⁇ M input/output ports of N/2 destinations, each having 2 ⁇ M input/output ports; and two shuffle circuits that respectively connect the N ⁇ M input/output ports out of the total 2 ⁇ M ⁇ N input/output ports of the M optical switch circuits to satisfy the desired connection relationship.
  • the M optical switch circuits are arranged in a row, with one of the two shuffle circuits located on the left side of the row and the other on the right side of the row.
  • the inward-facing port of the unit optical switch in the first column of the pth group is connected to the closer port of the unit optical switch in the first column in the p ⁇ 1th and p+1th groups, and the inward-facing port of the unit optical switch in the qth (q is an integer between 2 and N/2) column of the pth group is connected to the closer port of the outward-facing port of the unit optical switch in the q ⁇ 1th column in the p ⁇ 1th and p+1th groups.
  • each of the unit optical switches in the N/2th column a specific one of the outward-facing ports is used for either input or output, with adjacent groups having different types, with the first through Nth groups arranged leftward and the (N+1)th through (2xN)th groups arranged rightward.
  • each of the two shuffle circuits includes a first optical circuit layer on which MxN first optical waveguides are formed, and a second optical circuit layer on which MxN second optical waveguides are formed, and any one of the first optical waveguides and any one of the second optical waveguides is connected via a single interlayer connection structure to satisfy the desired connection relationship.
  • shuffle circuits can be used to connect N/2 destinations (e.g., chips), each with 2 x M input/output ports, without crossover.
  • N/2 destinations e.g., chips
  • Each of the M optical switch circuits is substantially the same as the optical switch circuit of the first aspect, allowing for a reduced number of unit optical switches and low-loss connection to destinations.
  • the first optical waveguide and the second optical waveguide are made of different materials.
  • the first optical waveguide may be made of Si and the second optical waveguide of SiN, or the first optical waveguide may be made of SiN and the second optical waveguide of Si.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Computing Systems (AREA)
  • Electromagnetism (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Optical Modulation, Optical Deflection, Nonlinear Optics, Optical Demodulation, Optical Logic Elements (AREA)
  • Optical Communication System (AREA)

Abstract

La présente invention concerne un circuit de commutation optique qui présente moins de pertes et qui est conçu de telle sorte que des ports d'entrée et des ports de sortie soient alternativement adjacents les uns aux autres, ledit circuit comprenant N × N commutateurs optiques individuels présentant chacun deux ports d'entrée et deux ports de sortie. Les N × N commutateurs optiques individuels sont répartis en des premier à 2 × Nième groupes présentant chacun le même nombre de commutateurs optiques individuels, le pième groupe (p étant un nombre entier égal ou supérieur à 1 et inférieur ou égal à 2×N) étant agencé de façon à être adjacent au (p + 1)ième groupe et au (p - 1)ième groupe. Dans chacun des groupes, des commutateurs optiques individuels d'une première rangée à une (N/2)ième rangée sont agencés de l'intérieur vers l'extérieur, et les ports d'entrée ou bien les ports de sortie des commutateurs optiques individuels sont agencés vers l'intérieur. Les ports orientés vers l'intérieur des commutateurs optiques individuels de la première rangée dans le pième groupe sont connectés aux ports des ports plus proches des commutateurs optiques individuels de la première rangée dans le (p - 1-)ème groupe et le (p + 1)ième groupe, et les ports orientés vers l'intérieur des commutateurs optiques individuels de la qième rangée (q étant un nombre entier égal ou supérieur à 2 et inférieur ou égal à N/2) dans le pième groupe sont connectés aux ports plus proches des ports orientés vers l'extérieur des commutateurs optiques individuels de la (q - 1)ième rangée dans le (p - 1)ième groupe et le (p + 1)ième groupe.
PCT/JP2025/006491 2024-04-09 2025-02-26 Circuit de commutation optique Pending WO2025215955A1 (fr)

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JP2024-062484 2024-04-09
JP2024062484A JP2025159756A (ja) 2024-04-09 2024-04-09 光スイッチ回路

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012172760A1 (fr) * 2011-06-14 2012-12-20 日本電気株式会社 Procédé de commande de commutateur optique, dispositif de commande de commutateur optique et système de transmission optique
JP2019197138A (ja) * 2018-05-09 2019-11-14 国立研究開発法人産業技術総合研究所 完全非閉塞光スイッチ
JP2020098232A (ja) * 2018-12-17 2020-06-25 国立研究開発法人産業技術総合研究所 光スイッチ
JP2022110753A (ja) * 2021-01-19 2022-07-29 日本電信電話株式会社 光スイッチ

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012172760A1 (fr) * 2011-06-14 2012-12-20 日本電気株式会社 Procédé de commande de commutateur optique, dispositif de commande de commutateur optique et système de transmission optique
JP2019197138A (ja) * 2018-05-09 2019-11-14 国立研究開発法人産業技術総合研究所 完全非閉塞光スイッチ
JP2020098232A (ja) * 2018-12-17 2020-06-25 国立研究開発法人産業技術総合研究所 光スイッチ
JP2022110753A (ja) * 2021-01-19 2022-07-29 日本電信電話株式会社 光スイッチ

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