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WO2025215224A1 - Procédé utilisé pour produire des trous d'interconnexion électriques - Google Patents

Procédé utilisé pour produire des trous d'interconnexion électriques

Info

Publication number
WO2025215224A1
WO2025215224A1 PCT/EP2025/060062 EP2025060062W WO2025215224A1 WO 2025215224 A1 WO2025215224 A1 WO 2025215224A1 EP 2025060062 W EP2025060062 W EP 2025060062W WO 2025215224 A1 WO2025215224 A1 WO 2025215224A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
zones
component
region
separation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/EP2025/060062
Other languages
German (de)
English (en)
Inventor
Sophie Billat
Alfons DÉHE
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hann-Schickard-Gesellschaft fuer Angewandte Forschung eV
Original Assignee
Hann-Schickard-Gesellschaft fuer Angewandte Forschung eV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hann-Schickard-Gesellschaft fuer Angewandte Forschung eV filed Critical Hann-Schickard-Gesellschaft fuer Angewandte Forschung eV
Publication of WO2025215224A1 publication Critical patent/WO2025215224A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B81C1/00095—Interconnects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0128—Processes for removing material
    • B81C2201/013—Etching
    • B81C2201/0132—Dry etching, i.e. plasma etching, barrel etching, reactive ion etching [RIE], sputter etching or ion milling
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0128—Processes for removing material
    • B81C2201/013—Etching
    • B81C2201/0133—Wet etching
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0174—Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
    • B81C2201/0181—Physical Vapour Deposition [PVD], i.e. evaporation, sputtering, ion plating or plasma assisted deposition, ion cluster beam technology

Definitions

  • the invention relates to a method for producing a component comprising a via region which extends along a vertical direction from a rear side to a front side of the component.
  • a substrate comprising an electrically conductive or semiconducting material is first provided.
  • the substrate is subdivided into two or more galvanically separated zones, wherein the subdivision is formed by a continuous separation of the substrate along the vertical direction and, after the separation, an empty region exists between the two or more zones.
  • the empty region is at least partially filled with an insulating material.
  • An electrical connection contact is applied to the front side and the rear side of at least one zone, such that the at least one zone functions as a via region.
  • the invention relates to a component that can be produced by the method according to the invention.
  • Vias refer to vertical electrical connections between conductor levels, as they are often found in semiconductor components. Vias are particularly common in integrated circuits and enable the transmission of current or electrical signals between different levels of a semiconductor component.
  • TSVs through-silicon vias
  • silicon vias can enable vertical electrical connections between stacked microchips in 3D integrated circuits.
  • MEMS components can also be operated within or on a silicon substrate or wafer stack.
  • the review article Sordo et al. (2018) describes common processes in the prior art for providing vias on a substrate. This usually involves etching a substrate first, creating trenches on the substrate. The substrate is then coated with an insulating material. This insulates, in particular, the sidewalls of the trenches. After the insulating material has been coated, the insulating material on the surface of the substrate is often at least partially removed to smooth the surface. Furthermore, the trenches are filled with an electrically conductive material, which forms the via in the substrate. To transmit the electrical current, additional metal layers are applied to both sides of the electrically conductive filler material to provide an electrical connection contact. Depending on the application, the via may extend through the entire substrate or only partially extend into the substrate to a surface.
  • Wafer stacks consist of multiple wafers or substrates that encapsulate a MEMS component. At least two substrates are used for this purpose, which are also referred to as the bottom substrate and the cap substrate.
  • the bottom substrate and the cap substrate For the electrical functionality of the MEMS component, it is usually necessary to form a via to the MEMS component of the wafer stack through the bottom substrate and/or the cap substrate, in particular for controlling and/or reading the MEMS component.
  • the bottom substrate and the cap substrate are bonded together.
  • the via can be formed before or after bonding to the bottom substrate and/or the cap substrate.
  • an etching is performed on the base substrate and/or cap substrate, passivation or insulation is performed by coating an insulating material, and then the trenches are filled with an electrically conductive material.
  • Copper, tungsten, and/or platinum are known in the art as electrically conductive filler materials for forming the via.
  • a substrate which comprises a carrier layer, an insulating layer, and a semiconductor layer located on the insulating layer.
  • a dry etching process is performed to etch down to the insulating layer, forming trenches in the semiconductor layer.
  • An oxide layer is then applied, thereby passivating the trenches.
  • the trenches are then filled with polysilicon, which serves as an electrically conductive material for forming the via.
  • the polysilicon is electrically contacted for an electrical connection.
  • US 9,459,224 B1 discloses a manufacturing method for a gas sensor.
  • trenches are introduced into a substrate. Initially, the trenches do not extend completely through the substrate.
  • the semiconductor substrate is thinned to expose the trenches so that they completely separate the substrate.
  • insulating structures are introduced into the trenches.
  • a dielectric layer is applied to the substrate along the trenches, and a membrane film is applied to the dielectric layer.
  • a heater is formed on the membrane film and electrically connected to the through-holes formed by portions of the semiconductor substrate.
  • US 2013/0147020 A1 relates to a method for providing vias.
  • a highly doped semiconductor substrate is initially provided.
  • a dielectric layer is first applied to the substrate surface.
  • the dielectric layer is opened in the areas where electrical contact with the substrate is to be established.
  • a functional layer is applied, in which a micromechanical sensor structure is incorporated.
  • a metallization serves as a bonding metal, onto which a cap wafer is applied.
  • a dielectric intermediate layer is applied to the back of the substrate and in an area of the via to be created. opened.
  • a trench or isolation trench extends across the entire thickness of the substrate down to the dielectric layer. This electrically isolates a connection area of the semiconductor substrate from the adjacent substrate material and forms a via in the semiconductor substrate, which is connected to the sensor structure via the conductor track.
  • the methods commonly used in the prior art are advantageous in that electrical functionality can be precisely specified through the geometric design and/or the selection of the electrically conductive filler material.
  • a disadvantage in terms of the process is that a large number of steps must be performed, such as complex metal filling, to form the via.
  • Another disadvantage is that a flat geometry of a substrate surface is often not achieved, since multiple connection components often have to be formed.
  • residues of insulating material remain on the surface of the substrate, which also have a detrimental effect on the provision of a smooth surface and can complicate integration into corresponding applications.
  • the object of the invention is to eliminate the disadvantages of the prior art.
  • one object of the invention is to provide a method that enables the simple production of a component with a through-hole connection with desired electrical properties, while preferably maintaining a flat substrate surface for subsequent integration.
  • the invention in a first aspect, relates to a method for producing a component comprising a via region which extends along a vertical direction from a rear side to a front side of the component, the method comprising the following steps: a) providing a substrate comprising an electrically conductive or semiconducting material, b) dividing the substrate into two or more galvanically separated zones, wherein the division is effected by a continuous separation of the substrate along the vertical direction and after the separation there is an empty region between the two or more zones, c) at least partially filling the empty region with an insulating material, d) applying an electrical connection contact on the front side and the rear side to at least one zone of the two or more zones, such that the at least one zone functions as a via region.
  • the claimed method is advantageously characterized by particularly efficient process control. In contrast to prior art methods, it is particularly unnecessary, after process steps for removing a region of the substrate have been performed, to fill the removed regions with a conductive material to create the via region. In the prior art, metal filling is often performed for this purpose, but this is technically complex.
  • the method according to the invention can advantageously completely dispense with this processing.
  • the inventive method utilizes the conductivity of the substrate itself to form via-hole regions.
  • galvanically separated zones are created that serve as a power or signal line along a vertical direction and can thus function as via-hole regions.
  • the simplification of the process steps allows for both time and cost savings, making the method particularly suitable for mass applications.
  • Another advantage is that by separating the substrate into galvanically separated zones, through-hole plating areas can be created, while simultaneously achieving a very flat or level geometry of the component's surface. This way, the flat surface of a substrate is advantageously not compromised by its separation into galvanically separated zones.
  • the zones can be contacted directly without unnecessarily disrupting the flat surface of the substrate.
  • planar design of the component can lead to a number of advantages, particularly from an application perspective. Firstly, it facilitates the integration of the component into more complex structures. If the component is a sensor, the planar surface can also ensure reduced disturbance to the environment, which is advantageous for flow sensors or aeroacoustic sensors, for example.
  • a further advantage of the method according to the invention is that, by designing the zones, electrical properties, such as a resistance and/or an inductance, of the via region can be adjusted with high flexibility with regard to the desired application.
  • the electrical resistance of the via region depends, among other things, on the internal resistance or specific resistance, the height and the cross-section of the via region.
  • the resistance is proportional to the vertical height and inversely proportional to the horizontal cross-section of the via region.
  • the height preferably refers to the dimension of the via region from the back to the front.
  • the horizontal cross-section of the via region is determined in particular by the (cross-sectional) area of the respective zones. Since the substrate is divided into a corresponding number of zones to form the via regions, the cross-sectional area of the zones can be selected to be high.
  • the sum of the (horizontal) cross-sectional areas of all zones preferably essentially corresponds to the (horizontal) cross-sectional area of the substrate.
  • an extremely low electrical resistance can be achieved.
  • gallium arsenide preferably doped with silicon and/or tin
  • a specific resistance p of 0.001 ⁇ cm can be assumed.
  • Such low electrical resistances reduce ohmic losses and increase the performance of the component, allowing particularly fast and interference-free signal transmission.
  • a further advantage of the method according to the invention is that by separating the substrate into galvanically separated zones, via-connection regions can be created that exhibit low (self-)inductance.
  • Inductance is a particularly relevant parameter for signal lines or alternating currents, since alternating magnetic fields can interfere with the signal or current lines. Since the (self-)inductance also decreases with a larger cross-section of the via-connection region, by separating the substrate into galvanically separated zones, via-connection regions with not only good conductivity but also low inductance can be advantageously created.
  • the cross section of the via region be only slightly lower, equal to, or greater than the height of the via region.
  • the ratio of a cross-sectional dimension of the via region (preferably the largest extent of the via region in a cross-sectional plane) to the height of the via region is at least approximately 0.5, 1, 2, 3, 5, 10, or more.
  • a low inductance for the component can be achieved through the geometric design of the via region.
  • Such a cross-section-to-height ratio allows for low resistance, low inductance, and low impedance.
  • the component manufactured using this process is particularly well-suited for low-impedance applications (low-impedance devices).
  • any detrimental formation of parasitic capacitances that may arise between the multiple zones or vias can be counteracted by at least partially filling the insulating material. This can be achieved, in particular, by selecting the insulating material, as will be described in more detail below.
  • a component that can be produced using the method according to the invention preferably refers to a component that is used for circuits in electrical engineering or electronics, in particular in connection with semiconductor materials.
  • the average person skilled in the art knows that the term "component" can be interpreted broadly.
  • a component within the meaning of the invention can comprise an integrated circuit that has transistors and/or diodes or can itself form such a component.
  • the integrated circuits are preferably manufactured on substrates that can in particular comprise a semiconductor material, but are not limited thereto.
  • components such as transistors, diodes and/or capacitors can be produced using the substrate material itself.
  • a component can also include, for example, or be itself, a circuit board, multiple processors, semiconductor memories, microcontrollers, converters, microchips, etc.
  • a component can preferably be a component for and/or from semiconductor technology and/or microsystem technology.
  • the component comprises, in particular, a via region.
  • a via region within the meaning of the invention, preferably refers to a vertical electrical connection through which current can be conducted (vertically) between different levels. The current flow serves, for example, for signal transmission.
  • the diameter and, if applicable, the shape of the via region can vary. This can be determined, in particular, by the design of the galvanically separated zones that function as via regions.
  • the via region runs vertically from the front side to the back side.
  • the front side and the back side refer to two opposite sides of the substrate and thus also to the zones.
  • the vertical direction preferably refers to the direction that extends along the front side and the back side.
  • a cross-sectional dimension (e.g., width) of the via region preferably refers to a dimension perpendicular to the vertical direction.
  • Current conduction and signal transmission in particular, occur along the vertical direction.
  • the continuous separation of the substrate to form the zones occurs, for example, starting from the front side, but can also occur starting from a back side.
  • a substrate comprising an electrically conductive or semiconducting material is first provided.
  • a substrate can, for example, A circular or square disc with a thickness in the millimeter or submillimeter range.
  • Semiconductor substrates are typically manufactured from monocrystalline or polycrystalline (semiconductor) blanks, so-called ingots, and generally serve as a substrate for, for example, coatings or components, in particular MEMS components and/or electronic circuits.
  • the use of the term "wafer” for the substrate is also known in the prior art, with the substrate preferably referring to the material to be treated.
  • the terms "wafer” and “substrate” can be used synonymously.
  • the substrate comprises an electrically conductive or semiconducting material.
  • the electrically conductive material preferably refers to an electrical conductor in the conventional sense.
  • the semiconducting material preferably refers to a semiconductor.
  • An electrically conductive material preferably has an electrical conductivity of at least 10 4 S/cm (Siemens per centimeter) or higher.
  • An electrically semiconductive material preferably has an electrical conductivity that lies between the electrical conductivity of an electrical conductor and an insulator (insulating material), i.e., preferably between 10 4 S/cm and 10 8 S/cm.
  • the data preferably refer to room temperature (approximately 20°C).
  • the substrate is divided into two or more galvanically separated zones.
  • Galvanic separation preferably means that there is such a separation between the zones that electrical insulation exists between the two or more zones.
  • there is an empty space between the zones which can be at least partially filled with an ambient fluid, air, vacuum, and/or an insulating material, but in any case does not allow a direct electrical connection between separated zones of the substrate.
  • the insulating material prevents, in particular, an electrical current from spreading in the transverse direction, but instead flows essentially along the height of the via region.
  • Preferred insulating materials are non-conductive materials (preferably with an electrical conductivity of less than 10' 8 S/cm) and/or materials with a high specific resistance, preferably of at least approximately 10 2 0 * cm, 10 3 0 * cm, 10 4 0 * cm, 10 5 0 * cm, 10 6 0 * cm, 10 7 0 * cm, 10 8 0 * cm, 10 9 0 * cm, 10 10 0 * cm, 10 11 0 * cm, 10 12 0 * cm or more.
  • the above-mentioned preferred resistivities for the insulating material advantageously enable reliable protection between the zones or vias during current transmission. This promotes the long-term functionality of the component for current transmission.
  • the galvanic separation of the zones already provides electrical insulation between the zones or through-hole areas.
  • the insulation through the separation or galvanic separation of the zones can preferably be characterized by a resistance of more than 1 kOhm, preferably more than 1 MOhm or more. of the substrate to form the zones, in particular, cross-conduction of a current between the galvanically separated zones is prevented.
  • the zones are preferably formed by a continuous separation of the substrate along the vertical direction. This preferably means that a separation is carried out through the substrate, wherein the separation preferably takes place from the front to the back or vice versa. With a continuous separation, preferably no area of the substrate remains between the separated zones.
  • a continuous separation can be carried out, for example, by reactive ion deep etching (DRIE, Bosch process) and is extremely simple and precise to carry out in terms of process technology.
  • Further preferred methods for separating the substrate into zones can be selected from a group comprising wet-chemical etching methods and/or dry etching methods, preferably physical and/or chemical dry etching methods and/or reactive ion etching.
  • a continuous separation of the substrate may mean that the separation to form adjacent zones takes place in multiple process steps.
  • a partial separation of the substrate initially takes place along its vertical direction.
  • the separation of the substrate can then preferably be continued to make the separation continuous.
  • Other process steps can preferably also be performed between the partial and complete separation of the substrate.
  • a partial and then a complete separation of the substrate can preferably take place starting from a single side of the substrate, for example only starting from the front side or from the back side. It may also be preferred that the preferably initially partial and then complete separation of the substrate takes place starting from a front side and from a back side (or vice versa).
  • a continuous separation of the substrate can, for example, also be made continuous by a partial separation from one side and then by a grinding process from the corresponding opposite side of the substrate. This also creates an empty area between two adjacent zones.
  • a void exists between the separated at least two zones.
  • the zones are provided by forming a void, which arises through or after the continuous separation of the substrate along the vertical direction.
  • the void preferably refers to a section of space that exists between the two or more zones after the continuous separation has been performed.
  • the void can also be understood as a recess.
  • the empty space is preferably at least partially filled with an insulating material.
  • an insulating material By at least partially filling the insulating material, a mechanical hold is achieved between the zones, while simultaneously ensuring galvanic separation. While the zones are galvanically separated from one another after the immediate, continuous separation, for example, by an empty space filled with (ambient) air, the integrity of the multi-part substrate, consisting of separate zones, would no longer be ensured.
  • the two or more zones are therefore also mechanically connected to one another, in particular by the insulating material, but electrically insulated from one another.
  • the at least partial filling preferably comprises a partial or complete filling of the empty space.
  • Partial filling preferably means a filling of the empty space by a proportion of at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80% or at least 90% of the volume of the empty space.
  • Complete filling preferably means a filling of the empty space by 95% - 100% of the volume.
  • the insulating material preferably means an electrically insulating material, ie in particular one or more dielectric materials, with preferred suitable materials being mentioned elsewhere herein.
  • Separating the substrate into zones preferably means that the resulting zones (or sections of the substrate) together form the entire substrate.
  • an electrical connection contact is preferably applied to the front and back of the respective zone.
  • the current flows from the front to the back, or vice versa, between the electrical connection contacts through the via.
  • An electrical connection contact preferably means an electrical connection to the zone or to the via.
  • an electrical connection contact can enable the transfer or (vertical) forwarding of the electrical current to other areas of the component.
  • the method is characterized in that the continuous separation of the substrate in a horizontal cross section of the substrate is non-rectilinear, so that preferably facing surfaces of the adjacent zones are characterized by a roughness which contributes to the mechanical stability of the component.
  • the horizontal cross-section preferably corresponds to a cross-section that is substantially perpendicular to the vertical direction along which the continuous separation of the substrate to form the zones is carried out.
  • a continuous separation is preferably carried out substantially vertically, but the separation line along which the separation is carried out is preferably non-rectilinear in a horizontal cross-section of the substrate.
  • the separation line preferably denotes a horizontal line along which the cut and thus the division of the substrate to form the zones is carried out.
  • the separation line can preferably be curved, wavy, meandering and/or angular, for example zigzag-shaped, rectangular and/or square.
  • the facing surfaces of the zones have a roughness, since the facing surfaces receive protrusions and/or notches (in a horizontal plane perpendicular to the vertical direction) corresponding to the separation line. Therefore, the facing surfaces of the zones are uneven, whereby the unevenness can preferably be characterized by a roughness (synonymously also roughness).
  • the preferred method advantageously allows the roughness of the facing surfaces of the zones to be adjusted. This can be determined, for example, by the design and/or dimensioning of the parting line along which the separation is carried out in the vertical direction in order to provide the zones from the substrate. Another advantage here is that the roughness of the facing surfaces of the zones supports mechanical stability between adjacent zones.
  • the mechanical connection between the facing surfaces of adjacent zones is made possible by a positive fit, which results from the non-linear separation of the substrate.
  • the mechanical connection via the roughness or a positive fit advantageously ensures a stable and strong connection between the adjacent zones.
  • Another advantage here is that a long-lasting connection between the adjacent zones can be ensured even under loads, for example of a thermal and/or mechanical nature.
  • the method is characterized in that adjacent zones in a horizontal cross-section comprise corrugations adapted to one another.
  • a corrugation preferably refers to an unevenness (e.g., a protrusion or indentation) of a surface of a zone facing an adjacent zone, wherein the unevenness preferably exists relative to a general surface profile of the surface.
  • the corrugation can preferably represent a protrusion that is present along a substantially planar surface of the zone.
  • multiple corrugations are present on facing surfaces of the zones.
  • a corrugation can preferably also be an indentation along a substantially planar surface of the zone.
  • the corrugations are preferably shape-matched. This preferably means that the geometry of the facing surfaces of the corrugations is such that the corrugations of mutually facing surfaces of the zones interlock.
  • shape-matched corrugations can refer to mutually congruent corrugations.
  • the interlocking of the corrugations preferably results from the shape of the corrugations, which preferably establishes a positive connection perpendicular to a connecting surface of the adjacent zones.
  • the mutually adapted corrugations comprise tongues and corresponding grooves, which establish a positive connection perpendicular to a connecting surface of the adjacent zones.
  • a tongue-and-groove connection is therefore provided by the corrugations of the adjacent zones.
  • a tongue-and-groove connection preferably refers to a plug-in connection in which a tongue is inserted into a groove to create a mechanical connection between the adjacent zones.
  • a tongue-and-groove connection is preferably present immediately after a (non-linear) separation of the substrate into different zones.
  • the tongue-and-groove connection blocks a possible direction of movement that is substantially perpendicular to a connecting surface of the zones.
  • a connecting surface preferably refers to the area spanned between the facing surfaces of adjacent zones and preferably corresponds to a projection of the empty area along its horizontal cross-section.
  • the connecting surface therefore preferably has the length of the dividing line and a height corresponding to the height of the substrate (vertical extension from the back to the front).
  • Tongues and corresponding grooves which establish a positive connection perpendicular to a connecting surface of the adjacent zones, can be formed in different ways.
  • a tongue preferably a protrusion from one of the mutually facing surfaces of the zones
  • the tongue can have a triangular or free-form shape in a horizontal cross-section, which widens or opens towards the adjacent zone.
  • the tongue can also be designed to be wider in one area than at its base, so that this area interlocks in a correspondingly complementarily shaped groove.
  • the shape-adapted corrugations preferably achieve an interlocking or wedging of the adjacent zones, thus achieving sufficient mechanical stability and preventing any displacement of the zones even under mechanical stress on the component.
  • a puzzle-like interlocking can also be advantageously achieved by appropriately designing the corrugations, which simultaneously allows a positive fit perpendicular to the connecting surface.
  • the geometric design of the substrate separation alone creates a component with extremely long-term stability in terms of functionality.
  • the shape of the separation line or the provision of a tongue-and-groove connection between adjacent zones can achieve a very stable form fit both perpendicular to the connecting surface of adjacent zones and along the separation line of adjacent zones.
  • the shape of the zones can thus particularly effectively withstand any stresses on the component in a horizontal plane.
  • the introduction of the insulating material as explained, can preferably help to achieve sufficient mechanical stability.
  • the substrate is monolithic.
  • a monolithic substrate preferably refers to a substrate consisting of a single, continuous piece of material.
  • the entire structure of the substrate is formed as a single, uninterrupted unit, without the need to connect different layers or components to achieve functionality.
  • the use of a monolithic substrate achieves a particularly pronounced degree of compactness. This expands and simplifies the integration options of the component produced by the method.
  • the method is characterized in that the substrate comprises a semiconductor, preferably a doped semiconductor, and/or a conductor.
  • the semiconductor is silicon, germanium and/or a III-V compound semiconductor.
  • the 111 V semiconductor is selected from a group comprising gallium nitride, aluminum nitride, indium nitride, boron nitride, scandium nitride, gallium phosphide, aluminum phosphide, indium phosphide, indium gallium phosphide, boron phosphide, gallium arsenide, aluminum arsenide, indium arsenide, boron arsenide, gallium antimonide, aluminum antimonide and/or indium antimonide.
  • the preferred semiconductor materials mentioned preferably have sufficient electrical conductivity to form a conductive via region or to be converted into one through appropriate processing steps.
  • the preferred materials mentioned are also advantageously inexpensive and easy to acquire. Furthermore, they can be advantageously processed using standardized processes from semiconductor and/or microsystems technology to make mechanical, electrical, and/or optical adjustments so that the formed zones exhibit desired properties.
  • the method is characterized in that the substrate has an electrical conductivity of at least 10' 6 S/cm (Siemens per centimeter), preferably of at least 10' 4 S/cm, particularly preferably of at least 10' 2 S/cm or more.
  • Electrical conductivity preferably refers to a property that describes how well electrical current can be conducted through the substrate and thus also through the zones that function as vias. In particular, conductivity represents the suitability for signal transmission via an electrical current through the via.
  • the substrate comprises a material having a resistivity of less than about 1 0 * cm, less than about 10 -1 0 * cm, less than about 10' 2 0 * cm, less than about 10' 3 0 * cm, less than about 10' 4 0 * cm, less than about 10' 5 0 * cm, less than about 10' 6 0 * cm, or less.
  • the aforementioned preferred electrical conductivities can be adjusted by appropriately selecting the materials for the substrate, with a wide range of materials available to those skilled in the art in semiconductor and/or microsystem technology.
  • the electrical conductivity of the substrate or one or more zones can also be further influenced by doping, for example, to specifically provide one or more zones with increased conductivity.
  • the method is characterized in that at least one zone has a region which has an increased conductivity compared to the substrate.
  • the region with increased conductivity is formed by filling a previously removed substrate region with a conductive material, preferably metal. It may be preferable for a substrate region to be first removed and then filled with a conductive material, preferably a metal. The region therefore preferably has, in particular, increased conductivity compared to the surrounding substrate (material).
  • the removal of the substrate region is preferably carried out using a preferred etching process.
  • the filling with a conductive material can preferably be carried out using a coating process.
  • the conductive material which is filled into the removed substrate region is selected from a group comprising copper, aluminum, iron, zinc, tin, tungsten, gold, their compounds and/or alloys.
  • an area within a zone with a higher conductivity than other areas of the zone can also be achieved by appropriate doping.
  • the method is characterized in that the zones have a horizontal distance from one another of 1 - 30 pm, preferably of 1 - 20 pm, particularly preferably of 2 - 10 pm and/or the zones have a vertical height of 10 - 400 pm, preferably of 10 - 100 pm, particularly preferably of 20 - 50 pm.
  • the horizontal distance preferably refers to the distance between two opposite sides of adjacent zones.
  • the horizontal distance preferably corresponds to a horizontal cross-sectional dimension of the empty area, i.e., preferably the dimension of the empty area perpendicular to the connecting surface of adjacent zones.
  • the aforementioned preferred horizontal spacings are advantageous from a process engineering perspective in that they allow the empty space to be at least partially filled with an insulating material particularly easily using the reliable coating methods known in the prior art.
  • conformal deposition of the insulating material is advantageously possible, thus achieving mechanical stability between the zones while simultaneously maintaining electrical insulation between the zones.
  • the aforementioned preferred horizontal spacings ensure a particularly hermetic seal of the empty space.
  • the vertical height of the zones preferably corresponds to the dimensioning of a zone from a rear side to the front side.
  • the vertical height of the zones that function as via-connection regions essentially corresponds to the height of the substrate that is provided at the beginning of the process.
  • the vertical height of the zones specifies, in particular, a path for the current or for a signal that is transmitted via the zone and thus via the via-connection region.
  • the aforementioned preferred vertical heights are advantageous in that corresponding via-connection regions can be used for a wide variety of applications.
  • the method is characterized in that the empty area is widened at least in sections along a horizontal direction, preferably by etching adjacent zones in a horizontal cross section.
  • the empty region be configured such that, along a vertical height, it has a greater widening in one section than other sections of the empty region.
  • the greater widening preferably extends along the directions that run towards the surfaces of the via region that are located opposite one another.
  • the widening of the empty region can thus be oriented substantially perpendicularly along the vertical height.
  • the widening of the empty region can preferably be present centrally along the vertical height.
  • Narrower sections of the empty region i.e., sections that are tapered compared to a preferred widening, can preferably form sections of the empty region that are directed towards the front and/or back of the substrate.
  • the empty region preferably comprises a tapered section, a widened section, and a tapered section.
  • a preferred widened section of the void area refers to a section created by etching adjacent zones along a horizontal direction.
  • a preferred tapered section refers to a section that is not affected or only insignificantly affected by the etching of the adjacent zones.
  • the widened section preferably comprises larger lateral dimensions than the tapered section, i.e., preferably larger dimensions in the horizontal direction.
  • the empty area in the region of the widened section is additionally widened laterally by at least 2 pm, preferably by at least 5 pm or even by at least 10 pm compared to the width of a tapered section, wherein it is preferred that the lateral widening is less than 20 pm, preferably less than 10 pm.
  • the tapered section has a depth or height of less than 5 pm and a width of less than 2 pm and/or the widened section has a width of at least 10 pm, preferably at least 20 pm.
  • the tapered section is characterized by a depth of at least 0.5 pm. preferably, at least 1 pm and a width of at least 0.1 pm, preferably at least 0.5 pm.
  • etching of adjacent zones in a horizontal cross-section results in a lateral widening of at least a portion (the widened portion) of the empty area.
  • the widening to a preferably widened section of the void area along the vertical height can preferably be carried out using an etching process.
  • the etching process can be carried out, for example, by reactive ion etching and/or reactive ion deep etching (Bosch process).
  • the lateral widening increases the width of the empty space. This also increases the horizontal distance between the zones at this vertical height. This advantageously reduces any parasitic capacitance that might arise between zones and impair signal transmission.
  • the tapered sections toward the front or back of the substrate i.e., those sections of the empty space that have not been widened, advantageously achieve a particularly stable mechanical connection and/or hermetic sealing. In particular, it is advantageously possible to reduce any parasitic capacitance that might arise in regions where a preferentially widened section of the empty space is present along the vertical height.
  • the parasitic capacitances that can arise can be described by a plate capacitor comprising two plates, wherein the two plates preferably correspond to the zones or via regions.
  • the average person skilled in the art knows that the capacitance of a plate capacitor is inversely proportional to the distance between the two plates. Accordingly, increasing the distance reduces the capacitance. By horizontally widening the empty space between adjacent zones, the distance is increased and parasitic capacitances are reduced.
  • the method is characterized in that the insulating material comprises a material selected from a group comprising silicon nitride, tetraethylorthosilicate, silicon oxynitride and/or silicon dioxide.
  • These materials are suitable for enabling high electrical insulation between the zones. Furthermore, their use can create a robust mechanical connection between the zones. Especially with horizontal distances, which are at least partially between adjacent zones, less than 5 ⁇ m, preferably less than 2 ⁇ m, the aforementioned materials achieve an extremely stable connection, ensuring a long product lifespan.
  • the preferred materials mentioned are also particularly easy and cost-effective to process and can be precisely introduced into the empty area using standardized technologies for coating.
  • the at least partial filling of the empty area is preferably carried out using coating methods known in the prior art.
  • the coating can be carried out using a coating process within a coating system that is preferably designed to carry out a coating process selected from a group comprising physical vapor deposition, chemical vapor deposition, atomic layer deposition, doctor blade coating, powder coating, and/or injection molding.
  • the method is characterized in that the insulating material comprises a low-k dielectric, which is preferably selected from a group comprising porous organic materials, porous carbon-doped silicon oxide, silica gel, silicatic aerogels, mesoporous organosilicates, porous hydrogen silsesquioxane, mesoporous silicate glasses, phosphor particles and/or aluminum oxide particles.
  • a low-k dielectric is preferably selected from a group comprising porous organic materials, porous carbon-doped silicon oxide, silica gel, silicatic aerogels, mesoporous organosilicates, porous hydrogen silsesquioxane, mesoporous silicate glasses, phosphor particles and/or aluminum oxide particles.
  • a low-k dielectric is a material that has a substantially lower relative permittivity than silicon dioxide (SiO2), i.e. E r ⁇ 3.9.
  • low-k dielectrics has proven particularly advantageous, as it significantly reduces parasitic capacitances.
  • One way to reduce the relative permittivity or keep it as low as possible is to lower the polarizability by using materials with low-polarity bonds.
  • Common examples of such bonds are carbon-carbon (C-C), carbon-hydrogen (C-H), silicon-fluorine (Si-F), and/or silicon-carbon (Si-C) bonds.
  • C-C carbon-carbon
  • C-H carbon-hydrogen
  • Si-F silicon-fluorine
  • Si-C silicon-carbon
  • Another way to reduce the relative permittivity and thus the parasitic capacitances is to reduce the material density, or in particular the dipole density, by creating free volume.
  • This can preferably be achieved by only partially filling the empty space with the insulating material. This can be achieved, for example, by lining the empty space with an insulating material, preferably a low-k dielectric. Complete filling of the empty space is not necessary, but can also be achieved in preferred embodiments.
  • porous dielectrics especially porous low-k dielectrics
  • Partial filling can also be almost complete filling with porous low-k dielectrics.
  • k-dielectrics where a free volume (not completely filled with a material) remains due to the existing pores.
  • the component manufactured using this process is particularly well suited for the operation of devices with low impedance, where higher parasitic capacitances (parasitic couplings) may also be unproblematic.
  • a capacitive coupling or a capacitance as parasitic capacitance that would develop in this case can be calculated in a first approximation according to the above calculation example with a substrate in which silicon dioxide is used as the insulating material, as follows:
  • the method is characterized in that the substrate is separated into 2, 3, 4, 5, 6, 7, 8, 9, 10 or more zones.
  • the advantage here is that a large number of zones can be formed from a single substrate. This opens up a wide range of applications, where multiple zones can be used for vias to ensure optimal power and thus signal transmission.
  • a large number of electrical contacting options are offered, which is advantageous for the electrical integration of the component. For example, it is possible to mount a Wheatstone bridge circuit on four zones, with each zone serving as a via providing an electrical connection to one branch of the Wheatstone bridge circuit.
  • the method is characterized in that the separation of the substrate is carried out by an etching process, wherein the etching process is preferably selected from a wet-chemical etching process and/or dry etching process, preferably by physical and/or chemical dry etching processes, particularly preferably by reactive ion etching and/or reactive ion deep etching (DRIE, Bosch process).
  • the etching process is preferably selected from a wet-chemical etching process and/or dry etching process, preferably by physical and/or chemical dry etching processes, particularly preferably by reactive ion etching and/or reactive ion deep etching (DRIE, Bosch process).
  • An etching process preferably refers to the removal of material from a surface.
  • the term etching process can also be used synonymously.
  • the removal can take the form of depressions, which, in the context of the invention, leave behind the empty space on the substrate.
  • dry etching refers to a group of abrasive microstructural processes that are not based on wet chemical reactions (such as wet chemical etching or chemical-mechanical polishing). Material removal occurs either by accelerated particles or with the aid of plasma-activated gases. Depending on the process, both chemical and physical effects are utilized. In wet chemical etching, an etch-resistant mask is transferred to the substrate through a chemical removal process.
  • etching processes are known to those skilled in the art.
  • advantageous methods can be selected to ensure efficient implementation of the empty region on the substrate and thus the formation of the zones.
  • the method is characterized in that the at least partial filling of the empty area with the insulating material is carried out by a coating method which is preferably selected from a group comprising physical vapor deposition, chemical vapor deposition, atomic layer deposition, doctor blade coating, powder coating and/or injection molding.
  • a coating method which is preferably selected from a group comprising physical vapor deposition, chemical vapor deposition, atomic layer deposition, doctor blade coating, powder coating and/or injection molding.
  • the aforementioned preferred methods are advantageous in that their use allows for rapid and reliable achievement of sufficient electrical insulation between individual zones. Furthermore, the aforementioned preferred methods are suitable for both partially filling the empty space and completely filling the empty space for electrical insulation.
  • the method is characterized in that dicing is carried out on the two or more zones, wherein the dicing preferably comprises one or more steps selected from a group comprising mechanical sawing, laser cutting and/or breaking.
  • Dicing refers to a process step in which a subsection of the zones is separated.
  • Dicing for separating a subsection of a zone can extend along a vertical direction in order to separate an area and adjust the horizontal cross-sectional area of the zone.
  • Dicing can also be carried out in a horizontal direction, for example, to adjust the height of the zones.
  • Dicing can therefore advantageously be used to cut or dimension the zone(s) with a view to further applications. For example, installation in further applications and/or systems (e.g. sensor systems) can be facilitated by making the zones more compact and/or by simplifying the mechanical integration of the component.
  • connection contact is selected from a group comprising a connection pad, conductor tracks, bond wires, solder connections, an electrically conductive adhesive and/or bumps.
  • a connection pad preferably comprises an electrically conductive material that is applied to a spatially restricted section of the sensor chip to enable electrical contact.
  • an insulating material can be applied first, delimiting the section to be contacted in such a way that a free area remains. The free area can then be filled with the electrically conductive material.
  • Conductor tracks also called conductive paths or conductive lines
  • Conductor tracks preferably refer to electrically conductive connections with a two-dimensional layout, i.e., along a plane, which can also be referred to as a conductor track or metallization plane.
  • the connection between individual conductor tracks can preferably be provided by vias. To prevent short circuits or high leakage currents, high electrical insulation between conductor tracks is preferred.
  • Conductor tracks preferably have a greater length (along the current flow direction) than width (or diameter or cross-sectional dimension), for example by a factor of 2, 5, 10 or more, and can therefore also be referred to as track- or strip-shaped.
  • Bond wires refer to an electrical connection option that is particularly used when components have previously been bonded. Bond wires are characterized by their particularly thin nature. This enables easy contacting of component connection pins.
  • a bond wire can preferably have a diameter of approximately 15-500 ⁇ m, preferably 15-100 ⁇ m, particularly preferably 15-50 ⁇ m or 100-500 ⁇ m.
  • a bond wire can comprise a material selected from a group comprising gold, aluminum, copper, their compounds, and/or alloys.
  • a solder connection preferably refers to an electrical connection using a solderable material.
  • the solderable material preferably refers to a material that melts after a certain temperature is applied, so that the melting process causes the material to spread and thus allows a specific area to be covered and/or filled with the material.
  • a preferred solder material can be selected from a group comprising silver, copper, tin, zinc, and their compounds and/or alloys.
  • An electrically conductive adhesive is preferably characterized in that solidification and thus a solid electrical connection can be provided without the application of pressure and/or heat. Instead, solidification of the electrically conductive adhesive occurs after a specific time interval.
  • An electrically conductive adhesive preferably comprises an adhesive and an electrically conductive filler.
  • the adhesive can preferably be selected from a group comprising epoxy (resin), silicone, acrylic, and/or bismaleimide.
  • the electrically conductive filler can preferably be selected from a group comprising gold, nickel, palladium, platinum, and/or silver.
  • a bump preferably refers to a substantially hump-shaped connecting element.
  • the connecting element is characterized in particular by its hump-shaped design.
  • a plurality of bumps is preferably used.
  • Bumps can preferably be applied to an underside of the sensor chip, for example, to enable electrical contact with at least one section of a base plate. Bumps can preferably be applied using thin-film technology, electroplating, or stencil printing.
  • connection has proven advantageous in that they are reliable and robust and can be provided easily by a person skilled in the art using known means of the prior art.
  • the method is characterized in that the zones are connected to a circuit carrier, preferably a printed circuit board.
  • a circuit carrier preferably refers to a component comprising an electrically insulating material on which electrically conductive connections (conductor tracks) and/or electronic components or assemblies are present.
  • a circuit carrier therefore preferably refers to a carrier for electronic components or electrically conductive connections, which serves both for mechanical fastening and for electrical connection. Since electronic components are preferably present on or in the circuit carrier, electrical connections are particularly present on or in the circuit carrier, which are mediated, for example, by wire bonds, conductor tracks and/or conductor track strips.
  • the circuit carrier therefore functions both as a mechanical carrier and for an electrical connection for implementing electrical functions.
  • the electrical connections of the circuit carrier serve, in particular, for the electrical contacting of components.
  • the insulating material of the circuit carrier preferably predetermines a basic shape of the circuit carrier, in particular to predetermine mechanical contact with the sensor chip.
  • the circuit carrier can preferably have a substantially flat or planar profile. It can also be preferred for the circuit carrier to have a curved configuration.
  • a printed circuit board is preferably used as the circuit carrier.
  • a printed circuit board preferably refers to the flat type of circuit carrier known in the art, which includes electrical connections and provides mechanical support for surface-mounted and/or socketed components.
  • a printed circuit board preferably comprises fiberglass, an epoxy, and/or another composite material as the insulating material.
  • a printed circuit board is characterized by its high stability, which is advantageous for a wide variety of applications of the component.
  • the filler material is preferably selected from a group comprising an epoxy resin, polyester resin, phenolic resin, and/or aminoplasts. These preferred filler materials have proven advantageous for a strong bond and hermetic encapsulation of the intermediate regions.
  • the invention relates to a component preferably producible by a method according to the above-described, comprising a via region which extends along a vertical direction from a rear side to a front side of the component, characterized in that the component has a substrate comprising an electrically conductive material, wherein the substrate is divided into two or more galvanically separated zones and wherein an electrical connection contact is present on the front side and the rear side on at least one zone of the two or more zones, so that the at least one zone functions as a via region.
  • the component utilizes the conductivity of the substrate itself, in which the vias are formed.
  • the substrate is divided into galvanically separated zones, which serve as a power or signal line along a vertical direction and can thus function as a via.
  • the galvanically separated zones are directly and clearly identifiable on the component. A person of ordinary skill in the art can recognize that they were created by severing the substrate.
  • Another advantage is that by separating the substrate into galvanically separated zones, through-hole plating areas can be achieved while simultaneously achieving a very flat or level geometry of the component's surface.
  • the flat surface of a substrate is advantageously not compromised by its separation into galvanically separated zones.
  • the zones can be contacted directly without unnecessarily disrupting the flat surface of the substrate.
  • planar design of the component can lead to a number of advantages, particularly from an application perspective. Firstly, it facilitates the integration of the component into more complex structures. If the component is a sensor, the planar surface can also ensure reduced disturbance to the environment, which is advantageous for flow sensors or aeroacoustic sensors, for example.
  • the through-hole contact areas of the component allow the desired adjustment or setting of the resistance and/or inductance.
  • a particular advantage is that a particularly low electrical resistance can be achieved for the through-hole area.
  • the horizontal cross-section of the via region is determined in particular by the (cross-sectional) area of the respective zones.
  • a further advantage of the method according to the invention is that by separating the substrate into galvanically separated zones, through-hole plating areas can be created, enabling signal conduction with low inductance.
  • the inductance also preferably decreases with an increase in the cross-section, so that only reduced interference occurs when conducting variable currents or signals.
  • the separation of the substrate into galvanically separated zones can be determined on the component itself. By dividing the substrate, the number of galvanically separated zones and thus the number of vias on the component can be adjusted accordingly.
  • the adjacent zones comprise corrugations that are shaped to match one another in a horizontal cross-section.
  • the corrugations that are shaped to match one another comprise tongues and corresponding grooves, which establish a positive connection perpendicular to a connecting surface of the adjacent zones.
  • the preferred, mutually conforming corrugations, as well as the tongues and grooves encompassed by them, can be identified on the component. These can preferably be identified on a front and/or back of the component, since an interlocking structure of the adjacent zones can also be identified from a front and/or back of the component. Thus, a structure can be identified on a surface of the component, similar to a puzzle.
  • the component is characterized in that the component has an electronic circuit and/or a MEMS component that is electrically connected to the via region.
  • Preferred electronic circuits include, without limitation, an integrated circuit (IC), an application-specific integrated circuit (ASIC), a programmable logic device (PLD), a field-programmable gate array (FPGA), a microprocessor, a microcomputer, a programmable logic controller, and/or another electronic, preferably programmable, circuit.
  • IC integrated circuit
  • ASIC application-specific integrated circuit
  • PLD programmable logic device
  • FPGA field-programmable gate array
  • microprocessor a microcomputer
  • programmable logic controller programmable logic controller
  • the electronic circuit may preferably be configured to receive and/or emit an electrical current or a signal passing through the via region
  • the electronic circuit can thus be present as evaluation, readout, and/or control electronics. If an evaluation is performed, the electronic circuit can also be referred to as a computing unit.
  • the term "computing unit” preferably refers to any device or unit that can be configured to perform computing operations.
  • the computing unit is preferably, for example, a processor, a processor chip, a microprocessor, and/or a microcontroller.
  • the computing unit may also preferably be a programmable circuit board.
  • the computing unit may also preferably comprise a computer-usable or computer-readable medium, such as a hard disk, random access memory (RAM), read-only memory (ROM), flash memory, etc.
  • Method steps for reading, controlling, and/or evaluating the signal to be transmitted through the via region are preferably performed by the electronic circuit or processing unit.
  • the phrase "configured to do so” preferably means that computer code and/or software is installed on the electronic circuit or processing unit to perform one or more method steps for corresponding reading, controlling, and/or evaluating.
  • the method steps can, for example, relate to controlling or evaluating measurement signals from a MEMS sensor, as explained in more detail here.
  • a MEMS component preferably refers to a component or part based on MEMS technology.
  • MEMS stands for microelectromechanical system (abbreviated to "micromechanical system” in the text), i.e. a microsystem whereby a compact design (in the micrometer range) with simultaneous excellent functionality and ever-lower manufacturing costs is achieved.
  • a MEMS component can, for example, be a MEMS sensor or a MEMS actuator.
  • Many MEMS components are known in the prior art.
  • the component according to the invention can be used to operate a wide variety of MEMS components by connecting it to the via region.
  • a MEMS component preferably comprises a miniaturized device, an assembly and/or a component whose components have smallest dimensions in the pm range and interact as a system.
  • the MEMS component is a MEMS sensor, wherein the MEMS sensor is preferably selected from a group comprising an acceleration sensor, a gyroscope, a pressure sensor and/or a flow sensor.
  • An acceleration sensor typically measures the displacement of a test mass using a position measuring circuit. For further digital processing, the measured signal is converted into digital information, for example, using an A/D converter. Since the acceleration of the test mass is directly proportional to the force acting on the body, the acceleration can be measured indirectly via a force acting on one of the axes of the acceleration sensor. Acceleration sensors preferably comprise bores, cavities, springs, and channels, which are manufactured using micromachining processes known in the art. The acceleration forces can be determined based on the Displacement of the test mass in relation to fixed electrodes can be measured, whereby preferably capacitance changes can be recorded
  • Gyroscopes are components that measure or maintain rotational motion. They are compact, low-cost sensors that measure angular velocity. The units of angular velocity are measured in degrees per second (°/s) or revolutions per second (rps). Gyroscopes can be used to determine orientation and are found in most autonomous navigation systems. During rotation, a small proof mass is displaced as the angular velocity changes. This movement is converted into very weak electrical signals that can be amplified and read by a microcontroller, for example.
  • the operating principle of many well-known gyroscopes is, analogous to accelerometers, preferably capacitive in nature.
  • Pressure sensors for example, comprise capacitors mounted on a wafer or a microchip, which can be formed, for example, via the sensor structure. When pressure is applied, the spacing between the sensor structures and thus the capacitances change. This operating principle is also capacitive. However, pressure sensors can also be based on other physical principles. These include inductive pressure sensors, piezoresistive pressure sensors, or pressure sensors based on the Hall effect.
  • Flow sensors are used to measure the flow of fluids.
  • Flow sensors can be based on thermal and non-thermal principles.
  • the most common non-thermal flow sensors in the state of the art are so-called drag force sensors, pressure drop sensors, and Coriolis sensors.
  • the thermal principle is based on the convective heat transfer from an electrically heated resistor to the flowing fluid, which leads to the cooling of the heater depending on the flow rate and can thus be measured electrically. Since the convective heat transfer is directly proportional to the mass flow, these sensors are mass flow sensors.
  • the component is characterized in that the component has a membrane which extends over a cavity of the substrate and an electronic circuit and/or a MEMS component is present on the membrane.
  • a cavity preferably refers to a recess in the substrate.
  • the presence of one or more cavities in the substrate can provide a suitable hollow space over which the MEMS component and/or the electronic circuit can be positioned.
  • the membrane refers to a preferred component of the component, which is designed to be flat and is preferably applied to the front side of the monolithic substrate and at least partially covers the flow channel.
  • the flat design of the membrane preferably means that dimensions such as a length and/or width are many times higher than an orthogonal height or thickness of the membrane. Thus, the length and/or The width can be greater than the thickness by a factor of 1.5, 2.5, 10, 100, 1,000, 10,000, or more.
  • the thickness of the membrane is preferably between approximately 0.1 and 20 pm, more preferably between approximately 0.2 and 10 pm.
  • Terms such as substantially, approximately, about, approx., etc. preferably describe a tolerance range of less than ⁇ 40%, preferably less than ⁇ 20%, particularly preferably less than ⁇ 10%, even more preferably less than ⁇ 5%, and especially less than ⁇ 1%, and always include the exact value.
  • preferably describes at least 5%, particularly preferably at least 10%, and especially at least 20%, in some cases at least 40%.
  • the membrane advantageously enables coverage above or over a cavity.
  • the attachment or use of a cavity is advantageous for a variety of applications.
  • a flow sensor can be provided that is characterized by a particularly flat design due to a flat topology.
  • a flow through the cavity can be used, for example, to take a measurement.
  • the substrate can act as a support structure.
  • the via-hole regions which have resulted from the division of the substrate into galvanically separated zones, advantageously enable a simple electrical connection to the flow sensor, which can preferably be attached to the membrane.
  • the advantageous electrical connection is also advantageously achieved with any electronic circuit on the substrate. It is advantageously not necessary to incorporate complex circuitry and/or vias into the substrate, since the via-hole regions themselves provide a contacting option.
  • the flat design of the substrate also enables easy integration into a printed circuit board without the need for great effort (see Fig. 4F).
  • a filler material to connect the component to a circuit board. This advantageously achieves greater stability and long-lasting vibration resistance.
  • FIG. 1 A-B Schematic representation of a preferred embodiment of the component according to the invention, in which a substrate was divided into galvanically separated zones.
  • FIG. 2A-B Schematic representation of a further preferred embodiment of the component according to the invention, wherein the galvanically separated zones serve as vias for a Wheaton bridge.
  • Fig. 3A-F Schematic representation of preferred process steps for producing a preferred embodiment of the component, wherein the galvanically separated zones serve as vias for a Wheaton bridge.
  • Fig. 4A-F Schematic representation of further preferred method steps for producing a preferred embodiment of the component in which an electronic circuit and/or a MEMS component are positioned on a membrane.
  • the component 1 utilizes the conductivity of the substrate 5 itself, in which the via-connection regions 11 are formed.
  • the substrate 5 is divided into galvanically separated zones 7, which serve to conduct current or signal along a vertical direction and can thus function as a via-connection region 11.
  • the galvanically separated zones 7 can be directly and clearly identified on the component 1. A person of ordinary skill in the art will recognize that they were created by a continuous separation of the substrate 5.
  • the zones can be contacted directly without unnecessarily disrupting the flat surface of the substrate 5.
  • planar design of component 1 can lead to a number of advantages, particularly in terms of applications. Firstly, it facilitates the integration of the component into more complex structures. If component 1 is a sensor, the planar surface can also ensure reduced disturbance to the environment, which is advantageous for flow sensors or aeroacoustic sensors, for example.
  • the through-hole contact areas 11 of the component 1 allow a desired setting or determination of the resistance and/or inductance.
  • the resistance is proportional to the vertical height and inversely proportional to the horizontal cross-section of the through-plating region 11.
  • the horizontal cross-section of the through-plating region 11 is determined in particular by the (cross-sectional) area of the respective zones 7.
  • a further advantage is that by separating the substrate 5 into galvanically separated zones 7, through-plating regions 11 can be provided, which enable a signal line with low inductance.
  • the inductance preferably also decreases with an increase in the cross-section of the through-plating region 11.
  • the separation of the substrate 5 into galvanically separated zones 7 can be determined on the component 1 itself. By dividing the substrate 5, the number of galvanically separated zones 7 and thus also the number of through-plating areas 11 on the component 1 can be adjusted accordingly.
  • Adjacent zones 7 of the component 1 comprise mutually shaped corrugations 17 in a horizontal cross-section.
  • the mutually shaped corrugations 17 comprise tongues and corresponding grooves, which establish a positive connection perpendicular to a connecting surface of the adjacent zones 7.
  • a corrugation 17 preferably denotes an unevenness (e.g., protrusion or indentation) of a surface of a zone 7 facing an adjacent zone 7, wherein the unevenness is present relative to a basic surface profile of the surface.
  • the corrugation 17 can preferably represent a protrusion that is present along a substantially planar surface of the zone.
  • a corrugation 17 can preferably also be a notch along a substantially planar surface of the zone 7.
  • the corrugations 17 are, in particular, shape-matched. This preferably means that the geometry of the facing surfaces of the corrugations 17 is such that the corrugations 17 of mutually facing surfaces of the zones 7 interlock.
  • shape-matched corrugations 17 can relate to mutually congruent corrugations 7. The interlocking of the corrugations 17 results from the shape of the corrugations 17, which establishes a positive connection perpendicular to a connecting surface of the adjacent zones 7.
  • the mutually adapted corrugations 17 comprise tongues and corresponding grooves, which establish a positive connection perpendicular to a connecting surface of the adjacent zones 7.
  • a tongue-and-groove connection is provided by the corrugations 17 of the adjacent zones 7.
  • a tongue-and-groove connection preferably refers to a plug-in connection in which a tongue is inserted into a groove. to create a mechanical connection between the adjacent zones 7.
  • a tongue and groove connection can be present immediately after a (non-linear) separation of the substrate 5 into different zones.
  • the tongue and groove connection blocks a possible direction of movement that is substantially perpendicular to a connecting surface of the zones 7.
  • the connecting surface preferably means the surface spanned between the mutually facing surfaces of adjacent zones 7 and preferably corresponds to a projection of the empty space along its horizontal cross-section.
  • the connecting surface therefore preferably has the length of the dividing line and a height corresponding to the height of the substrate (vertical extension from the rear side R to the front side V).
  • the empty regions 9 resulting from the separation of the substrate 5 into zones are filled by at least partially filling an empty region 9 with an insulating material 13.
  • an insulating material 13 By at least partially filling the insulating material 13, in particular, a mechanical hold is achieved between the zones 7, while at the same time galvanic separation is still ensured. While the zones 7 are galvanically separated from one another after the immediate, continuous separation (for example, by an empty region 9 filled with (ambient) air), the integrity of the multi-part substrate 5, comprising separate zones 7, might no longer be ensured under certain circumstances.
  • the zones 7 are therefore also mechanically connected to one another, in particular by the insulating material 13, but remain electrically insulated from one another.
  • the insulating material 13 preferably refers to an electrically insulating material.
  • Fig. 2 schematically shows a preferred embodiment of a component 1 according to the invention, wherein the galvanically separated zones serve as vias for a Wheaton bridge.
  • Fig. 2A shows a plan view of the component 1, starting from a front side V.
  • Fig. 2B shows a three-dimensional representation of the component 1.
  • the component 1 comprises a plurality of via regions 11 extending along a vertical direction from a rear side R to a front side V of the component 1.
  • the substrate of the component 1 comprises an electrically conductive material or semiconducting material.
  • the substrate is divided into two or more galvanically separated zones 7.
  • An electrical connection contact can be present on the front side V and the rear side R of the zones 7, so that the zones 7 function as via regions 11.
  • a large number of zones 7 can be formed from a single substrate s.
  • This offers a wide variety of applications in which multiple zones can be used for vias 11 to ensure optimal current and thus signal transmission.
  • a large number of electrical contacting options are offered, which is particularly advantageous for the electrical integration of the component 1.
  • a Wheatstone bridge circuit it is advantageously possible, as shown in Fig. 2, for a Wheatstone bridge circuit to be applied to four zones 7, with each zone 7 serving as a via 11 and providing an electrical connection to a branch of the Wheatstone bridge circuit.
  • the component 1 has a membrane 19 which extends over a cavity of the substrate 5, and the Wheatstone bridge circuit is present as an electronic circuit on the membrane 19.
  • Figs. 3A-F show preferred method steps for producing a preferred embodiment of a component 1 (preferably the embodiment according to Fig. 2), wherein the galvanically separated zones serve as vias for a Wheaton bridge.
  • Fig. 3A shows a substrate 5 comprising an electrically conductive or semiconducting material.
  • a membrane 19 is applied to the substrate 5.
  • An electronic circuit 21 is present on the membrane 19.
  • a connection pad 23 is applied.
  • the substrate 5 is divided into galvanically separated zones 7. The division of the substrate 5 into the zones 7 is achieved by a continuous separation of the substrate 5 along the vertical direction. This creates an empty space 9 between the zones 7. The separation of the substrate 5 is carried out by an etching process.
  • the empty space 9 is filled with an insulating material 13.
  • the insulating material provides electrical insulation between the zones 7. Furthermore, the influence of any resulting parasitic capacitances can advantageously be reduced by the selection of the insulating material 13.
  • FIG. 3E another connection pad 23 is applied to the back of zones 7, so that zones 7 function as through-hole contact areas 11.
  • Fig. 3F shows dicing of the substrate 5. Dicing separates a portion of zones 7. This advantageously allows for optimizing the dimensioning of zone 7. This can also have a beneficial effect on the installation in other applications and/or systems (e.g., sensor systems), for example, by achieving greater compactness, which simplifies the mechanical integration of the component.
  • other applications and/or systems e.g., sensor systems
  • a particular advantage is that the method ensures efficient process control.
  • the method according to the invention eliminates the process step known from the prior art of filling a remote region of a substrate 5 with a conductive material to provide the via region. Instead, the method utilizes the conductivity of the substrate 5. Zones 7 are provided from the substrate 5 itself, which function as via regions 11, so that current can flow across them in a vertical direction. This advantageously enables rapid production of the component, since a step for filling an electrical material is not carried out. Consequently, the method is also suitable for mass applications and also saves costs, thus achieving considerable economic efficiency.
  • Fig. 4A-F schematically shows further preferred method steps for producing a preferred embodiment of a component 1 according to the invention, in which an electronic circuit and/or a MEMS component is positioned on a membrane.
  • Fig. 4A shows that a substrate 5 comprising an electrically conductive or semiconducting material is provided. A membrane 19 is applied to the substrate 5. An electronic circuit 21 is present on the membrane 19.
  • Fig. 4B shows that a cavity 20 is formed on the component 1, over which the membrane 19 extends.
  • Fig. 3B shows that the substrate 5 is divided into zones 7 by the formation of an empty area 9.
  • Fig. 4C shows that the empty area 9 is filled with the insulating material 13.
  • Fig. 3E shows dicing of the substrate so that the dimensioning of the component can be optimized.
  • zones 7 are connected to a printed circuit board 29. The electrical connection is established via the connection pad 23, a solder connection 25, and a feedthrough 27.
  • intermediate regions of the printed circuit board 29 are filled with a filler material 31. This advantageously ensures a more stable connection to the printed circuit board 29. Furthermore, it is advantageous that the risk of foreign material entering the intermediate regions, which could lead to a degradation of the component's performance, is reduced or eliminated.
  • the membrane 19 advantageously enables a cover above or over a cavity 20.
  • the attachment or use of a cavity 20 is advantageous for a variety of applications.
  • a flow sensor can be provided which is characterized by a particularly flat design due to a flat topology.
  • a flow through the cavity 20 can be used to take a measurement.
  • the substrate 5 can function as a support structure.
  • the via-connection regions 11, which have resulted from the division of the substrate 5 into galvanically separated zones 7, advantageously enable a simple electrical connection to the flow sensor, which can be attached to the membrane 19.
  • the advantageous electrical connection is also successful with any electronic circuit on the substrate 5. In this case, it is advantageously not necessary to incorporate complex circuits and/or vias into the substrate 5, since a contacting option is provided by the via-connection regions themselves.
  • the flat design of the substrate 5 further enables easy integration into a circuit board 29 without requiring significant effort (see Fig. 4F).
  • a filler material 31 to connect the component 1 to a circuit board 29. This advantageously achieves greater stability and long-lasting vibration resistance.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne un procédé utilisé pour produire un composant présentant une région de trou d'interconnexion s'étendant dans une direction verticale d'un côté arrière à un côté avant du composant. Tout d'abord, l'invention concerne un substrat comprenant un matériau électroconducteur ou semi-conducteur. Le substrat est subdivisé en au moins deux zones galvaniquement séparées, la subdivision étant formée par séparation continue du substrat dans la direction verticale et, après la séparation, une région vide étant présente entre les deux zones ou plus. La région vide est au moins partiellement remplie d'un matériau isolant. Un contact de borne électrique est disposée sur le côté avant et le côté arrière d'au moins une zone, de telle sorte que la ou les zones fonctionnent comme une région de trou d'interconnexion. L'invention concerne en outre un composant pouvant être produit par le procédé décrit.
PCT/EP2025/060062 2024-04-11 2025-04-11 Procédé utilisé pour produire des trous d'interconnexion électriques Pending WO2025215224A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP24169632.7 2024-04-11
EP24169632 2024-04-11

Publications (1)

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WO2025215224A1 true WO2025215224A1 (fr) 2025-10-16

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PCT/EP2025/060062 Pending WO2025215224A1 (fr) 2024-04-11 2025-04-11 Procédé utilisé pour produire des trous d'interconnexion électriques

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130147020A1 (en) 2010-05-31 2013-06-13 Julian Gonska Component Having a Via and Method for Manufacturing It
DE102011080774B4 (de) 2011-08-10 2015-02-19 Hahn-Schickard-Gesellschaft für angewandte Forschung e.V. Verfahren zum herstellen einer halbleiterstruktur und halbleiterstruktur
US9459224B1 (en) 2015-06-30 2016-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Gas sensor, integrated circuit device using the same, and manufacturing method thereof
WO2020081006A1 (fr) * 2018-10-16 2020-04-23 Agency For Science, Technology And Research Arrangement empilé et son procédé de formation

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130147020A1 (en) 2010-05-31 2013-06-13 Julian Gonska Component Having a Via and Method for Manufacturing It
DE102011080774B4 (de) 2011-08-10 2015-02-19 Hahn-Schickard-Gesellschaft für angewandte Forschung e.V. Verfahren zum herstellen einer halbleiterstruktur und halbleiterstruktur
US9459224B1 (en) 2015-06-30 2016-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Gas sensor, integrated circuit device using the same, and manufacturing method thereof
WO2020081006A1 (fr) * 2018-10-16 2020-04-23 Agency For Science, Technology And Research Arrangement empilé et son procédé de formation

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
SORDO, GUIDODANIEL NILSEN WRIGHTSIGURD T. MOE., THROUGH SILICON VIAS IN MEMS PACKAGING, A REVIEW, 2019
XUE, XINGJUN ET AL.: "Silicon diode uncooled FPA with three-dimensional integrated CMOS readout circuits", IEEE SENSORS JOURNAL, vol. 19, no. 2, 2018, pages 426 - 434, XP011694683, DOI: 10.1109/JSEN.2018.2878098

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