WO2025214599A1

WO2025214599A1 - Device for detection and/or stimulation and method for manufacturing the device

Info

Publication number: WO2025214599A1
Application number: PCT/EP2024/059769
Authority: WO
Inventors: Yiannos Manoli; Stephan Knappmann; Hermann Scheithauer; Daniel DE DORIGO
Original assignee: Hann-Schickard-Gesellschaft fuer Angewandte Forschung eV; Albert Ludwigs Universitaet Freiburg
Current assignee: Hann-Schickard-Gesellschaft fuer Angewandte Forschung eV; Albert Ludwigs Universitaet Freiburg
Priority date: 2024-04-11
Filing date: 2024-04-11
Publication date: 2025-10-16
Anticipated expiration: 2026-10-11

Abstract

An embodiment relates to a device comprising a substrate comprising material that is biocompatible and flexible. Further, the device comprises a plurality of electrodes arranged on the substrate and a plurality of electronic chips embedded in the substrate in a serial arrangement underneath at least one of the plurality of electrodes. Each of the plurality of electronic chips comprises a conversion unit that comprises at least one of an analog-to-digital conversion unit and a digital-to-analog conversion unit. The device comprises further a trace structure between the plurality of electronic chips and the plurality of electrodes. The trace structure has conductive traces that connect each of the plurality of electrodes to one of the plurality of electronic chips.

Description

DEVICE FOR DETECTION AND/OR STIMULATION AND METHOD FOR MANUFACTURING THE DEVICE

Description

Technical Field

Embodiments according to the invention relate to a device and a system for detection and/or stimulation and a method for manufacturing the device and/or system. One aspect relates to the assembly and packaging of flexible, e.g., subcortical, probes for recording of bioelectrical signals and/or for stimulating biomaterial.

Background

Common probes for deep brain stimulation systems have mostly only few and/or large contacts used for stimulation purposes. For a detection of biosignals there exists two- dimensional and one-dimensional Arrays with multiple passive electrodes, e.g., for brainmachine interface [1]. The silicon electrodes are connected with small cables to a bulky external connector for processing detected signals. A drawback of such systems is the large external system for signal conditioning.

Beside such systems, document [2] describes fully immersible subcortical neural probes with a delta-sigma ADC integrated under each electrode for parallel readout of 144 recording sites. However, this device can only detect biosignals and cannot stimulate biomaterial.

A further drawback of the commonly known probes and arrays is that same might not be customizable or that customized probes and arrays result in high costs and complex manufacturing processes.

Therefore, it is desired to provide a concept which makes a better compromise between increasing a number of contacts, i.e. recording and/or stimulation sites, enabling an individual arrangement of the contacts at low costs and using an efficient manufacturing process, enabling a recording and a stimulation with the same device and reducing damages of biomaterial at an insertion of the device. This is achieved by the subject matter of the independent claims of the present application.

Further embodiments according to the invention are defined by the subject matter of the dependent claims of the present application.

Summary of the Invention

In accordance with a first aspect of the present invention, the inventors of the present application realized that one problem encountered with stimulation or recording arrays stems from the fact that such arrays cover only a limited stimulation or recording area. In this context, the inventors found that just increasing a number of stimulation or recording sites reduces a robustness of a transmission of signals between a processing unit and stimulation or recording sites, since paths between same increase. Normally amplitudes of transmitted signals are very small and susceptible to interference sources, in particular when the conductor carrying the signal has a length of several centimeters. Crosstalk between different paths may occur, such that an original source/electrode can no longer be identified. According to the first aspect of the present application, this difficulty is overcome by integrating electrodes and signal processing units in near proximity to each other. This is based on the idea that it is advantageous to process signals in direct proximity to the electrodes instead of having to transmit signals between a common base and the electrodes via individual long cables. Especially, the inventors found that it is possible to integrate a plurality of processing units, like electronic chips, in a stimulation and/or recording device without significantly increasing a volume of the device. The possibility to integrate a plurality of electronic chips enables to significantly increase a number of electrodes and thus a covered stimulation or recording area, wherein at the same time a robustness of transmitted signals is increased and a size of the device can be controlled. Additionally, the inventors found that it is possible to arrange electrodes and electronic chips on different sides of a substrate allowing a stimulation and/or a recording in different directions without significantly increasing a size of the device. This is especially advantageous for stimulation and/or a recording devices, which are insertable into tissue, so that tissue damage is minimal. The electronic chips are connected to electrodes via a trace structure. The trace structure allows to distribute the electrodes on the substrate in an individual manner, i.e. as required by an application of the device. For example, the trace structure enables an individual spacing of the electrodes and allows to position electrodes between neighboring electronic chips, so that gaps between electronic chips are also covered. The trace structure allows an individual layout of the electrodes on the substrate compared to a predefined layout of corresponding pins on the respective electronic chip. The inventors found that it is advantageous to embed standardized electronic chips in a substrate and to customize the device using a trace structure to realize individual electrode layouts. This is based on the finding that such a device can be manufactured very efficiently and with reduced costs and enables to define a number and position of the electrodes of the device independent of a predefined layout and number of pins of an embedded electronic chip.

Accordingly, in accordance with a first aspect of the present application, a device comprises a substrate comprising material that is biocompatible and flexible. Further, the device comprises a first plurality of electrodes arranged on a first side of the substrate, e.g., on a first surface area or a first face, and a second plurality of electrodes arranged on a second side of the substrate, e.g., on a second surface area or a second face. The first side may face a different direction than the second side, e.g., the first side may face the opposite direction than the second side or the first side may be arranged perpendicular to the second side, or the first side may be inclined or tilted with respect to the second side. The first side and the second side, for example, are faces of the substrate arranged in different planes. The first side may represent a first face of the substrate and the second side may represent a second face of the substrate. Additionally, the device comprises a first plurality of electronic chips embedded in the substrate in a serial arrangement in a plane parallel to the first side and a second plurality of electronic chips embedded in the substrate in a serial arrangement in a plane parallel to the second side. The device comprises further a first trace structure between the first plurality of electronic chips and the first plurality of electrodes and a second trace structure between the second plurality of electronic chips and the second plurality of electrodes. The first trace structure has conductive traces that connect each of the first plurality of electrodes to one of the first plurality of electronic chips and the second trace structure has conductive traces that connect each of the second plurality of electrodes to one of the second plurality of electronic chips.

According to an embodiment, the first plurality of electronic chips are aligned with the first plurality of electrodes and the second plurality of electronic chips are aligned with the second plurality of electrodes. The first plurality of electronic chips, for example, are aligned with the first plurality of electrodes, so that a projection of at least one of the first plurality of electrodes onto the plane in which the first plurality of electronic chips are arranged overlaps with an area covered by one of the first plurality of electronic chips. Optionally, for electrodes of the first plurality of electrodes, a respective projection onto the plane in which the first plurality of electronic chips are arranged either at least partially overlaps with an area covered by one of the first plurality of electronic chips or is arranged in an area between two neighboring electronic chips of the first plurality of electronic chips. The second plurality of electronic chips, for example, are aligned with the second plurality of electrodes, so that a projection of at least one of the second plurality of electrodes onto the plane in which the second plurality of electronic chips are arranged overlaps with an area covered by one of the second plurality of electronic chips. Optionally, for electrodes of the second plurality of electrodes, a respective projection onto the plane in which the second plurality of electronic chips are arranged either at least partially overlaps with an area covered by one of the second plurality of electronic chips or is arranged in an area between two neighboring electronic chips of the second plurality of electronic chips. Thus, the electronic chips and the electrodes are arranged in near proximity resulting in a robust signal transmission between the electronic chips and the electrodes.

According to an embodiment, each electronic chip of the first plurality of electronic chips and of the second plurality of electronic chips comprises a conversion unit that comprises an analog-to-digital conversion unit and/or a dig ital-to-analog conversion unit. The inventors found that it is advantageous to transmit analog signals only on short paths, e.g. between an electrode and an associated electronic chip, and to transmit digital signal over long paths, e.g. between an electronic chip and a base. For which reason an electronic chip, for example, comprises an analog-to-digital conversion unit for signals recorded by an associated electrode and/or a digital-to-analog conversion unit for providing an analog stimulation signal to an associated electrode. This enables an implementation of a small external processing unit, i.e. a small external unit for signal conditioning, or even the waiving of an external processing unit, and a more robust transmission of signals.

According to an embodiment, an analog-to-digital conversion unit comprised by a conversion unit may comprise a multiplexer and/or a digital-to-analog conversion unit comprised by a conversion unit may comprise a demultiplexer. At a multiplex-readoutprocess analog signals obtained from two or more electrodes of the first plurality of electrodes or of the second plurality of electrodes are digitized by a common analog-to- digital conversion unit, wherein the analog signals of the two or more electrodes are converted one after the other, e.g., using the multiplexer. In order to maintain the sampling rate per electrode, a sampling rate of the common analog-to-digital conversion unit should be increased accordingly. This increases the demands on the electronics, especially with regard to noise (higher bandwidth) and clock frequency. Similarly, at a multiplex-stimulation- process digital signals are converted into analog signals by a common digital-to-analog conversion unit one after the other using the demultiplexer, i.e. one channel after the other is processed, wherein each channel is associated with one of the electrodes connected to the respective electronic chip, which comprises the common digital-to-analog conversion unit. Each obtained analog signal is provided to the associated electrode of the first plurality of electrodes or of the second plurality of electrodes. Using a multiplexer or demultiplexer has the advantage that a smaller area is needed for the electronics within the respective electronic chip per electrode. This allows a denser arrangement of the electrodes on the substrate. Further, a power consumption per electrode remains approximately the same when using multiplexing. It is proposed that subsets of up to a predefined number of electrodes share a conversion unit that comprises at least one of an analog-to-digital conversion unit and a digital-to-analog conversion unit. The predefined number of electrodes, for example, may be 16, 8 or 4. The inventors found that multiplexing is especially advantageous for up to four or 8 channels.

According to an embodiment, the first plurality of electronic chips and/or the second plurality of electronic chips comprise at least one electronic chip with a conversion unit that comprises, for each electrode connected to the respective electronic chip, an analog-to- digital conversion unit and/or a digital-to-analog conversion unit. For example, the respective conversion unit may comprise a plurality of analog-to-digital conversion units, wherein a number of the plurality of analog-to-digital conversion units may be equal to a number of electrodes connected to the respective electronic chip comprising the respective conversion unit. Additionally, or alternatively, the respective conversion unit may comprise a plurality of digital-to-analog conversion units, wherein a number of the plurality of digital- to-analog conversion units may be equal to a number of electrodes connected to the respective electronic chip comprising the respective conversion unit. In other words, a subset of the first plurality of electrodes having at least two electrodes may be connected to a common electronic chip of the first plurality of electronic chips and the common electronic chip comprises for each electrode connected to the common electronic chip an analog-to-digital conversion unit and/or a digital-to-analog conversion unit and/or a subset of the second plurality of electrodes having at least two electrodes may be connected to a common electronic chip of the second plurality of electronic chips and the common electronic chip comprises for each electrode connected to the common electronic chip an analog-to-digital conversion unit and/or a digital-to-analog conversion unit. The usage of separate analog-to-digital conversion units and/or a digital-to-analog conversion units for each electrode has the advantage that signals can be processed with high precision and high efficiency for each electrode individually. Such an implementation allows to control two or more electrodes associated with the same electronic chip at the same time, i.e. the respective electronic chip may be configured to read out and process signals recorded by two or more associated electrodes at the same time and/or provide signals to two or more associated electrodes at the same time.

According to an embodiment, the first trace structure has at least one redistribution layer parallel to the first side and is adapted for redistributing, for electronic chips of the first plurality of electronic chips, a respective pin-pattern of the respective electronic chip to at least a part of an electrode-pattern of the first plurality of electrodes or vice versa. Additionally, or alternatively, the second trace structure has at least one redistribution layer parallel to the second side and is adapted for redistributing, for electronic chips of the second plurality of electronic chips, a respective pin-pattern of the respective electronic chip to at least a part of an electrode-pattern of the second plurality of electrodes or vice versa. For example, each of the first plurality of electronic chips may be connected to a respective subset of electrodes of the first plurality of electrodes via the first trace structure and the first trace structure is configured to redistribute, for each of the first plurality of electronic chips, a respective pin-pattern to an electrode pattern of the respective subset of electrodes via the at least one redistribution layer. For example, each of the second plurality of electronic chips may be connected to a respective subset of electrodes of the second plurality of electrodes via the second trace structure and the second trace structure is configured to redistribute, for each of the second plurality of electronic chips, a respective pin-pattern to an electrode pattern of the respective subset of electrodes via the at least one redistribution layer. Within a redistribution layer, for example, at least one of the conductive traces, e.g., a first conductive trace for connecting a first electrode with a first pin, runs parallel to a side of the substrate, e.g. parallel to the first side for the redistribution layer of the first trace structure or parallel to the second side for the redistribution layer of the second trace structure. Such a conductive trace, for example, offsets a position of the first electrode in relation to a position of the first pin. The electrodes and the pins may be connected to the at least one redistribution layer by vertical tracks, e.g., a first vertical track may connect the first pin with an end of the first conductive trace within the redistribution layer and a second vertical track may connect another end of the first conductive trace of the redistribution layer with the first electrode. According to some embodiments the first trace structure and/or the second trace structure may comprise two or more redistribution layers, e.g., a multilayer structure, wherein, e.g., pins of the respective electronic chips are connected to a first redistribution layer, in a direction from a chip layer to an electrode layer, by vertical tracks, neighboring redistribution layers are connected by vertical tracks and the respective electrodes are connected to a last redistribution layer, in a direction from the chip layer to the electrode layer, by vertical tracks. Each of the two or more redistribution layers may comprise at least one conductive trace running parallel to the chip plane. The usage of one or more redistribution layers enable an efficient production of customized devices for stimulation and/or recording using a customized electrode pattern. The redistribution layer allows to realize an individual application specific electrode pattern despite embedding in the substrate electronic chips with a standardized or predefined pin pattern. Thus, a customized device can be produced cost efficiently.

According to an embodiment, the device comprises a communication unit. Within the first plurality of electronic chips and within the second plurality of electronic chips, the respective electronic chips are connected serially with respect to each other. The first plurality of electronic chips and the second plurality of electronic chips are connected parallel with respect to each other and to the communication unit. This implementation has the advantage that a high amount of data is transmittable between the electronic chips and the communication unit and thus, a high number of electrodes can be comprised by the device.

According to an embodiment, the substrate comprises a cavity with a longitudinal axis parallel to an axis of the serial arrangement of the first plurality of electronic chips and parallel to an axis of the serial arrangement of the second plurality of electronic chips. In other words, the substrate is at least partially hollow. The cavity, for example, is closed on one end, e. g., a first end, along the longitudinal axis and open on an opposite end, e.g., a second end, along the longitudinal axis. The cavity may comprise side walls, e.g., connecting the first end with the second end. For example, the cavity may comprises two side walls parallel to the first side and two side walls perpendicular to the first side. The first plurality of electronic chips and the first trace structure may be embedded in a first side wall of the side walls of the cavity and the first side, on which the first plurality of electrodes are arranged, may represent an outer surface of the first side wall facing away from the cavity. The second plurality of electronic chips and the second trace structure may be embedded in a second side wall of the side walls of the cavity and the second side, on which the second plurality of electrodes are arranged, may represent an outer surface of the second side wall facing away from the cavity. A stylet is insertable into the cavity to facilitate insertion of the device into tissue. By directly integrating the cavity within the substrate of the device, an easier handling of the device is achieved.

According to an embodiment, a side or face of the substrate on which no electrodes are arranged comprises a plurality of openings to the cavity. In other words, a side wall in which no electronic chip is embedded may at least partially be perforated. The openings make it easier to create the cavity. For example, a sacrificial layer may be arranged within the substrate, which can be etched away to form the cavity within the substrate. The openings allows an easier etching of the sacrificial layer.

An embodiment relates to a method for manufacturing a device. The method comprises embedding in a serial arrangement a first plurality of electronic chips in a plane parallel to a first side of a substrate that comprises an embedding material that is biocompatible and flexible. The method further comprises embedding in a serial arrangement a second plurality of electronic chips in a plane parallel to a second side of the substrate that comprises the embedding material that is biocompatible and flexible. Additionally, the method comprises arranging a first plurality of electrodes on the first side of the substrate and arranging a second plurality of electrodes on the second side of the substrate. The method is carried out such that a first trace structure is formed between the first plurality of electronic chips and the first plurality of electrodes and such that a second trace structure is formed between the second plurality of electronic chips and the second plurality of electrodes. The first trace structure has conductive traces that connect each of the first plurality of electrodes to one of the first plurality of electronic chips and the second trace structure has conductive traces that connect each of the second plurality of electrodes to one of the second plurality of electronic chips.

The method as described above is based on the same considerations as the abovedescribed device. The method can, by the way, be completed with all features and functionalities, which are also described with regard to the device.

Another embodiment relates to a device comprising a substrate comprising material that is biocompatible and flexible. The device comprises a plurality of electrodes arranged on the substrate, a plurality of electronic chips embedded in the substrate in a serial arrangement underneath at least one of the plurality of electrodes and a trace structure between the plurality of electronic chips and the plurality of electrodes. The trace structure has conductive traces that connect each of the plurality of electrodes to one of the plurality of electronic chips. The device comprises further, laterally spaced from the plurality of electrodes, a further plurality of electrodes arranged on the substrate, and, laterally spaced from the plurality of electronic chips, a further plurality of electronic chips embedded in the substrate in a serial arrangement underneath at least one of the further plurality of electrodes, and, laterally spaced from the trace structure a further trace structure between the further plurality of electronic chips and the further plurality of electrodes. The further trace structure has conductive traces that connect each of the further plurality of electrodes to one of the further plurality of electronic chips. The substrate comprises a trench separating the plurality of electrodes, the plurality of electronic chips and the trace structure from the further plurality of electrodes, the further plurality of electronic chips and the further trace structure. The trench facilitates a bending of the substrate, so that the plurality of electrodes face a different direction than the further plurality of electrodes. This allows a stimulation and/or a recording in different directions. Additionally, the separation of the device components using the trench results in an efficient manufacturing of the device, since the devices can be build up in layers, i.e. the plurality of electronic chips and the further plurality of electronic chips can be implemented in a first layer, the trace structure and the further trace structure can be implemented in a second layer and the plurality of electrodes and the further plurality of electrodes can be implemented in a third layer. Thus, a good compromise between increasing a stimulation and/or a recording area and increasing a manufacturing efficiency is achieved.

The device as described above is based on the same considerations as the abovedescribed device. The device can, by the way, be completed with all features and functionalities, which are also described with regard to the other device.

According to an embodiment, the device comprises a cavity between a side of the substrate facing away from the side of the substrate on which the plurality of electrodes and the further plurality of electrodes are arranged and the electronic chips of the plurality of electronic chips and the further plurality of electronic chips. The two portions of the device separated by the trench may be tilted apart at an insertion of a stylet into the cavity. In other words, a stylet is insertable into the cavity, wherein the stylet is configured to bend the device along the trench, so that the plurality of electrodes face a different direction than the further plurality of electrodes. By directly integrating the cavity within the substrate of the device, an easier handling of the device is achieved, e.g., in terms of coupling same to a stylet to facilitate inserting the device into tissue and/or in terms of directing the plurality of electrodes and the further plurality of electrodes into predefined directions. A form of the stylet may define a bending angle between the plurality of electrodes and the further plurality of electrodes along the trench.

According to an embodiment, the side of the substrate facing away from the side of the substrate on which the plurality of electrodes and the further plurality of electrodes are arranged comprises a plurality of openings to the cavity. In other words, the side may at least partially be perforated. The openings make it easier to create the cavity. For example, a sacrificial layer may be arranged within the substrate, which can be etched away to form the cavity within the substrate. The openings allows an easier etching of the sacrificial layer.

An embodiment relates to a method for manufacturing a device. The method comprises embedding a plurality of electronic chips in a substrate that comprises an embedding material that is biocompatible and flexible, in a serial arrangement and underneath at least one of a plurality of electrodes; and embedding laterally spaced from the plurality of electronic chips a further plurality of electronic chips in the substrate in a serial arrangement and underneath at least one of a further plurality of electrodes. Further, the method comprises arranging the plurality of electrodes on the substrate and arranging the further plurality of electrodes laterally spaced from the plurality of electrodes on the substrate. The method is carried out a trace structure is formed between the plurality of electronic chips and the plurality of electrodes and such that a further trace structure is formed between the further plurality of electronic chips and the further plurality of electrodes. The trace structure has conductive traces that connect each of the plurality of electrodes to one of the plurality of electronic chips and the further trace structure has conductive traces that connect each of the further plurality of electrodes to one of the further plurality of electronic chips. Additionally, the method comprises forming a trench in the substrate separating the plurality of electrodes, the plurality of electronic chips and the trace structure from the further plurality of electrodes, the further plurality of electronic chips and the further trace structure.

The method as described above is based on the same considerations as the abovedescribed devices. The method can, by the way, be completed with all features and functionalities, which are also described with regard to the devices.

In accordance with a second aspect of the present invention, the inventors of the present application realized that one problem encountered when trying to customize stimulation or recording arrays stems from the fact that no standardized manufacturing process can be used and that a flexibility at such an individualization is limited. According to the second aspect of the present application, this difficulty is overcome by integrating electrodes and signal processing units individually in the device. This allows to manufacture the signal processing units, e.g., electronic chips, with a standardized process and to arrange electrodes independent from an arrangement of corresponding pins on an electronic chip. Thus, a complete individual layout of the electrodes, e.g., stimulating and/or recording sites, on the device can be realized while at the same time costs can be reduced and an efficiency at a production of the device can be increased. Each electronic chip may be associated with a subset of the plurality of electrodes of the devices and may be arranged in near proximity to the electrodes of the respective subset of electrodes. For example, an electronic chip may be arranged underneath at least one of the electrodes of the respective subset of electrodes. This is based on the idea that it is advantageous to process signals in direct proximity to the electrodes instead of having to transmit signals between a common base and the electrodes via individual small cables. Especially, the inventors found that it is advantageous to transmit analog signals only on short paths, e.g. between an electrode and an associated electronic chip, and to transmit digital signal over long paths, e.g. between an electronic chip and a base. For which reason an electronic chip, for example, comprises an analog-to-digital conversion unit for signals recorded by an associated electrode and/or a digital-to-analog conversion unit for providing an analog stimulation signal to an associated electrode. This enables an implementation of a small external processing unit, i.e. a small external unit for signal conditioning, or even the waiving of an external processing unit, and a more robust transmission of signals. The electronic chips are embedded in the substrate on which the electrodes are arranged in near proximity to the electrodes and are connected to the respective subset of electrodes via a trace structure. The trace structure allows to distribute the electrodes on the substrate in an individual manner, i.e. as required by an application of the device. For example, the trace structure enables an individual spacing of the electrodes and allows to position electrodes between neighboring electronic chips, so that gaps between electronic chips are also covered. The trace structure allows an individual layout of the electrodes on the substrate compared to a predefined layout of corresponding pins on the respective electronic chip. The inventors found that it is advantageous to embed standardized electronic chips in a substrate and to customize the device using a trace structure to realize individual electrode layouts. This is based on the finding that such a device can be manufactured very efficiently and with reduced costs and enables to define a number and position of the electrodes of the device independent of a predefined layout and number of pins of an embedded electronic chip.

Accordingly, in accordance with a second aspect of the present application, a device, e.g., for stimulating and/or recording, is provided. The device comprises a substrate comprising material that is biocompatible and flexible, e.g., comprising polyimid-material (e.g., kapton) or parylene C-material. Alternatively, the substrate is rigid or stiff, e.g., comprising silicon- material. Further, the device comprises a plurality of electrodes, e.g., stimulation and/or recording sites, arranged, e.g., fixed, on the substrate and a plurality of electronic chips, e.g., application-specific integrated circuits (ASICs), embedded in the substrate in a serial arrangement underneath at least one of the plurality of electrodes. Serial arrangement, for example, means that the plurality of electronic chips are positioned next to each other in a row, i.e. the serial arrangement may represent a one-dimensional array of electronic chips. The device may comprise an electrode plane, e.g., an electrode layer, in which the plurality of electrodes are arranged, i.e. a surface auf the substrate, and a chip plane, e.g., a chip layer, in which the plurality of electronic chips are positioned, i.e. a plane within the substrate. The electrode plane and the chip plane represent two parallel planes, e.g., spaced apart from each other. A projection of an area in which the plurality of electrodes are arranged within the electrode plane onto the chip plane may at least partially overlap with an area in which the plurality of electronic chips are positioned within the chip plane, e.g., at least a projection of a position of one of the plurality of electrodes onto the chip plane lies within an area covered by at least one of the plurality of electronic chips. Preferably, each electronic chip is arranged underneath at least one of the plurality of electrodes, i.e. for each electronic chip, a projected position of an electrode of the plurality of electrodes onto the chip plane lies within an area covered by the respective electronic chip.

Each of the plurality of electronic chips comprises a conversion unit that comprises at least one of an analog-to-digital conversion unit and a digital-to-analog conversion unit. The analog-to-digital conversion unit may be configured to obtain an analog signal from an electrode of the plurality of electrodes and convert same into a digital signal and the digital- to-analog conversion unit may be configured to convert a digital signal into an analog signal and provide same to an electrode of the plurality of electrodes. The analog-to-digital conversion unit may be used for recording purposes and the digital-to-analog conversion unit may be used for stimulation purposes. It is not necessary that all electronic chips comprise the same type of conversion units. For example, a first electronic chip of the plurality of electronic chips may comprise a conversion unit comprising an analog-to-digital conversion unit, a second electronic chip of the plurality of electronic chips may comprise a conversion unit comprising a digital-to-analog conversion unit and/or a third electronic chip of the plurality of electronic chips may comprise a conversion unit comprising a digital-to- analog conversion unit and an analog-to-digital conversion unit.

As described above, each of the plurality of electronic chips comprises a respective conversion unit. Same may be shared by multiple electrodes, i.e., each electronic chip may be associated with a respective subset of electrodes of the plurality of electrodes and the conversion unit may be shared among the electrodes of the respective subset of electrodes. In case of the respective conversion unit comprising an analog-to-digital conversion unit and a digital-to-analog conversion unit, it is not necessary that the electrodes of the respective subset of electrodes are connected to both, i.e. the analog-to-digital conversion unit and the digital-to-analog conversion unit. For example, it is possible that one or more stimulating electrodes of the subset of electrodes are connected to the digital-to-analog conversion unit of the respective conversion unit and/or that one or more recording electrodes of the subset of electrodes are connected to the analog-to-digital conversion unit of the respective conversion unit and/or that one or more stimulating-and-recording electrodes of the subset of electrodes are connected to the digital-to-analog conversion unit and the analog-to-digital conversion unit of the respective conversion unit.

The device comprises further a trace structure, e.g., comprising flat tracks and vertical tracks, e.g. vias, between the plurality of electronic chips and the plurality of electrodes, i.e. between the chip layer and the electrode layer. The trace structure has conductive traces that connect each of the plurality of electrodes to one of the plurality of electronic chips. For example, each electronic chip may comprise two or more pins and the trace structure connects each of the plurality of electrodes with one of the pins, wherein a pin is associated with maximum one electrode. The trace structure may be configured to connect each of the plurality of electrodes with one of the pins but not necessarily each pin with one of the plurality of electrodes, e.g., realizing a bijective or injective connection. The number of electrodes of the plurality of electrodes may be equal to (corresponding to an bijective connection) or lower than (corresponding to an injective connection) the number of pins of the plurality of electronic chips. For example, the conductive traces of the trace structure may bijectively connect the plurality of electrodes to the pins of the plurality of electronic chips, i.e., number of electrodes is equal to the number of pins, or the conductive traces of the trace structure may injectively connect the plurality of electrodes to the pins of the plurality of electronic chips, i.e., number of electrodes is lower than the number of pins.

According to an embodiment, the trace structure has at least one redistribution layer and is adapted for redistributing, for each of the plurality of electronic chips, a respective pinpattern, e.g. defined by pins of the respective electronic chip, of the respective electronic chip to at least a part of an electrode-pattern of the plurality of electrodes or vice versa. For example, each electronic chip may be connected to a respective subset of electrodes of the plurality of electrodes via the trace structure and the trace structure is configured to redistribute, for each of the plurality of electronic chips, a respective pin-pattern to an electrode pattern of the respective subset of electrodes via the at least one redistribution layer. Within the redistribution layer, for example, at least one of the conductive traces, e.g., a first conductive trace for connecting a first electrode with a first pin, runs parallel to a surface of the first electronic chip facing the plurality of first electrodes, for example, offsetting a position of the first electrode in relation to a position of the first pin. The plurality of electrodes and the pins may be connected to the at least one redistribution layer by vertical tracks, e.g., a first vertical track may connect the first pin with an end of the first conductive trace within the redistribution layer and a second vertical track may connect another end of the first conductive trace of the redistribution layer with the first electrode. According to some embodiments the trace structure may comprise two or more redistribution layers, e.g., a multilayer structure, wherein, e.g., pins of the electronic chips are connected to a first redistribution layer, in a direction from the chip layer to the electrode layer, by vertical tracks, neighboring redistribution layers are connected by vertical tracks and the plurality of electrodes are connected to a last redistribution layer, in a direction from the chip layer to the electrode layer, by vertical tracks. Each of the two or more redistribution layers may comprise at least one conductive trace running parallel to the chip plane. The usage of one or more redistribution layers enable an efficient production of customized devices for stimulation and/or recording using a customized electrode pattern. The redistribution layer allows to realize an individual application specific electrode pattern despite embedding in the substrate electronic chips with a standardized or predefined pin pattern. Thus, a customized device can be produced cost efficiently.

According to an embodiment, an electrode is electrically connected to a conversion unit via a pin of an associated electronic chip. For example, a conducting trace of the trace structure connects the electrode with the pin of the associated electronic chip and the pin is electrically coupled to the conversion unit of the associated electronic chip.

According to an embodiment, one or more of the plurality of electronic chips comprises beside the respective conversion unit one or more respective further conversion units, wherein each of the one or more respective further conversion units comprises at least one of an analog-to-digital conversion unit and a digital-to-analog conversion unit. Optionally, one or more of the plurality of electronic chips comprise for each electrode connected to the respective electronic chip a separate conversion unit. For example, the respective electronic chip may comprise a plurality of conversion units, e.g., comprising the respective conversion unit and the one or more further conversion units, and a number of conversion units of the plurality of conversion units may be equal to a number of electrodes connected with the respective electronic chip. In other words, a subset of the plurality of electrodes having at least two electrodes may be connected to a common electronic chip of the plurality of electronic chips and the common electronic chip comprises for each electrode connected to the common electronic chip a conversion unit comprising at least one of an analog-to- digital conversion unit and a digital-to-analog conversion unit. The usage of separate conversion units for each electrode has the advantage that signals can be processed with high precision and high efficiency for each electrode individually. Such an implementation allows to control two or more electrodes associated with the same electronic chip at the same time, i.e. the respective electronic chip may be configured to read out and process signals recorded by two or more associated electrodes at the same time and/or provide signals to two or more associated electrodes at the same time.

According to an embodiment, an analog-to-digital conversion unit comprised by a conversion unit may comprise a multiplexer and/or a digital-to-analog conversion unit comprised by a conversion unit may comprise a demultiplexer. At a multiplex-readoutprocess analog signals obtained from two or more electrodes of the plurality of electrodes are digitized by a common analog-to-digital conversion unit, wherein the analog signals of the two or more electrodes are converted one after the other, e.g., using the multiplexer. In order to maintain the sampling rate per electrode, a sampling rate of the common analog- to-digital conversion unit should be increased accordingly. This increases the demands on the electronics, especially with regard to noise (higher bandwidth) and clock frequency. Similarly, at a multiplex-stimulation-process digital signals are converted into analog signals by a common digital-to-analog conversion unit one after the other using the demultiplexer, i.e. one channel after the other is processed, wherein each channel is associated with one of the electrodes connected to the respective electronic chip, which comprises the common digital-to-analog conversion unit. Each obtained analog signal is provided to the associated electrode of the plurality of electrodes. Using a multiplexer or demultiplexer has the advantage that a smaller area is needed for the electronics within the respective electronic chip per electrode. This allows a denser arrangement of the plurality of electrodes on the substrate. Further, a power consumption per electrode remains approximately the same when using multiplexing. It is proposed that subsets of up to a predefined number of electrodes of the plurality of electrodes share a conversion unit that comprises at least one of an analog-to-digital conversion unit and a digital-to-analog conversion unit. The predefined number of electrodes, for example, may be 16, 8 or 4. The inventors found that multiplexing is especially advantageous for up to four or 8 channels. According to an embodiment, the device comprises a communication unit, e.g., an input/output/base. The communication unit may be configured to provide stimulation signals to one or more of the electronic chips and/or obtain recorded signals from one or more of the electronic chips. The communication unit may be configured to transmit data obtained from one or more of the electronic chips to an external processing device and/or obtain the stimulation signals from the external processing device wireless or via a cable.

According to an embodiment, the plurality of electronic chips are connected serially with respect to each other and to the communication unit or parallel with respect to each other and to the communication unit. The serial arrangement is especially advantageous in terms of area consumption within the device, since only a small number of connecting lines may be needed. For example, with a serial connection of the electronic chips a minimum number of five connecting lines may be achieved, e.g., two data lines (a forward path and a backward path), a clock line and two lines for a power supply.

According to an alternative embodiment, a serial connection of electronic chips and a parallel connection of electronic chips may be combined. For example, the plurality of electronic chips are partitioned into subsets of electronic chips. Within each subset of electronic chips, the respective electronic chips are connected serially with respect to each other. The subsets of electronic chips are connected parallel with respect to each other and to the communication unit. An amount of data transmittable via a serial interface, i.e. the serial connection, may be limited. In order to increase the amount of data transmittable between the electronic chips and the communication unit, groups of serially connected electronic chips are connected in parallel with the communication unit. This implementation has the advantage that a high number of electrodes can be comprised by the device.

According to an embodiment, the device comprises a connection region, e.g., e connection portion, for a connection of the substrate to a stylet. For example, the substrate may be deposited on the stylet, so that the substrate is fixed/adhered to the stylet with a surface opposite to the surface on which the plurality of electrodes are arranged. For example, the stylet may be formed out of a wafer, e.g. comprising silicon material, onto which the substrate may be deposited, so that same adheres to the stylet. Alternatively, the substrate may comprise, e.g., at one end, a ring, hole or loop into which the stylet is insertable, so that the substrate is fixed to the stylet. Alternatively, the substrate may comprise, e.g., a pocket in the substrate in which the stylet is insertable, so that the substrate is fixed to the stylet. Being able to connect the substrate to a stylet has the advantage, that the device can be guided to a predetermined position much easier using the stylet and/or that the device can be inserted into tissue much easier using the stylet.

According to an embodiment, the plurality of electrodes are arranged on two or more surfaces of the substrate. This has the advantage that the device is not only configured to record signals from one side and/or provide stimulation signals to one side, but also to record signals from one or more further sides and/or provide stimulation signals to one or more further sides. Additionally, such an implementation may increase a stimulation and/or recording accuracy compared to a device using one 360°-electrode, e.g., a cylindrical electrode. Optionally, electronic chips may be embedded in the substrate parallel to each of the two or more surfaces of the substrate on which the plurality of electrodes are arranged, e.g., a first electronic chip may be embedded in the substrate underneath a first electrode parallel to a first surface on which the first electrode is arranged and a second electronic chip may be embedded in the substrate underneath a second electrode parallel to a second surface on which the second electrode is arranged. Thus a signal processing is implemented near the electrodes, so that artefact vulnerable analog signals are transmitted only on short paths between the respective electrode and the associated electronic chip.

A further embodiment relates to a system comprising a plurality of the herein described devices arranged in a two dimensional arrangement next to each other and sharing the same substrate. For example, a chip layer, a trace structure and an electrode layer of a first device are arranged in this order at a first position of the substrate and a chip layer, a trace structure and an electrode layer of a second device are arranged in this order at a second position of the substrate, wherein the first position and the second position are laterally spaced from each other. In other words the system may correspond to a device comprising a substrate comprising material that is biocompatible and flexible, a chip layer, a trace structure layer and an electrode layer. The chip layer, the trace structure layer and the electrode layer are stacked in this order. The chip layer comprises a plurality of electronic chips embedded in the substrate in a two dimensional arrangement, the electrode layer comprises a plurality of electrodes arranged on a surface of the substrate in a two dimensional arrangement and the trace structure layer comprises a trace structure connecting each of the plurality of electrodes to one of the plurality of electronic chips. The system enables an efficient stimulation and/or recording of a surface. Optionally, the substrate comprises one or more openings, i.e., slits and/or holes. According to an embodiment, a herein described device, e.g., formed as a needle, or a needle with recording sites and/or stimulation sites may be passable through the one or more openings. The one or more openings, for example, have corresponding dimensions as the respective device or needle, which is passable through the respective opening. This implementation enables to combine surface stimulation and/or recording and deep stimulation and/or recording. Therefore, a three dimensional area can be stimulated and/or signals originating from this area can be recorded.

The system as described above is based on the same considerations as the abovedescribed device. The system can, by the way, be completed with all features and functionalities, which are also described with regard to the device.

A further embodiment relates to a method for manufacturing a device, e.g., one of the herein described devices. The method comprises embedding a plurality of electronic chips in a substrate that comprises an embedding material that is biocompatible and flexible, in a serial arrangement and underneath at least one of a plurality of electrodes. Each of the plurality of electronic chips comprises a conversion unit that comprises at least one of an analog-to-digital conversion unit and a dig ital-to-analog conversion unit. Further, the method comprises arranging the plurality of electrodes on the substrate. The method is performed such that a trace structure is formed between the plurality of electronic chips and the plurality of electrodes. The trace structure has conductive traces that connect each of the plurality of electrodes to one of the plurality of electronic chips.

The method as described above is based on the same considerations as the abovedescribed device and system. The method can, by the way, be completed with all features and functionalities, which are also described with regard to the device and system.

Brief Description of the Drawings

The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the invention are described with reference to the following drawings, in which:

Fig. 1 shows schematically an embodiment of a device for recording and/or stimulation;

Fig. 2a)-e) show embodiments of electronic chips for a herein described device; Fig. 3 shows schematically embodiments of a device comprising chips with vias and metal pads as contacts;

Fig. 4 shows schematically embodiments of a device comprising chips with vias and metal pads as contacts with additional tracks between substrate 1 10 and wafer 410;

Fig. 5 shows an excerpt of a device illustrating a redistribution layer;

Fig. 6 shows schematically an embodiment of a device comprising a redistribution layer and a chip with a tip;

Fig. 7 shows schematically an embodiment of a device comprising a loop into which a stylet is insertable;

Fig. 8 shows schematically a 3D view of an embodiment of a device comprising a loop;

Fig. 9 shows schematically an embodiment of a device comprising a loop and a redistribution layer;

Fig. 10 shows schematically an embodiment of a device comprising a pocket;

Fig. 1 1 shows schematically an embodiment of a device comprising a perforated pocket;

Fig. 12 shows a cross section through an embodiment of a device comprising a pocket;

Fig. 13a)-b) show schematically embodiments of a device comprising a pocket realized using a sacrificial layer;

Fig. 14a)-b) show schematically embodiments of a multidirectional device comprising a pocket realized using a sacrificial layer;

Fig. 15 shows schematically an embodiment of a cylindrical device 100;

Fig. 16 shows schematically an embodiment of a device 100 comprising a catheter;

Fig. 17 shows schematically an embodiment of a device 100 with four shafts;

Fig. 18 shows schematically an embodiment of a device 100 for surface stimulation and/or recording;

Fig. 19 shows schematically an embodiment of a device 100 for surface and deep stimulation and/or recording;

Fig. 20 shows different possible length of herein described devices, if same is manufactured using a 6” wafer;

Fig. 21 shows schematically a manufacturing of herein described devices on a wafer in 3D;

Fig. 22 shows schematically steps at a manufacturing of herein described devices on a wafer; Fig. 23 shows schematically devices arranged on a wafer and an excerpt of a device resulting at the manufacturing using a wafer;

Fig. 24 shows a block diagram of a method for manufacturing a herein described device;

Fig. 25 shows schematically devices with a joined cable on a wafer;

Fig. 26 shows schematically excerpts of multidirectional devices comprising a pocket formed by folding the device;

Fig. 27 shows schematically an up-side-down method for manufacturing a herein described device;

Fig. 28 shows an embodiment of a device with a metal housing; and

Fig. 29 shows an embodiment of a device with stimulation and/or recording sites facing different directions.

Detailed Description of the Embodiments

Equal or equivalent elements or elements with equal or equivalent functionality are denoted in the following description by equal or equivalent reference numerals or are identified with the same name, and a repeated description of elements provided with the same reference number or being identified with the same name is typically omitted, even if occurring in different figures. Hence, descriptions provided for elements having the same or similar reference numbers or being identified with the same names are mutually exchangeable or may be applied to one another in the different embodiments.

In the following description, a plurality of details is set forth to provide a more thorough explanation of embodiments of the present invention. However, it will be apparent to those skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form rather than in detail in order to avoid obscuring embodiments of the present invention. In addition, features of the different embodiments described herein after may be combined with each other, unless specifically noted otherwise.

For facilitating the description of the different embodiments, some of the figures comprise a Cartesian coordinate system x, y, z, wherein the x-y-plane corresponds, i.e. is parallel, to a first main surface region of a substrate (= a reference plane = x-y-plane), e.g. the x-y-plane may corresponds to a plane in which the herein described electronic chips, or traces or electrodes are arranged. The direction vertically up with respect to the reference plane (x- y-plane) corresponds to the “+z” direction, and wherein the direction vertically down with respect to the reference plane (x-y-plane) corresponds to the “-z” direction. In the following description, the term “lateral” means a direction parallel to the x- and/or y-direction, i.e. parallel to the x-y-plane, wherein the term “vertical” means a direction parallel to the z- direction.

Fig. 1 shows an embodiment of a device 100 in the top view on the top and in the side view on the bottom. The device 100 may be configured to measure one or more signals, e.g., analog signals, and/or provide one or more signals, e.g., analog signals. The device 100 may represent a recording and/or stimulation device.

The device 100 comprises a substrate 110. The substrate 1 10 comprises biocompatible material, e.g., material that is biocompatible and flexible and/or material that is biocompatible and rigid. Preferably the substrate represents a biocompatible and flexible substrate. Flexible is to be understood in terms of reversibly deformable, i.e. a flexible material can change its shape when a force is applied and will return to its original shape after the force is removed. The substrate may comprise as biocompatible and flexible material parylene C or polyimide-material, e.g., kapton.

A plurality of electrodes, see 120i to 120?, is arranged, e.g., fixed, on a first main surface region 1 12 of the substrate 110. When generally referring to the electrodes the reference numeral 120 is used in the following. The plurality of electrodes 120, e.g., are out of conducting polymer material, e.g., PEDOT:PSS, Pt, TiN or IrOx.

Fig. 1 shows exemplarily a serial arrangement of the plurality of electrodes 120 on the substrate 110, e.g., along an x-direction. With such an arrangement a slim/narrow device 100 can be realized, e.g., a device 100 with a small width, i.e. a small dimension in the y- direction. This is especially advantageous for applications at which the device 100 is inserted into material, e.g., tissue, since the small cross section reduces possible damages of the material due to the penetration of the device 100. A device with such an electrode arrangement may be usable as a neural probe, e.g. for deep brain recording and/or stimulation.

Alternatively, the plurality of electrodes 120 may be arranged on the substrate 1 10 in form of a two-dimensional arrangement, e.g. in form of a two dimensional array or according to an individual electrode layout. A device 100 with a two-dimensional arrangement of the plurality of electrodes 120 may be advantageous for surface recordings and/or surfaces stimulations. However, the inventors found that devices 100 with a two-dimensional array n x m with n being two or three might also be suitable for deep material recordings and/or stimulations, wherein n may represent a number of electrodes 120 along a first direction, e.g., the y-direction, and m may represent a number of electrodes 120 along a second direction, e.g., the x-direction. The second direction is perpendicular to the first direction. The two-dimensional array n x m may represent an array with n rows and m columns of electrodes 120.

Further, the device 100 comprises a plurality of electronic chips, see 130i and 1302, embedded in the substrate 1 10. When generally referring to the electronic chips the reference numeral 130 is used in the following. The plurality of electronic chips 130 may represent or comprise integrated circuits, e.g., ASICs. Fig. 1 shows exemplarily a device 100 with two electronic chips 130, i.e. a first electronic chip 130i and a second electronic chip 1302.

Fig. 1 shows exemplarily a serial arrangement of the plurality of electronic chips 130, e.g., along an x-direction. The arrangement of the plurality of electronic chips 130 may be aligned with the arrangement of the plurality of electrodes 120. For example, the plurality of electronic chips 130 may be arranged underneath at least one of the plurality of electrodes 120. Fig. 1 shows exemplarily two electronic chips 130 arranged underneath three electrodes, see 1202, 120s and 120e, of the plurality of electrodes 120. Underneath means a position in a direction vertically down with respect to the first main surface region 1 12 of the substrate 110, e.g., in -z-direction. Being arranged underneath at least one of the plurality of electrodes 120 means that a projection of an electrode 120 onto a plane in which the plurality of electronic chips 130 are arranged overlaps at least partly with an area covered by one of the plurality of electronic chips 130. An axis along which the plurality of electronic chips 130 are arranged may be parallel to an axis along which the plurality of electrodes120 are arranged. The two axes are vertically spaced. In Fig. 1 exemplarily the two axes are aligned within the x-y-plane, i.e. the two axes are not laterally spaced. However, it might also be possible that the two axes are, additionally to being vertically spaced, laterally spaced.

Alternatively, the plurality of electronic chips 130 may be embedded in the substrate 110 in a two dimensional arrangement underneath at least one of the plurality of electrodes 120. For example, the plurality of electronic chips 130 may form a two dimensional array. The device 100 may have a multilayer structure along a vertical direction, i.e. along the z-direction. The multilayer structure may comprise a chip layer 102, e.g., a first layer, comprising the plurality of electronic chips 130 and an electrode layer 106, e.g., a second layer, comprising the plurality of electrodes 120. The chip layer 102 and the electrode layer 106 may be arranged in this order in the z-direction, i.e. the electrode layer 106 is arranged vertically above the chip layer 102.

Each of the plurality of electronic chips 130 comprises a conversion unit, see 132i and 132₂. When generally referring to the conversion units the reference numeral 132 is used in the following. Each conversion unit 132 comprises at least one of an analog-to-digital conversion unit 133 and a digital-to-analog conversion unit 134. For example, the first conversion unit 132i may represent an analog-to-digital conversion unit 133 and the second conversion unit 132₂ may comprise both, an analog-to-digital conversion unit 133 and a digital-to-analog conversion unit 134. It is also possible that a conversion unit 132 represents a digital-to-analog conversion unit 134. Fig. 1 shows a plurality of electronic chips 130 with different types of conversion units 132. Alternatively, all electronic chips 130 of the plurality of electronic chips 130 may comprise the same type of conversion unit 132, i.e. an analog-to-digital conversion unit 133 or a digital-to-analog conversion unit 134 or a conversion unit comprising an analog-to-digital conversion unit 133 and a digital-to-analog conversion unit 134.

The device 100 comprises a trace structure 140 between the plurality of electronic chips 130 and the plurality of electrodes 120. The trace structure 140 has conductive traces 142 that connect each of the plurality of electrodes 120 to one of the plurality of electronic chips 130. Fig. 1 shows exemplarily a trace structure 140 with conductive traces 142 connecting a first electrode 120i, a second electrode 120₂ and a third electrode 120s to the first electronic chip 130i and with conductive traces 142 connecting a fourth electrode 1204, a fifth electrode 120s, a sixth electrode 120e and a seventh electrode 120? to the second electronic chip 130₂. Each electrode 120 of the plurality of electrodes 120 is associated with one of the plurality of electronic chips 130.

The multilayer structure may additionally, i.e. in addition to the electrode layer 106 and the chip layer 102, comprise a trace structure layer 104, i.e. a third layer, comprising the trace structure 140. The chip layer 102, the trace structure layer 104 and the electrode layer 106 may be arranged in this order in the z-direction, i.e. the trace structure layer 104 may be arranged between the electrode layer 106 and the chip layer 102. Each electronic chip 130 may comprise pins 136, i.e. conductive surface areas. The trace structure 140 may be configured to connect each electrode 120 to the respective electronic chip 130 via the pins 136, wherein each electrode 120 is connected to one of the pins 136 of the respective electronic chip 130. Each electrode 120 of the plurality of electrodes 120 is associated with one of the pins 136 of the respective electronic chip 130. It is not necessary that each pin 136 is connected to an electrode 120, e.g., in Fig. 1 only three of four pins 136 of the first electronic chip 130i are connected to a respective electrode 120. At maximum, there is one electrode 120 per pin 136. The conductive traces 142 of the trace structure 140 may bijectively, see the second electronic chip 1302, or injectively, see the first electronic chip 130i , connect electrodes 120 of the plurality of electrodes 120 to pins 136 of the respective electronic chip 130.

For example, the plurality of electrodes 120 may comprise subsets of electrodes 120, wherein each subset of electrodes 120 is associated with one of the plurality of electronic chips 130. The plurality of electrodes 120 may comprise one subset of electrodes 120 per electronic chip 130 of the plurality of electronic chips 130. Fig. 1 shows exemplarily a first subset of electrodes 120 comprising the first electrode 120i , the second electrode 12O2 and the third electrode 12O3 and a second subset of electrodes 120 comprising the fourth electrode 1204, the fifth electrode 120s, the sixth electrode 120e and the seventh electrode 12O7, wherein the first subset of electrodes 120 is associated with the first electronic chip 130i and the second subset of electrodes 120 is associated with the second electronic chip 1302. For each subset of electrodes 120, the conductive traces 142 of the trace structure 140 may connect the respective electrodes 120 either injectively, see the first subset of electrodes 120 and the first electronic chip 130i, or bijectively, see the second subset of electrodes 120 and the second electronic chip 1302, to the pins 136 of the respective electronic chip 130.

The trace structure 140, for example, has at least one redistribution layer and is adapted for redistributing, for each of the plurality of electronic chips 130, a respective pin-pattern of the respective electronic chip 130 to at least a part of an electrode-pattern of the plurality of electrodes 120 or vice versa. Fig. 1 shows exemplarily a redistribution of a pin pattern in form of a two dimensional array to an electrode pattern in form of a serial arrangement, e.g. a 2x2 pin pattern of the first electronic chip 130i is redistributed to a 1 x3 electrode pattern and a 2x2 pin pattern of the second electronic chip 1302 is redistributed to a 1x4 electrode pattern. The redistribution layer allows to realize different electrode patterns independent of a predetermined pin pattern of an electronic chip 130 of the plurality of electronic chips 130.

Fig. 1 shows exemplarily that electrodes 120 associated with an electronic chip 130 are connected to the conversion unit 132 of the respective electronic chip 130. For example the electrodes 120i to 120s are connected to the conversion unit 132i of the first electronic chip 130i and the electrodes 1204 to 120? are connected to the conversion unit 132₂ of the second electronic chip 130₂. In case of a respective conversion unit 132 comprising both the analog-to-digital conversion unit 133 and the digital-to-analog conversion unit 134, all electrodes 120 associated with the respective electronic chip 130 may be connected to both the analog-to-digital conversion unit 133 and the digital-to-analog conversion unit 134. Alternatively, some of the associated electrodes 120 may be connected to the analog-to- digital conversion unit 133 and/or some of the associated electrodes 120 may be connected to the digital-to-analog conversion unit 134 and optionally some of the associated electrodes 120 may be connected to both the analog-to-digital conversion unit 133 and the digital-to- analog conversion unit 134. Fig. 1 shows exemplarily for electrodes 120 associated with the second electronic chip 130₂, that the electrode denoted with the reference numeral 120s is connected to both the analog-to-digital conversion unit 133 and the digital-to-analog conversion unit 134 of the second electronic chip 130₂ and that the electrode denoted with the reference numeral 120e is connected to the analog-to-digital conversion unit 133 of the second electronic chip 130₂.

An electrode 120 of the plurality of electrodes 120 may obtain from a digital-to-analog conversion unit 134, to which the respective electrode 120 is connected, an analog signal and provide same as a stimulus.

An electrode 120 of the plurality of electrodes 120 may provide to an analog-to-digital conversion unit 133, to which the respective electrode 120 is connected, an analog signal, e.g., a biosignal, detected by the respective electrode 120.

Optionally, one or more electronic chips 130 of the plurality of electronic chips 130 comprise two or more conversion units 132, each comprising at least one of an analog-to-digital conversion unit 133 and a digital-to-analog conversion unit 134. For example, subsets of up to four electrodes 120 associated with the respective electronic chip 130, i.e. subsets comprising one to four electrodes, may be connected to a common conversion unit 132, e.g., a first subset of associated electrodes 120 may be connected to a first one of the two or more conversion units 132 of a respective electronic chip 130 and a second subset of associated electrodes 120 may be connected to a second one of the two or more conversion units 132 of the respective electronic chip 130. According to an embodiment the respective electronic chip 130 may comprise for each associated electrode a separate conversion unit

132 comprising at least one of an analog-to-digital conversion unit 133 and a digital-to- analog conversion unit 134.

A herein discussed analog-to-digital conversion unit 133 may comprise a multiplexer. This may especially be the case when the respective analog-to-digital conversion unit 133 is connected to two or more electrodes 120. The respective analog-to-digital conversion unit

133 may be configured to digitize analog signals obtained from the two or more electrodes 120 connected to the respective analog-to-digital conversion unit 133 one after the other using the multiplexer.

The analog signals obtained from the two or more electrodes 120 may represent signals detected by the two or more electrodes 120, e.g., from a surrounding of the device 100. The analog signals may represent biosignals.

A herein discussed digital-to-analog conversion unit 134 may comprise a demultiplexer. This may especially be the case when the respective digital-to-analog conversion unit 134 is connected to two or more electrodes 120. The digital-to-analog conversion unit 134 may be configured to convert digital signals one after the other into analog signals using the demultiplexer and provide individual analog signals to the two or more electrodes 120 connected to the respective digital-to-analog conversion unit 134. Each obtained analog signal may be provided to one of the two or more electrodes 120 connected to the respective digital-to-analog conversion unit 134. The respective electrode 120 may be configured to provide the analog signal as a stimulus, e.g., for stimulating tissue or neurons.

There might be some further electronic components between the respective conversion unit 132 and the electrodes 120 connected to the respective conversion unit 132.

A herein described device 100 may have dimensions of 2 to 190 mm in x-direction, i.e. along an axis along which the plurality of electronic chips 130 are serially arranged.

An electronic chip 130 implemented in one of the herein described devices 100 may have dimensions of two to ten mm in x-direction, i.e. along an axis along which the plurality of electronic chips 130 are serially arranged. Fig. 2a to 2e show different electronic chip configurations in the top view. The plurality of electronic chips 130 embedded in the substrate 1 10 of one of the herein described devices 100 may comprise electronic chips 130 of one or more of the configurations described with regard to Fig. 2a to 2e.

Generally speaking, each electronic chip 130 comprises two or more pins 136, e.g., CMOS pads. In Fig. 2a to 2e the pins 136 are numbered from 1 to 20 or rather from 1 to XX or to YY, wherein pins 136 with three dots together with the pins 136 denoted with XX and YY make it clear that different numbers of pins 136 can be realized. The plurality of pins 136 may represent metal pads, e.g., comprising aluminum material, e.g., see Fig. 2a and Fig. 2e. Optionally the metal pads may be covered by conductive material, e.g., Pt-material, TiN- material, IrOx-material or PEDOT-material, e.g., see Fig. 2b to 2d. Exemplarily the pins 136 are arranged in a 2xn array. Alternative arrangements of the pins 136 are also possible.

Additionally to the pins 136, the respective electronic chip 130 may comprise contacts 138i to 138s. The respective electronic chip 130 may be connected to connecting lines via the contacts 138i to 138s. For example, a first contact 138i and a second contact 1382 may be configured to connect the respective electronic chip 130 to two power supply lines, a third contact 138s may be configured to connect the respective electronic chip 130 to a clock line and a fourth contact 1384 and a fifth contact 138s may be configured to connect the respective electronic chip 130 to two data lines (e.g., a forward path and a backward path). An electronic chip 130 may be connected to a communication unit, e.g., an input and/or output or a base, via the connecting lines. Two or more electronic chips 130 may be serially connected via the connecting lines.

A herein described electronic chip 130 may be configured to provide per channel, i.e. per electrode 120, depending on configurations between 7 and 12 Bit raw data with a sampling rate of up to 20000 per second. However, it is also possible to use electronic chips 130 configured to provide per channel less than 7 Bit raw data or more than 12 Bit raw data with a sampling rate of up to 20000 per second or more than 20000 per second. This results in 140-240kbit/sec per channel. A group of 128 electrodes provides data of 17.9- 30.72 Mbit/sec. This amount of data can be transmitted via one data line. For transferring more data it might be advantageous to parallelize the data transfer. For example, to record signals of 512 electrodes 120 it would be advantageous to use four data lines. This calculations are for cases, where raw data is obtained from the electrodes 120. Since individual electronic chips 130 can be deactivated or can be used with a smaller sampling rate, it is also possible to implement less data lines as a maximum of needed data lines.

Therefore, it might be advantageous to combine a serial connection of electronic chips 130 and a parallel connection of electronic chips 130. For example, the plurality of electronic chips 130 are partitioned into subsets of electronic chips 130. Within each subset of electronic chips 130, the respective electronic chips 130 are connected serially with respect to each other and the subsets of electronic chips are connected parallel with respect to each other. It has been found that it is advantageous, when a subset of electronic chips 130 is associated with a maximum of 128 electrodes 120 of the plurality of electrodes 120.

The contacts 138i to 138s can be implemented in different ways, e.g., as metal pads, e.g., comprising aluminum material, see Fig. 2a and Fig. 2b, or as vias, e.g., as through-silicon- vias (TSVs), see Fig. 2c to 2e.

Different arrangements of the contacts 138i to 138s are possible, e.g., a serial arrangement in the x-direction, see Fig. 2a to 2c, or a serial arrangement in the y-direction, see Fig. 2d and 2e. In other words the contact 138i to 138s may be arranged in a row, e.g., in a 1 xn array of contacts, or in a column, e.g. in an nx1 array of contacts.

Fig. 2a to 2e show exemplarily all contacts 138i to 138s arranged at one end of the respective chip 130. However, it is also possible that some contacts are positioned at one end of the electronic chip 130 and the other contacts are positioned at an opposite end of the electronic chip 130, wherein the pins 136 are arranged in-between, e.g., see Fig. 3 and Fig. 4.

Fig. 3 and Fig. 4 show devices 100, which can comprise features and/or functionalities as described with regard to Fig. 1 . Fig. 3 and Fig. 4 show each two devices 100 differing among each other in that the upper device 100 comprises a trace structure 140 without a redistribution layer and the lower device 100 comprises a trace structure 140 with a redistribution layer 144.

Exemplarily, two electronic chips 130 are embedded within a substrate 110 of the shown devices 100. On a main surface area 1 12 of the substrate 1 10 a plurality of electrodes 120 is arranged. The trace structure 140 connects each of the electrodes 120 with one of the two electronic chips 130. According to an embodiment Fig. 3 and Fig. 4 may only show sections of a device 100 and the respective device 100 may comprise further electrodes 120 and further electronic chips 130. For example, the respective device 100 may comprise two or more of the respective shown section connected with each other.

In the upper device 100 in Fig. 3 and Fig. 4 the trace structure 140 comprises conductive traces, e.g., vias, running vertically up from pins of the respective electronic chip 130 to associated electrodes 120 on the main surface area 112 of the substrate 110. A pattern defined by the position of the pins on the respective electronic chip 130 is reproduced on the main surface area 112 of the substrate 110 by the electrodes 120 connected to the respective electronic chip 130.

In the lower device 100 in Fig. 3 and Fig. 4 the trace structure 140 comprises conductive traces running vertically and laterally within the substrate 1 10. The trace structure 140 comprises conductive traces with first vertical portions, e.g., vias, running up from pins of the electronic chips 130 to the redistribution layer 144. Within the redistribution layer 144 the conductive traces may comprise lateral portions running parallel to the main surface area 1 12. Further, the conductive traces may comprise second vertical portions, e.g., vias, running up from the redistribution layer 144 to the electrodes 120. Optionally, the trace structure 140 may comprise more than one redistribution layer 144, wherein neighboring redistribution layers are connected by vertical portions, e.g., vias, of the conductive traces and a last redistribution layer, i.e. the layer closest to the plurality of electrodes 120 in z- direction, is connected to the electrodes 120 by vertical portions, e.g., vias, of the conductive traces. The one or more redistribution layers 144 are adapted for redistributing, for each of the two electronic chips 130, a respective pin-pattern of the respective electronic chip 130 to at least a part of an electrode-pattern of the plurality of electrodes 120 or vice versa. For example, the pins on the electronic chips 130 may be equally spaced, whereas the electrodes 120 may be spaces differently. Fig. 3 and Fig. 4 show exemplarily an equally spaced serial arrangement of pins on the electronic chips 130. This pin pattern is redistributed by the redistribution layer onto an electrode pattern with outer electrodes of a serial arrangement of electrodes 120 having a greater distance to inner electrodes than the inner electrodes have between each other. The redistribution layer 144 can be configured to position the electrodes 120 at positions that are not only on top of the pins of the respective electronic chip and vertically spaced from the electronic chips 130 but also so that same cover the gaps between the electronic chips 130. The redistribution layer 144 allows an efficient adaptation of an electrode arrangement on the substrate 1 10 dependent on an application of the device 100 and at the same time the usage of electronic chips 130 with a predefined pin pattern. Thus, application specific devices can be produced more efficiently than having to adapt the pin pattern on each electronic chip 130.

The electronic chips 130 of the devices 100 shown in Fig. 3 and 4 are serially connected. As described with regard to Fig. 2a to 2e, the electronic chips 130 may comprise contacts for connecting the respective chip to connecting lines 148. Exemplarily, the electronic chips 130 shown in Fig. 3 and 4 comprise one or more contacts at two opposing ends of the respective electronic chip 130, wherein the pins are arranged between the contacts. The contacts and the pins are arranged on a surface of the respective electronic chip 130 facing the electrodes 120. The opposing ends represent ends of the respective electronic chip 130 along an x-direction, e.g., along a direction being parallel to an axis along which the electronic chips 130 are arranged in a serial arrangement.

The contacts of the devices 100 shown in Fig. 3 may be implemented as metal pads arranged on the surface of the respective electronic chip 130 facing the electrodes 120. Alternatively, the contacts may be implemented as vias, e.g., as through-silicon-vias, as exemplarily depicted in Fig. 4 with regard to the lower device 100 or as metal pads arranged on a surface of the respective electronic chip 130 facing away from the electrodes 120, as shown with respect to the upper device 100 in Fig. 4. The vias enable to connect the respective electronic chip 130 to the connecting lines 148 on the side facing the electrodes and/or on the opposite side. Some contacts may be connected to a connecting line 148 on the upper side, i.e. the side facing the electrodes 120, some contacts may be connected to a connecting line 148 on the lower side, i.e. the side opposite to the side facing the electrodes 120, and some contacts may be connected to a connecting lines 148 on both sides. A connection on both sides is more robust, especially with regard to defects, like a breakage of a connection line 148.

Fig. 5 shows an excerpt of a herein described device 100. Fig. 5 shows a top view illustrating schematically how an electrode pattern on a substrate surface 112 of the device 100 may differ from a pin pattern on an electronic chip 130 embedded within the substrate due to a redistribution layer comprised by a trace structure of the device 100. The two-sided arrows show how the redistribution layer redistributes the positions of the pins 136 on an electronic chip 130 to positions of the electrodes 120 on a surface of the substrate of the device 100. The pins 136, for example, may be arranged on a surface of the respective electronic chip 130 in two rows, e.g., in a 2xn array, wherein n is a positive integer of at least two. The electrodes 120 associated with the respective electronic chip 130, i.e. the electrodes 120 connected to the respective electronic chip 130, may also be arranged in two rows, but with a different lateral spacing between at least some of the electrodes 120 compared to a spacing between the pins 136. For example, the electrodes 120 may be arranged in a 2xm array, wherein m is a positive integer equal to or less than n. Alternatively, two rows with different numbers of electrodes 120, or only one row of electrodes or more than two rows of electrodes 120 or individual arrangements of the electrodes 120 are possible. A number of electrodes 120 associated with a respective electronic chip 130 may be equal to or less than the number of pins 136 comprised by the respective electronic chip 130.

Fig. 5 shows exemplarily an electrode pattern comprising electrodes 120 associated with an electronic chip 130. The electrode pattern comprises two electrodes 120 positioned vertically above the electronic chip 130 and further electrodes 120 being positioned vertically and laterally spaced with respect to the electronic chip 130.

A herein described device 100 may comprise a plurality of electrodes 120 and a plurality of electronic chips 130, wherein each electronic chip 130 is associated with a unique subset of electrodes 120 of the plurality of electrodes 120. A subset of electrodes 120 associated with an electronic chip 130 may comprise a number of electrodes 120 being equal to or smaller than a number of pins 136 of the respective electronic chip 130.

Fig. 5 shows exemplarily an electronic chip 130 with contacts 138 surrounding the pins 136. The contacts 138 are arranged on a chip surface facing the electrodes 120 on four sides of the respective electronic chip 130. The contacts 138 may be realized as metal pads on the chip surface or as vias.

Fig. 6 shows a device 100 in a side view. The device 100 may be implemented similarly as the lower device 100 in Fig. 3 with at least two electronic chips 130 embedded in a substrate 110, with a plurality of electrodes 120 arranged on a main surface area 112 of the substrate 110 and with a trace structure 140 comprising a redistribution layer 144, wherein the trace structure 140 connects each of the a plurality of electrodes 120 with one of the two or more electronic chips 130.

A difference between the device 100 in Fig. 6 and the device 100 in Fig. 3, for example, is that the plurality of electrodes 120 are arranged in two rows in Fig. 6 and in one row in Fig. 3. The rows of electrodes 120, for example, run parallel to an axis along which the two or more electronic chips 130 are serially arranged. The two row arrangement of the electrodes 120 is indicated in Fig. 6 by the blocks with the numbers above the device 100, wherein each number may indicate a pin with which the respective electrode 120 is associated, i.e. a number of a pin of the electronic chip 130 with which the respective electrode 120 is connected, e.g., compare with Fig. 5. Pairs of electrodes 120 may be aligned along the y-direction, i.e. two electrodes 120 may be positioned behind each other in the y-direction, e.g. forming a column of two electrodes. The electrodes 120 may be spaced differently within a row along an x-direction. Fig. 6 shows exemplarily that both rows of electrodes 120 have the same spacing between the respective electrodes 120 along the x-direction. Exemplarily, the electrodes 120 are positioned on the main surface area 112 so that also areas between two adjacent electronic chips 130 are covered, e.g., see the electrodes 120 associated with the pins numbered 2, 3, 6 and 7.

The two electronic chips 130 shown in Fig. 6 may have the same pin pattern, but different electrode pattern, i.e. the electrodes 120 associated with one of the two electronic chips 130 may be arranged differently on the main surface area 1 12 of the substrate 110 than the electrodes 120 associated with the other one of the two electronic chips 130. This adaptation of a pattern defined by the pins of the respective electronic chip 130 onto a pattern defined by electrodes 120 associated with the respective electronic chip 130 may be realized by the redistribution layer 144.

Optionally an electronic chip 130 of the two or more electronic chips 130, which is arranged at one end of the device 100, e.g., in x-direction, may comprise a tip 150 or may be fixed to a tip 150, wherein the tip 150 faces the one end of the device 100. The tip 150 may pierce through the substrate 110, so that at least a part of the tip 150 emerges from a surface being perpendicular to the main surface area 1 12. Such an arrangement allows the device 100 to be inserted better into tissue. A device 100 comprising a tip 150 at one end, i.e. at an end along the axis along which the two or more electronic chips 130 are serially arranged, may represent a recording and/or stimulation needle, e.g., a neuronal probe.

It is to be noted that the figures are not to scale. For example, considering Fig. 6, the horizontal extension of the electronic chips 130 is at least ten times compressed compared to other dimensions. Fig. 7 shows on the top an excerpt of a herein described device 100 and on the bottom a detailed view of a loop 115 of the substrate 110 of the device 100, which is arranged at one end of the device 100. The excerpt of the device 100 shows only the one end with one electronic chip 130 and associated electrodes 120. However, the device 100 comprises at least two electronic chips 130 with respective associated electrodes 120.

For example, at one end of a serial arrangement of the two or more electronic chips 130 of the device 100, the device 100 may comprise a connection region, e.g., a connection portion, for a connection of the substrate 1 10 with a stylet 200. The connection region may be positioned at an end along an axis along which the two or more electronic chips 130 are arranged, e.g., along the x-direction. Fig. 7 shows exemplarily a connection region comprising the loop 1 15, e.g., a ring, formed in the substrate 1 10. The loop 115 is configured to fix the device 100 to the stylet 200.

Alternatively to the loop 1 15 the connection portion may comprise a pocket as described with regard to Fig. 10 to 15.

Alternatively or additionally to the loop 1 15 or the pocket, the connection portion may comprise at least a part of a surface area of the substrate 110, wherein the surface area is facing away from the plurality of electrodes 120, i.e. the surface area may represent a surface opposite to the main surface area 1 12. The part of the surface area may be covered by an adhesive, so that the device 100 is fixable to the stylet 200 via the connection portion. The adhesive may be biocompatible. Optionally, the adhesive may be dissoluble, e.g., by certain fluids, bio fluids, tissue fluids or body fluids, so that the stylet 200 is removable after an insertion of the device 100 into tissue.

According to an embodiment, an electronic chip 130 positioned at the end of the device 100 at which the connection region is arranged may be tapered or the device 100 may be tapered at the end at which the connection region is arranged. This increases an insertability of the device 100 into tissue.

At the bottom of Fig. 7, for example, a top view of a base layer of the substrate 110 is shown, e.g., a polyimide-cable, with a hole, see the opening 1 14, etched in the middle of the end of the substrate 1 10 to receive the stylet 200, see the loop 1 15, etched for releasing the ring with the stylet hole. The ring can be pulled up to insert the stylet 200. The base layer for the stylet hole is, for example, depicted at the YY’-cross section and a second layer for connecting lines, for example, is depicted at the XX’ -cross section. The base layer may also be used as a base for the two or more electronic chips 130 of the device 100.

The base layer of the substrate 1 10 may comprise an extension portion extending in the x- direction further than one or more further layers of the substrate 110, like the chip layer 102, the trace structure layer 104 and the electrode layer 106 shown in Fig. 1 . The opening 114 may be arranged in the extension portion of the base layer, e.g., so that a loop 115 is formed in the substrate 1 10.

In other words, the device 100 may comprise an opening 114, e.g., a slit or a hole, extending vertically through the device 100, i.e. perpendicular to a plane in which the two or more electronic chips 130 are arranged. For example, the opening may reach from a surface area 113 of the base layer to an opposite side of the substrate 110, wherein the surface area 113 of the base layer is facing the two or more electronic chips 130, e.g., the two or more electronic chips 130 may be arranged on the surface area 113 of the base layer.

A cross section of the opening 114 may not necessarily be round or oval, as shown in Fig. 7. Alternative shapes, like a square shape, a rectangular shape, triangular shape or polygonal shape, may also be possible.

Fig. 8 shows a three-dimensional view of an end portion of a herein described device 100. The end portion shows the device 100 at an end of a serial arrangement of two or more electronic chips 130. The end portion comprises a connection region, e.g., a connection portion. The connection region may comprise a loop 115. A stylet 200 is fixable to the device 100 via the connection region, e.g., by passing a tip of the stylet 200 through the loop 1 15.

As shown in Fig. 8, a plurality of electrodes 120, e.g., electrode contacts, associated with the shown electronic chip 130, e.g., a chiplet or CMOS chiplet, are arranged on a main surface area 1 12 of the substrate 1 10 of the device 100, wherein the associated electrodes 120 are arranged differently on the main surface area 1 12 than a pattern defined by pins of the shown electronic chip 130. Parts of the pin pattern may be reflected in the respective electrode pattern, i.e. may be identical. For example, some electrodes 120 may be positioned vertically above, i.e. in z-direction, the respective pin, e.g., using vias 146. Other electrodes 120 associated with the shown electronic chip 130 may be positioned laterally offset with respect to a projection of the respective pins of the shown electronic chip 130 onto the main surface area 112, e.g., using flat tracks 145 within a redistribution layer of the device 100. The other electrodes 120 may be positioned laterally offset along an axis along which the two or more electronic chips 130 may be arranged serially, e.g., so that at least some of the other electrodes 120 are arranged on the main surface area 112 between two adjacent electronic chips 130.

The loop 1 15 in the connection region of the device 100 may be formed by an opening 1 14. The opening may extend through the substrate 110 from the main surface area 1 12 to an opposite side of the substrate 110. The loop 115 may represent an anchor loop for the stylet 200, e.g., an insertion tool.

According to an embodiment, the substrate 1 10 may represent a flat flexible organic cable.

Fig. 9 shows a device 100, which may have features and/or functionalities as described with regard to the device in Fig. 6, especially with regard to the electronic chips 130, the trace structure 140 and the electrodes 120.

The substrate 1 10 of the device 100 may be tapered at an end of a serial arrangement of the two or more electronic chips 130. The tapered area of the substrate may comprise a connection portion, e.g., comprising a loop 1 15, for a connection of the device 100 with an insertion tool, e.g., a stylet 200. The loop 115 or connection portion may be implemented as described with regard to Fig. 7 or Fig. 8. The stylet 200 can be retracted after insertion of the device 100 into tissue. The stylet 200 is configured for pushing and penetrating during insertion and to be removed afterwards for chronic experiments.

Additionally, or alternatively, for example, a last electronic chip 130 of the two or more electronic chips 130 may be tapered or may comprise a tip fixed to a surface facing the end of the serial arrangement of the two or more electronic chips 130.

The implantation process is gentle for the neural tissue in comparison to other invasive electrodes. The device’s 100 size and flexibility allow for a minimally invasive implantation and an enhanced lifetime. The device 100 can be implanted through the dura mater with the help of an inserter needle, e.g., the stylet 200, avoiding the necessity to make large craniotomies, or open the dura during implantation.

Alternatively to the loop 1 15, a herein described device 100 may comprise a connection portion comprising a pocket 1 18 as shown in Fig. 10. A stylet 200 is insertable into the pocket 1 18. The pocket 118 is configured to fix the device 100 to the stylet 200, wherein the stylet is removable from the pocket 1 18. For acute experiments the stylet 200 may be part of the pocket 118, e.g., a tube, and stays in. For chronic experiments the stylet 200, for example, is a little narrower than the pocket 118 and can be retracted after insertion of the device 100 into tissue.

The pocket 1 18 is formed within the substrate 1 10 of the device 100. The pocket 118 may represent a cavity within the substrate 1 10 with one opening through which an insertion tool, e.g., the stylet 200, is insertable into the pocket 118. The pocket 118 is configured, so that the insertion tool is insertable parallel to an axis along which the plurality of electronic chips 130 are serially arranged.

The pocket 118 may be arranged on a side of the device 100 being opposite to the main surface area 112 on which the plurality of electrodes 120 are arranged. For example, the pocket 118 may be arranged vertically below the plurality of electronic chips 130. The pocket 118, the chip layer 102, the trace structure layer 104 and the electrode layer 106 of the device 100 may be arranged in this order in the vertical direction, i.e. in the z-direction, e.g., in a direction perpendicular to an area in which the plurality of electronic chips 130 are arranged. The pocket 1 18 is arranged on a side of the device 100 being opposite to a side on which the plurality of electronic chips 130 are arranged.

As shown in Fig. 10, the pocket 1 18 may extend/run parallel to an axis along which the plurality of electronic chips 130 are serially arranged, i.e. parallel to the x-direction. Along this direction the pocket 1 18 is closed at one side and open at an opposite side, e.g., a closed end of the pocket 118 faces a first end of the serial arrangement of the plurality of electronic chips 130 and an open end of the pocket 1 18 faces a second end of the serial arrangement of the plurality of electronic chips 130, wherein the first end is opposite to the second end. The pocket 1 18 may end at an end of the serial arrangement of the plurality of electronic chips 130. The pocket 1 18 is closed at this end. As shown in Fig. 10, this may also be the end of the device 100. The pocket 118, for example, may be arranged at one end of the device 100 along the x-direction. It is not necessary that the pocket 18 runs along the complete length of the device 100.

The device 100 may be tapered at the end of the serial arrangement of the plurality of electronic chips 130. The pocket 118 may also be tapered at its closed end, especially if same goes up to the end of the device 100, see Fig. 10. Optionally, the pocket 118 may at least partially be perforated, as shown in Fig. 1 1. For example, a wall of the pocket 118 facing away from the plurality of electronic chips 130 of a herein described device 100 may be perforated. Optionally, additionally or alternatively, one or both sides, i.e. sidewalls, of the pocket 118 being arranged perpendicular to the wall of the pocket 1 18 facing away from the plurality of electronic chips 130 may be perforated. For example, considering the cross section of a herein described device 100 shown in Fig. 12, at least parts of a first pocket wall 118a, a second pocket wall 118b and/or a third pocket wall 1 18c of a pocket 1 18 may be perforated. The first pocket wall 1 18a, the second pocket wall 118b and the third pocket wall 118c do not comprise a wall 118d being arranged adjacent to the chip layer 102 of a herein described device 100. An at least partially perforated pocket 1 18 allows an easier etching of a sacrificial layer.

For example, at a manufacturing of a herein described device 100 a sacrificial layer may be formed within the substrate 110 of the device 100. The sacrificial layer is etched away to form a cavity within the substrate 1 10. The cavity may represent the pocket 1 18. The sacrificial layer may have the form of a stylet 200, which is insertable into the cavity formed within the substrate 1 10. The sacrificial layer may represent a place holder for the stylet 200. Alternatively, the sacrificial layer may represent the stylet or part of the stylet 200. The sacrificial layer may, e.g., for chronic experiments, be configured to dissolve after the stylet 200 is inserted into the tissue.

Fig. 1 1 and 12 show a device 100 with a deep cavity in the substrate 110. Such a configuration is especially advantageous for acute applications of the device 100. For acute applications the stylet 200 may be fixed to the substrate of the device 100 via the deep pocket 1 18. The stylet 200 may have a cuboidal or a round, circular cross section.

Fig. 13a and 13b show an embodiment of a herein described device 100 with a pocket 1 18 into which no stylet is inserted. Fig. 13b shows a top view of an end portion of a herein described device 100 or a longitudinal section through the end portion and Fig. 13a shows cross sections through a herein described device 100.

The pocket 1 18 is formed by a cavity within the substrate 1 10 of a herein described device 100. The substrate 1 10 comprises the cavity at a side opposite to the side on which the plurality of electrodes are arranged. For example, the cavity is arranged at the chip side of the substrate 1 10. As can be seen in Fig. 13a and 13b, the pocket 1 18 may be flat without a stylet being inserted. Due to the substrate 1 10 comprising flexible material the flat pocket 118 can open up to receive the stylet.

As depicted in Fig. 13a, the cavity may be sandwiched between a first pocket layer 1 19a of the substrate 1 10 and a second pocket layer 1 19b of the substrate 1 10. The first pocket layer 1 19a, the cavity, the second pocket layer 119b, the chip layer 102, the trace structure layer 104 and the electrode layer 106 of the device 100 may be arranged in this order in the vertical direction, i.e. in the z-direction, e.g., in a direction perpendicular to an area in which the plurality of electronic chips 130 are arranged.

At a manufacturing of the device 100 a sacrificial layer may be sandwiched between the first pocket layer 119a and the second pocket layer 119b and the sacrificial layer is then etched away or dissolved to allow an opening/separation of the first pocket layer 119a and the second pocket layer 119b, i.e. to form the cavity. As described with regard to Fig. 11 and 12, the first pocket layer 119a may be perforated to allow easier etching or dissolving of the sacrificial layer.

Fig. 13a and 13b show a device 100 with a flat cavity in the substrate 1 10. Such a configuration is especially advantageous for chronic applications of the device 100. For chronic applications the stylet may be removable from the pocket 118. The pocket 1 18, for example, is configured to open up when a stylet is inserted into the pocket 110. Optionally, the pocket 1 18 is further configured to return back to its flat shape when a stylet is removed from the pocket 1 18. This may reduce tissue damage at chronic applications.

The pocket, for example, is formed by a flat but wide cavity, e.g., wider than a width of an electronic chip of the plurality of electronic chips, and, for example, by polyimide-layers that can open up to receive the stylet. The width of an electronic chip or the pocket 1 18, for example, represents an extension/dimension perpendicular to an axis along which the plurality of electronic chips 130 are serially arranged, i.e. the width may extend parallel to the y-direction. As shown in Fig. 13a and 13b, the device 100 may be tapered at the end portion and thus, also a width of the pocket 1 18 may decrease along the x-direction, i.e. in the direction of an end of the device 100, e.g. at which a tip is formed. This is especially the case when the pocket 1 18 reaches up to the tip of the device 100. This increases an insertion efficiency of the device 100 into tissue. Fig. 14a and 14b show a device 100 with a plurality of electronic chips 130 and a plurality of electrodes configured to be arranged on two or more side walls of a pocket 1 18 of a herein described device 100. Fig. 14b shows a top view of an end portion of a herein described device 100 or a longitudinal section through the end portion and Fig. 14a shows cross sections through a herein described device 100. The top most cross section in Fig. 14a shows a herein described device 100 with a stylet 200 being inserted into its pocket 118 and the two cross section at the bottom of Fig. 14a show a herein described device 100 without a stylet 200 being inserted into its pocket 1 18 at different positions along the x- direction.

The device 100 may comprise a first set of electrodes 120a, e.g., the herein described plurality of electrodes or a first plurality of electrodes, and a second set of electrodes 120b, e.g., a further plurality of electrodes or a second plurality of electrodes. The first set of electrodes 120a and the second set of electrodes 120b may be arranged laterally spaced on a main surface area 112 of a substrate 1 10, see the two lower cross sections in Fig. 14a. A trench 160 within the main surface area 112 may separate the first set of electrodes 120a from the second set of electrodes 120b. The trench may run parallel to an x-axis. The trench 160 may be configured to tilt apart a first portion of the substrate 1 10 comprising the first set of electrodes 120a and a second portion of the substrate 1 10 comprising the second set of electrodes 120b, when a stylet 200 is inserted into the pocket 118, see the top most cross section in Fig. 14a.

Further, the device 100 may comprise a first set of electronic chips 130a, e.g., the herein described plurality of electronic chips or a first plurality of electronic chips, and a second set of electronic chips 130b, e.g., a further plurality of electronic chips or a second plurality of electronic chips. The first set of electronic chips 130a are embedded in the substrate 1 10 in a serial arrangement underneath at least one of the first set of electrodes 120a and the second set of electronic chips 130b are embedded in the substrate 1 10 in a serial arrangement underneath at least one of the second set of electrodes 120b. In other words, the first set of electronic chips 130a are aligned with the first set of electrodes 120a and the second set of electronic chips 130b are aligned with the second set of electrodes 120b. An axis along which the electronic chips 130a of the first set of electronic chips 130a are serially arranged runs parallel to an axis along which the electronic chips 130b of the second set of electronic chips 130b are serially arranged. The first set of electronic chips 130a and the second set of electronic chips 130b may be laterally spaced. The trench 160, for example, separates the first set of electronic chips 130a from the second set of electronic chips 130b. The electronic chips of the first set of electronic chips 130a and of the second set of electronic chips 130b may be implemented as described with regard to any herein described device 100. For example, the first set of electronic chips 130a and/or the second set of electronic chips 130b may comprise electronic chips of one or more of the configurations described with regard to Fig. 2a to 2e.

The device 100 further comprises a first trace structure 140a, e.g., the herein described trace structure, and a second trace structure 140b, e.g., a further trace structure. The first trace structure 140a has conductive traces that connect each of the first set of electrodes 130a to one of the first set of electronic chips 120a and the second trace structure 140b has conductive traces that connect each of the second set of electrodes 130b to one of the second set of electronic chips 130b.

As shown in the cross sections at the top and in the middle of Fig. 14a, a first portion of the substrate 1 10 comprising the first set of electronic chips 130a, the first trace structure 140a and the first set of electrodes 120a is separated from a second portion of the substrate 110 comprising the second set of electronic chips 130b, the second trace structure 140b and the second set of electrodes 120b by the trench 160. The two portions of the substrate 1 10, i.e. the first portion and the second portion, may be arranged adjacent to each other, e.g., laterally spaced by the trench 160.

The device 100 comprises a pocket 1 18 formed by a cavity within the substrate 1 10. As shown in the middle of Fig. 14a, the two portions of the substrate 1 10 are arranged next to each other on one side of the cavity. As can be seen in Fig. 14a and 14b, the pocket 1 18 may be flat without a stylet 200 being inserted and may be deep, i.e. open up, when the stylet 200 is positioned within the pocket 1 18 of the device 100. When the stylet 200 is positioned within the pocket 1 18, the first portion of the substrate 110 and the second portion of the substrate 1 10 may tilt apart, as shown in the top most of Fig. 14a.

The cavity, for example, has a longitudinal axis parallel to an axis of the serial arrangement of the first set of electronic chips 130a and parallel to an axis of the serial arrangement of the second set of electronic chips 130b.

Considering the top most cross section in Fig. 14a, the pocket 1 18 may comprise a plurality of side walls, e.g., at least three side walls. A first side wall 1 18a of the pocket 118 may comprise the first set of electronic chips 130a, the first trace structure 140a and the first set of electrodes 120a and a second side wall 1 18b of the pocket 1 18 may comprise the second set of electronic chips 130b, the second trace structure 140b and the second set of electrodes 120b. The first set of electronic chips 130a are embedded within the first side wall 1 18a and the first set of electrodes 120a are arranged on an outer surface of the first side wall 1 18a, wherein the outer surface represents a surface facing away from the cavity within the substrate 1 10. The second set of electronic chips 130b are embedded within the second side wall 118b and the second set of electrodes 120b are arranged on an outer surface of the second side wall 1 18b, wherein the outer surface represents a surface facing away from the cavity within the substrate 110.

In the version with the stylet 200 within the pocket 1 18, see the top on Fig. 14a, the cavity comprises two side walls parallel to a first side of the substrate 1 10 and two side walls perpendicular to the first side, wherein the first set of electrodes 120a are arranged on the first side of the substrate 1 10. A second side of the substrate 1 10 is arranged perpendicular to the first side and the second set of electrodes 120b are arranged on the second side.

Fig. 14a and Fig. 14b show a device 100 with two portions of the substrate 110 or two side walls of the pocket 1 18 comprising electronic chips, a trace structure and electrodes. However, it is also possible that the device 100 comprises three or more portions or side walls comprising electronic chips, a trace structure and electrodes. Each portion may be configured as described with regard to the first portion or the second portion and each portion may be separated from a neighboring portion by a trench. Each side wall may be configured as described with regard to the first side wall 1 18a or the second side wall 118b. Configurations with two or more of such portions or side walls allow a stimulation and/or a recording in different directions.

According to an embodiment, the electronic chips serially arranged within a portion of the substrate 1 10 or within a side wall are serially connected with respect to each other and optionally with respect to a communication unit, i.e. a base, e.g., an input and/or an output. Electronic chips of different portions of the substrate 110 or of different side walls are connected in parallel with respect to each other and optionally with respect to the communication unit. For example, the electronic chips 130a of the first set of electronic chips 130a are serially connected and the electronic chips 130b of the second set of electronic chips 130b are serially connected, but the electronic chips 130a of the first set of electronic chips 130a are parallel connected to the electronic chips 130b of the second set of electronic chips 130b. As already described with regard to Fig. 13a, the cavity may be sandwiched between a first pocket layer 119a of the substrate 1 10 and a second pocket layer 119b of the substrate 110. The first portion of the substrate 1 10 and the second portion of the substrate 1 10, for example, are arranged on the second pocket layer 1 19b of the substrate 110, e.g., laterally spaced.

At a manufacturing of the device 100 a sacrificial layer may be sandwiched between the first pocket layer 119a and the second pocket layer 119b and the sacrificial layer is then etched away to allow an opening/separation of the first pocket layer 1 19a and the second pocket layer 119b, i.e. to form the cavity. As described with regard to Fig. 11 and 12, the first pocket layer 119a may be perforated to allow easier etching of the sacrificial layer. Considering the top most cross section in Fig. 14a, a side wall in which no electronic chip is embedded may at least partially be perforated, e.g., a third side wall 118c and/or a fourth side wall 1 18d.

The pocket, for example, is formed by a flat but wide cavity, e.g., wider than a width of an electronic chip of the plurality of electronic chips, and, for example, by polyimide-layers that can open up to receive the stylet. The width of an electronic chip or the pocket 118, for example, represents an extension/dimension perpendicular to an axis along which the plurality of electronic chips 130 are serially arranged, i.e. the width may extend parallel to the y-direction. As shown in Fig. 14a and 14b, the device 100 may be tapered at the end portion and thus, also a width of the pocket 1 18 may decrease along the x-direction, i.e. in the direction of an end of the device 100, e.g. at which a tip is formed. This is especially the case when the pocket 1 18 reaches up to the tip of the device 100. This increases an insertion efficiency of the device 100 into tissue.

It is also possible that the device 100 shown in Fig. 14a is realized without the pocket 1 18. That means, for example, that the device looks similar to the device 100 shown in the cross section in the top of Fig. 14a, wherein the stylet 200 is replace by the material of the substrate 1 10. In other words, the substrate may have a solid body with electrodes arranged on different sides of the substrate. Additionally, per side of the substrate on which electrodes are arranged, the substrate may comprise electronic chips 130 embedded in the substrate 110 in a serial arrangement in a plane parallel to the respective side and a trace structure connecting each of the electrodes arranged on the respective side to one of the electronic chips of the respective side. Such an embodiment is also described in more detail with respect to Fig. 29.

As shown in Fig. 10 to 14b, the substrate 110 may have the form of a needle with a tip and a body and the plurality of electrodes 120 are arranged on a surface of the body. The body, for example, is at least partially a hollow body with side walls. The cavity within the body may have the form of a cylinder, a cuboid or any other prism and may extend up to the tip. The cavity within the body may comprise an opening, e.g., a single opening, facing away from the tip. As exemplarily depicted in Fig. 10, the body may only partially be hollow, e.g., only a front part near the tip, and one or more of the sidewalls may further extend, e.g., a side wall in which the plurality of electronic chips 130 and the trace structure are embedded. The body may have at least three side walls. As can be seen in the cross section shown in Fig. 12, the plurality of electronic chips 130 and the trace structure are embedded in one of these side walls, see reference numeral 118d, and the plurality of electrodes 120 are arranged on an outer surface of this side wall 1 18d. Compare also Fig. 14a, in which the plurality of electronic chips 130a and the trace structure 140a are embedded in a first side wall 1 18a and the plurality of electrodes 120a are arranged on an outer surface of the first side wall 118a and in which a further plurality of electronic chips 130b and a further trace structure 140b are embedded in a second side wall 1 18b and a further plurality of electrodes 120b are arranged on an outer surface of the second side wall 1 18b.

Fig. 15 shows an embodiment of a cylindrical device 100, which may be hollow or which may comprise a cavity in the cylinder, e.g., within a cylindrical substrate. A substrate 110 of the device 100 is rolled-up, e.g., using thermo-forming. Within the substrate 110 a plurality of electronic chips 130 are embedded and on a surface facing away from the stylet 200 a plurality of electrodes 120 are arranged. A trace structure between the plurality of electronic chips 130 and the plurality of electrodes 120 has conductive traces that connect each of the plurality of electrodes 120 to one of the plurality of electronic chips 130.

At a manufacturing of the device 100, the substrate 1 10 is rolled-up around a wire, e.g., a stylet 200. A metal cylinder 210 may be used to fold and thermo-form the substrate 110 with the plurality of electronic chips 130, the trace structure and the plurality of electrodes 120. The wire has a diameter 202 in the range of 100 pm to 170 pm. However, in case of long devices 100, i.e. devices with a large extension along their longitudinal direction, the wire may have a diameter 202 greater than 170 pm. According to an embodiment, the device 100 comprises the wire as a stylet 200. In this case, the wire is not removed after the folding and thermo-forming of the substrate 110. The wire may be removable, so that the hollow cylindrical device 100 is obtainable. A stylet 200 may be insertable into the cavity within the cylindrical device 100. The cylindrical cavity in the middle of the substrate 110 may represent a pocket, which is configured to receive a stylet 200.

According to an embodiment, the substrate 110 comprises two or more sets of serially arranged electronic chips 130 with respective associated electrodes 120 arranged laterally spaced from each other, e.g., comparable to the embodiment described with regard to Fig. 14a and 14b, wherein it is in this case not necessary that a trench separates neighboring sets of serially arranged electronic chips 130 with respective associated electrodes 120. Such a configuration allows stimulation and/or recording in multiple directions.

As described above, a herein described device 100 may comprise a connection region or a connection portion for a connection with a stylet 200 for increasing an efficiency at an insertion of the device 100 into tissue. Alternatively, the device 100 may comprise a catheter 220 as shown in Fig. 16 or may be insertable into a catheter as shown in Fig. 16.

The catheter 220 comprises a tube, having a tube shell 222. The tube shell 222 has an opening 224 along a longitudinal axis of the tube. A wall 226 is positioned within the tube. A first cavity 225 is arranged between a first side of the wall 226 and the tube shell 222, and a second cavity 227 is arranged between a second side of the wall 226 opposing the first side and the tube shell 222. The opening 224 in the tube shell 222 is an opening to the first cavity 225. The tube shell 222 and the wall 226 may be integrally formed.

The opening 224 may be at a location of the plurality of electrodes 120 of the probe 100’ or may run along a complete length of the catheter 220. However, the length of the opening 224 does not necessarily have to be the same as the length of the tube. The opening 224 does not have to reach an end of the tube. Optionally, the catheter 220 may comprise two or more openings to the first cavity 225 at locations of the plurality of electrodes 120.

The tube may have an outside-to-outside dimension (OD) in the range of 200 pm to 250 pm, e.g., 230 pm, or in the range of 200 pm to 2000 pm, 200 pm to 1000 pm or 900 pm to 1300 pm. An inside-to-inside dimension (ID) may be in the range of 150 pm to 195 pm, e.g., 180 pm. The wall 226 may have a thickness 226a in the range of 10pm to 100pm or 15pm to 55pm, e.g., 25pm or 50pm. The tube shell 222 may have a thickness 222a in the range of 10pm to 100pm or 15pm to 55pm, e.g., 25pm or 50pm.

The catheter 220 may comprise FEP-material (Fluorethylen-Propylen-material). The catheter may be formed using fluoropolymer extrusion.

A substrate 110 of a herein described device 100 is arranged within the first cavity 225 and the plurality of electrodes 120 arranged on the substrate 110 are aligned with the opening 224. The catheter 220 is configured to clamp the substrate 110 within the first cavity 225, so that the plurality of electrodes 120 have access to an outside of the tube via the opening 224, e.g., so that the plurality of electrodes 120 can get into contact with tissue into which the catheter 220 is insertable. A probe 100’ clamped within the catheter 220 may have features and/or functionalities as described with regard to the device 100 in Fig. 1 to 6.

Optionally, a width of the substrate 1 10, e.g., a dimension along the transverse direction, may be smaller near the main surface area 1 12 on which the plurality of electrodes 120 are arranged and may be greater at the opposite side of the substrate 1 10. For example, the portion of the substrate 110 with the smaller width may have a width in the range of 60 pm to 110 pm, e.g., 70 pm or 100 pm, and a height, i.e. a dimension perpendicular to the transverse direction and the longitudinal direction, in the range of 10 pm to 70 pm, e.g., 20 pm or 50 pm. The portion of the substrate 110 with the smaller width may have a cross section of 20 pm x 70 pm or 50 pm x 100 pm. The portion of the substrate 110 with the greater width may have a width in the range of 120 pm to 160 pm, e.g., 140 pm, and a height in the range of 5 pm to 30 pm, e.g., 15 pm. The portion of the substrate 110 with the greater width may have a cross section of 15 pm x 140 pm.

The portion of the substrate 1 10 with the greater width may expands within the first cavity 225 and prevent that the probe 100’ from falling out of the catheter 220. The portion of the substrate 110 with the smaller width may be positioned within the opening 224. The tube shell 222 may clamp the portion of the substrate 1 10 with the smaller width within the opening 224.

At a manufacturing of the device 100, the probe 100’ may be inserted into a catheter 220, by pulling from an opening at one end where a connector, e.g., a communication unit, will be. The tip at other end of the catheter 220 is then closed. Further, one or more openings to the first cavity 225, e.g., the opening 224, are created on the catheter 220 at one or more probe locations, e.g., at one or more positions of the plurality of electrodes 120, either before or after the insertion of the probe 100’ into the catheter 220. In case of one opening 224, same may be aligned with all of the plurality of electrodes 120, i.e. all of the plurality of electrodes 120 may have access to the outside of the catheter 220 through the opening 224.

Further, the device 100 shown in Fig. 16 may comprise a stylet 200 positioned within the second cavity 227 of the catheter 220. The stylet 200 may have a diameter in the range of 100 pm to 160 pm, e.g., 130 pm.

The wall 226 and/or the tube shell 222 of the catheter 220 may comprise a flexible material. The catheter 220, for example, is configured to clamp the probe 100’, e.g., the substrate 110 of the probe 100’, within the first cavity 225 and the stylet 200 within the second cavity 227 based on the flexible material.

According to an embodiment, a herein described device 100 may be implemented with one or more shafts. Fig. 17 shows exemplarily a device 100 with four shafts. Each shaft may be implemented as described with regard to one of the devices 100 in Fig. 1 to 16.

Fig. 17 shows exemplarily a device 100 with shafts implemented as described with regard to the devices 100 in Fig. 10 to 14b. Each shaft may comprise a substrate 110 that has the form of a needle with a tip 150, e.g., shaft tips, and a body. A plurality of electrodes 120 are arranged on a surface of the respective body. Each shaft may comprise a pocket 1 18, e.g., a cavity or an at least partially hollow body, for an insertion tool like a stylet. The respective hollow body comprises side walls. Within one of the side walls of each shaft a respective plurality of electronic chips 130 and a respective trace structure 140 are embedded and on a surface of the respective side wall the respective plurality of electrodes 120 are arranged. Within each shaft the respective plurality of electronic chips 130 are embedded in the respective side wall in a serial arrangement and with a serial connection, e.g., via connecting lines 148 like digital data lines. The different shafts are connected in parallel, e.g., to a communication unit 170 for data redistribution. The shafts of the device 100 can have different length. Fig. 17 shows exemplarily that the device 100 can comprise electronic chips 130 with different numbers of pins. Further the pin pattern of some electronic chips 130 is reflected by the electrode pattern of the associated electrodes 120, e.g., see the chiplets with electrode contacts near the dura 300, and the pin pattern of some other electronic chips 130 is redistributed to a different electrode pattern of the associated electrodes 120 using a redistribution layer, e.g., see the two chiplets with electrode contacts near the tip 150 of a first shaft.

The substrate 110 may represent a flexible organic multilayer substrate with embedded wiring.

The electronic chips 130 may represent modular recording/stimulating chiplets with on site digitization, e.g., with on site analog-to-digital conversion and/or on site digital-to-analog conversion.

Optionally, the device 100 comprises an external connector 172 connected to the communication unit 170.

The shafts shown in Fig. 17 may represent neuronal probes, e.g., for deep brain recordings and/or stimulations. The shafts may be insertable into a brain through a dura 300.

Fig. 18 on the other hand shows an embodiment of a device 100 for surface recordings and/or stimulations. The device 100 comprises a substrate 110 in which a plurality of electronic chips 130 are arranged in a two dimensional arrangement, i.e. a two-dimensional array of electronic chips 130 is embedded in the substrate 1 10. Further, a plurality of electrodes 120 is arranged on a main surface area 1 12 of the substrate 110. The plurality of electronic chips 130 are arranged in a first plane and the plurality of electrodes 120 are arranged in a second plane, wherein the first plane is parallel to the second plane and wherein an area covered by the plurality of electrodes 120 is aligned with an area covered by the plurality of electronic chips 130.

According to an embodiment, the plurality of electronic chips 120 are partitioned into subsets of electronic chips 120, e.g. into subsets of up to four electronic chips 120. The electronic chips 120 of a subset of electronic chips 120 are connected serially with respect to each other. This may apply to each subset. Further, the subsets of electronic chips 120 are connected parallel with respect to each other.

The arrangement shown in Fig. 18 can also be viewed as an arrangement at which two or more rows 180 of serially arranged electronic chips 130 are embedded next to each other in the substrate 110. Each row 190 may be implemented as described with regard to a device 100 in Fig. 1 , 3, 4 and 5, wherein the rows share the same substrate 110. For example, the device 100 may comprise a substrate 110 with two or more stimulation and/or recording rows 190, wherein each stimulation and/or recording row 190 may comprise

- a plurality of electrodes 120 arranged on the substrate 110, e.g., on a substrate surface of the respective row 190; and

- a plurality of electronic chips 130 embedded in the substrate 110 in a serial arrangement underneath at least one of the respective plurality of electrodes 120, wherein each of the respective plurality of electronic chips 130 comprises a conversion unit that comprises at least one of an analog-to-digital conversion unit and a dig ital-to-analog conversion unit; and

- a trace structure between the respective plurality of electronic chips 130 and the respective plurality of electrodes 120, the trace structure having conductive traces that connect each of the respective plurality of electrodes 120 to one of the respective plurality of electronic chips 130.

The arrangement shown in Fig. 18 may be regarded as a system comprising a plurality of herein described devices 100, e.g., as described with regard to Fig. 1 , 3, 4 and 5, arranged in a two dimensional arrangement next to each other and sharing the same substrate 110.

According to an embodiment, the substrate 1 10 comprises one or more openings 192, e.g., holes and/or slits. The slits, for example, make it easier to adapt the device 100 to a surface, e.g., to rough or uneven surfaces. Through the holes on the other hand a needle with recording sites and/or stimulating sites is passable, as shown in Fig. 19. One or more of the needles may be implemented as described with regard to a device 100 in Fig. 6 to 17.

The substrate 1 10 of the device 100 shown in Fig. 18 and 19 has the form of a slice or disk, but other forms are also possible. For example, the main surface area 112 may have the form of a circle, an oval, a square, a rectangle, a polygon or any other individual form. The circular, oval or square form are especially advantageous in terms of production efficiency, since a device 100 with such a main surface area 1 12 can be manufactured using a wafer without having to adjust the form of the substrate 110 after removing or etching the wafer away.

In the following methods 400 are described for manufacturing a herein described device 100. The devices 100, for example, are manufactured using a wafer, e.g., a circular or square disc with a thickness of about one millimeter. The wafer, for example, is made from monocrystalline or polycrystalline (semiconductor) blanks, so-called ingots. In most cases, a wafer is made of monocrystalline silicon, but other materials such as glass, silicon carbide, gallium arsenide and indium phosphide are also possible.

Fig. 20 shows exemplarily a 6” wafer 410, on the basis of which different possible length of herein described devices 100 are illustrated. In Fig. 20 a length is shown along an x- direction. For example, length of 145 mm, 140 mm, 120 mm or 106 mm are exemplarily depicted. As will be described later, per device 100 a part of the wafer 410 may be kept, wherein this part may function as stylet. Therefore, the illustrated length may represent possible length of the stylet, e.g., a silicon-stylet, of the respective device 100.

It is possible to manufacture a plurality of devices 100 using one wafer 410. Fig. 20 shows exemplarily a width within which the plurality of devices 100 may be arranged, e.g., see also Fig. 21. In Fig. 20 the width is shown along a y-direction. A minimal width of a herein described device 100 may be 70 pm or 75 pm, e.g., of a device 100 with one row of electrodes 120 as described with regard to Fig. 1 , 3 and 4. Using a 6” wafer 410, a width of 38 mm is available for devices 100 of 145 mm length, a width of 53 mm is available for devices 100 of 140 mm length, a width of 90 mm is available for devices 100 of 120 mm length or a width of 106 mm is available for devices 100 of 106 mm length. A plurality of herein described devices 100 may be arranged on the waver 410 next to each other, wherein a total width of all devices 100 arranged parallel to each other may be equal to or smaller than the available width for the respective device length. Alternatively, the respective width may represent the width of one device 100, e.g., of a device 100 as described with regard to Fig. 18 or 19.

Fig. 21 shows schematically how herein described devices 100 could be arranged on a wafer 410. It is to be noted that the figure is not to scale. The devices 100 are greatly enlarged in comparison to the wafer 410.

At a manufacturing of one or more herein described devices 100 one or more elongated recesses 412 may be formed in a wafer-substrate, i.e. in the wafer 410. For example, one elongated recesses 412 per device 100. In each of the one or more elongated recesses 412 a plurality of electronic chips 130 are embedded within a substrate comprising biocompatible and/or flexible material, e.g., embedding material. The electronic chips 130 of the respective plurality of electronic chips 130 may be arranged serially or in a two- dimensional arrangement, e.g., in rows of serially arranged electronic chips 130, within the substrate.

As exemplarily depicted in Fig. 21 , a first substrate layer, i.e. a layer of the embedding material, may be provided within the one or more recesses 412 and on a surface of the respective first substrate layer, i.e. on a surface facing away from the wafer 410, connecting lines 148 may be arranged. The electronic chips 130 of the respective plurality of electronic chips 130 may be connected to the respective connecting lines 148 via contacts 138 of the respective electronic chips 130. The contacts 138, for example, are implemented as vias. The connecting lines 148 may preferably connect the electronic chips 130 of the respective plurality of electronic chips 130 serially with respect to each other, but a parallel connection or a combination of parallel and serial connection as described above may also be possible.

A further layer of the embedding material, e.g., a second substrate layer, may be provided within the respective recess 412, so that the respective connecting lines 148 and the respective plurality of electronic chips 130 are embedded within the substrate. Within the second substrate layer a trace structure may be formed between the plurality of electronic chips 130 and a plurality of electrodes arranged on a surface of the second substrate layer, i.e. on a surface facing away from the wafer 410. The trace structure has conductive traces that connect each of the plurality of electrodes to one of the plurality of electronic chips 130, e.g., each electrode may be connected to a pin 136 of one of the plurality of electronic chips 130. Optionally, the trace structure may comprise a redistribution layer as described herein.

After the assembly the rest of the wafer 410 may be removed or etched away. Optionally, at least a part of the wafer 410 may be kept per device 100, e.g. as stabilizing portion or stabilizing guide unit. The stabilizing portion or stabilizing guide unit may function as stylet and, e.g., improve an insertion efficiency of the device 100 into tissue. Optionally, as described with regard to Fig. 23, 25 and 26, at the etching of the wafer 410, at one end of the device 100 a tip may be formed, i.e. a tip of the device 100 is formed out of the wafersubstrate.

It is possible to realize up to 10000 electrodes on a probe, e.g., a device 100, with vias, e.g. TSVs (see the contacts 138), and signal traces, see the connecting lines 148, on a 6” wafer 410. With the present solution about 200 electrodes can be implemented in two rows on a length of 3.5 mm, e.g., plus 1 mm or 1 .5 mm for the contacts. Thus, 1000 electrodes would need a length of about 25 mm. On a length of about 100mm 4000 to 5000 electrodes can be accommodated and for applications accepting a factor 2 wider shaft, the number of electrodes can reach up to 8000 to 10000 electrodes.

Fig. 22 shows the method 400 for manufacturing the device 100 in more detail.

The method 400, for example, comprises lithographically structuring 41 1 a wafer 410. At the lithographic structuring 41 1 a plurality of elongated recesses 412 may be formed in a surface 414 of the wafer 410.

Within each elongated recess 412 a substrate 1 10 is provided and a respective plurality of electronic chips 130 are serially arranged on the respective substrate within the respective elongated recess 412, see step 422. Optionally, laterally spaced to the respective plurality of electronic chips 130, a respective further plurality of electronic chips is serially arranged on the respective substrate within the respective elongated recess 412. For example, a first layer of the substrate 1 10 is provided within each elongated recess 412 and the respective plurality of electronic chips 130 and optionally the respective further plurality of electronic chips are placed on a surface of the first layer within the respective elongated recess, wherein the surface faces away from the wafer 410. The result of step 422 is shown first in a top view and then in a side view. The substrate 110 may comprise an embedding material, e.g., a flexible material, e.g., a polymer. The substrate 110, i.e., the first layer of the substrate 1 10, may be cured, e.g., hardened, before the respective plurality of electronic chips 130 and optionally the respective further plurality of electronic chips are arranged thereon.

Optionally, the elongated recesses 412 may be covered by a “separating agent”, e.g., a form release agent, and then the substrate 110 may be provided. The “separating agent” simplifies a detachment of the substrate 110 from the wafer surface at a later stage. The “separating agent” is configured to enable a sufficient bonding force, e.g., by means of adhesion and/or other bonding forces, between the wafer 410 and the substrate for subsequent process steps, e.g., for the steps denoted by the reference numerals 424, 440 and 450.

The substrate 110 may be further provided 424 within each elongated recess 412, e.g., a second layer of the substrate 1 10 is provided 424 within each elongated recess 412. The second layer may be provided, so that the electronic chips 130 are covered by the substrate 110, e.g., within each recess, the electronic chips 130 of the respective plurality of electronic chips 130 and optionally the electronic chips 130 of the respective further plurality of electronic chips are covered by the substrate. The result of step 424 is shown first in a top view and then in a side view. The substrate 1 10 may be cured, e.g., hardened, i.e. the second layer of the substrate 110 may be cured.

Steps 422 and 424 may be performed to embed 420 within each elongated recess 412 the respective plurality of electronic chips 130 and optionally the further plurality of electronic chips in the respective substrate 1 10.

Contacts 138 and pins 136 of the electronic chips 130 are exposed, e.g., using lithography, and connecting lines 148 are formed on a surface of the second layer of the substrate 1 10, wherein the connecting lines 148 are connected to the exposed contacts 138, see step 440. The result of step 440 is shown first in a top view and then in a side view. Exposed means that the substrate 110 is removed from the pins 136 and from the contacts 138, i.e., they are laid bare or the substrate is lifted from the pins 136 and the contacts 138. The exposed pins 136 may be metalized, i.e. a metal-material may be provided on the exposed pins 136. The connecting lines 148 may be formed by a structured deposition of metal-material on the second layer of the substrate 110. The connecting lines 148 may be formed, so that within each recess the electronic chips 130 of the respective plurality of electronic chips 130 are connected serially with respect to each other and optionally so that the electronic chips 130 of the respective further plurality of electronic chips 130 are connected serially with respect to each other.

The substrate 1 10 may be even further provided at each elongated recess 412, e.g., a third layer of the substrate 110 is provided, the pins 136, e.g., the metalized pins 136, are exposed, e.g., using lithography, and metalized, see step 450. The result of step 450 is shown first in a top view and then in a side view. Exposed means that the substrate 1 10 is removed from the pins 136 or the metalized pins 136, i.e., they are laid bare or the substrate is lifted from the pins 136 or the metalized pins 136. Metalized, for example, means that a metal-material may be provided on the exposed pins 136. Metal areas exposed to an environment may represent electrodes 120 arranged on the substrate 1 10, e.g., metal areas protruding the surface of the third layer of the substrate 1 10 may represent the electrodes 120.

Optionally, a redistribution layer may be provided on the third layer of the substrate 110, for redistributing a pattern defined by the pins 136 to a pattern defined by the electrodes 120, wherein one or more traces are formed on the third layer of the substrate 110 by structured deposition of metal-material, further substrate 110 is provided and exposing and metallization steps may be performed. When a redistribution layer is formed, the pattern defined by the pins 136 differs from the pattern defined by the electrodes 120.

Each process, see the reference numerals 41 1 , 422, 424, 440 and 450, in turn may consist of one or more sub-steps. For example, the lithographic structuring 411 may comprise cleaning, applying a resist, drying, exposing, developing, etching, and/or removing resist residues.

Additionally, if a plurality of electronic chips 130 and a further plurality of electronic chips 130 are arranged in a recess, i.e. in the same recess, the method 400 may additionally, comprise the step of forming a trench in the substrate separating the plurality of electrodes, the plurality of electronic chips and the trace structure from the further plurality of electrodes, the further plurality of electronic chips and the further trace structure. For example, the trench is formed as shown in Fig. 14a.

A further step comprised by the method 400 may be to lift or detach the substrate 110 from the wafer 410. This may be accomplished by etching the wafer 410 away. Alternatively, the substrate 1 10 may be mechanically detached from the “separating agent” or the “separating agent” may be mechanically detached from the wafer 410. The “separating agent” is tunable in terms of whether same adheres more to the substrate 1 10 or to the wafer 410.

As will be described with regard to Fig. 21 to 26, it is also possible that the wafer 410, e.g., underneath each recess 412 is at least partially kept and that the devices 100 are separated, e.g., by slicing the wafer 410 with a diamond saw into individual devices 100 or by performing one or more lithographic steps. Optionally, the wafer 410 may be thinned but not completely removed.

If the method 400 comprises the above mentioned step of forming a trench in the substrate, the method 400 may additionally, comprise a step of bending the substrate around the at least partially kept wafer-substrate 410 along the trench so that the plurality of electrodes face a first side of the device and the further plurality of electrodes face a second side of the device. Alternatively, if the method 400 comprises the above mentioned step of forming a trench in the substrate, the method 400 may additionally, comprise a step of providing a sacrificial layer within the first layer of the substrate 110 and a step of etching away the sacrificial layer so that a pocket is formed, e.g., to form the pocket 1 18 as shown in Fig. 14. Optionally, the first layer is perforated, e.g., enabling an easier access to the sacrificial layer, before the etching, e.g., by forming openings to the sacrificial layer through the substrate at a side of the sacrificial layer, which faces away from the plurality of electronic chips.

Optionally, the method may comprise a step of inserting a stylet into the pocket, wherein the stylet bends the substrate along the trench so that the plurality of electrodes face a first side of the device and the further plurality of electrodes face a second side of the device.

It might also be possible to manufacture a herein described device 100 using a wafer 410 without forming one or more elongated recesses 412 in a surface of the wafer 410. However, the one or more elongated recesses 412 simplify an arrangement of the respective plurality of electronic chips and the respective plurality of electrodes of the respective device 100 on the wafer 410.

As shown, for example in Fig. 23, a substrate 110 is provided on the wafer 410 and a plurality of electronic chips 130 are serially arranged on the substrate 110, e.g., on a surface of a first layer of the substrate 110. A plurality of devices 100 may be manufactured in parallel on the wafer 410, e.g., by arranging the respective plurality of electronic chips 130 laterally spaced on the substrate 1 10. The substrate 1 10 may comprise an embedding material, e.g., a flexible material, e.g., a polymer. The substrate 1 10, i.e., the first layer of the substrate 1 10, may be cured, e.g., hardened, before the respective plurality of electronic chips 130 are arranged thereon.

In case contacts of the electronic chips 130 are implemented as vias or arranged on a side opposite to pins of the respective electronic chip 130, connecting lines 148 may be realized on the substrate 1 10, i.e. on a surface of the first layer of the substrate 110, e.g., by a structured deposition of metal-material on the surface of the first layer of the substrate 110 or on the wafer 410, before the respective plurality of electronic chips 130 are arranged thereon (see also Fig. 4). The connecting lines 148 may connect the electronic chips 130 of the respective plurality of electronic chips 130 of the respective device 100 serially with respect to each other. Subsequently, further substrate 110 may be provided 424, e.g., a second layer of the substrate 1 10 is provided 424. The second layer may be provided, so that the electronic chips 130 are covered by the substrate 1 10, i.e. the electronic chips are embedded within the substrate 110. The substrate 110 may be cured, e.g., hardened, i.e. the second layer of the substrate 1 10 may be cured.

By providing the first layer and the second layer of the substrate 1 10 on the wafer 410 and arranging the electronic chips 130 in-between, the electronic chips 130 are embedded in the substrate 1 10.

Contacts 138 and pins 136 of the electronic chips 130 are exposed, e.g., using lithography, and connecting lines 148 are formed on a surface of the second layer of the substrate 1 10, wherein the connecting lines 148 are connected to the exposed contacts 138. Exposed means that the substrate 110 is removed from the pins 136 and from the contacts 138, i.e., they are laid bare or the substrate 1 10 is lifted from the pins 136 and the contacts 138. The exposed pins 136 may be metalized, i.e. a metal-material may be provided on the exposed pins 136. The connecting lines 148 may be formed by a structured deposition of metalmaterial on the second layer of the substrate 1 10 or the electronic chips 130 or the respective plurality of electronic chips 130 may be connected to a respective cable comprising the connecting lines using ACF foil (ACF = Anisotropic Conductive Film). The respective connecting lines 148 may serially connect the electronic chips 130 of the respective plurality of electronic chips 130 per device 100. In case of the respective connecting lines 148 being already formed on the first layer of the substrate 110, it is not necessary in this step to expose the contacts 138 and to form the connecting lines 148 on the second layer of the substrate 110. However, having connecting lines 148 on the first layer and on the second layer of the substrate 1 10 may increase a robustness of the electrical connections.

The substrate 1 10 may be further provided to at least cover the connecting lines 148 arranged on the second layer of the substrate 110 and may be cured. Alternatively, the connecting lines arranged on the second layer of the substrate 1 10 may be covered by a protective film. In case of the connecting lines 148 on the second layer of the substrate and the metalized pins 136 being cover by the substrate 110, the metalized pins 136 may be exposed and metalized to form the electrodes 120 on the substrate 110. In case of the metalized pins 136 not being covered by the substrate, same may represent the electrodes 120 on the substrate 1 10. Optionally, one or more redistribution layers may be provided, as described herein.

The devices 100 on the wafer 410 may be separated from each other by slicing the wafer 410 with a diamond saw into individual devices 100 or by performing one or more lithographic steps, e.g., by etching the wafer 410. Each of the isolated/separated or individual devices 100 may comprise a respective portion of the wafer 410 fixed to the first layer of the respective substrate 110 on a surface facing away from the respective electronic chips 130. The respective portion of the wafer 410 and the respective serially arranged electronic chips 130 are aligned. The respective portion of the wafer 410 may be kept, thinned, e.g., using etching, or removed, e.g., using etching.

Along a longitudinal axis of the respective portion of the wafer 410 same may be covered with PEG and then Parylen in an area reaching from a first electronic chip 130 of the respective serially arranged electronic chips 130 to a last electronic chip 130 of the respective serially arranged electronic chips 130. The portion of the wafer 410 may at least on one side, i.e. on a side of the first electronic chip 130 and/or on a side of the last electronic chip 130, extend further, wherein this subportion of the wafer 410 is not covered by PEG and Parylen. This subportion may be etched to form the tip 150.

Generally, as shown in Fig. 24, a method 400 for manufacturing a device 100 comprises embedding 420 a plurality of electronic chips in a substrate and arranging 430 a plurality of electrodes on the substrate, e.g., on a surface of the substrate. The substrate comprises an embedding material that is biocompatible. The embedding material may be flexible or rigid, wherein a flexible embedding material is preferable.

The plurality of electronic chips are embedded 420 in the substrate in a serial arrangement and underneath at least one of the plurality of electrodes, i.e., at least one of the plurality of electrodes is arranged on the substrate above an electronic chip of the plurality of electronic chips. Underneath means a position in a direction vertically down with respect to surface of the substrate on which the plurality of electrodes are arranged. Above means a position in a direction vertically up with respect to plane in which the plurality of electronic chips are arranged. As discussed before, each of the plurality of electronic chips comprises a conversion unit that comprises at least one of an analog-to-digital conversion unit and a digital-to-analog conversion unit.

The method 400 is performed such that a trace structure is formed between the plurality of electronic chips and the plurality of electrodes. The trace structure has conductive traces that connect each of the plurality of electrodes to one of the plurality of electronic chips.

The method 400 can comprise features and/or functionalities as described with regard to Fig. 21 -23 and 25 to 27.

For example, the embedding 420 may comprise arranging the plurality of electronic chips in an elongated recess in a wafer and providing the embedding material to embed, e.g., at least partially, the plurality of electronic chips, as described with regard to Fig. 21 and 22.

As described with regard to Fig. 21 -23 and 25 to 27, the method 400 can be performed using a wafer 410. The method 400 may comprise one or more lithographic steps and/or a process for thinning the wafer, i.e. a wafer-substrate, and for separating the devices, so that a remaining part of the wafer forms a stabilizing guide unit of the device.

As will be described with regard to Fig. 25 and 26, it is possible to manufacture on a wafer a device 100 for stimulating and/or recording in different directions. Fig. 25 shows exemplarily a device 100 configured for stimulation and/or recording in three directions and Fig. 26 shows exemplarily a device 100 configured for stimulation and/or recording in four directions. Devices 100 for another number of stimulation and/or recording directions is also possible.

The devices 100 in Fig. 25 and 26 may be implemented and manufactured as described with regard to Fig. 14a and 14b, by realizing a pocket within the substrate 1 10. On the wafer a plurality of the devices 100 can be manufactured in parallel. For example, a substrate 110 is provided on the wafer 410 (and may be cured) and, for each device 100, on the substrate 110 a sacrificial layer is provided, i.e., on a surface of a first layer of the substrate 1 10, wherein the first layer may represent a first pocket layer. The sacrificial layers are then covered by the substrate 1 10, i.e. a second layer of the substrate 110 is provided, wherein the second layer may represent a second pocket layer. After a separation of the plurality of devices 100 from each other and a lifting of the respective device 100 from the wafer, the respective sacrificial layer can be etched away to allow an opening of the pocket of the respective device 100. For each device 100 the respective sacrificial layer may define an area with which further features of the respective device 100 are aligned. The further features, like electronic chips, a trace structure, connecting lines and electrodes, may be manufactured and/or implemented as described in the following, wherein in this case the above described second layer of the substrate 1 10 covering the sacrificial layers may represent the below described basis layer of the substrate 1 10. Alternatively, the further features may be manufactured and/or implemented as described with regard to Fig. 14a and 14b, with the difference that not only two stimulation and/or recording directions are implemented, but three (see Fig. 25) or four (see Fig. 26).

Devices 100 with multiple stimulation and/or recording directions, as shown in Fig. 25 and 26, can also be manufactured without providing a sacrificial layer within the substrate 110. A difference is only that a basis layer of the substrate 110 on which further features of the devices are implemented is, in case of manufacturing a pocket using a sacrificial layer, the above mentioned second pocket layer, and in case of no usage of a sacrificial layer, the first layer of the substrate provided directly on the wafer.

The device 100 may comprise for one or more, e.g., for each, of the stimulation and/or recording directions features and/or functionalities as described with regard to Fig. 1 to 6.

As shown on the top of Fig. 26 and in the cross section in Fig. 26, a first plurality of electrodes 120 is arranged on a first side of the substrate 1 10, a second plurality of electrodes 120 is arranged on a second side of the substrate 1 10, a third plurality of electrodes 120 is arranged on a third side of the substrate 1 10 and a fourth plurality of electrodes 120 is arranged on a fourth side of the substrate 1 10. The first side and the third side, for example, are arranged parallel to each other and face opposite directions and the second side and the fourth side are arranged perpendicular to the first side and the third side and the second side and the fourth side face opposite directions. A first plurality of electronic chips 130 is embedded in the substrate 110 in a serial arrangement in a plane parallel to the first side; a second plurality of electronic chips 130 is embedded in the substrate 110 in a serial arrangement in a plane parallel to the second side; a third plurality of electronic chips 130 is embedded in the substrate 110 in a serial arrangement in a plane parallel to the third side and a fourth plurality of electronic chips 130 is embedded in the substrate 1 10 in a serial arrangement in a plane parallel to the fourth side. A first trace structure is arranged between the first plurality of electronic chips 130 and the first plurality of electrodes 120, wherein the first trace structure comprises conductive traces that connect each of the first plurality of electrodes 120 to one of the first plurality of electronic chips 130. A second trace structure is arranged between the second plurality of electronic chips 130 and the second plurality of electrodes 120, wherein the second trace structure comprises conductive traces that connect each of the second plurality of electrodes 120 to one of the second plurality of electronic chips 130. A third trace structure is arranged between the third plurality of electronic chips 130 and the third plurality of electrodes 120, wherein the third trace structure comprises conductive traces that connect each of the third plurality of electrodes 120 to one of the third plurality of electronic chips 130. A fourth trace structure is arranged between the fourth plurality of electronic chips 130 and the fourth plurality of electrodes 120, wherein the fourth trace structure comprises conductive traces that connect each of the fourth plurality of electrodes 120 to one of the fourth plurality of electronic chips 130.

In the cross-section shown in Fig. 26 the device comprises four device portions I OO1-4 arranged around a stylet 200. However, it is also possible that the device 100 is realized without the pocket 1 18 and without the stylet 200. That means, for example, that the space occupied by the stylet 200 is filled with the material of the substrate 1 10. In other words, the substrate 110 may have a solid body with electrodes 120 arranged on different sides of the substrate 1 10. Additionally, per side of the substrate 110 on which electrodes 120 are arranged, the substrate 110 may comprise electronic chips 130 embedded in the substrate 110 in a serial arrangement in a plane parallel to the respective side and a trace structure connecting each of the electrodes 120 arranged on the respective side to one of the electronic chips 130 of the respective side. Such an embodiment is also described in more detail with respect to Fig. 29.

For each device 100 two or more device portions, see 100i to I OO3 in Fig. 25 and 100i to I OO4 in Fig. 26, each corresponding to one of the stimulation and/or recording directions of the device 100 may be arranged parallel to each other and laterally spaced from each other on the wafer. The respective two or more device portions of a device 100 may be arranged next to each other.

Each of the respective two or more device portions comprises a plurality of electronic chips 130, which are serially arranged. The respective plurality of electronic chips 130 may be serially arranged on the basis layer of the substrate 1 10, e.g., on a surface of the basis layer of the substrate 1 10, wherein the surface faces away from the wafer. As described above, it is possible that connecting lines 148 are formed on the basis layer of the substrate 1 10. Each of the respective two or more device portions may comprise connecting lines 148 serially connecting the electronic chips of the respective plurality of electronic chips 130.

The substrate 110 may be further provided, so that the electronic chips 130 are embedded within the substrate 1 10, e.g., a further layer of the substrate 1 10 may cover the electronic chips 130. Within the further layer of the substrate 110 a trace structure between the plurality of electronic chips 130 and the plurality of electrodes 120 is realized. The trace structure has conductive traces that connect each of the plurality of electrodes 120 to one of the plurality of electronic chips 130. Optionally, the trace structure comprises one or more redistribution layers, as described herein. The trace structure can be formed within the further layer of the substrate 1 10 using one or more lithographic and/or metallization steps and steps of providing the substrate 110.

Optionally, the connecting lines 148 or additional connecting lines may be provided within the further layer of the substrate 110. This may by realized using steps of lifting the substrate 110, e.g., from contacts of the electronic chips 130, and using steps of structured deposition of metal-material, see also the description of Fig. 22 and 23.

As can be seen in Fig. 25, per device portion, see 100i, I OO2 and I OO3, the respective electronic chips 130 are serially connected and the device portions, i.e. the electronic chips 130 of different device portions, are connected in parallel. For example, the electronic chips 130 of a device 100 may be partitioned into subsets of electronic chips, e.g., a first subset comprised by a first device portion 100i, a second subset comprised by a second device portion I OO2 and a third subset comprised by a third device portion I OO3. The electronic chips 130 of the first subset are serially connected, electronic chips 130 of the second subset are serially connected and the electronic chips 130 of the third subset are serially connected. The electronic chips 130 of the first subset are connected in parallel to the electronic chips 130 of the second and third subset and the electronic chips 130 of the second subset are connected in parallel to the electronic chips 130 of the first and third subset and the electronic chips 130 of the third subset are connected in parallel to the electronic chips 130 of the first and second subset. The devices 100 may be separated, e.g., by slicing the wafer 410 with a diamond saw into individual devices 100 or by performing one or more lithographic steps.

The substrate 110 of individual devices 100 may be lifted from the wafer, e.g., using mechanical detachment or etching of the wafer.

If the respective device 100 is manufactured without sacrificial layer, the device 100 may be folded, e.g., along its longitudinal axis, to form a pocket 118 on a side opposite to the side on which the electrodes 120 are arranged, see the XX’-cross section in Fig. 26. The folding results in a hollow device 100. For example, the device 100 is folded between each device portion, see 100i to 1004 in Fig. 26, to form the pocket 118. The first device portion 100i can be connected/fixed to a last device portion, see the fourth device portion I OO4 in Fig. 26 or the third device portion in Fig. 25. A stylet 200 is insertable into the cavity formed by the folding of the device 100.

A pocket 1 18 of a device 100 with two device portions may be manufactured using the sacrificial layer and a pocket 118 of a device 100 with three or more device portions may be manufactured using the folding between the device portions of the device 100.

Optionally, the substrate 1 10 of individual devices 100 may only partially be lifted from the wafer, e.g., using mechanical detachment or etching of the wafer. For example aligned with one of the device portions a portion of the wafer may be kept, i.e. a portion of the wafer keeps attached to one of the device portions. A width of a surface of the portion of the wafer connected to the substrate 110 may be equal to or smaller than a width of the device portion arranged adjacent to the portion of the wafer, i.e. a width of the device portion connected to the portion of the wafer. The width may represent a dimension along the portion’ transverse direction.

According to an embodiment, the wafer may be etched, so that the portion of the wafer may comprise a prism-portion. A cross section of the prism-portion of the wafer perpendicular to the prism-portion’s longitudinal direction may be an n-sided polygon, wherein n is equal to or greater than a number of the stimulation and/or recording directions of the device 100. For example, the device 100 shown in Fig. 25 may comprise a portion of the wafer with a cross-section in the form of a three-sided polygon, i.e. a triangle, and the device 100 shown in Fig. 26 may comprise a portion of the wafer with a cross-section in the form of a foursided polygon, i.e. a square (see the cross section in Fig. 26). It may be possible that corners of the n-sided polygon are rounded, see the cross section in Fig. 26. The substrate 110 can be folded around the prism-portion of the portion of the wafer, so that each device portion is arranged on one side of the prism-portion, see the cross section in Fig. 26.

According to an embodiment, an end portion of the portion of the wafer may be etched to form a tip 150. The tip 150 may be covered by the substrate 110, see the top left in Fig. 26, or the tip 150 may at least partially be covered by the substrate 110, see the top right in Fig. 26, or the tip 150 may not be covered by the substrate 1 10.

With regard to the methods described with regard to Fig. 20 to 26, it is to be noted that it is also possible that the plurality of electronic chips are arranged directly on the wafer 410 and are then embedded in the substrate 1 10 by providing the substrate 1 10.

A herein described device 100 may comprise a chip layer 102, a trace structure layer 104 and an electrode layer 106. As described with regard to Fig. 20 to 26 a herein described device 100 may be manufactured by providing the chip layer 102, the trace structure layer 104 and the electrode layer 106 in this order on a wafer 410. Alternatively, as shown in Fig. 27, it is also possible to provide the electrode layer 106, the trace structure layer 104 and the chip layer 102 in this order on the wafer 410.

As shown in Fig. 27, a sacrificial layer 460 may be positioned between the wafer 410 and the electrode layer 106. The sacrificial layer 460 improves a lifting of the device 100 from the wafer 410, e.g., by mechanical detachment or by etching away the sacrificial layer 460.

The manufacturing method shown in Fig. 27 may be considered as an up-side-down method. The steps described with regard to Fig. 20 to 26 may be performed in reverse. The only difference is that at the up-side-down method, the device 100 is always completely lifted from the wafer 410. No portion of the wafer 410 will be kept.

The up-side-down method may be performed by arranging a plurality of electrodes 120 on the sacrificial layer 460 or directly on the wafer 410, e.g., by depositing metal material. Optionally, a plurality of recesses may be formed within the sacrificial layer 460 or within the wafer 410 and metal-material may be provided within the plurality of recesses to form the plurality of electrodes 120. Substrate 1 10, e.g., comprising embedding material, may be provided on the sacrificial layer 460 or on the wafer 410 (if no sacrificial layer 460 is present) to form a substrate layer. Within the substrate layer a trace structure 140 may be formed using steps of lifting embedding material, metallization steps and steps of providing the substrate 110.

A plurality of electronic chips 130 are arranged in a serial manner on the substrate layer. The trace structure 140 has conductive traces that connect each of the plurality of electrodes 120 to one of the plurality of electronic chips 130. The substrate 110 is further provided to embed the plurality of electronic chips 130 in the substrate 110.

Connecting lines 148 serially connecting the plurality of electronic chips 130 may be arranged on the sacrificial layer, see the top of Fig. 27, or on the wafer 410 (if no sacrificial layer 460 is present) or on the substrate layer, see the bottom of Fig. 27. The connecting lines may be formed by a structured deposition of metal material.

The device 100 shown on the top of Fig. 27 may represent a version of the device 100 shown on the top of Fig. 3 manufactured with an up-side-down method and the device 100 shown on the bottom of Fig. 27 may represent a version of the device 100 shown on the bottom of Fig. 3 manufactured with an up-side-down method. The devices in Fig. 3 comprise a portion of the wafer 410 as a stabilizing unit. If same is etched away, the resulting devices would be the same as the devices resulting from the up-side-down method shown in Fig. 27.

Fig. 28 shows an embodiment of a device 100 within a metal housing 500, e.g., a metal package, e.g., inserted into the tissue by a syringe or cannula. The metal housing 500 comprises feed-throughs for the electrodes 510 and power and data wires 149. The power and data wires 149 may be connected to connecting lines 148, e.g. via feed-throughs in the metal housing 500.

The herein described substrate 1 10 with connecting lines 148 may also be understood as a flex-cable. The herein described electronic chips 130 may also be understood as probechips. A device 100 may comprise a flex-cable (e.g. with cross-section of 15 pm x 140 pm) connected to probe-chips (e.g. 25pm x 100pm cross section and 3-5mm length). Electronic chips 130, for example, are embedded in the flex cable, as shown in the previous Figures, or bonded to the cable and only partially embedded within the substrate 110, as shown in Fig. 28. In the example shown in Fig. 28 a cross-section through the metal housing 500 perpendicular to a longitudinal axis of the metal housing is a segment of a circle, i.e. a circular segment or a disk segment or a two-dimensional space that is bounded by a circular arc and by the circular chord connecting the endpoints of the arc. In other words the metal housing 500 has along its longitudinal axis on one side a round surface, i.e. a rounded side or a semi-circular part, and on an opposite side a flat surface, i.e. a flat side or a flat part. The metal housing 500 is hollow, i.e. it comprises a cavity in which the device 100 is insertable or in which the device 100 is arranged. Further, the metal housing 500 comprises in the flat surface feed-throughs or openings to the cavity.

The electronic chips 130 of the device 100 arranged within the metal housing 500 are connected with outside electrodes 510 arranged on the flat surface of the metal housing 500 via the openings in the flat surface to the cavity. The electronic chips 130 are connected with a front side via feed-throughs of the flat side of the metal housing 500 leading to the electrodes 510 on the outside. The data and power wires 149 of the device 100, e.g. a flex carrier, are connected to or passed through one end of the metal housing. The metal housing has two ends along its longitudinal axis, wherein one of this two ends is the one to which the data and power wires 149 are connected or through which the data and power wires 149 are passed. The other end of the metal housing 500 may form a tip.

A manufacturing of the device 100 encapsulated within the metal housing 500 as shown in Fig. 28 may comprise connecting the electronic chips 130 to the flex cable, e.g., as described with regard to Fig. 21 -24 and Fig. 27 or by bonding and only partially encapsulating the electronic chips 130, and then connecting the electronic chips 130 with the outside electrode 510 and optionally connecting or passing the data and power wires 149 to or through an end of the metal housing 500. The two steps above can be also performed in reverse order.

The semi-circular part of the metal housing 500 may be welded to the flat part of the metal housing 500 which carries electrodes 510, so that the device 100 is encapsulated within the metal housing 500, i.e. the metal housing 500 forms a sealed package.

The probe shown in Fig. 28 can be inserted into the tissue by a syringe or cannula or certain similar method like some other probes. Alternatively to arranging a device 100 with a flexible substrate 110 within the metal housing 500, it is possible to arrange, e.g., embed, a silicon probe with digital electrodes within the metal housing 500.

Fig. 29 shows an embodiment of a herein described device 100 with stimulation and/or recording sites, i.e. electrodes 120, facing different directions. In the example shown in Fig. 29 two opposite directions are covered by electrodes 120. However, it is also possible that more sides are covered by electrodes 120, e.g., see Fig. 26. A substrate 110 on which the electrodes 120 are arranged may be cuboidal, as shown in Fig. 29, wherein two to four sides of the substrate 110 may be covered by electrodes 120. Alternatively, the substrate 110 can have the form of an n-sided prism with n being in the range of three to six and a number of sides covered by electrodes 120 being in the range of two to n.

Fig. 29 shows in the top a cross section of the device 100 along its longitudinal axis and on the bottom a cross section of the device 100 perpendicular to its longitudinal axis.

The device 100 shown in Fig. 29 may be manufactured as described with regard to Fig. 26, wherein in the case of two opposite directions being covered by electrodes 120, for example, only the first device portion 100i and the third device portion I OO3 may comprise stimulation and/or recording sites and the second device portion I OO2 and the fourth device portion I OO4 may comprise no stimulation and/or recording sites. The device portions may be folded, as described with regard to Fig. 26, to form the device 100 shown in Fig. 29. Similarly a device with two neighboring/adjacent sides, e.g., being perpendicular to each other, being covered by electrodes 120, or a device with three or more sides covered by electrodes 120 can be realized.

A device with two neighboring/adjacent sides being covered by electrodes 120, i.e. the first side 112a and the second side 112b being arranged perpendicular to each other, may be manufactured as described with regard to Fig. 14a.

The device 100, for example, comprises a first plurality of electrodes 120a arranged on a first side 1 12a of the substrate 1 10 and a second plurality of electrodes 120b arranged on a second side 1 12b of the substrate 1 10. The first side 112a and the second side 1 12b, for example, are arranged parallel to each other and face opposite directions. Alternatively, it is possible that the first side 112a and the second side 1 12b are arranged perpendicular to each other, e.g., as shown in Fig. 14a. A first plurality of electronic chips 130a is embedded in the substrate 110 in a serial arrangement, e.g., along the longitudinal axis of the device 100, in a plane parallel to the first side 1 12a and a second plurality of electronic chips 130b is embedded in the substrate 110 in a serial arrangement, e.g., along the longitudinal axis of the device 100, in a plane parallel to the second side 1 12b. A first trace structure 140a is arranged between the first plurality of electronic chips 130a and the first plurality of electrodes 120a and a second trace structure 140b is arranged between the second plurality of electronic chips 130b and the second plurality of electrodes 120b. The first trace structure 140a comprises conductive traces that connect, for each of the first plurality of electrodes 120, the respective electrode to one of the first plurality of electronic chips 130a. The second trace structure 140b comprises conductive traces that connect, for each of the second plurality of electrodes 120b, the respective electrode to one of the second plurality of electronic chips 130b. Different electrodes 120 can be connected to different electronic chips 130.

The first plurality of electronic chips 130a, for example, are aligned with the first plurality of electrodes 120a, e.g., both the electrodes 120 and the electronic chips 130 may be arranged along the longitudinal axis of the device 100. Additionally, or alternatively, the second plurality of electronic chips 130b, for example, are aligned with the second plurality of electrodes 120b, e.g., both the electrodes 120 and the electronic chips 130 may be arranged along the longitudinal axis of the device 100. The first plurality of electronic chips 130a, for example, are aligned with the first plurality of electrodes 120a, so that a projection of an area covered by the first plurality of electrodes 120a onto the plane in which the first plurality of electronic chips 130a are arranged overlaps at least partially with an area covered by the first plurality of electronic chips 130a. The second plurality of electronic chips 130b, for example, are aligned with the second plurality of electrodes 120b, so that a projection of an area covered by the second plurality of electrodes 120b onto the plane in which the second plurality of electronic chips 130b are arranged overlaps at least partially with an area covered by the second plurality of electronic chips 130b.

The device 100 may comprise features and/or functionalities as described with regard to any other herein described device 100.

The electrodes of the first plurality of electrodes 120a and/or of the second plurality of electrodes 120b may be implemented and/or arranged on their respective side 1 12a or 1 12b as described with regard to any herein described device 100, for example, as described with regard to the plurality of electrodes 120 in Fig. 1 , Fig. 3-6 and/or Fig. 8. The electronic chips of the first plurality of electronic chips 130a and/or of the second plurality of electronic chips 130b may be implemented as described with regard to any herein described device 100. For example, the first plurality of electronic chips 130a and/or the second plurality of electronic chips 130b may comprise electronic chips of one or more of the configurations described with regard to Fig. 2a to 2e.

The first trace structure 140a and/or the second trace structure 140b may be implemented as described with regard to any herein described device 100, for example, as described with regard to the trace structure 140 in Fig. 1 , Fig. 3-6 and/or Fig. 8.

As mentioned above, the electrodes, see 120a and 120b, may be arranged on a first side 112a and a second side 1 12b respectively. The first trace structure 140a may have at least one redistribution layer, e.g., as described herein, parallel to the first side 1 12a and/or the second trace structure 140b may have at least one redistribution layer, e.g., as described herein, parallel to the second side 112b. The at least one redistribution layer of the first trace structure 140a, for example, is adapted for redistributing, for electronic chips of the first plurality of electronic chips 130a, a respective pin-pattern of the respective electronic chip to at least a part of an electrode-pattern of the first plurality of electrodes 120a or vice versa and/or the at least one redistribution layer of the second trace structure 140b, for example, is adapted for redistributing, for electronic chips of the second plurality of electronic chips 130b, a respective pin-pattern of the respective electronic chip to at least a part of an electrode-pattern of the second plurality of electrodes 120b or vice versa.

Optionally, the device 100 comprises a communication unit 170. The electronic chips within the first plurality of electronic chips 130a, for example, are connected serially with respect to each other and the electronic chips within the second plurality of electronic chips 130b, for example, are connected serially with respect to each other. The first plurality of electronic chips 130a and the second plurality of electronic chips 130b, for example, are connected parallel with respect to each other and to the communication unit 170.

Optionally, the substrate 110 comprises a cavity 1 18 with a longitudinal axis parallel to an axis of the serial arrangement of the first plurality of electronic chips 130a and parallel to an axis of the serial arrangement of the second plurality of electronic chips 130b, i.e. the longitudinal axis of the cavity is parallel to the longitudinal axis of the deice 100. The cavity 118, for example, is limited along its longitudinal axis on all its sides, e.g., on four sides in Fig. 29, by the substrate 110. The cavity 1 18 may have the form of a cylinder or of an n- sided prism. The cavity 1 18 shown in Fig. 29, for example, comprises two side walls parallel to the first side 112a and two side walls perpendicular to the first side 1 12a. The cavity 1 18, for example, is configured so that a stylet is insertable into the cavity 118, e.g., for stabilizing the device 100 and for simplifying an insertion of the device 100 into material like tissue.

According to an embodiment, a side 112c of the substrate 1 10 on which no electrodes 120 are arranged comprises a plurality of openings 111 to the cavity 1 18, e.g., the side 112c is perforated. In Fig. 29 exemplarily the side 1 12c perpendicular to the first side 112a is perforated.

Additional embodiments and aspects are now described that may be used alone or in combination with the features and functionalities described herein.

A first aspect concerns a device 100 comprising a substrate 110 comprising material that is biocompatible and flexible; a plurality of electrodes 120 arranged on the substrate 110; and a plurality of electronic chips 130 embedded in the substrate 110 in a serial arrangement underneath at least one of the plurality of electrodes 120. Each of the plurality of electronic chips 130 comprises a conversion unit 132 that comprises at least one of an analog-to- digital conversion unit 133 and a digital-to-analog conversion unit 134. Further, the device 100 comprises a trace structure 140 between the plurality of electronic chips 130 and the plurality of electrodes 120, the trace structure 140 having conductive traces 142 that connect each of the plurality of electrodes 120 to one of the plurality of electronic chips 130.

According to a second aspect with reference to the first aspect, at least an analog-to-digital conversion unit 133 comprised by a conversion unit 132 comprises a multiplexer; and/or at least a digital-to-analog conversion unit 134 comprised by a conversion unit 132 comprises a demultiplexer.

According to a third aspect with reference to the first aspect, a subset of the plurality of electrodes 120 having at least two electrodes 120 is connected to a common electronic chip of the plurality of electronic chips 130. The common electronic chip comprises for each electrode connected to the common electronic chip a conversion unit 132 comprising at least one of an analog-to-digital conversion unit 133 and a digital-to-analog conversion unit 134. According to a fourth aspect with reference to one of the previous aspects, the trace structure 140 has at least one redistribution layer 144 and is adapted for redistributing, for each of the plurality of electronic chips 130, a respective pin-pattern of the respective electronic chip to at least a part of an electrode-pattern of the plurality of electrodes 120 or vice versa.

According to a fifth aspect with reference to one of the previous aspects, the device 100 further comprises a communication unit 170, wherein the plurality of electronic chips 130 are connected serially with respect to each other and to the communication unit 170.

According to a sixth aspect with reference to one of the aspects 1 to 4, the device 100 further comprises a communication unit 170. The plurality of electronic chips 130 are partitioned into subsets of electronic chips 130. Within each subset of the subsets of electronic chips 130, the respective electronic chips 130 of the respective subset are connected serially with respect to each other, and the subsets of electronic chips 130 are connected parallel with respect to each other and to the communication unit 170.

According to a seventh aspect with reference to one of the previous aspects, at least a digital-to-analog conversion unit 134 comprised by a conversion unit 132 of an electronic chip of the plurality of electronic chips 130 is configured to provide an analog signal to an electrode connected to the electronic chip and the electrode is configured to provide the analog signal as a stimulus, and at least an analog-to-digital conversion unit 133 comprised by a conversion unit 132 of an electronic chip of the plurality of electronic chips 130 is configured to obtain an analog signal from an electrode connected to the electronic chip and the electrode is configured to detect the analog signal.

According to an eighth aspect with reference to the seventh aspect, the analog signal obtained by the analog-to-digital conversion unit 133 from the electrode represents a biosignal.

According to a ninth aspect with reference to one of the previous aspects, the device 100 comprises a connection region for a connection of the substrate 1 10 with a stylet.

According to a tenth aspect with reference to one of the previous aspects, the substrate 110 comprises a cavity at a side opposite to the side on which the plurality of electrodes 120 are arranged. According to an eleventh aspect with reference to one of the previous aspects, the substrate 110 has the form of a needle with a tip 150 and a body and the plurality of electrodes 120 are arranged on a surface of the body.

According to a twelfth aspect with reference to the eleventh aspect, the body is at least partially a hollow body with side walls, and the plurality of electronic chips 130 and the trace structure 140 are embedded in a first side wall of these side walls and the plurality of electrodes 120 are arranged on an outer surface of the first side wall.

According to a thirteenth aspect with reference to the twelfth aspect, the device 100 comprises a further plurality of electrodes 120 arranged on an outer surface of a second wall of the side walls; and a further plurality of electronic chips 130 embedded in the second side wall in a serial arrangement underneath at least one of the further plurality of electrodes 120. Each of the further plurality of electronic chips 130 comprises a conversion unit 132 that comprises at least one of an analog-to-digital conversion unit 133 and a digital-to- analog conversion unit 134. Further, the device 100 comprises a further trace structure 140 between the further plurality of electronic chips 130 and the further plurality of electrodes 120, the further trace structure 140 having conductive traces 142 that connect each of the further plurality of electrodes 120 to one of the further plurality of electronic chips 130.

According to a fourteenth aspect with reference to the thirteenth aspect, the device 100 comprises a communication unit 170. Within the plurality of electronic chips 130 and within the further plurality of electronic chips 130, the respective electronic chips 130 are connected serially with respect to each other, and the plurality of electronic chips 130 and the further plurality of electronic chips 130 are connected parallel with respect to each other and to the communication unit 170.

According to a fifteenth aspect with reference to one of the aspects 12 to 14, a side wall in which no electronic chip is embedded is at least partially perforated.

According to a sixteenth aspect with reference to one of the previous aspects, the device 100 comprises, laterally spaced from the plurality of electrodes 120, laterally spaced from the plurality of electronic chips 130 and laterally spaced from the trace structure 140: a further plurality of electrodes 120 arranged on the substrate 110; a further plurality of electronic chips 130 embedded in the substrate 110 in a serial arrangement underneath at least one of the further plurality of electrodes 120; and a further trace structure 140 between the further plurality of electronic chips 130 and the further plurality of electrodes 120, the further trace structure 140 having conductive traces 142 that connect each of the further plurality of electrodes 120 to one of the further plurality of electronic chips 130. Each of the further plurality of electronic chips 130 comprises a conversion unit 132 that comprises at least one of an analog-to-digital conversion unit 133 and a digital-to-analog conversion unit 134. The substrate 1 10 comprises a trench separating the plurality of electrodes 120, the plurality of electronic chips 130 and the trace structure 140 from the further plurality of electrodes 120, the further plurality of electronic chips 130 and the further trace structure 140.

According to a seventeenth aspect with reference to one of the previous aspects, the device 100 comprises a catheter 220 with a tube. The tube has a tube shell 222 and a wall 226 positioned within the tube. The tube shell 222 has an opening 224 along a longitudinal axis of the tube. A first cavity 225 is arranged between a first side of the wall 226 and the tube shell 222, and a second cavity 227 is arranged between a second side of the wall 226 opposing the first side and the tube shell 222. The opening 224 in the tube shell 222 is an opening 224 to the first cavity 225. The substrate 110 of the device 100 is arranged within the first cavity 225 and the plurality of electrodes 120 arranged on the substrate 110 are aligned with the opening 224.

According to an eighteenth aspect with reference to the seventeenth aspect, the tube shell 222 and the wall 226 are integrally formed.

According to a nineteenth aspect with reference to the seventeenth aspect or the eighteenth aspect, the device 100 further comprises a stylet 200 positioned within the second cavity 227 of the catheter 220.

According to a twentieth aspect with reference to the nineteenth aspect, at least one of the wall 226 and the tube shell 222 of the catheter 220 comprises a flexible material. The catheter 220 is configured to clamp the substrate 1 10 within the first cavity 225 and the stylet 200 within the second cavity 227 based on the flexible material.

A twenty-first aspect concerns a system comprising a metal housing 500, power and data wires 149 and a device 100 according to one of the aspects 1 to 8. The power and data wires 149 are connected to the device 100. The device 100 is encapsulated by the metal housing 500 and the metal housing 500 comprises feed-throughs for the power and data wires 149 and for the electrodes 510 of the device 100.

A twenty-second aspect concerns a system comprising a plurality of devices 100 according to one of the aspects 1 to 8 arranged in a two dimensional arrangement next to each other and sharing the same substrate 110.

According to a twenty-third aspect with reference to the twenty-second aspect, the substrate 110 comprises one or more openings 192.

According to a twenty-fourth aspect with reference to the twenty-third aspect, the system further comprises one or more devices 100 according to one of the aspects 9 to 20 passable through the one or more openings 192, or one or more needles with recording sites and/or stimulating sites passable through the one or more openings 192.

A twenty-fifth aspect concerns a method 400 for manufacturing a device 100. The method 400 comprises embedding 420 a plurality of electronic chips 130 in a substrate 110 that comprises an embedding material that is biocompatible and flexible, in a serial arrangement and underneath at least one of a plurality of electrodes 120. Each of the plurality of electronic chips 130 comprises a conversion unit 132 that comprises at least one of an analog-to-digital conversion unit 133 and a digital-to-analog conversion unit 134. The method 400 further comprises arranging 430 a plurality of electrodes 120 on the substrate 110. The method 400 comprises or performes the above mentioned steps, such that a trace structure 140 is formed between the plurality of electronic chips 130 and the plurality of electrodes 120, the trace structure 140 having conductive traces 142 that connect each of the plurality of electrodes 120 to one of the plurality of electronic chips 130.

According to a twenty-sixth aspect with reference to the twenty-fifth aspect, the method 400 comprises forming an elongated recess 412 in a wafer-substrate 410. The embedding 420 of the plurality of electronic chips 130 comprises arranging the plurality of electronic chips 130 in the elongated recess 412 and providing the embedding material to at least partially embed the plurality of electronic chips 130.

According to a twenty-seventh aspect with reference to the twenty-sixth aspect, the embedding 420 of the plurality of electronic chips 130 comprises providing a first layer of a first embedding material in the elongated recess 412, arranging the plurality of electronic chips 130 at the first layer; and arranging a second layer of an embedding material to at least partially embed the plurality of electronic chips 130.

According to a twenty-eighth aspect with reference to the twenty-sixth aspect or the twentyseventh aspect, the method further comprises one or more lithographic steps and/or a process for thinning the wafer-substrate 410 and for separating the devices 100, so that a remaining part of the wafer-substrate 410 forms a stabilizing guide unit of the device 100.

According to a twenty-nineth aspect with reference to one of the aspects 26 to 28, the method further comprises forming a plurality of elongated recesses 412 in the wafersubstrate 410, the plurality of elongated recesses 412 comprising the elongated recess 412, to manufacture a plurality of devices 100.

Although some aspects have been described in the context of an apparatus, it is clear that these aspects also represent a description of the corresponding method, where a block or device corresponds to a method step or a feature of a method step. Analogously, aspects described in the context of a method step also represent a description of a corresponding block or item or feature of a corresponding apparatus.

The above described embodiments are merely illustrative for the principles of the present invention. It is understood that modifications and variations of the arrangements and the details described herein will be apparent to others skilled in the art. It is the intent, therefore, to be limited only by the scope of the impending patent claims and not by the specific details presented by way of description and explanation of the embodiments herein.

References

[1] https://www.electronicsweekly.com/news/research-news/robot-arm-controlled- quadriplegics-intentions-2015-05/

[2] “Fully immersible subcortical neural probes with modular architecture and a deltasigma ADC integrated under each electrode for parallel readout of 144 recording sites”; D. De Dorigo et al., IEEE Journal of Solid-State Circuits 53 (1 1 ), 311 1 -3125

Claims

1 . Device (100), comprising a substrate (1 10) comprising material that is biocompatible and flexible; a plurality of electrodes (120) arranged on the substrate (110); and a plurality of electronic chips (130) embedded in the substrate (1 10) in a serial arrangement underneath at least one of the plurality of electrodes (120); wherein each of the plurality of electronic chips (130) comprises a conversion unit (132) that comprises at least one of an analog-to-digital conversion unit (133) and a digital-to-analog conversion unit (134); a trace structure (140) between the plurality of electronic chips (130) and the plurality of electrodes (120), the trace structure (140) having conductive traces (142) that connect each of the plurality of electrodes (120) to one of the plurality of electronic chips (130).

2. Device (100) according to claim 1 , wherein at least an analog-to-digital conversion unit (133) comprised by a conversion unit (132) comprises a multiplexer; and/or wherein at least a digital-to-analog conversion unit (134) comprised by a conversion unit (132) comprises a demultiplexer.

3. Device (100) according to claim 1 , wherein a subset of the plurality of electrodes (120) having at least two electrodes (120) is connected to a common electronic chip of the plurality of electronic chips (130); wherein the electronic chip comprises for each electrode connected to the electronic chip a conversion unit (132) comprising at least one of an analog-to-digital conversion unit (133) and a digital-to-analog conversion unit (134).

4. Device (100) according to one of claims 1 to 3, wherein the trace structure (140) has at least one redistribution layer (144) and is adapted for redistributing, for each of the plurality of electronic chips (130), a respective pin-pattern of the respective electronic chip to at least a part of an electrode-pattern of the plurality of electrodes (120) or vice versa.

5. Device (100) according to one of claims 1 to 4, further comprising a communication unit (170), wherein the plurality of electronic chips (130) are connected serially with respect to each other and to the communication unit (170).

6. Device (100) according to one of claims 1 to 4, further comprising a communication unit (170); wherein the plurality of electronic chips (130) are partitioned into subsets of electronic chips (130), wherein, within each subset of the subsets of electronic chips (130), the respective electronic chips (130) of the respective subset are connected serially with respect to each other, and wherein the subsets of electronic chips (130) are connected parallel with respect to each other and to the communication unit (170).

7. Device (100) according to one of claims 1 to 6, wherein at least a digital-to-analog conversion unit (134) comprised by a conversion unit (132) of an electronic chip of the plurality of electronic chips (130) is configured to provide an analog signal to an electrode connected to the electronic chip and the electrode is configured to provide the analog signal as a stimulus, and wherein at least an analog-to-digital conversion unit (133) comprised by a conversion unit (132) of an electronic chip of the plurality of electronic chips (130) is configured to obtain an analog signal from an electrode connected to the electronic chip and the electrode is configured to detect the analog signal.

8. Device (100) according to claim 7, wherein the analog signal obtained by the analog- to-digital conversion unit (133) from the electrode represents a biosignal.

9. Device (100) according to one of claims 1 to 8, comprising a connection region for a connection of the substrate (110) with a stylet.

10. Device (100) according to one of claims 1 to 9, wherein the substrate (110) comprises a cavity at a side opposite to the side on which the plurality of electrodes (120) are arranged.

11 . Device (100) according to one of claims 1 to 10, wherein the substrate (110) has the form of a needle with a tip (150) and a body; and the plurality of electrodes (120) are arranged on a surface of the body.

12. Device (100) according to claim 11 , wherein the body is at least partially a hollow body with side walls, and the plurality of electronic chips (130) and the trace structure (140) are embedded in a first side wall of these side walls and the plurality of electrodes (120) are arranged on an outer surface of the first side wall.

13. Device (100) according to claim 12, comprising a further plurality of electrodes (120) arranged on an outer surface of a second wall of the side walls; a further plurality of electronic chips (130) embedded in the second side wall in a serial arrangement underneath at least one of the further plurality of electrodes (120); wherein each of the further plurality of electronic chips (130) comprises a conversion unit (132) that comprises at least one of an analog-to-digital conversion unit (133) and a digital-to-analog conversion unit (134); and a further trace structure (140) between the further plurality of electronic chips (130) and the further plurality of electrodes (120), the further trace structure (140) having conductive traces (142) that connect each of the further plurality of electrodes (120) to one of the further plurality of electronic chips (130).

14. Device (100) according to claim 13, comprising a communication unit (170); wherein, within the plurality of electronic chips (130) and within the further plurality of electronic chips (130), the respective electronic chips (130) are connected serially with respect to each other, and wherein the plurality of electronic chips (130) and the further plurality of electronic chips (130) are connected parallel with respect to each other and to the communication unit (170).

15. Device (100) according to one of claims 12 to 14, wherein a side wall in which no electronic chip is embedded is at least partially perforated.

16. Device (100) according to one of claims 1 to 15, comprising, laterally spaced from the plurality of electrodes (120), the plurality of electronic chips (130) and the trace structure (140), a further plurality of electrodes (120) arranged on the substrate (1 10); a further plurality of electronic chips (130) embedded in the substrate (110) in a serial arrangement underneath at least one of the further plurality of electrodes (120); wherein each of the further plurality of electronic chips (130) comprises a conversion unit (132) that comprises at least one of an analog-to-digital conversion unit (133) and a digital-to-analog conversion unit (134), and a further trace structure (140) between the further plurality of electronic chips (130) and the further plurality of electrodes (120), the further trace structure (140) having conductive traces (142) that connect each of the further plurality of electrodes (120) to one of the further plurality of electronic chips (130) wherein the substrate (1 10) comprises a trench separating the plurality of electrodes (120), the plurality of electronic chips (130) and the trace structure (140) from the further plurality of electrodes (120), the further plurality of electronic chips (130) and the further trace structure (140).

17. Device (100) according to one of claims 1 to 16, comprising a catheter (220) with a tube, having a tube shell (222), the tube shell (222) having an opening (224) along a longitudinal axis of the tube, and a wall (226) positioned within the tube; wherein a first cavity (225) is arranged between a first side of the wall (226) and the tube shell (222), and wherein a second cavity (227) is arranged between a second side of the wall (226) opposing the first side and the tube shell (222); wherein the opening (224) in the tube shell (222) is an opening (224) to the first cavity (225); wherein the substrate (110) is arranged within the first cavity (225) and the plurality of electrodes (120) arranged on the substrate (110) are aligned with the opening (224).

18. Device (100) according to claim 17, wherein the tube shell (222) and the wall (226) are integrally formed.

19. Device (100) according to claim 17 or claim 18, further comprising a stylet (200) positioned within the second cavity (227) of the catheter (220).

20. Device (100) according to claim 19, wherein at least one of the wall (226) and the tube shell (222) of the catheter (220) comprises a flexible material; wherein the catheter (220) is configured to clamp the substrate (110) within the first cavity (225) and the stylet (200) within the second cavity (227) based on the flexible material.

21 . System comprising a metal housing (500), power and data wires (149) and a device (100) according to one of claims 1 to 8, wherein the power and data wires (149) are connected to the device (100); wherein the device (100) is encapsulated by the metal housing (500); and wherein the metal housing (500) comprises feed-throughs for the power and data wires (149) and for the electrodes (510) of the device (100).

22. System comprising a plurality of devices (100) according to one of claims 1 to 8 arranged in a two dimensional arrangement next to each other and sharing the same substrate (110),

23. System according to claim 22, wherein the substrate (110) comprises one or more openings (192).

24. System according to claim 23 further comprising one or more probes comprising a device (100) according to one of claims 1 to 20 passable through the one or more openings (192), or one or more probes with recording sites and/or stimulating sites, wherein the one or more probes are passable through the one or more openings (192).

25. Method (400) for manufacturing a device (100), wherein the method (400) comprises embedding (420) a plurality of electronic chips (130) in a substrate (110) that comprises an embedding material that is biocompatible and flexible, in a serial arrangement and underneath at least one of a plurality of electrodes (120), wherein each of the plurality of electronic chips (130) comprises a conversion unit (132) that comprises at least one of an analog-to-digital conversion unit (133) and a digital-to- analog conversion unit (134); arranging (430) a plurality of electrodes (120) on the substrate (110); and such that a trace structure (140) is formed between the plurality of electronic chips (130) and the plurality of electrodes (120), the trace structure (140) having conductive traces (142) that connect each of the plurality of electrodes (120) to one of the plurality of electronic chips (130).

26. Method (400) of claim 25 comprising forming an elongated recess (412) in a wafer-substrate (410); and wherein embedding (420) the plurality of electronic chips (130) comprises: arranging the plurality of electronic chips (130) in the elongated recess (412); and providing the embedding material to at least partially embed the plurality of electronic chips (130).

27. Method (400) of claim 26, wherein embedding (420) the plurality of electronic chips (130) comprises: providing a first layer of a first embedding material in the elongated recess (412), arranging the plurality of electronic chips (130) at the first layer; and arranging a second layer of an embedding material to at least partially embed the plurality of electronic chips (130).

28. Method (400) of claim 26 or 27, comprising further one or more lithographic steps and/or a process for thinning the wafer-substrate (410) and for separating the devices (100), so that a remaining part of the wafer-substrate (410) forms a stabilizing guide unit of the device (100).

29. Method (400) of one of claims 26 to 28, comprising: forming a plurality of elongated recesses (412) in the wafer-substrate (410), the plurality of elongated recesses (412) comprising the elongated recess (412), to manufacture a plurality of devices (100).

30. Device (100), comprising a substrate (1 10) comprising material that is biocompatible and flexible; a first plurality of electrodes (120a) arranged on a first side of the substrate (110); a second plurality of electrodes (120b) arranged on a second side of the substrate (110); a first plurality of electronic chips (130a) embedded in the substrate (1 10) in a serial arrangement in a plane parallel to the first side; a second plurality of electronic chips (130b) embedded in the substrate (1 10) in a serial arrangement in a plane parallel to the second side; a first trace structure (140a) between the first plurality of electronic chips (130a) and the first plurality of electrodes (120a), the first trace structure (140a) having conductive traces (142) that connect each of the first plurality of electrodes (120a) to one of the first plurality of electronic chips (130a); and a second trace structure (140b) between the second plurality of electronic chips (130b) and the second plurality of electrodes (120b), the second trace structure (140b) having conductive traces (142) that connect each of the second plurality of electrodes (120b) to one of the second plurality of electronic chips (130b).

31 . Device according to claim 30, wherein the first plurality of electronic chips are aligned with the first plurality of electrodes and the second plurality of electronic chips are aligned with the second plurality of electrodes.

32. Device (100) according to claim 30 or claim 31 , wherein each electronic chip of the first plurality of electronic chips (130a) and of the second plurality of electronic chips (130b) comprises a conversion unit (132) that comprises an analog-to-digital conversion unit (133) and/or a digital-to-analog conversion unit (134).

33. Device (100) according to claim 32, wherein at least an analog-to-digital conversion unit (133) comprised by a conversion unit (132) comprises a multiplexer; and/or wherein at least a digital-to-analog conversion unit (134) comprised by a conversion unit (132) comprises a demultiplexer.

34. Device (100) according to one of claims 30 to 33, wherein the first plurality of electronic chips (130a) and/or the second plurality of electronic chips (130b) comprise at least one electronic chip with a conversion unit (132) that comprises, for each electrode connected to the respective electronic chip, an analog-to-digital conversion unit (133) and/or a digital-to-analog conversion unit (134).

35. Device (100) according to one of claims 30 to 34, wherein the first trace structure (140a) has at least one redistribution layer (144) parallel to the first side and is adapted for redistributing, for electronic chips of the first plurality of electronic chips (130a), a respective pin-pattern of the respective electronic chip to at least a part of an electrode-pattern of the first plurality of electrodes (120a) or vice versa; and/or wherein the second trace structure (140b) has at least one redistribution layer (144) parallel to the second side and is adapted for redistributing, for electronic chips of the second plurality of electronic chips (130b), a respective pin-pattern of the respective electronic chip to at least a part of an electrode-pattern of the second plurality of electrodes (120b) or vice versa.

36. Device (100) according to one of claims 30 to 35, comprising a communication unit (170); wherein, within the first plurality of electronic chips (130a) and within the second plurality of electronic chips (130b), the respective electronic chips (130) are connected serially with respect to each other, and wherein the first plurality of electronic chips (130a) and the second plurality of electronic chips (130b) are connected parallel with respect to each other and to the communication unit (170).

37. Device according to one of claims 30 to 36, wherein the substrate (1 10) comprises a cavity with a longitudinal axis parallel to an axis of the serial arrangement of the first plurality of electronic chips and parallel to an axis of the serial arrangement of the second plurality of electronic chips.

38. Device according to claim 37, wherein the cavity comprises two side walls parallel to the first side and two side walls perpendicular to the first side; and/or wherein a side of the substrate (1 10) on which no electrodes are arranged comprises a plurality of openings to the cavity.

39. Device (100), comprising a substrate (1 10) comprising material that is biocompatible and flexible; a plurality of electrodes (120a) arranged on the substrate (1 10); and a plurality of electronic chips (130a) embedded in the substrate (1 10) in a serial arrangement underneath at least one of the plurality of electrodes (120a); a trace structure (140a) between the plurality of electronic chips (130a) and the plurality of electrodes (120a), the trace structure (140a) having conductive traces (142) that connect each of the plurality of electrodes (120a) to one of the plurality of electronic chips (130a). further comprising, laterally spaced from the plurality of electrodes (120a), the plurality of electronic chips (130a) and the trace structure (140a), a further plurality of electrodes (120b) arranged on the substrate (1 10); a further plurality of electronic chips (130b) embedded in the substrate (1 10) in a serial arrangement underneath at least one of the further plurality of electrodes (120b); a further trace structure (140b) between the further plurality of electronic chips (130b) and the further plurality of electrodes (120b), the further trace structure (140b) having conductive traces (142) that connect each of the further plurality of electrodes (120b) to one of the further plurality of electronic chips (130b) wherein the substrate (110) comprises a trench separating the plurality of electrodes (120a), the plurality of electronic chips (130a) and the trace structure (140a) from the further plurality of electrodes (120b), the further plurality of electronic chips (130b) and the further trace structure (140b).

40. Device (100) according to claim 39, comprising a cavity between a side of the substrate facing away from a side of the substrate on which the plurality of electrodes and the further plurality of electrodes are arranged and the electronic chips of the plurality of electronic chips and of the further plurality of electronic chips.

41 . Device (100) according to claim 40, wherein the side of the substrate facing away from the side of the substrate on which the plurality of electrodes and the further plurality of electrodes are arranged comprises a plurality of openings to the cavity.

42. Method (400) for manufacturing a device, wherein the method (400) comprises embedding (420) a plurality of electronic chips in a substrate that comprises an embedding material that is biocompatible and flexible, in a serial arrangement and underneath at least one of a plurality of electrodes; embedding (420) laterally spaced from the plurality of electronic chips a further plurality of electronic chips in the substrate in a serial arrangement and underneath at least one of a further plurality of electrodes; arranging (430) the plurality of electrodes on the substrate; arranging (430) the further plurality of electrodes laterally spaced from the plurality of electrodes on the substrate; such that a trace structure is formed between the plurality of electronic chips and the plurality of electrodes, the trace structure having conductive traces that connect each of the plurality of electrodes to one of the plurality of electronic chips; such that a further trace structure is formed between the further plurality of electronic chips and the further plurality of electrodes, the further trace structure having conductive traces that connect each of the further plurality of electrodes to one of the further plurality of electronic chips; and forming a trench in the substrate separating the plurality of electrodes, the plurality of electronic chips and the trace structure from the further plurality of electrodes, the further plurality of electronic chips and the further trace structure.

43. Method (400) of claim 42 comprising forming a first elongated recess (412) in a wafer-substrate (410); and wherein the embedding (420) of the plurality of electronic chips and of the further plurality of electronic chips comprises: providing a first layer of the embedding material in the first elongated recess (412), arranging the plurality of electronic chips on the first layer and arranging laterally spaced to the plurality of electronic chips the further plurality of electronic chips on the first layer; and arranging a second layer of the embedding material to at least partially embed the plurality of electronic chips and the further plurality of electronic chips.

44. Method (400) of claim 43, further comprising one or more lithographic steps and/or a process for thinning the wafer-substrate (410) and for separating the devices (100), so that a remaining part of the wafer-substrate (410) forms a stabilizing guide unit of the device (100).