WO2025208601A1

WO2025208601A1 - Concatenation of convolutional code and line code

Info

Publication number: WO2025208601A1
Application number: PCT/CN2024/086220
Authority: WO
Inventors: Chao Wei; Mingxi YIN; Changlong Xu; Kazuki Takeda; Hao Xu
Original assignee: Qualcomm Inc
Current assignee: Qualcomm Inc
Priority date: 2024-04-05
Filing date: 2024-04-05
Publication date: 2025-10-09
Anticipated expiration: 2026-10-05

Abstract

Certain aspects of the present disclosure provide techniques for generating and transmitting signals with concatenated convolutional code and line code. A method for wireless communications by a wireless communications device comprises encoding, with a systematic convolutional encoder, a first set of bits from a plurality of information bits to generate a first set of coded bits; line coding, with a line coder, one of the first set of bits or the first set of coded bits to generate one or more line coded bits; concatenating, with a bit mapper component, the one or more line coded bits with the other of the one of the first set of bits or the first set of coded bits that is not line coded to generate a sequence of bits; modulating a carrier waveform with the sequence of bits; and transmitting the modulated carrier waveform.

Description

CONCATENATION OF CONVOLUTIONAL CODE AND LINE CODE

INTRODUCTION

Field of the Disclosure

Aspects of the present disclosure relate to wireless communications, and more particularly, to techniques for generating and transmitting signals with concatenated convolutional code and line code.

Description of Related Art

Wireless communications systems are widely deployed to provide various telecommunication services such as telephony, video, data, messaging, broadcasts, or other similar types of services. These wireless communications systems may employ multiple-access technologies capable of supporting communications with multiple users by sharing available wireless communications system resources with those users.

Although wireless communications systems have made great technological advancements over many years, challenges still exist. For example, complex and dynamic environments can still attenuate or block signals between wireless transmitters and wireless receivers. Accordingly, there is a continuous desire to improve the technical performance of wireless communications systems, including, for example: improving speed and data carrying capacity of communications, improving efficiency of the use of shared communications mediums, reducing power used by transmitters and receivers while performing communications, improving reliability of wireless communications, avoiding redundant transmissions and/or receptions and related processing, improving the coverage area of wireless communications, increasing the number and types of devices that can access wireless communications systems, increasing the ability for different types of devices to intercommunicate, increasing the number and type of wireless communications mediums available for use, and the like. Consequently, there exists a need for further improvements in wireless communications systems to overcome the aforementioned technical challenges and others.

SUMMARY

One aspect provides a method for wireless communications by an apparatus. The method includes encoding, with a systematic convolutional encoder, a first set of bits from a plurality of information bits to generate a first set of coded bits; line coding, with a line coder, one of the first set of bits or the first set of coded bits to generate one or more line coded bits; concatenating, with a bit mapper component, the one or more line coded bits with the other of the one of the first set of bits or the first set of coded bits that is not line coded to generate a sequence of bits; modulating a carrier waveform with the sequence of bits; and transmitting the modulated carrier waveform.

Another aspect provides a method for wireless communications by an apparatus. The method includes encoding, with a non-systematic convolutional encoder, a first set of bits from a plurality of information bits to generate a first set of coded bits and a second set of coded bits corresponding to the first set of bits; line coding, with a line coder, one of the first set of coded bits or the second set of coded bits to generate one or more line coded bits; concatenating, with a bit mapper component, the one or more line coded bits with the other of the one of the first set of coded bits or the second set of coded bits that is not line coded to generate a sequence of bits; modulating a carrier waveform with the sequence of bits; and transmitting the modulated carrier waveform.

Other aspects provide: one or more apparatuses operable, configured, or otherwise adapted to perform any portion of any method described herein (e.g., such that performance may be by only one apparatus or in a distributed fashion across multiple apparatuses) ; one or more non-transitory, computer-readable media comprising instructions that, when executed by one or more processors of one or more apparatuses, cause the one or more apparatuses to perform any portion of any method described herein (e.g., such that instructions may be included in only one computer-readable medium or in a distributed fashion across multiple computer-readable media, such that instructions may be executed by only one processor or by multiple processors in a distributed fashion, such that each apparatus of the one or more apparatuses may include one processor or multiple processors, and/or such that performance may be by only one apparatus or in a distributed fashion across multiple apparatuses) ; one or more computer program products embodied on one or more computer-readable storage media comprising code for performing any portion of any method described herein (e.g., such that code may be stored in only one computer-readable medium or across computer-readable media in a distributed fashion) ; and/or one or more apparatuses comprising one or more means for performing any portion of any method described herein (e.g., such that performance would be by only one apparatus or by multiple apparatuses in a distributed fashion) . By way of example, an apparatus may comprise a processing system, a device with a processing system, or processing systems cooperating over one or more networks. An apparatus may comprise one or more memories; and one or more processors configured to cause the apparatus to perform any portion of any method described herein. In some examples, one or more of the processors may be preconfigured to perform various functions or operations described herein without requiring configuration by software.

The following description and the appended figures set forth certain features for purposes of illustration.

BRIEF DESCRIPTION OF DRAWINGS

The appended figures depict certain features of the various aspects described herein and are not to be considered limiting of the scope of this disclosure.

FIG. 1 depicts an example wireless communications network.

FIG. 2 depicts an example disaggregated base station architecture.

FIG. 3 depicts aspects of an example base station and an example user equipment (UE) .

FIGS. 4A, 4B, 4C, and 4D depict various example aspects of data structures for a wireless communications network.

FIG. 5 depicts an example backscattering wireless communications device.

FIGs. 6A-6E depict example deployment scenarios for a backscattering wireless communications device.

FIGS. 7A-7D depict example diagrams illustrating various encoding scenarios for concatenation of convolutional coded bits and line coded bits for modulation and transmission.

FIG. 8 depicts an illustrative example of block interleaving performed by the concatenator.

FIGS. 9A-9B depict illustrative diagrams corresponding to flexible encoding rate scenarios having a convolutional encoder with a code rate of 1/2.

FIGS. 10A-10B depict illustrative diagrams corresponding to flexible encoding rate scenarios having a convolutional encoder with a code rate of 1/3.

FIGS. 11A-11B depict illustrative diagrams corresponding to flexible encoding rate scenarios having a convolutional encoder with a code rate of 2/3.

FIGS. 12A-12B depict illustrative diagrams corresponding to flexible encoding rate scenarios having a convolutional encoder with a code rate of 3/4.

FIG. 13 depicts a method for wireless communications.

FIG. 14 depicts another method for wireless communications.

FIG. 15 depicts aspects of an example communications device.

FIG. 16 depicts aspects of an example communications device.

DETAILED DESCRIPTION

Aspects of the present disclosure provide apparatuses, methods, processing systems, and computer-readable mediums for generating and transmitting signals with concatenated convolutional code and line code, such as for low power devices.

For example, certain aspects provide techniques for a transmission coding structure that may be capable of achieving both clock recovery capability and coding gains, such as in low power devices, such as ambient Internet of Things (A-IoT) devices. Coding gain is the measure of the difference between the signal-to-noise ratio (SNR) levels between an uncoded system and coded system required to reach the same bit error rate (BER) levels when used with the error correcting code (ECC) . Though certain aspects are discussed herein with respect to techniques for a transmission coding structure for A-IoT devices, it should be noted that the techniques for a transmission coding structure discussed herein may similarly be used for other suitable wireless communications devices, such as other types of user equipments (UEs) , base stations (BSs) , etc.

A-IoT devices may have low complexity designs configured to use low power for communicating (e.g., transmitting and/or receiving) wireless signals. For example, A-IoT devices may generally have limited energy storage capabilities, such as limited storage batteries or a capacitor or other short term energy storage device. In some cases, A-IoT devices rely on energy harvesting from one or more external sources. The one or more external sources may include: solar energy, thermal energy, kinetic energy, radio frequency (RF) energy, electromagnetic radiation (EMR) , other types of ambient energy, and the like. For example, an A-IoT device may include one or more components that allow the A-IoT device to harvest energy, such as solar cells, RF power converters, and the like. Example A-IoT devices include tags, such as radio frequency identification (RFID) tags, passive UEs, backscattering UEs, and the like.

An A-IoT device may not include active RF components, and instead may use passive radio equipment (e.g., a backscatter-type radio) for communicating. For example, A-IoT devices are generally capable of asynchronous communication and may not have a power amplifier or a low-noise amplifier. A-IoT UEs may generally utilize a light protocol stack.

In certain aspects, an A-IoT device, using passive radio equipment, is configured to modulate and reflect incident RF signals (e.g., a carrier wave (CW) ) . For example, another device (e.g., UE, BS, etc. ) may transmit a CW in the direction of the A-IoT device. The A-IoT device, using the passive radio equipment, modulates and reflects the CW to communicate data.

A technical problem for low power devices, such as A-IoT devices, is the tradeoff between power consumption of the device and capability of the device. For example, some low power devices do not support certain capabilities, such as channel coding to provide forward error correction (FEC) , in order to reduce power consumption. However, lack of such capabilities may make such low power devices not well suited for certain communication scenarios. For example, there is a desire to increase the target coverage of A-IoT devices, and therefore it would be advantageous to apply channel coding to improve coding gains compared to only line coding operations.

However, there are at least two technical drawbacks to applying channel coding and line coding in order to achieve coding gains and/or clock recovery capability. Clock recovery capability refers to the process of extracting timing information from a serial data stream, such as a line coded sequence, allowing the timing of the data in the stream to be accurately determined without separate clock information. That is, a clock period may be recovered by observing transitions in the received line coded sequence.

A first technical drawback is the reduction of data rate. For example, the total coding rate may be reduced to 1/4 when FM0 line coding and 1/2 rate convolutional coding are adopted. Second, the performance of a sequential concatenation of FM0 line coding and channel coding could result in multiple bit errors when decoded because FM0 line coding has memory and if one bit is decoded in error, then the subsequent bit may also be decoded in error, for example, when using the Viterbi algorithm for decoding.

While a technical solution of using joint or iterative forward error correction (FEC) and line decoding at the receiver end may improve the aforementioned problem, this may require receiving devices (e.g., UE, BS, etc. ) to implement highly complex decoders for A-IoT backscatter link (BL) signals.

Accordingly, certain aspects herein solve the above technical problem by providing techniques for generating and transmitting signals with concatenated convolutional code and line code. Certain such aspects may have the technical effect of providing additional capabilities to devices, while keeping low power consumption and complexity.

Certain aspects provide techniques for generating transmission coding structures that concatenate convolutional coded bits and line coded bits for transmitting signals by low power devices. In particular, aspects include line coding only a select set of bits, which may be check bits or information bits depending on the type of convolutional encoder. The one or more line coded bits are then concatenated with the other of the one or more bits that are not line coded to generate a sequence of bits for modulation and transmission. In certain aspects, the one or more line coded bits are concatenated with the other of the one or more bits that are not line coded in an interleaved manner, such as to enhance error correction. In certain cases, a technical effect of the concatenation of line coded and non-line coded bits is the ability to achieve clock recovery capability as a sequence of line coded bits are provided in a first block of bits. Additionally, coding gains may be achieved as channel coding is provided through the convolutional encoder encoding a set of the information bits. As will be appreciated by the detailed discussion herein, certain aspects may achieve higher data rate than simple concatenation along with improved performance and reduced power in transmission since not every bit in the transmission may need to be line coded to provide the clock recovery capability.

Introduction to Wireless Communications Networks

The techniques and methods described herein may be used for various wireless communications networks. While aspects may be described herein using terminology commonly associated with 3G, 4G, 5G, 6G, and/or other generations of wireless technologies, aspects of the present disclosure may likewise be applicable to other communications systems and standards not explicitly mentioned herein.

FIG. 1 depicts an example of a wireless communications network 100, in which aspects described herein may be implemented.

Generally, wireless communications network 100 includes various network entities (alternatively, network elements or network nodes) . A network entity is generally a communications device and/or a communications function performed by a communications device (e.g., a user equipment (UE) , a base station (BS) , a component of a BS, a server, etc. ) . As such communications devices are part of wireless communications network 100, and facilitate wireless communications, such communications devices may be referred to as wireless communications devices. For example, various functions of a network as well as various devices associated with and interacting with a network may be considered network entities. Further, wireless communications network 100 includes terrestrial aspects, such as ground-based network entities (e.g., BSs 102) , and non-terrestrial aspects (also referred to herein as non-terrestrial network entities) , such as satellite 140 and transporter, which may include network entities on-board (e.g., one or more BSs) capable of communicating with other network elements (e.g., terrestrial BSs) and UEs.

In the depicted example, wireless communications network 100 includes BSs 102, UEs 104, and one or more core networks, such as an Evolved Packet Core (EPC) 160 and 5G Core (5GC) network 190, which interoperate to provide communications services over various communications links, including wired and wireless links.

FIG. 1 depicts various example UEs 104, which may more generally include: a cellular phone, smart phone, session initiation protocol (SIP) phone, laptop, personal digital assistant (PDA) , satellite radio, global positioning system, multimedia device, video device, digital audio player, camera, game console, tablet, smart device, wearable device, vehicle, electric meter, gas pump, large or small kitchen appliance, healthcare device, implant, sensor/actuator, display, internet of things (IoT) devices, always on (AON) devices, edge processing devices, data centers, or other similar devices. UEs 104 may also be referred to more generally as a mobile device, a wireless device, a station, a mobile station, a subscriber station, a mobile subscriber station, a mobile unit, a subscriber unit, a wireless unit, a remote unit, a remote device, an access terminal, a mobile terminal, a wireless terminal, a remote terminal, a handset, and others.

BSs 102 wirelessly communicate with (e.g., transmit signals to or receive signals from) UEs 104 via communications links 120. The communications links 120 between BSs 102 and UEs 104 may include uplink (UL) (also referred to as reverse link) transmissions from a UE 104 to a BS 102 and/or downlink (DL) (also referred to as forward link) transmissions from a BS 102 to a UE 104. The communications links 120 may use multiple-input and multiple-output (MIMO) antenna technology, including spatial multiplexing, beamforming, and/or transmit diversity in various aspects.

BSs 102 may generally include: a NodeB, enhanced NodeB (eNB) , next generation enhanced NodeB (ng-eNB) , next generation NodeB (gNB or gNodeB) , access point, base transceiver station, radio base station, radio transceiver, transceiver function, transmission reception point, and/or others. Each of BSs 102 may provide communications coverage for a respective coverage area 110, which may sometimes be referred to as a cell, and which may overlap in some cases (e.g., small cell 102’ may have a coverage area 110’ that overlaps the coverage area 110 of a macro cell) . A BS may, for example, provide communications coverage for a macro cell (covering relatively large geographic area) , a pico cell (covering relatively smaller geographic area, such as a sports stadium) , a femto cell (relatively smaller geographic area (e.g., a home) ) , and/or other types of cells.

Generally, a cell may refer to a portion, partition, or segment of wireless communication coverage served by a network entity within a wireless communication network. A cell may have geographic characteristics, such as a geographic coverage area, as well as radio frequency characteristics, such as time and/or frequency resources dedicated to the cell. For example, a specific geographic coverage area may be covered by multiple cells employing different frequency resources (e.g., bandwidth parts) and/or different time resources. As another example, a specific geographic coverage area may be covered by a single cell. In some contexts (e.g., a carrier aggregation scenario and/or multi-connectivity scenario) , the terms “cell” or “serving cell” may refer to or correspond to a specific carrier frequency (e.g., a component carrier) used for wireless communications, and a “cell group” may refer to or correspond to multiple carriers used for wireless communications. As examples, in a carrier aggregation scenario, a UE may communicate on multiple component carriers corresponding to multiple (serving) cells in the same cell group, and in a multi-connectivity (e.g., dual connectivity) scenario, a UE may communicate on multiple component carriers corresponding to multiple cell groups.

While BSs 102 are depicted in various aspects as unitary communications devices, BSs 102 may be implemented in various configurations. For example, one or more components of a base station may be disaggregated, including a central unit (CU) , one or more distributed units (DUs) , one or more radio units (RUs) , a Near-Real Time (Near-RT) RAN Intelligent Controller (RIC) , or a Non-Real Time (Non-RT) RIC, to name a few examples. In another example, various aspects of a base station may be virtualized. More generally, a base station (e.g., BS 102) may include components that are located at a single physical location or components located at various physical locations. In examples in which a base station includes components that are located at various physical locations, the various components may each perform functions such that, collectively, the various components achieve functionality that is similar to a base station that is located at a single physical location. In some aspects, a base station including components that are located at various physical locations may be referred to as a disaggregated radio access network architecture, such as an Open RAN (O-RAN) or Virtualized RAN (VRAN) architecture. FIG. 2 depicts and describes an example disaggregated base station architecture.

Different BSs 102 within wireless communications network 100 may also be configured to support different radio access technologies, such as 3G, 4G, and/or 5G. For example, BSs 102 configured for 4G LTE (collectively referred to as Evolved Universal Mobile Telecommunications System (UMTS) Terrestrial Radio Access Network (E-UTRAN) ) may interface with the EPC 160 through first backhaul links 132 (e.g., an S1 interface) . BSs 102 configured for 5G (e.g., 5G NR or Next Generation RAN (NG-RAN) ) may interface with 5GC 190 through second backhaul links 184. BSs 102 may communicate directly or indirectly (e.g., through the EPC 160 or 5GC 190) with each other over third backhaul links 134 (e.g., X2 interface) , which may be wired or wireless.

Wireless communications network 100 may subdivide the electromagnetic spectrum into various classes, bands, channels, or other features. In some aspects, the subdivision is provided based on wavelength and frequency, where frequency may also be referred to as a carrier, a subcarrier, a frequency channel, a tone, or a subband. For example, 3GPP currently defines Frequency Range 1 (FR1) as including 410 MHz –7125 MHz, which is often referred to (interchangeably) as “Sub-6 GHz”. Similarly, 3GPP currently defines Frequency Range 2 (FR2) as including 24,250 MHz –71,000 MHz, which is sometimes referred to (interchangeably) as a “millimeter wave” ( “mmW” or “mmWave” ) . In some cases, FR2 may be further defined in terms of sub-ranges, such as a first sub-range FR2-1 including 24,250 MHz –52,600 MHz and a second sub-range FR2-2 including 52,600 MHz –71,000 MHz. A base station configured to communicate using mmWave/near mmWave radio frequency bands (e.g., a mmWave base station such as BS 180) may utilize beamforming (e.g., 182) with a UE (e.g., 104) to improve path loss and range.

The communications links 120 between BSs 102 and, for example, UEs 104, may be through one or more carriers, which may have different bandwidths (e.g., 5, 10, 15, 20, 100, 400, and/or other MHz) , and which may be aggregated in various aspects. Carriers may or may not be adjacent to each other. Allocation of carriers may be asymmetric with respect to DL and UL (e.g., more or fewer carriers may be allocated for DL than for UL) .

Communications using higher frequency bands may have higher path loss and a shorter range compared to lower frequency communications. Accordingly, certain base stations (e.g., 180 in FIG. 1) may utilize beamforming 182 with a UE 104 to improve path loss and range. For example, BS 180 and the UE 104 may each include a plurality of antennas, such as antenna elements, antenna panels, and/or antenna arrays to facilitate the beamforming. In some cases, BS 180 may transmit a beamformed signal to UE 104 in one or more transmit directions 182’. UE 104 may receive the beamformed signal from the BS 180 in one or more receive directions 182”. UE 104 may also transmit a beamformed signal to the BS 180 in one or more transmit directions 182”. BS 180 may also receive the beamformed signal from UE 104 in one or more receive directions 182’. BS 180 and UE 104 may then perform beam training to determine the best receive and transmit directions for each of BS 180 and UE 104. Notably, the transmit and receive directions for BS 180 may or may not be the same. Similarly, the transmit and receive directions for UE 104 may or may not be the same.

Wireless communications network 100 further includes a Wi-Fi AP 150 in communication with Wi-Fi stations (STAs) 152 via communications links 154 in, for example, a 2.4 GHz and/or 5 GHz unlicensed frequency spectrum.

Certain UEs 104 may communicate with each other using device-to-device (D2D) communications link 158. D2D communications link 158 may use one or more sidelink channels, such as a physical sidelink broadcast channel (PSBCH) , a physical sidelink discovery channel (PSDCH) , a physical sidelink shared channel (PSSCH) , a physical sidelink control channel (PSCCH) , and/or a physical sidelink feedback channel (PSFCH) .

EPC 160 may include various functional components, including: a Mobility Management Entity (MME) 162, other MMEs 164, a Serving Gateway 166, a Multimedia Broadcast Multicast Service (MBMS) Gateway 168, a Broadcast Multicast Service Center (BM-SC) 170, and/or a Packet Data Network (PDN) Gateway 172, such as in the depicted example. MME 162 may be in communication with a Home Subscriber Server (HSS) 174. MME 162 is the control node that processes the signaling between the UEs 104 and the EPC 160. Generally, MME 162 provides bearer and connection management.

Generally, user Internet protocol (IP) packets are transferred through Serving Gateway 166, which itself is connected to PDN Gateway 172. PDN Gateway 172 provides UE IP address allocation as well as other functions. PDN Gateway 172 and the BM-SC 170 are connected to IP Services 176, which may include, for example, the Internet, an intranet, an IP Multimedia Subsystem (IMS) , a Packet Switched (PS) streaming service, and/or other IP services.

BM-SC 170 may provide functions for MBMS user service provisioning and delivery. BM-SC 170 may serve as an entry point for content provider MBMS transmission, may be used to authorize and initiate MBMS Bearer Services within a public land mobile network (PLMN) , and/or may be used to schedule MBMS transmissions. MBMS Gateway 168 may be used to distribute MBMS traffic to the BSs 102 belonging to a Multicast Broadcast Single Frequency Network (MBSFN) area broadcasting a particular service, and/or may be responsible for session management (start/stop) and for collecting eMBMS related charging information.

5GC 190 may include various functional components, including: an Access and Mobility Management Function (AMF) 192, other AMFs 193, a Session Management Function (SMF) 194, and a User Plane Function (UPF) 195. AMF 192 may be in communication with Unified Data Management (UDM) 196.

AMF 192 is a control node that processes signaling between UEs 104 and 5GC 190. AMF 192 provides, for example, quality of service (QoS) flow and session management.

Internet protocol (IP) packets are transferred through UPF 195, which is connected to the IP Services 197, and which provides UE IP address allocation as well as other functions for 5GC 190. IP Services 197 may include, for example, the Internet, an intranet, an IMS, a PS streaming service, and/or other IP services.

In various aspects, a network entity or network node can be implemented as an aggregated base station, as a disaggregated base station, a component of a base station, an integrated access and backhaul (IAB) node, a relay node, a sidelink node, to name a few examples.

FIG. 2 depicts an example disaggregated base station 200 architecture. The disaggregated base station 200 architecture may include one or more central units (CUs) 210 that can communicate directly with a core network 220 via a backhaul link, or indirectly with the core network 220 through one or more disaggregated base station units (such as a Near-Real Time (Near-RT) RAN Intelligent Controller (RIC) 225 via an E2 link, or a Non-Real Time (Non-RT) RIC 215 associated with a Service Management and Orchestration (SMO) Framework 205, or both) . A CU 210 may communicate with one or more distributed units (DUs) 230 via respective midhaul links, such as an F1 interface. The DUs 230 may communicate with one or more radio units (RUs) 240 via respective fronthaul links. The RUs 240 may communicate with respective UEs 104 via one or more radio frequency (RF) access links. In some implementations, the UE 104 may be simultaneously served by multiple RUs 240.

Each of the units, e.g., the CUs 210, the DUs 230, the RUs 240, as well as the Near-RT RICs 225, the Non-RT RICs 215 and the SMO Framework 205, may include one or more interfaces or be coupled to one or more interfaces configured to receive or transmit signals, data, or information (collectively, signals) via a wired or wireless transmission medium. Each of the units, or an associated processor or controller providing instructions to the communications interfaces of the units, can be configured to communicate with one or more of the other units via the transmission medium. For example, the units can include a wired interface configured to receive or transmit signals over a wired transmission medium to one or more of the other units. Additionally or alternatively, the units can include a wireless interface, which may include a receiver, a transmitter or transceiver (such as a radio frequency (RF) transceiver) , configured to receive or transmit signals, or both, over a wireless transmission medium to one or more of the other units.

In some aspects, the CU 210 may host one or more higher layer control functions. Such control functions can include radio resource control (RRC) , packet data convergence protocol (PDCP) , service data adaptation protocol (SDAP) , or the like. Each control function can be implemented with an interface configured to communicate signals with other control functions hosted by the CU 210. The CU 210 may be configured to handle user plane functionality (e.g., Central Unit –User Plane (CU-UP) ) , control plane functionality (e.g., Central Unit –Control Plane (CU-CP) ) , or a combination thereof. In some implementations, the CU 210 can be logically split into one or more CU-UP units and one or more CU-CP units. The CU-UP unit can communicate bidirectionally with the CU-CP unit via an interface, such as the E1 interface when implemented in an O-RAN configuration. The CU 210 can be implemented to communicate with the DU 230, as necessary, for network control and signaling.

The DU 230 may correspond to a logical unit that includes one or more base station functions to control the operation of one or more RUs 240. In some aspects, the DU 230 may host one or more of a radio link control (RLC) layer, a medium access control (MAC) layer, and one or more high physical (PHY) layers (such as modules for forward error correction (FEC) encoding and decoding, scrambling, modulation and demodulation, or the like) depending, at least in part, on a functional split, such as those defined by the 3^rd Generation Partnership Project (3GPP) . In some aspects, the DU 230 may further host one or more low PHY layers. Each layer (or module) can be implemented with an interface configured to communicate signals with other layers (and modules) hosted by the DU 230, or with the control functions hosted by the CU 210.

Lower-layer functionality can be implemented by one or more RUs 240. In some deployments, an RU 240, controlled by a DU 230, may correspond to a logical node that hosts RF processing functions, or low-PHY layer functions (such as performing fast Fourier transform (FFT) , inverse FFT (iFFT) , digital beamforming, physical random access channel (PRACH) extraction and filtering, or the like) , or both, based at least in part on the functional split, such as a lower layer functional split. In such an architecture, the RU (s) 240 can be implemented to handle over the air (OTA) communications with one or more UEs 104. In some implementations, real-time and non-real-time aspects of control and user plane communications with the RU (s) 240 can be controlled by the corresponding DU 230. In some scenarios, this configuration can enable the DU (s) 230 and the CU 210 to be implemented in a cloud-based RAN architecture, such as a vRAN architecture.

The SMO Framework 205 may be configured to support RAN deployment and provisioning of non-virtualized and virtualized network elements. For non-virtualized network elements, the SMO Framework 205 may be configured to support the deployment of dedicated physical resources for RAN coverage requirements which may be managed via an operations and maintenance interface (such as an O1 interface) . For virtualized network elements, the SMO Framework 205 may be configured to interact with a cloud computing platform (such as an open cloud (O-Cloud) 290) to perform network element life cycle management (such as to instantiate virtualized network elements) via a cloud computing platform interface (such as an O2 interface) . Such virtualized network elements can include, but are not limited to, CUs 210, DUs 230, RUs 240 and Near-RT RICs 225. In some implementations, the SMO Framework 205 can communicate with a hardware aspect of a 4G RAN, such as an open eNB (O-eNB) 211, via an O1 interface. Additionally, in some implementations, the SMO Framework 205 can communicate directly with one or more DUs 230 and/or one or more RUs 240 via an O1 interface. The SMO Framework 205 also may include a Non-RT RIC 215 configured to support functionality of the SMO Framework 205.

The Non-RT RIC 215 may be configured to include a logical function that enables non-real-time control and optimization of RAN elements and resources, Artificial Intelligence/Machine Learning (AI/ML) workflows including model training and updates, or policy-based guidance of applications/features in the Near-RT RIC 225. The Non-RT RIC 215 may be coupled to or communicate with (such as via an A1 interface) the Near-RT RIC 225. The Near-RT RIC 225 may be configured to include a logical function that enables near-real-time control and optimization of RAN elements and resources via data collection and actions over an interface (such as via an E2 interface) connecting one or more CUs 210, one or more DUs 230, or both, as well as an O-eNB, with the Near-RT RIC 225.

In some implementations, to generate AI/ML models to be deployed in the Near-RT RIC 225, the Non-RT RIC 215 may receive parameters or external enrichment information from external servers. Such information may be utilized by the Near-RT RIC 225 and may be received at the SMO Framework 205 or the Non-RT RIC 215 from non-network data sources or from network functions. In some examples, the Non-RT RIC 215 or the Near-RT RIC 225 may be configured to tune RAN behavior or performance. For example, the Non-RT RIC 215 may monitor long-term trends and patterns for performance and employ AI/ML models to perform corrective actions through the SMO Framework 205 (such as reconfiguration via O1) or via creation of RAN management policies (such as A1 policies) .

FIG. 3 depicts aspects of an example BS 102 and a UE 104.

Generally, BS 102 includes various processors (e.g., 318, 320, 330, 338, and 340) , antennas 334a-t (collectively 334) , transceivers 332a-t (collectively 332) , which include modulators and demodulators, and other aspects, which enable wireless transmission of data (e.g., data source 312) and wireless reception of data (e.g., data sink 314) . For example, BS 102 may send and receive data between BS 102 and UE 104. BS 102 includes controller/processor 340, which may be configured to implement various functions described herein related to wireless communications.

Generally, UE 104 includes various processors (e.g., 358, 364, 366, 370, and 380) , antennas 352a-r (collectively 352) , transceivers 354a-r (collectively 354) , which include modulators and demodulators, and other aspects, which enable wireless transmission of data (e.g., retrieved from data source 362) and wireless reception of data (e.g., provided to data sink 360) . UE 104 includes controller/processor 380, which may be configured to implement various functions described herein related to wireless communications.

In regards to an example downlink transmission, BS 102 includes a transmit processor 320 that may receive data from a data source 312 and control information from a controller/processor 340. The control information may be for the physical broadcast channel (PBCH) , physical control format indicator channel (PCFICH) , physical hybrid automatic repeat request (HARQ) indicator channel (PHICH) , physical downlink control channel (PDCCH) , group common PDCCH (GC PDCCH) , and/or others. The data may be for the physical downlink shared channel (PDSCH) , in some examples.

Transmit processor 320 may process (e.g., encode and symbol map) the data and control information to obtain data symbols and control symbols, respectively. Transmit processor 320 may also generate reference symbols, such as for the primary synchronization signal (PSS) , secondary synchronization signal (SSS) , PBCH demodulation reference signal (DMRS) , and channel state information reference signal (CSI-RS) .

Transmit (TX) multiple-input multiple-output (MIMO) processor 330 may perform spatial processing (e.g., precoding) on the data symbols, the control symbols, and/or the reference symbols, if applicable, and may provide output symbol streams to the modulators (MODs) in transceivers 332a-332t. Each modulator in transceivers 332a-332t may process a respective output symbol stream to obtain an output sample stream. Each modulator may further process (e.g., convert to analog, amplify, filter, and upconvert) the output sample stream to obtain a downlink signal. Downlink signals from the modulators in transceivers 332a-332t may be transmitted via the antennas 334a-334t, respectively.

In order to receive the downlink transmission, UE 104 includes antennas 352a-352r that may receive the downlink signals from the BS 102 and may provide received signals to the demodulators (DEMODs) in transceivers 354a-354r, respectively. Each demodulator in transceivers 354a-354r may condition (e.g., filter, amplify, downconvert, and digitize) a respective received signal to obtain input samples. Each demodulator may further process the input samples to obtain received symbols.

RX MIMO detector 356 may obtain received symbols from all the demodulators in transceivers 354a-354r, perform MIMO detection on the received symbols if applicable, and provide detected symbols. Receive processor 358 may process (e.g., demodulate, deinterleave, and decode) the detected symbols, provide decoded data for the UE 104 to a data sink 360, and provide decoded control information to a controller/processor 380.

In regards to an example uplink transmission, UE 104 further includes a transmit processor 364 that may receive and process data (e.g., for the PUSCH) from a data source 362 and control information (e.g., for the physical uplink control channel (PUCCH) ) from the controller/processor 380. Transmit processor 364 may also generate reference symbols for a reference signal (e.g., for the sounding reference signal (SRS) ) . The symbols from the transmit processor 364 may be precoded by a TX MIMO processor 366 if applicable, further processed by the modulators in transceivers 354a-354r (e.g., for SC-FDM) , and transmitted to BS 102.

At BS 102, the uplink signals from UE 104 may be received by antennas 334a-t, processed by the demodulators in transceivers 332a-332t, detected by a RX MIMO detector 336 if applicable, and further processed by a receive processor 338 to obtain decoded data and control information sent by UE 104. Receive processor 338 may provide the decoded data to a data sink 314 and the decoded control information to the controller/processor 340.

Memories 342 and 382 may store data and program codes for BS 102 and UE 104, respectively.

Scheduler 344 may schedule UEs for data transmission on the downlink and/or uplink.

In various aspects, BS 102 may be described as transmitting and receiving various types of data associated with the methods described herein. In these contexts, “transmitting” may refer to various mechanisms of outputting data, such as outputting data from data source 312, scheduler 344, memory 342, transmit processor 320, controller/processor 340, TX MIMO processor 330, transceivers 332a-t, antenna 334a-t, and/or other aspects described herein. Similarly, “receiving” may refer to various mechanisms of obtaining data, such as obtaining data from antennas 334a-t, transceivers 332a-t, RX MIMO detector 336, controller/processor 340, receive processor 338, scheduler 344, memory 342, and/or other aspects described herein.

In various aspects, UE 104 may likewise be described as transmitting and receiving various types of data associated with the methods described herein. In these contexts, “transmitting” may refer to various mechanisms of outputting data, such as outputting data from data source 362, memory 382, transmit processor 364, controller/processor 380, TX MIMO processor 366, transceivers 354a-t, antenna 352a-t, and/or other aspects described herein. Similarly, “receiving” may refer to various mechanisms of obtaining data, such as obtaining data from antennas 352a-t, transceivers 354a-t, RX MIMO detector 356, controller/processor 380, receive processor 358, memory 382, and/or other aspects described herein.

In some aspects, a processor may be configured to perform various operations, such as those associated with the methods described herein, and transmit (output) to or receive (obtain) data from another interface that is configured to transmit or receive, respectively, the data.

In various aspects, artificial intelligence (AI) processors 318 and 370 may perform AI processing for BS 102 and/or UE 104, respectively. The AI processor 318 may include AI accelerator hardware or circuitry such as one or more neural processing units (NPUs) , one or more neural network processors, one or more tensor processors, one or more deep learning processors, etc. The AI processor 370 may likewise include AI accelerator hardware or circuitry. As an example, the AI processor 370 may perform AI-based beam management, AI-based channel state feedback (CSF) , AI-based antenna tuning, and/or AI-based positioning (e.g., global navigation satellite system (GNSS) positioning) . In some cases, the AI processor 318 may process feedback from the UE 104 (e.g., CSF) using hardware accelerated AI inferences and/or AI training. The AI processor 318 may decode compressed CSF from the UE 104, for example, using a hardware accelerated AI inference associated with the CSF. In certain cases, the AI processor 318 may perform certain RAN-based functions including, for example, network planning, network performance management, energy-efficient network operations, etc.

FIGS. 4A, 4B, 4C, and 4D depict aspects of data structures for a wireless communications network, such as wireless communications network 100 of FIG. 1.

In particular, FIG. 4A is a diagram 400 illustrating an example of a first subframe within a 5G (e.g., 5G NR) frame structure, FIG. 4B is a diagram 430 illustrating an example of DL channels within a 5G subframe, FIG. 4C is a diagram 450 illustrating an example of a second subframe within a 5G frame structure, and FIG. 4D is a diagram 480 illustrating an example of UL channels within a 5G subframe.

Wireless communications systems may utilize orthogonal frequency division multiplexing (OFDM) with a cyclic prefix (CP) on the uplink and downlink. Such systems may also support half-duplex operation using time division duplexing (TDD) . OFDM and single-carrier frequency division multiplexing (SC-FDM) partition the system bandwidth (e.g., as depicted in FIGS. 4B and 4D) into multiple orthogonal subcarriers. Each subcarrier may be modulated with data. Modulation symbols may be sent in the frequency domain with OFDM and/or in the time domain with SC-FDM.

A wireless communications frame structure may be frequency division duplex (FDD) , in which, for a particular set of subcarriers, subframes within the set of subcarriers are dedicated for either DL or UL. Wireless communications frame structures may also be time division duplex (TDD) , in which, for a particular set of subcarriers, subframes within the set of subcarriers are dedicated for both DL and UL.

In FIG. 4A and 4C, the wireless communications frame structure is TDD where D is DL, U is UL, and X is flexible for use between DL/UL. UEs may be configured with a slot format through a received slot format indicator (SFI) (dynamically through DL control information (DCI) , or semi-statically/statically through radio resource control (RRC) signaling) . In the depicted examples, a 10 ms frame is divided into 10 equally sized 1 ms subframes. Each subframe may include one or more time slots. In some examples, each slot may include 12 or 14 symbols, depending on the cyclic prefix (CP) type (e.g., 12 symbols per slot for an extended CP or 14 symbols per slot for a normal CP) . Subframes may also include mini-slots, which generally have fewer symbols than an entire slot. Other wireless communications technologies may have a different frame structure and/or different channels.

In certain aspects, the number of slots within a subframe (e.g., a slot duration in a subframe) is based on a numerology, which may define a frequency domain subcarrier spacing and symbol duration as further described herein. In certain aspects, given a numerology μ, there are 2^μ slots per subframe. Thus, numerologies (μ) 0 to 6 may allow for 1, 2, 4, 8, 16, 32, and 64 slots, respectively, per subframe. In some cases, the extended CP (e.g., 12 symbols per slot) may be used with a specific numerology, e.g., numerology 2 allowing for 4 slots per subframe. The subcarrier spacing and symbol length/duration are a function of the numerology. The subcarrier spacing may be equal to 2^μ×15 kHz, where μ is the numerology 0 to 6. As an example, the numerology μ=0 corresponds to a subcarrier spacing of 15 kHz, and the numerology μ=6 corresponds to a subcarrier spacing of 960 kHz. The symbol length/duration is inversely related to the subcarrier spacing. FIGS. 4A, 4B, 4C, and 4D provide an example of a slot format having 14 symbols per slot (e.g., a normal CP) and a numerology μ=2 with 4 slots per subframe. In such a case, the slot duration is 0.25 ms, the subcarrier spacing is 60 kHz, and the symbol duration is approximately 16.67 μs.

As depicted in FIGS. 4A, 4B, 4C, and 4D, a resource grid may be used to represent the frame structure. Each time slot includes a resource block (RB) (also referred to as physical RBs (PRBs) ) that extends, for example, 12 consecutive subcarriers. The resource grid is divided into multiple resource elements (REs) . The number of bits carried by each RE depends on the modulation scheme including, for example, quadrature phase shift keying (QPSK) or quadrature amplitude modulation (QAM) .

As illustrated in FIG. 4A, some of the REs carry reference (pilot) signals (RS) for a UE (e.g., UE 104 of FIGS. 1 and 3) . The RS may include demodulation RS (DMRS) and/or channel state information reference signals (CSI-RS) for channel estimation at the UE.The RS may also include beam measurement RS (BRS) , beam refinement RS (BRRS) , and/or phase tracking RS (PT-RS) .

FIG. 4B illustrates an example of various DL channels within a subframe of a frame. The physical downlink control channel (PDCCH) carries DCI within one or more control channel elements (CCEs) , each CCE including, for example, nine RE groups (REGs) , each REG including, for example, four consecutive REs in an OFDM symbol.

A primary synchronization signal (PSS) may be within symbol 2 of particular subframes of a frame. The PSS is used by a UE (e.g., 104 of FIGS. 1 and 3) to determine subframe/symbol timing and a physical layer identity.

A secondary synchronization signal (SSS) may be within symbol 4 of particular subframes of a frame. The SSS is used by a UE to determine a physical layer cell identity group number and radio frame timing.

Based on the physical layer identity and the physical layer cell identity group number, the UE can determine a physical cell identifier (PCI) . Based on the PCI, the UE can determine the locations of the aforementioned DMRS. The physical broadcast channel (PBCH) , which carries a master information block (MIB) , may be logically grouped with the PSS and SSS to form a synchronization signal (SS) /PBCH block. The MIB provides a number of RBs in the system bandwidth and a system frame number (SFN) . The physical downlink shared channel (PDSCH) carries user data, broadcast system information not transmitted through the PBCH such as system information blocks (SIBs) , and/or paging messages.

As illustrated in FIG. 4C, some of the REs carry DMRS (indicated as R for one particular configuration, but other DMRS configurations are possible) for channel estimation at the base station. The UE may transmit DMRS for the PUCCH and DMRS for the PUSCH. The PUSCH DMRS may be transmitted, for example, in the first one or two symbols of the PUSCH. The PUCCH DMRS may be transmitted in different configurations depending on whether short or long PUCCHs are transmitted and depending on the particular PUCCH format used. UE 104 may transmit sounding reference signals (SRS) . The SRS may be transmitted, for example, in the last symbol of a subframe. The SRS may have a comb structure, and a UE may transmit SRS on one of the combs. The SRS may be used by a base station for channel quality estimation to enable frequency-dependent scheduling on the UL.

FIG. 4D illustrates an example of various UL channels within a subframe of a frame. The PUCCH may be located as indicated in one configuration. The PUCCH carries uplink control information (UCI) , such as scheduling requests, a channel quality indicator (CQI) , a precoding matrix indicator (PMI) , a rank indicator (RI) , and HARQ ACK/NACK feedback. The PUSCH carries data, and may additionally be used to carry a buffer status report (BSR) , a power headroom report (PHR) , and/or UCI.

Aspects Related to Backscattering

FIG. 5 depicts an example backscattering wireless communications device 506. The backscattering wireless communications device 506 may be an AIoT device, a UE (e.g., similar to UE 104 of FIG. 1) , or the like.

As shown, backscattering wireless communications device 506 includes an antenna 552, an energy harvesting (EH) circuit 554, a microcontroller 556, a switch 558, and impedance circuits 560. In other aspects, backscattering wireless communications device 506 may include additional components (e.g., a battery or capacitor) , or fewer components (e.g., removal of EH circuit 554) .

Antenna 552 may be similar to antenna 352a of FIG. 3. Antenna 552 is coupled to EH circuit 554. EH circuit 554 may include one or more power converters and/or the like for receiving (e.g., RF) energy and converting it into usable energy for backscattering wireless communications device 506. EH circuit 554 is further coupled to microcontroller 556. In other aspects, microcontroller 556 may be directly coupled to antenna 552.

Microcontroller 556 is coupled to switch 558 and configured to control switch 558 to selectively couple impedance circuits 560 to the circuit including antenna 552. Impedance circuits 560 may be any components that provide impedance.

FIG. 5 further depicts a wireless communications device 501, such as a UE (e.g., UE 104 of FIG. 1) , BS (e.g., BS 102 of FIG. 1) , or the like. Wireless communications device 501 further includes antennas 534a and 534b, which may be similar to antennas 334a and 334b of FIG. 3.

In certain aspects, wireless communications device 501 is configured to transmit a carrier wave from antenna 534a. A carrier wave is a waveform (e.g., sinusoidal waveform) that can be modulated with data (e.g., an information-bearing signal) to generate a modulated signal that conveys the data.

In certain aspects, backscattering wireless communications device 506 is configured to receive the carrier wave, transmitted by wireless communications device 501, at antenna 552. Backscattering wireless communications device 506 modulates the carrier wave be switching the switch 558 to vary the impedance coupled to the antenna 552. In particular, the switch 558 varies the impedance by switching a number or size of impedance circuits 560 coupled to antenna 552. Varying the impedance coupled to the antenna 552 varies an amplitude and/or phase of the carrier wave. For example, when the antenna 552 is coupled to a high impedance, the mismatch between the antenna and load impedance reflects all the power received on antenna 552 back. When the antenna 552 is coupled to an impedance matched to an impedance of the antenna, the match between the antenna and load impedances causes the power to be absorbed at backscattering wireless communications device 506 and little power is reflected on antenna 552. Therefore, switching between a high impedance and matched impedance modulates an amplitude of the carrier wave reflected. The frequency of switching between the impedances may be associated with a data rate of communicating data.

Accordingly, the microcontroller 556 controls the switch 558 to modulate the carrier wave with data, to generate a modulated backscattered signal. For example, microcontroller 556 controls the switch 558 to perform amplitude-shift keying (ASK) modulation to vary the amplitude of the carrier wave and or phase-shift keying (PSK) modulation to vary the phase of the carrier wave and or frequency-shift keying (FSK) modulation to vary the frequency of the carrier wave. Backscattering wireless communications device 506 transmits (e.g., reflects) the modulated backscattered signal via antenna 552.

In certain aspects, wireless communications device 501 is configured to receive the modulated backscattered signal on antenna 534b. The wireless communications device 501 may process the modulated backscattered signal to decode the data transmitted by backscattering wireless communications device 506.

FIG. 6A depicts a monostatic deployment scenario, whereby backscattering wireless communications device 606 (e.g., backscattering wireless communications device 506 of FIG. 5) is configured to receive a carrier wave from and reflect a modulated backscattered signal to the same wireless communications device 601 (e.g., UE 104 or BS 102 of FIG. 1, wireless communications device 501 of FIG. 5) . For example, wireless communications device 601 may be capable of full duplex communications. As shown, wireless communications device 601 transmits a signal to backscattering wireless communications device 606 that serves as both a carrier wave (CW) and a forward link (FL) signal that carries control signaling. Backscattering wireless communications device 606 modulates and reflects the signal as a backscatter link (BL) signal that carries data. In certain aspects, the CW and FL signals may be sent separately.

FIGs. 6B-6E depict different bi-static deployment scenarios, whereby backscattering wireless communications device 606 is configured to receive a carrier wave from one device and reflect a modulated backscattered signal to a different device, such as for half-duplex communications.

FIG. 6B illustrates a scenario whereby backscattering wireless communications device 606 is configured to receive a signal that serves as both a CW and FL signal from BS 602 (e.g., BS 102 of FIG. 1) . Backscattering wireless communications device 606 modulates and reflects the signal as a BL signal that carries data to UE 604 (e.g., UE 104 of FIG. 1) . In certain aspects, the CW and FL signals may be sent separately.

FIG. 6C illustrates a scenario whereby backscattering wireless communications device 606 is configured to receive a signal that serves as both a CW and FL signal from UE 604. Backscattering wireless communications device 606 modulates and reflects the signal as a BL signal that carries data to BS 602. In certain aspects, the CW and FL signals may be sent separately.

FIG. 6D illustrates a scenario whereby backscattering wireless communications device 606 is configured to receive a CW from BS 602. Backscattering wireless communications device 606 modulates and reflects the CW signal as a BL signal that carries data to UE 604. Backscattering wireless communications device 606 further receives an FL signal from UE 604.

FIG. 6E illustrates a scenario whereby backscattering wireless communications device 606 is configured to receive a CW from UE 604. Backscattering wireless communications device 606 modulates and reflects the CW signal as a BL signal that carries data to BS 602. Backscattering wireless communications device 606 further receives an FL signal from BS 602.

Aspects Related to Generating and Transmitting Signals with Concatenated Convolutional Code and Line Code

FIGS. 7A-7D depict example diagrams illustrating various encoding scenarios 700, 710, 720, and 730 comprising concatenation of convolutional coded bits and line coded bits in an interleaved manner for modulation and transmission. In some aspects, the convolutional coded bits and line coded bits are concatenated in an interleaved manner.

In certain aspects, any one or more of the encoding scenarios 700, 710, 720, and 730 may be used in a backscattering wireless communications device, such as backscattering wireless communications device 506 of FIG. 5 or backscattering wireless communications device 606 of FIG. 6. In certain aspects, any one or more of the encoding scenarios 700, 710, 720, and 730 may be used in another wireless communications device, such as a UE (e.g., UE 104 of FIG. 1) , a BS (e.g., BS 102 of FIG. 1) , or other network entity.

In certain aspects, any one or more of the encoding scenarios 700, 710, 720, and 730 may be used in a wireless communications device for downlink (DL) transmissions. For example, any one or more of the encoding scenarios 700, 710, 720, and 730 may be used in a UE (e.g., UE 104 of FIG. 1) , a BS (e.g., BS 102 of FIG. 1) , or other network entity to transmit data to a backscattering wireless communications device or other UE. For example, the encoding schemes used to encode data with one of the encoding scenarios 700, 710, 720, and 730 may achieve higher data rate than the simple concatenation along with improved performance and reduced power in transmission since not every bit in the transmission needs to be line coded to provide the clock recovery capability in a transmission.

In certain aspects, any one or more of the encoding scenarios 700, 710, 720, and 730 may be used for uplink (UL) transmissions.

The encoding scenarios 700, 710, 720, and 730 depicted in FIGS. 7A-7D can be grouped into two types, encoding scenarios 700 and 710 implementing systematic convolutional encoder 702 and systematic convolutional encoder 712, respectively, as depicted and described with reference FIGS. 7A-7B and encoding scenarios 720 and 730 implementing non-systematic convolutional encoder 722 and non-systematic convolutional encoder 732, respectively, as depicted and described with reference FIGS. 7C-7D. In each of the encoding scenarios 700, 710, 720, and 730, information bits (b1) are encoded through one of the encoding scenarios 700, 710, 720, and 730 which includes a convolutional encoder (e.g., systematic convolutional encoder 702, systematic convolutional encoder 712, non-systematic convolutional encoder 722, or non-systematic convolutional encoder 732) and a line coder, such as one or more of line coder 704, 714, 724, or 734. As described in more detail herein with reference to each of the encoding scenarios 700, 710, 720, and 730, respectively, the line coded bits (e.g., line coded information bits, line coded check bits, or convolution coded bits referred to herein as a first set of coded bits corresponding to the information bits from a non-systematic convolutional encoder 722 or 732) and the non-line coded bits (e.g., information bits, check bits, or convolution coded bits referred to herein as a first set of coded bits corresponding to the information bits from a non-systematic convolutional encoder 722 or 732) are respectively concatenated with a concatenator 706, 716, 726, or 736.

A systematic convolutional encoder (e.g., 702 or 712) and a non-systematic convolutional encoder (e.g., 722 or 732) may both types of error-correcting encoder that generate parity symbols, also referred to as check bits, via a sliding application of a boolean polynomial function to a data stream such as the plurality of information bits (b1) .

Convolutional codes are often characterized by the base code rate and the depth (or memory) of the encoder [n, k, K] . The base code rate is typically given as n/k, where n is the raw input data rate and k is the data rate of output channel encoded stream. n is less than k because channel coding inserts redundancy in the input bits. The memory is often called the “constraint length” K, where the output is a function of the current input as well as the previous K-1 inputs. The depth may also be given as the number of memory elements v in the polynomial or the maximum possible number of states of the encoder (e.g., 2^v) .

Convolutional codes can be systematic or non-systematic. Systematic convolutional encoders repeat the structure of the message before encoding, while non-systematic convolutional encoders change the initial structure of the input data. For example, given illustrative input information bits [101] , a non-systematic convolutional encoder may output [101101] , where the second, fourth, and sixth bit represent the check bits and the first, third, and fifth bit represent the encoded information bits. Similarly, for example, given illustrative input information bits [101] , a systematic convolutional encoder may output [110110] , where the second, fourth, and sixth bit represent the check bits and the first, third, and fifth bit represent the encoded information bits. It is observable that the first, third, and fifth bit output by the systematic convolutional encoder directly correspond to the input information bits, thus appearing unchanged at the output. Conversely, a non-systematic convolutional encoder encodes the input information bits, thus the output of the first, third, and fifth bit does not directly correspond to the input information bits.

The line coders 704, 714, 724, and 734 form a pattern of voltage, current, or photons used to represent digital data for transmitting on a communication channel or written into a storage medium. Line codes are useful for clock recovery and identifying symbol boundary during data reception. Some example line coders considered, such as for A-IoT devices, may include FM0 encoders, Manchester encoders, Miller-Modulated Subcarrier (MMS) 2, 4, or 8 encoder, or the like.

The concatenator 706, 716, 726, or 736 may be configured to receive as input a plurality of line coded and non-line coded bits. In certain aspects, concatenator 706, 716, 726, or 736 may be coupled directly to a respective convolutional encoder 702, 712, 722, or 732 and a respective line coder 704, 714, 724, or 734, depending on the respective encoding scenarios 700, 710, 720, or 730. The concatenator 706, 716, 726, or 736 may be a multiplexer.

The concatenator 706, 716, 726, or 736 is configured to concatenate the line coded bits with the non-line coded bits to generate a sequence of bits for modulation by the respective modulator 708, 718, 728, or 728. In certain aspects, the concatenator 706, 716, 726, or 736 is configured to concatenate the line coded bits with the non-line coded bits in an interleaved manner. Concatenation refers to linking the plurality of the line coded bits and the non-line coded bits into a single series of bits. For example, where a first set of line coded bits includes 000111, a second set of line coded bits includes 000111, a first set of non-line coded bits includes 111000, and a second set of non-line coded bits includes 010101, concatenating the sets of bits results in a sequence of bits, such as 000111 000111 111000 010101, or such as 000111 111000 000111 010101. Spacing is added for illustration only. In certain aspects, the line coded bits with the non-line coded bits are interleaved. For example, the first set of non-line coded bits are interleaved between the first set of line coded bits and the second set of line coded bits, and the second set of non-line coded bits is added after the second set of line coded bits. This is just one example. A further example of concatenation of the line coded bits and the non-line coded bits will be illustrated further with reference to FIG. 8.

As noted above, a modulator 708, 718, 728, or 738 may receive the sequence of bits for modulation and subsequent transmission by a transmitter comprising components such as impedance circuits 560 and one or more antennas 552.

Modulator 708, 718, 728, or 738 may be configured to perform one or more types of modulation and may be a single component or multiple components (e.g., each performing a separate modulation) . Modulator 708, 718, 728, or 738 may be configured to receive as input the sequence of bits from the respective concatenator 706, 716, 726, or 736. In certain aspects, the modulator 708, 718, 728, or 738 is coupled directly to a respective concatenator 706, 716, 726, or 736. In certain aspects, additional processing may be performed on the sequence of bits prior to being input into modulator 708, 718, 728, or 738.

In certain aspects, the modulator 708, 718, 728, or 738 is configured to modulate the carrier waveform with the data using any suitable modulation scheme, such as after performing PIE, FM0 encoding, Manchester encoding, Miller 2, 4, or 8 encoding, or the like, or without performing PIE, FM0 encoding, Manchester encoding, Miller 2, 4, or 8 encoding, or the like. For example, the modulator 708, 718, 728, or 738 may modulate the carrier waveform using ASK, PSK, and/or FSK. In certain aspects, use of ASK, PSK, and/or FSK provides backward compatibility with other systems, such as RFID systems. As another example, the modulator 708, 718, 728, or 738 may additionally or alternatively modulate the carrier waveform using quadrature modulation (QAM) , such as 16QAM, 64QAM, etc. As another example, the modulator 708, 718, 728, or 738 may additionally or alternatively modulate the carrier waveform using quadrature PSK (QPSK) .

FIG. 7A depicts a first illustrative encoding scenario 700. Encoding scenario 700 includes a systematic convolutional encoder 702. The illustrated coding rate of the systematic convolutional encoder 702 is 1/2, though other coding rates may be used. The information input bits (b1) , which are also referred to herein as a first set of bits from the plurality of information bits, are received by both the systematic convolutional encoder 702 and the concatenator 706. The systematic convolutional encoder 702 encodes the first set of bits to generate a first set of check bits (x2) . The first set of check bits (x2) generated by the systematic convolutional encoder 704 are subsequently line coded with a line coder 704 to form one or more line coded bits (e.g., sets of line coded bits z2 and z3, where a set of bits includes one or more bits) . The concatenator 706 receives the information input bits (b1) as non-line coded bits (z1) and one or more line coded bits (z2, z3) . The concatenator 706 concatenates the line coded bits with the non-line coded bits (e.g., in an interleaved manner) to generate a sequence of bits for modulation by the modulator 708.

FIG. 7B depicts a second illustrative encoding scenario 710. Encoding scenario 710 also includes a systematic convolutional encoder 712. The illustrated coding rate of the systematic convolutional encoder 712 is 1/2, though other coding rates may be used. The information input bits (b1) , which are also referred to herein as a first set of bits from the plurality of information bits, are received by both the systematic convolutional encoder 712 and the line coder 714. The systematic convolutional encoder 712 encodes the first set of bits to generate a first set of check bits (x2) . The line coder 714 line codes the first set of bits to form one or more line coded bits (e.g., sets of line coded bits z1 and z2) . The concatenator 716 receives the one or more line coded bits (z1, z2) and the first set of check bits (x2) as non-line coded bits z3. The concatenator 716 concatenates the line coded bits with the non-line coded bits (e.g., in an interleaved manner) to generate a sequence of bits for modulation by the modulator 718.

FIG. 7C depicts a third illustrative encoding scenario 720. Encoding scenario 720 also includes a non-systematic convolutional encoder 722. The illustrated coding rate of the non-systematic convolutional encoder 722 is 1/2, though other coding rates may be used. Unlike the encoding scenarios 700 and 710 which include systematic convolutional encoder 702 and 712, respectively, the information input bits (b1) are only received by the non-systematic convolutional encoder 722. The non-systematic convolutional encoder 722 generates a first set of check bits (e.g., x1) and a first set of coded bits (e.g., x2) corresponding to the first set of bits (e.g., the information input bits (b1) ) . In encoding scenario 720, the line coder 724 is configured to line code the first set of check bits (e.g., x1) to form one or more line coded bits (e.g., sets of line coded bits z1 and z2) . The concatenator 726 receives the one or more line coded bits (z1, z2) and the first set of coded bits (e.g., x2) as non-line coded bits (z3) . The concatenator 726 concatenates the line coded bits (z1, z2) with the non-line coded bits (z3) (e.g., in an interleaved manner) to generate a sequence of bits for modulation by the modulator 728.

FIG. 7D depicts a fourth illustrative encoding scenario 730. Encoding scenario 730 also includes a non-systematic convolutional encoder 732. The illustrated coding rate of the non-systematic convolutional encoder 732 is 1/2, though other coding rates may be used. The information input bits (b1) are received by the non-systematic convolutional encoder 732. The non-systematic convolutional encoder 732 generates a first set of check bits (e.g., x1) and a first set of coded bits (e.g., x2) corresponding to the first set of bits (e.g., the information input bits (b1) ) . In encoding scenario 730, the line coder 734 is configured to line code the first set of coded bits (e.g., x2) to form one or more line coded bits (e.g., sets of line coded bits z2 and z3) . The concatenator 736 receives the one or more line coded bits (z2, z3) and the first set of check bits (e.g., x1) as non-line coded bits (z1) . The concatenator 736 concatenates the line coded bits (z2, z3) with the non-line coded bits (z1) (e.g., in an interleaved manner) to generate a sequence of bits for modulation by the modulator 738.

FIG. 8 depicts an illustrative example of block interleaving performed by the concatenator 806 (e.g., one of the concatenator 706, 716, 726, or 736 depicted in FIGS. 7A-7D) . Since the bits output by the line coder 704, 714, 724, or 734 may be used for clock sync and continuous symbol timing recovery by a receiver (Rx) , it may be beneficial in certain cases for the line coded bits to be evenly distributed within all the encoded bits for transmission. Accordingly, block based distributed mapping may be implemented by the concatenator 706, 716, 726, or 736. Block based distributed mapping defines a plurality of blocks 810-850 where one block of line coded bits may be followed by another block of non-line coded bits. For example, in certain encoding scenarios that have a coding rate of 1/3, one block (e.g., block 1 810) may have 2M line coded bits followed by another block (e.g., block-2 820) of M non-line coded bits where M is block size dependent on the line codes. For example, M may be equal to one for a Manchester encoder, and M may be greater than one for a FM0 or Miller encoder, such as so that the phase transition property across symbols can be captured within the block for clock sync. The pattern of line coded bits assigned to one block followed by another block assigned with non-lined coded bit may be repeated.

FIGS. 9A-12B depict illustrative diagrams corresponding to flexible encoding rate scenarios. In certain aspects, the number of bits from the non-systematic convolutional encoder 722 or 732 that are subsequently processed by the line coder 724 or 734, respectively, may be variable or configurable, allowing for a variable coding rate.

By varying the number of bits input to a line coder, such as line coders 724, 734 depicted and described with reference to encoding scenarios 720, 730 in FIGS. 7C and 7D, and implementing a concatenation of convolutional encoder and line coding having a defined coding rate, a flexible coding rate (e.g., an effective coding rate) for the encoding scenario can be achieved. For example, the effective coding rate of the encoding scenario may be calculated bywhere R₁ is the coding rate of the convolutional encoder and R₂ is the ratio of the bits for line coding from the convolutional encoder output. R₂ may be either fixed dependent on the effective coding rate of the concatenated code or configured by a reader, e.g., for CC-1/3, R₂ can be either 1/3 or 2/3, where 1/3 corresponds to one bit per 3 bits and 2/3 corresponds to 2 bits per 3 bits from the convolutional encoder output fed into and used by the line coder. Table 1 presented below provides some illustrative examples of flexible encoding rate scenarios which respectively correspond to the illustrative diagrams depicted in FIGS. 9A-12B.

FIGS. 9A and 9B depict illustrative diagrams corresponding to flexible encoding rate scenarios having a convolutional encoder with a code rate of 1/2. For example, as depicted in FIG 9A the effective coding rate is configured to be 1/3. To achieve an effective coding rate of 1/3 using the convolutional encoder with a code rate of 1/2, one bit of the coded bits (e.g., x1 or x2) is configured to be line coded with the line coder. Accordingly, as depicted three bits (z1, z2, and z3) are received by the concatenator, thus the effective coding rate is 1/3.

As depicted in FIG 9B the effective coding rate is configured to be 1/4. To achieve an effective coding rate of 1/4 using the convolutional encoder with a code rate of 1/2, two bits of the coded bits (e.g., x1 and x2) are configured to be line coded with the line coder. Accordingly, as depicted four bits (z1, z2, z3, and z4) are received by the concatenator, thus the effective coding rate is 1/4.

FIGS. 10A and 10B depict illustrative diagrams corresponding to flexible encoding rate scenarios having a convolutional encoder with a code rate of 1/3. For example, as depicted in FIG 10A the effective coding rate is configured to be 1/4. To achieve an effective coding rate of 1/4 using the convolutional encoder with a code rate of 1/3, one bit of the coded bits (e.g., x1 or x2 or x3) is configured to be line coded with the line coder. Accordingly, as depicted four bits (z1, z2, z3, and z4) are received by the concatenator, thus the effective coding rate is 1/4.

As depicted in FIG 10B the effective coding rate is configured to be 1/5. To achieve an effective coding rate of 1/5 using the convolutional encoder with a code rate of 1/3, two bits of the coded bits (e.g., x1 and x2, or x1 and x3, or x2 and x3) are configured to be line coded with the line coder. Accordingly, as depicted five bits (z1, z2, z3, z4, and z5) are received by the concatenator, thus the effective coding rate is 1/5.

FIGS. 11A-11B depict illustrative diagrams corresponding to flexible encoding rate scenarios having a convolutional encoder with a code rate of 2/3. For example, as depicted in FIG 11A the effective coding rate is configured to be 1/2. To achieve an effective coding rate of 1/2 using the convolutional encoder with a code rate of 2/3, one bit of the coded bits (e.g., x1 or x2 or x3) is configured to be line coded with the line coder. Accordingly, as depicted four bits (z1, z2, z3, and z4) are received by the concatenator. Since two information bits (b1 and b2) are input and four bits (z1, z2, z3, and z4) are received by the concatenator the effective coding rate is 2/4 or 1/2.

As depicted in FIG 11B the effective coding rate is configured to be 2/5. To achieve an effective coding rate of 2/5 using the convolutional encoder with a code rate of 2/3, two bits of the coded bits (e.g., x1 and x2, or x1 and x3, or x2 and x3) are configured to be line coded with the line coder. Accordingly, as depicted five bits (z1, z2, z3, z4, and z5) are received by the concatenator, thus the effective coding rate is 2/5.

FIGS. 12A-12B depict illustrative diagrams corresponding to flexible encoding rate scenarios having a convolutional encoder with a code rate of 3/4. For example, as depicted in FIG 12A the effective coding rate is configured to be 3/5. To achieve an effective coding rate of 3/5 using the convolutional encoder with a code rate of 3/4, one bit of the coded bits (e.g., x1 or x2 or x3 or x4) is configured to be line coded with the line coder. Accordingly, as depicted five bits (z1, z2, z3, z4, and z5) are received by the concatenator. Since three information bits (b1, b2, and b3) are input and five bits (z1, z2, z3, z4, and z5) are received by the concatenator the effective coding rate is 3/5.

As depicted in FIG 12B the effective coding rate is configured to be 1/2. To achieve an effective coding rate of 1/2 using the convolutional encoder with a code rate of 3/4, two bits of the coded bits (e.g., x1 and x2, or x1 and x3, or x1 and x4, or x2 and x3, x2 and x4, or x3 and x4) are configured to be line coded with the line coder. Accordingly, as depicted six bits (z1, z2, z3, z4, z5, and z6) are received by the concatenator. Since three information bits (b1, b2, and b3) are input and six bits (z1, z2, z3, z4, z5, and z6) are received by the concatenator the effective coding rate is 3/6 or 1/2.

These are only a few examples of encoding scenarios having an effective coding rate that is variable, for example, different from the code rate of the convolutional encoder.

Example Operations of a Wireless Communication Device

FIG. 13 shows a method 1300 of wireless communications by an apparatus, such as UE 104 of FIGS. 1 and 3, BS 102 of FIGS. 1 and 3, or a disaggregated base station discussed with respect to FIG. 2.

Method 1300 begins at block 1305 with encoding, with a systematic convolutional encoder, a first set of bits from a plurality of information bits to generate a first set of coded bits.

Method 1300 then proceeds to block 1310 with line coding, with a line coder, one of the first set of bits or the first set of coded bits to generate one or more line coded bits.

Method 1300 then proceeds to block 1315 with concatenating, with a bit mapper component, the one or more line coded bits with the other of the one of the first set of bits or the first set of coded bits that is not line coded to generate a sequence of bits.

Method 1300 then proceeds to block 1320 with modulating a carrier waveform with the sequence of bits.

Method 1300 then proceeds to block 1325 with transmitting the modulated carrier waveform.

In certain aspects, block 1315 includes distributing, with the bit mapper component, the one or more line coded bits into a first plurality of blocks and the other of the one of the first set of bits or the first set of coded bits that is not line coded into a second plurality of blocks; wherein each block of the first plurality of blocks has a first block size and each block of the second plurality of blocks has a second block size; and wherein the first plurality of blocks is interleaved with the second plurality of blocks.

In certain aspects, the first block size is equal to the second block size.

In certain aspects, the line coder is a Manchester encoder; the one of the first set of bits or the first set of coded bits is the first set of bits; and the first block size is one bit.

In certain aspects, the line coder is one of a FM0 encoder or a Miller encoder; the one of the first set of bits or the first set of coded bits is the first set of coded bits; and the first block size is greater than one bit.

In certain aspects, the one of the first set of bits or the first set of coded bits is the first set of bits; and the other of the one of the first set of bits or the first set of coded bits that is not line coded is the first set of coded bits.

In certain aspects, the one of the first set of bits or the first set of coded bits is the first set of coded bits; and the other of the one of the first set of bits or the first set of coded bits that is not line coded is the first set of bits.

In certain aspects, method 1300, or any aspect related to it, may be performed by an apparatus, such as communications device 1500 of FIG. 15, which includes various components operable, configured, or adapted to perform the method 1300. Communications device 1500 is described below in further detail.

Note that FIG. 13 is just one example of a method, and other methods including fewer, additional, or alternative operations are possible consistent with this disclosure.

FIG. 14 shows a method 1400 of wireless communications by an apparatus, such as UE 104 of FIGS. 1 and 3, BS 102 of FIGS. 1 and 3, or a disaggregated base station discussed with respect to FIG. 2.

Method 1400 begins at block 1405 with encoding, with a non-systematic convolutional encoder, a first set of bits from a plurality of information bits to generate a first set of coded bits and a second set of coded bits corresponding to the first set of bits.

Method 1400 then proceeds to block 1410 with line coding, with a line coder, one of the first set of coded bits or the second set of coded bits to generate one or more line coded bits.

Method 1400 then proceeds to block 1415 with concatenating, with a bit mapper component, the one or more line coded bits with the other of the one of the first set of coded bits or the second set of coded bits that is not line coded to generate a sequence of bits.

Method 1400 then proceeds to block 1420 with modulating a carrier waveform with the sequence of bits.

Method 1400 then proceeds to block 1425 with transmitting the modulated carrier waveform.

In certain aspects, block 1415 includes distributing, with the bit mapper component, the one or more line coded bits into a first plurality of blocks and the other of the one of the first set of coded bits or the second set of coded bits that is not line coded into a second plurality of blocks, wherein each block of the first plurality of blocks has a first block size and each block of the second plurality of blocks has a second block size; and wherein the first plurality of blocks is interleaved with the second plurality of blocks.

In certain aspects, the first block size is equal to the second block size.

In certain aspects, the line coder is a Manchester encoder; the one of the first set of coded bits or the second set of coded bits is the first set of coded bits; and the first block size is one bit.

In certain aspects, the line coder is one of a FM0 encoder or a Miller encoder; the one of the first set of coded bits or the second set of coded bits is the second set of coded bits; and the first block size is greater than one bit.

In certain aspects, the one of the first set of coded bits or the second set of coded bits is the first set of coded bits; and the other of the one of the first set of coded bits or the second set of coded bits that is not line coded is the second set of coded bits.

In certain aspects, the one of the first set of coded bits or the second set of coded bits is the second set of coded bits; and the other of the one of the first set of coded bits or the second set of coded bits that is not line coded is the first set of coded bits.

In certain aspects, a coding rate of the non-systematic convolutional encoder is variable; and at least one of a number of the first set of check bits or a number of the first set of coded bits is based on the coding rate.

In certain aspects, block 1420 includes using one or more of: amplitude-shift keying; phase-shift keying; or frequency-shift keying.

In certain aspects, method 1400, or any aspect related to it, may be performed by an apparatus, such as communications device 1600 of FIG. 16, which includes various components operable, configured, or adapted to perform the method 1400. Communications device 1600 is described below in further detail.

Note that FIG. 14 is just one example of a method, and other methods including fewer, additional, or alternative operations are possible consistent with this disclosure.

Example Communications Devices

FIG. 15 depicts aspects of an example communications device 1500. In some aspects, communications device 1500 is a user equipment, such as UE 104 described above with respect to FIGS. 1 and 3. In some aspects, communications device 1500 is a network entity, such as BS 102 of FIGS. 1 and 3, or a disaggregated base station as discussed with respect to FIG. 2.

The communications device 1500 includes a processing system 1505 coupled to a transceiver 1575 (e.g., a transmitter and/or a receiver) and/or a network interface 1585. The transceiver 1575 is configured to transmit and receive signals for the communications device 1500 via an antenna 1580, such as the various signals as described herein. The network interface 1585 is configured to obtain and send signals for the communications device 1500 via communications link (s) , such as a backhaul link, midhaul link, and/or fronthaul link as described herein, such as with respect to FIG. 2. The processing system 1505 may be configured to perform processing functions for the communications device 1500, including processing signals received and/or to be transmitted by the communications device 1500.

The processing system 1505 includes one or more processors 1510. In various aspects, the one or more processors 1510 may be representative of one or more of receive processor 338, receive processor 358, transmit processor 320, transmit processor 364, TX MIMO processor 330, TX MIMO processor 366, controller/processor 340, and/or controller/processor 380, as described with respect to FIG. 3. The one or more processors 1510 are coupled to a computer-readable medium/memory 1540 via a bus 1570. In certain aspects, the computer-readable medium/memory 1540 is configured to store instructions (e.g., computer-executable code) that when executed by the one or more processors 1510, enable and cause the one or more processors 1510 to perform the method 1300 described with respect to FIG. 13, or any aspect related to it, including any operations described in relation to FIG. 13. Note that reference to a processor performing a function of communications device 1500 may include one or more processors performing that function of communications device 1500, such as in a distributed fashion.

In the depicted example, computer-readable medium/memory 1540 stores code for encoding 1545, code for line coding 1550, code for concatenating 1555, code for modulating 1560, and code for transmitting 1565. Processing of the code 1545-1565 may enable and cause the communications device 1500 to perform the method 1300 described with respect to FIG. 13, or any aspect related to it.

The one or more processors 1510 include circuitry configured to implement (e.g., execute) the code stored in the computer-readable medium/memory 1540, including circuitry for encoding 1515, circuitry for line coding 1520, circuitry for concatenating 1525, circuitry for modulating 1530, and circuitry for transmitting 1535. Processing with circuitry 1515-1535 may enable and cause the communications device 1500 to perform the method 1300 described with respect to FIG. 13, or any aspect related to it.

More generally, means for communicating, transmitting, sending or outputting for transmission may include: the transceivers 332, antenna (s) 334, transmit processor 320, TX MIMO processor 330, AI processor 318, and/or controller/processor 340 of the BS 102 illustrated in FIG. 3; the transceivers 354, antenna (s) 352, transmit processor 364, TX MIMO processor 366, AI processor 370, and/or controller/processor 380 of the UE 104 illustrated in FIG. 3; transceiver 1575, antenna 1580, and/or network interface 1585 of the communications device 1500 in FIG. 15; and/or one or more processors 1510 of the communications device 1500 in FIG. 15. Means for communicating, receiving or obtaining may include: the transceivers 332, antenna (s) 334, receive processor 338, AI processor 318, and/or controller/processor 340 of the BS 102 illustrated in FIG. 3; the transceivers 354, antenna (s) 352, receive processor 358, AI processor 370, and/or controller/processor 380 of the UE 104 illustrated in FIG. 3; transceiver 1575, antenna 1580, and/or network interface 1585 of the communications device 1500 in FIG. 15; and/or one or more processors 1504 of the communications device 1500 in FIG. 15.

FIG. 16 depicts aspects of an example communications device 1600. In some aspects, communications device 1600 is a user equipment, such as UE 104 described above with respect to FIGS. 1 and 3. In some aspects, communications device 1600 is a network entity, such as BS 102 of FIGS. 1 and 3, or a disaggregated base station as discussed with respect to FIG. 2.

The communications device 1600 includes a processing system 1605 coupled to a transceiver 1675 (e.g., a transmitter and/or a receiver) and/or a network interface 1685. The transceiver 1675 is configured to transmit and receive signals for the communications device 1600 via an antenna 1680, such as the various signals as described herein. The network interface 1685 is configured to obtain and send signals for the communications device 1600 via communications link (s) , such as a backhaul link, midhaul link, and/or fronthaul link as described herein, such as with respect to FIG. 2. The processing system 1605 may be configured to perform processing functions for the communications device 1600, including processing signals received and/or to be transmitted by the communications device 1600.

The processing system 1605 includes one or more processors 1610. In various aspects, the one or more processors 1610 may be representative of one or more of receive processor 338, receive processor 358, transmit processor 320, transmit processor 364, TX MIMO processor 330, TX MIMO processor 366, controller/processor 340, and/or controller/processor 380, as described with respect to FIG. 3. The one or more processors 1610 are coupled to a computer-readable medium/memory 1640 via a bus 1670. In certain aspects, the computer-readable medium/memory 1640 is configured to store instructions (e.g., computer-executable code) that when executed by the one or more processors 1610, enable and cause the one or more processors 1610 to perform the method 1400 described with respect to FIG. 14, or any aspect related to it, including any operations described in relation to FIG. 14. Note that reference to a processor performing a function of communications device 1600 may include one or more processors performing that function of communications device 1600, such as in a distributed fashion.

In the depicted example, computer-readable medium/memory 1640 stores code for encoding 1645, code for line coding 1650, code for concatenating 1655, code for modulating 1660, and code for transmitting 1665. Processing of the code 1645-1665 may enable and cause the communications device 1600 to perform the method 1400 described with respect to FIG. 14, or any aspect related to it.

The one or more processors 1610 include circuitry configured to implement (e.g., execute) the code stored in the computer-readable medium/memory 1640, including circuitry for encoding 1615, circuitry for line coding 1620, circuitry for concatenating 1625, circuitry for modulating 1630, and circuitry for transmitting 1635. Processing with circuitry 1615-1635 may enable and cause the communications device 1600 to perform the method 1400 described with respect to FIG. 14, or any aspect related to it.

More generally, means for communicating, transmitting, sending or outputting for transmission may include: the transceivers 332, antenna (s) 334, transmit processor 320, TX MIMO processor 330, AI processor 318, and/or controller/processor 340 of the BS 102 illustrated in FIG. 3; the transceivers 354, antenna (s) 352, transmit processor 364, TX MIMO processor 366, AI processor 370, and/or controller/processor 380 of the UE 104 illustrated in FIG. 3; transceiver 1675, antenna 1680, and/or network interface 1685 of the communications device 1600 in FIG. 16; and/or one or more processors 1610 of the communications device 1600 in FIG. 16. Means for communicating, receiving or obtaining may include: the transceivers 332, antenna (s) 334, receive processor 338, AI processor 318, and/or controller/processor 340 of the BS 102 illustrated in FIG. 3; the transceivers 354, antenna (s) 352, receive processor 358, AI processor 370, and/or controller/processor 380 of the UE 104 illustrated in FIG. 3; transceiver 1675, antenna 1680, and/or network interface 1685 of the communications device 1600 in FIG. 16; and/or one or more processors 1604 of the communications device 1600 in FIG. 16.

Example Clauses

Implementation examples are described in the following numbered clauses:

Clause 1: A method for wireless communications by an apparatus comprising: encoding, with a systematic convolutional encoder, a first set of bits from a plurality of information bits to generate a first set of coded bits; line coding, with a line coder, one of the first set of bits or the first set of coded bits to generate one or more line coded bits; concatenating, with a bit mapper component, the one or more line coded bits with the other of the one of the first set of bits or the first set of coded bits that is not line coded to generate a sequence of bits; modulating a carrier waveform with the sequence of bits; and transmitting the modulated carrier waveform.

Clause 2: The method of Clause 1, wherein: concatenating comprises distributing, with the bit mapper component, the one or more line coded bits into a first plurality of blocks and the other of the one of the first set of bits or the first set of coded bits that is not line coded into a second plurality of blocks; each block of the first plurality of blocks has a first block size and each block of the second plurality of blocks has a second block size; and the first plurality of blocks is interleaved with the second plurality of blocks.

Clause 3: The method of Clause 2, wherein the first block size is equal to the second block size.

Clause 4: The method of Clause 2, wherein: the line coder is a Manchester encoder; the one of the first set of bits or the first set of coded bits is the first set of bits; and the first block size is one bit.

Clause 5: The method of Clause 2, wherein: the line coder is one of a FM0 encoder or a Miller encoder; the one of the first set of bits or the first set of coded bits is the first set of coded bits; and the first block size is greater than one bit.

Clause 6: The method of any one of Clauses 1-5, wherein: the one of the first set of bits or the first set of coded bits is the first set of bits; and the other of the one of the first set of bits or the first set of coded bits that is not line coded is the first set of coded bits.

Clause 7: The method of any one of Clauses 1-6, wherein: the one of the first set of bits or the first set of coded bits is the first set of coded bits; and the other of the one of the first set of bits or the first set of coded bits that is not line coded is the first set of bits.

Clause 8: A method for wireless communications by an apparatus comprising: encoding, with a non-systematic convolutional encoder, a first set of bits from a plurality of information bits to generate a first set of coded bits and a second set of coded bits corresponding to the first set of bits; line coding, with a line coder, one of the first set of coded bits or the second set of coded bits to generate one or more line coded bits; concatenating, with a bit mapper component, the one or more line coded bits with the other of the one of the first set of coded bits or the second set of coded bits that is not line coded to generate a sequence of bits; modulating a carrier waveform with the sequence of bits; and transmitting the modulated carrier waveform.

Clause 9: The method of Clause 8, wherein: concatenating comprises distributing, with the bit mapper component, the one or more line coded bits into a first plurality of blocks and the other of the one of the first set of coded bits or the second set of coded bits that is not line coded into a second plurality of blocks, each block of the first plurality of blocks has a first block size and each block of the second plurality of blocks has a second block size; and the first plurality of blocks is interleaved with the second plurality of blocks.

Clause 10: The method of Clause 9, wherein the first block size is equal to the second block size.

Clause 11: The method of Clause 9, wherein: the line coder is a Manchester encoder; the one of the first set of coded bits or the second set of coded bits is the first set of coded bits; and the first block size is one bit.

Clause 12: The method of Clause 9, wherein: the line coder is one of a FM0 encoder or a Miller encoder; the one of the first set of coded bits or the second set of coded bits is the second set of coded bits; and the first block size is greater than one bit.

Clause 13: The method of any one of Clauses 8-12, wherein: the one of the first set of coded bits or the second set of coded bits is the first set of coded bits; and the other of the one of the first set of coded bits or the second set of coded bits that is not line coded is the second set of coded bits.

Clause 14: The method of any one of Clauses 8-13, wherein: the one of the first set of coded bits or the second set of coded bits is the second set of coded bits; and the other of the one of the first set of coded bits or the second set of coded bits that is not line coded is the first set of coded bits.

Clause 15: The method of any one of Clauses 8-14, wherein: a coding rate of the non-systematic convolutional encoder is variable; and at least one of a number of the first set of coded bits or a number of the second set of coded bits is based on the coding rate.

Clause 16: The method of any one of Clauses 8-15, wherein modulating the carrier waveform comprises using one or more of: amplitude-shift keying; phase-shift keying; or frequency-shift keying.

Clause 17: One or more apparatuses, comprising: one or more memories comprising executable instructions; and one or more processors configured to execute the executable instructions and cause the one or more apparatuses to perform a method in accordance with any one of Clauses 1-16.

Clause 18: One or more apparatuses, comprising: one or more memories; and one or more processors, coupled to the one or more memories, configured to cause the one or more apparatuses to perform a method in accordance with any one of Clauses 1-16.

Clause 19: One or more apparatuses, comprising: one or more memories; and one or more processors, coupled to the one or more memories, configured to perform a method in accordance with any one of Clauses 1-16.

Clause 20: One or more apparatuses, comprising means for performing a method in accordance with any one of Clauses 1-16.

Clause 21: One or more non-transitory computer-readable media comprising executable instructions that, when executed by one or more processors of one or more apparatuses, cause the one or more apparatuses to perform a method in accordance with any one of Clauses 1-16.

Clause 22: One or more computer program products embodied on one or more computer-readable storage media comprising code for performing a method in accordance with any one of Clauses 1-16.

Additional Considerations

The preceding description is provided to enable any person skilled in the art to practice the various aspects described herein. The examples discussed herein are not limiting of the scope, applicability, or aspects set forth in the claims. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. For example, changes may be made in the function and arrangement of elements discussed without departing from the scope of the disclosure. Various examples may omit, substitute, or add various procedures or components as appropriate. For instance, the methods described may be performed in an order different from that described, and various actions may be added, omitted, or combined. Also, features described with respect to some examples may be combined in some other examples. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, the scope of the disclosure is intended to cover such an apparatus or method that is practiced using other structure, functionality, or structure and functionality in addition to, or other than, the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of a claim.

The various illustrative logical blocks, modules and circuits described in connection with the present disclosure may be implemented or performed with a general purpose processor, an AI processor, a digital signal processor (DSP) , an ASIC, a field programmable gate array (FPGA) or other programmable logic device (PLD) , discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, a system on a chip (SoC) , or any other such configuration.

As used herein, a phrase referring to “at least one of” a list of items refers to any combination of those items, including single members. As an example, “at least one of: a, b, or c” is intended to cover a, b, c, a-b, a-c, b-c, and a-b-c, as well as any combination with multiples of the same element (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c or any other ordering of a, b, and c) .

As used herein, the term “determining” encompasses a wide variety of actions. For example, “determining” may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database or another data structure) , ascertaining and the like. Also, “determining” may include receiving (e.g., receiving information) , accessing (e.g., accessing data in a memory) and the like. Also, “determining” may include resolving, selecting, choosing, establishing and the like.

As used herein, “coupled to” and “coupled with” generally encompass direct coupling and indirect coupling (e.g., including intermediary coupled aspects) unless stated otherwise. For example, stating that a processor is coupled to a memory allows for a direct coupling or a coupling via an intermediary aspect, such as a bus.

The methods disclosed herein comprise one or more actions for achieving the methods. The method actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of actions is specified, the order and/or use of specific actions may be modified without departing from the scope of the claims. Further, the various operations of methods described above may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and/or software component (s) and/or module (s) , including, but not limited to a circuit, an application specific integrated circuit (ASIC) , or processor.

The following claims are not intended to be limited to the aspects shown herein, but are to be accorded the full scope consistent with the language of the claims. Reference to an element in the singular is not intended to mean only one unless specifically so stated, but rather “one or more. ” The subsequent use of a definite article (e.g., “the” or “said” ) with an element (e.g., “the processor” ) is not intended to invoke a singular meaning (e.g., “only one” ) on the element unless otherwise specifically stated. For example, reference to an element (e.g., “aprocessor, ” “acontroller, ” “amemory, ” “a transceiver, ” “an antenna, ” “the processor, ” “the controller, ” “the memory, ” “the transceiver, ” “the antenna, ” etc. ) , unless otherwise specifically stated, should be understood to refer to one or more elements (e.g., “one or more processors, ” “one or more controllers, ” “one or more memories, ” “one more transceivers, ” etc. ) . The terms “set” and “group” are intended to include one or more elements, and may be used interchangeably with “one or more. ” Where reference is made to one or more elements performing functions (e.g., steps of a method) , one element may perform all functions, or more than one element may collectively perform the functions. When more than one element collectively performs the functions, each function need not be performed by each of those elements (e.g., different functions may be performed by different elements) and/or each function need not be performed in whole by only one element (e.g., different elements may perform different sub-functions of a function) . Similarly, where reference is made to one or more elements configured to cause another element (e.g., an apparatus) to perform functions, one element may be configured to cause the other element to perform all functions, or more than one element may collectively be configured to cause the other element to perform the functions. Unless specifically stated otherwise, the term “some” refers to one or more. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims.

Claims

A wireless communications device comprising: one or more memories comprising processor-executable instructions; and one or more processors configured to execute the processor-executable instructions and cause the wireless communications device to:

encode, with a systematic convolutional encoder, a first set of bits from a plurality of information bits to generate a first set of coded bits;

line code, with a line coder, one of the first set of bits or the first set of coded bits to generate one or more line coded bits;

concatenate, with a bit mapper component, the one or more line coded bits with the other of the one of the first set of bits or the first set of coded bits that is not line coded to generate a sequence of bits;

modulate a carrier waveform with the sequence of bits; and

transmit the modulated carrier waveform.
The wireless communications device of claim 1, wherein:

to concatenate, the one or more processors are configured to execute the processor-executable instructions and cause the wireless communications device to distribute, with the bit mapper component, the one or more line coded bits into a first plurality of blocks and the other of the one of the first set of bits or the first set of coded bits that is not line coded into a second plurality of blocks;

each block of the first plurality of blocks has a first block size and each block of the second plurality of blocks has a second block size; and

the first plurality of blocks is interleaved with the second plurality of blocks.
The wireless communications device of claim 2, wherein the first block size is equal to the second block size.
The wireless communications device of claim 2, wherein:

the line coder is a Manchester encoder;

the one of the first set of bits or the first set of coded bits is the first set of bits; and

the first block size is one bit.
The wireless communications device of claim 2, wherein:

the line coder is one of a FM0 encoder or a Miller encoder;

the one of the first set of bits or the first set of coded bits is the first set of coded bits; and

the first block size is greater than one bit.
The wireless communications device of claim 1, wherein:

the one of the first set of bits or the first set of coded bits is the first set of bits; and

the other of the one of the first set of bits or the first set of coded bits that is not line coded is the first set of coded bits.
The wireless communications device of claim 1, wherein:

the one of the first set of bits or the first set of coded bits is the first set of coded bits; and

the other of the one of the first set of bits or the first set of coded bits that is not line coded is the first set of bits.
A wireless communications device comprising: one or more memories comprising processor-executable instructions; and one or more processors configured to execute the processor-executable instructions and cause the wireless communications device to:

encode, with a non-systematic convolutional encoder, a first set of bits from a plurality of information bits to generate a first set of coded bits and a second set of coded bits corresponding to the first set of bits;

line code, with a line coder, one of the first set of coded bits or the second set of coded bits to generate one or more line coded bits;

concatenate, with a bit mapper component, the one or more line coded bits with the other of the one of the first set of coded bits or the second set of coded bits that is not line coded to generate a sequence of bits;

modulate a carrier waveform with the sequence of bits; and

transmit the modulated carrier waveform.
The wireless communications device of claim 8, wherein:

to concatenate, the one or more processors are configured to execute the processor-executable instructions and cause the wireless communications device to distribute, with the bit mapper component, the one or more line coded bits into a first plurality of blocks and the other of the one of the first set of coded bits or the second set of coded bits that is not line coded into a second plurality of blocks,

each block of the first plurality of blocks has a first block size and each block of the second plurality of blocks has a second block size; and

the first plurality of blocks is interleaved with the second plurality of blocks.
The wireless communications device of claim 9, wherein the first block size is equal to the second block size.
The wireless communications device of claim 9, wherein:

the line coder is a Manchester encoder;

the one of the first set of coded bits or the second set of coded bits is the first set of coded bits; and

the first block size is one bit.
The wireless communications device of claim 9, wherein:

the line coder is one of a FM0 encoder or a Miller encoder;

the one of the first set of coded bits or the second set of coded bits is the second set of coded bits; and

the first block size is greater than one bit.
The wireless communications device of claim 8, wherein:

the one of the first set of coded bits or the second set of coded bits is the first set of coded bits; and

the other of the one of the first set of coded bits or the second set of coded bits that is not line coded is the second set of coded bits.
The wireless communications device of claim 8, wherein:

the one of the first set of coded bits or the second set of coded bits is the second set of coded bits; and

the other of the one of the first set of coded bits or the second set of coded bits that is not line coded is the first set of coded bits.
The wireless communications device of claim 8, wherein:

a coding rate of the non-systematic convolutional encoder is variable; and

at least one of a number of the first set of coded bits or a number of the second set of coded bits is based on the coding rate.
The wireless communications device of claim 8, wherein to modulate the carrier waveform, the one or more processors are configured to execute the processor-executable instructions and cause the wireless communications device to use one or more of:

amplitude-shift keying;

phase-shift keying; or

frequency-shift keying.
A method for wireless communications by a wireless communications device comprising:

encoding, with a systematic convolutional encoder, a first set of bits from a plurality of information bits to generate a first set of coded bits;

line coding, with a line coder, one of the first set of bits or the first set of coded bits to generate one or more line coded bits;

concatenating, with a bit mapper component, the one or more line coded bits with the other of the one of the first set of bits or the first set of coded bits that is not line coded to generate a sequence of bits;

modulating a carrier waveform with the sequence of bits; and

transmitting the modulated carrier waveform.
The method of claim 17, wherein:

the step of concatenating comprises distributing, with the bit mapper component, the one or more line coded bits into a first plurality of blocks and the other of the one of the first set of bits or the first set of coded bits that is not line coded into a second plurality of blocks;

each block of the first plurality of blocks has a first block size and each block of the second plurality of blocks has a second block size; and

the first plurality of blocks is interleaved with the second plurality of blocks.
The method of claim 17, wherein:

the one of the first set of bits or the first set of coded bits is the first set of bits; and

the other of the one of the first set of bits or the first set of coded bits that is not line coded is the first set of coded bits.
The method of claim 17, wherein:

the one of the first set of bits or the first set of coded bits is the first set of coded bits; and

the other of the one of the first set of bits or the first set of coded bits that is not line coded is the first set of bits.