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WO2025206719A1 - Carte de circuit imprimé et boîtier pour semi-conducteurs la comprenant - Google Patents

Carte de circuit imprimé et boîtier pour semi-conducteurs la comprenant

Info

Publication number
WO2025206719A1
WO2025206719A1 PCT/KR2025/003821 KR2025003821W WO2025206719A1 WO 2025206719 A1 WO2025206719 A1 WO 2025206719A1 KR 2025003821 W KR2025003821 W KR 2025003821W WO 2025206719 A1 WO2025206719 A1 WO 2025206719A1
Authority
WO
WIPO (PCT)
Prior art keywords
via electrode
build
insulating layer
wiring portion
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/KR2025/003821
Other languages
English (en)
Korean (ko)
Inventor
신준식
장우영
이종민
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LG Innotek Co Ltd
Original Assignee
LG Innotek Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020250005306A external-priority patent/KR20250146153A/ko
Application filed by LG Innotek Co Ltd filed Critical LG Innotek Co Ltd
Publication of WO2025206719A1 publication Critical patent/WO2025206719A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

Definitions

  • the embodiment relates to a circuit board and a semiconductor package including the same.
  • semiconductor packages applied to products that provide the Internet of Things (IoT), autonomous vehicles, and high-performance servers are expanding their concept to semiconductor chiplets as the number of semiconductor elements and/or the size of each semiconductor element increases in line with the trend toward high integration, or as the functional parts of semiconductor elements are divided.
  • the semiconductor package suffers from greater warpage. Furthermore, as the number of semiconductor devices and/or semiconductor chiplets increases, heat generation becomes more severe, necessitating further improvements in heat dissipation characteristics.
  • circuit boards used in conventional semiconductor packages typically include a heat-dissipating member that functions as a heat sink.
  • the heat-dissipating member may be a structure inserted into the circuit board, such as a heat-dissipating coin.
  • a heat-dissipating member such as a heat-dissipating coin
  • a new method is required to further improve the heat dissipation characteristics of circuit boards, simplify the circuit board manufacturing process, and improve product yield.
  • the embodiment provides a circuit board of a novel structure and a semiconductor package including the same.
  • the embodiment provides a circuit board with improved heat dissipation characteristics and a semiconductor package including the same.
  • the embodiment provides a circuit board with improved bending characteristics and a semiconductor package including the same.
  • a circuit board comprises a build-up insulating layer including a plurality of insulating layers stacked along a vertical direction; a wiring portion including a plurality of via electrodes respectively disposed within the plurality of insulating layers of the build-up insulating layer; and a through-via electrode penetrating the build-up insulating layer, wherein the through-via electrode includes a first portion having a horizontal width widening along a direction from an upper surface of the build-up insulating layer toward a lower surface of the build-up insulating layer, a second portion disposed on the first portion and having a horizontal width narrowing along a direction from an upper surface of the build-up insulating layer toward a lower surface of the build-up insulating layer, and a base portion disposed between the first portion and the second portion, wherein at least one of the plurality of via electrodes of the wiring portion is connected to the base portion.
  • the wiring portion further includes a plurality of intermediate pad portions arranged between the plurality of via electrodes, and the wiring portion includes a first wiring portion including the via electrodes connected to the base portion and the plurality of via electrodes and the plurality of intermediate pad portions electrically connected to the first portion and the second portion of the through-via electrode through the base portion.
  • the wiring portion further includes a second wiring portion that is further away from the through-via electrode than the first wiring portion, the first wiring portion being disposed between the second wiring portion and the through-via electrode in a horizontal direction, and the second wiring portion being electrically spaced apart from the first wiring portion and the through-via electrode.
  • the crystal grains of the first or second portion of the through via electrode and the crystal grains of the base portion are different from each other.
  • the size of the crystal grains of at least one region of the base portion is smaller than the size of the crystal grains of the first portion or the second portion of the through via electrode.
  • the first portion or the second portion of the through via electrode includes a first region in contact with the inner wall of the through hole of the build-up insulating layer, and a second region located on the inner side of the through hole further from the inner wall than the first region, and the size of the crystal grains in the first region is the same as the size of the crystal grains in the second region.
  • the boundary between the first portion of the through-via electrode and the build-up insulating layer is located between the lower surface of the lower build-up insulating layer and the lower surface of the base portion, and the boundary between the second portion of the through-via electrode and the upper build-up insulating layer is located between the upper surface of the upper build-up insulating layer and the upper surface of the base portion.
  • the first wiring portion includes a lower wiring portion arranged on a lower surface of the base portion and arranged along a circumferential direction of the first portion of the through-via electrode, and an upper wiring portion arranged on a lower surface of the base portion and arranged along a circumferential direction of the second portion of the through-via electrode.
  • the plurality of via electrodes of the lower wiring portion include a plurality of lower via electrodes arranged in each of the plurality of lower insulating layers and spaced apart from each other along the circumferential direction of the first portion of the through-via electrode
  • the plurality of via electrodes of the upper wiring portion include a plurality of upper via electrodes arranged in each of the plurality of upper insulating layers and spaced apart from each other along the circumferential direction of the second portion of the through-via electrode.
  • the width in the horizontal direction of at least one of the plurality of via electrodes of the upper wiring portion and the plurality of via electrodes of the lower wiring portion is greater than the width in the horizontal direction of at least one of the plurality of via electrodes of the second wiring portion.
  • At least one of the plurality of via electrodes of the lower wiring portion and the plurality of via electrodes of the upper wiring portion has a closed loop shape surrounding the first portion or the second portion of the through via electrode.
  • the lower wiring portion includes a lower pad portion arranged on a lower surface of the lower build-up insulating layer
  • the upper wiring portion includes an upper pad portion arranged on an upper surface of the upper build-up insulating layer
  • the through-via electrode includes a lower through-electrode pad portion arranged on a lower surface of the first portion and an upper through-electrode pad portion arranged on an upper surface of the second portion, and the lower pad portion and the lower through-electrode pad portion, or the upper pad portion and the upper through-electrode pad portion, are formed integrally.
  • a plurality of intermediate pad portions of each of the upper wiring portion and the lower wiring portion are spaced apart from the first portion and the second portion of the through-via electrode in the horizontal direction.
  • first portion and the second portion of the through via electrode have a symmetrical shape with respect to the base portion.
  • At least one of the first portion and the second portion of the through-via electrode includes a first-first portion and a first-second portion spaced apart along a horizontal direction
  • the first wiring portion includes a first-first wiring portion arranged along a circumferential direction of the first-first portion, and a first-second wiring portion arranged along a circumferential direction of the first-second portion.
  • the horizontal central axis of the first portion of the through via electrode and the horizontal central axis of the second portion are misaligned.
  • the lower wiring portion is disposed on one side of the first portion of the through-via electrode
  • the upper wiring portion is disposed on the other side of the second portion of the through-via electrode
  • the upper wiring portion and the lower wiring portion do not overlap each other along the vertical direction.
  • a circuit board of an embodiment includes a plurality of insulating layers stacked along a vertical direction, wiring portions arranged in the plurality of insulating layers, and through-via electrodes integrally penetrating the plurality of insulating layers.
  • the wiring portions include a plurality of via electrodes respectively arranged in the plurality of insulating layers, and a plurality of pad portions connected to the plurality of via electrodes.
  • the embodiment can electroplating the through-via electrodes using a portion of the wiring portion including the via electrodes and the pad portions.
  • the wiring portion can include a first wiring portion arranged adjacent to the through-via electrode, and the plurality of pad portions of the first wiring portion can include a base portion connected to the through-via electrode, and a second pad portion spaced apart from the through-via electrode.
  • the plurality of pad portions of the first wiring portion including the base portion connected to the through-via electrode means that the pad portion and the via electrode of the first wiring portion can be utilized as seed layers for electroplating the through-via electrode.
  • the current for electroplating the through-via electrode can be uniformly provided in the vertical direction through the base portion. Therefore, in the embodiment, plating can be performed with a uniform height in the vertical direction based on the upper surface of the base portion, and the flatness of the through-via electrode can be improved accordingly. Therefore, in the embodiment, the process for manufacturing the through-via electrode can be simplified. For example, in the embodiment, the through hole corresponding to the through-via electrode can be completely filled while the upper surface is flat through a single plating process. Therefore, in the embodiment, a polishing process, etc. can be omitted, and the manufacturing process can be simplified and the manufacturing cost can be reduced. Furthermore, in the embodiment, the polishing process, etc. can be omitted, so that the electrodes provided on the circuit board can be prevented from being damaged by the polishing process. Therefore, in the embodiment, the product yield can be further improved.
  • the grain size of the through-via electrode may be different from the grain size of the wiring portion.
  • the grain size of the through-via electrode may be different from the grain size of at least a region of the base portion. That is, the base portion may include a chemical copper plating layer and an electrolytic plating layer.
  • the through-via electrode may be provided with only an electrolytic plating layer.
  • the through-via electrode can have a uniform grain size throughout the entire area.
  • the through-via electrode can include a first area in contact with the inner wall of a through-hole that integrally penetrates a plurality of insulating layers, and a second area on the inner side of the through-via electrode that is further away from the inner wall of the through-hole than the first area.
  • the grain sizes in each of the first area and the second area of the through-via electrode can be the same.
  • the through-via electrode can be formed by performing electroplating, but for this purpose, a chemical copper plating layer must be necessarily disposed on the inner wall of the through-hole, and accordingly, the grain sizes in the first area and the second area of the through-via electrode in the comparative example are different.
  • the embodiment can have a uniform grain size in the first area and the second area of the through-via electrode, thereby improving the flatness of the through-via electrode while providing high heat dissipation characteristics.
  • the inclination angle of the through-via electrode may be different from the inclination angle of the via electrode of the wiring portion.
  • the inclination angle of the through-via electrode with respect to the upper surface of the build-up insulating layer may be closer to 90 degrees than the inclination of the via electrode of the wiring portion with respect to the upper surface of the build-up insulating layer.
  • the through-via electrode when used as a heat dissipation electrode with a heat dissipation function, the heat dissipation characteristics can be further improved by maximizing the volume of the through-via electrode.
  • the semiconductor device can be operated more stably, and the product reliability can be further improved accordingly.
  • the embodiment can ensure that the current for plating the upper through-via electrode is uniformly applied, thereby further securing the flatness of the upper through-via electrode. Furthermore, the embodiment can further improve the heat dissipation function by increasing the area of the first wiring portion, thereby enabling the circuit board and semiconductor package to operate more stably.
  • the upper through-via electrode and the lower through-via electrode may have an asymmetrical shape with respect to the base portion.
  • the horizontal width and/or the vertical thickness of the upper through-via electrode may be different from the horizontal width and/or the vertical thickness of the lower through-via electrode.
  • the horizontal width of the upper through-via electrode may be different from the horizontal width of the lower through-via electrode.
  • the horizontal width of the upper through-via electrode may be smaller than the horizontal width of the lower through-via electrode.
  • the upper through-via electrodes may be provided in multiple numbers and spaced apart from each other in the horizontal direction.
  • the upper through-via electrodes may include a first upper through-via electrode that integrally penetrates multiple insulating layers of the upper insulating layer, and a second upper through-via electrode that integrally penetrates multiple insulating layers of the upper insulating layer and is spaced apart from the first upper through-via electrode in the horizontal direction.
  • the first upper through-via electrode and the second upper through-via electrode may transfer heat through mutually branched paths.
  • the embodiment may enable heat dissipation to be performed through multiple paths rather than a single path, thereby further improving heat dissipation characteristics.
  • a plurality of semiconductor devices may be arranged on the circuit board, and the first upper through-via electrode may be provided in an area where the first semiconductor device is arranged.
  • the second upper through-via electrode may be provided in an area where the second semiconductor device is arranged. That is, the embodiment may provide an upper through-via electrode corresponding to each of the multiple semiconductor devices arranged on the circuit board. Through this, the embodiment can further maximize the heat dissipation characteristics in a semiconductor package equipped with a plurality of semiconductor elements.
  • the first wiring portion may include an upper wiring portion provided only on one side of the upper through-via. Additionally, the first wiring portion may include a lower wiring portion provided only on the other side of the lower through-via. Accordingly, the embodiment may further increase the volume of the upper through-via electrode and/or the lower through-via electrode within the same area as the area of the circuit board. Through this, the embodiment may further improve heat dissipation characteristics.
  • Figure 1 is a cross-sectional view illustrating a circuit board according to the first embodiment.
  • FIG. 2a is a drawing for explaining a problem in a method for manufacturing a through-via electrode of a circuit board according to a comparative example.
  • FIGS. 2b and 2c are drawings for explaining a through-via electrode according to an embodiment compared to FIG. 2a.
  • Figure 3 is an enlarged view of the upper part of the base in Figure 1.
  • Figure 4 is a plan view of the area where the third base part is placed.
  • Figure 5 is a cross-sectional view along the A-A' direction of Figure 3.
  • Fig. 6 is a drawing showing the shape of a via electrode of a first wiring section according to the first embodiment.
  • Fig. 7 is a drawing showing the shape of a via electrode of a first wiring section according to the second embodiment.
  • Fig. 8 is a drawing showing the shape of a via electrode of a first wiring section according to a third embodiment.
  • Figure 9 is a cross-sectional view showing a circuit board according to the second embodiment.
  • Fig. 11 is a cross-sectional view showing a circuit board according to the fourth embodiment.
  • Fig. 13 is a cross-sectional view showing a circuit board according to the sixth embodiment.
  • Fig. 14 is a drawing showing a semiconductor package according to the first embodiment.
  • Figures 16 to 20 are cross-sectional views showing a method for manufacturing a circuit board according to one embodiment in process order.
  • the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc.
  • the electronic device is not limited thereto, and it goes without saying that the electronic device may be any other electronic device that processes data.
  • An electronic device includes a main board (not shown).
  • the main board may be physically and/or electrically connected to various components.
  • the main board may be electrically connected to a semiconductor package of the embodiment.
  • the semiconductor package includes a circuit board, a semiconductor element, a bonding portion for electrically connecting the semiconductor element and the circuit board, a resin portion for filling the space between the semiconductor element and the circuit board, and a molding portion for entirely enclosing the semiconductor element.
  • Semiconductor devices may include active and/or passive components and may have various functions. Active devices may be in the form of integrated circuits (ICs) in which hundreds to millions of transistors are integrated into a single semiconductor device, and may be, for example, logic chips, memory chips, etc.
  • the logic chip may be an application processor (AP) device including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), etc., or a set of devices including a specific combination of the above.
  • the memory chip may be a stacked memory such as HBM.
  • the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.
  • the thickness of the via electrode (160) in the vertical direction may be smaller than the thickness of the through via electrode (170) in the vertical direction.
  • the planar area of the via electrode (160) may be smaller than the planar area of the through via electrode (170).
  • the volume of the via electrode (160) may be smaller than the volume of the through via electrode (170).
  • the through via electrode (170) may be larger than the via electrode (160) in at least one of the width in the horizontal direction, the thickness in the vertical direction, the planar area, and the volume.
  • the through via electrode (170) may mean a via electrode having a relatively large area.
  • the build-up insulating layer (110) may include an upper build-up insulating layer (111) including a plurality of insulating layers (113, 114, 115) stacked along a vertical direction, and a lower build-up insulating layer (112) including a plurality of insulating layers (116, 117, 118) stacked along a vertical direction and positioned below the upper build-up insulating layer (111).
  • the upper build-up insulating layer (111) and the lower build-up insulating layer (112) may be distinguished based on the position of a pad that serves as a reference for forming a through-via electrode (170).
  • the upper build-up insulating layer (111) and the lower build-up insulating layer (112) can be distinguished based on the through-via electrode (170).
  • the through-via electrode (170) can include a first portion (171), a second portion (172), and a base portion (173) between the first portion (171) and the second portion (172).
  • the base portion (173) can mean a base pad that serves as a reference for forming the through-via electrode (170).
  • the first portion (171) of the through-via electrode (170) can be a through-via electrode positioned below the base portion (173)
  • the second portion (172) of the through-via electrode (170) can be a through-via electrode positioned above the base portion (173).
  • the upper build-up insulating layer (111) may refer to insulating layers located above the base portion (173) that serves as a reference, and the lower build-up insulating layer (112) may refer to insulating layers located below the base portion (173).
  • the upper build-up insulating layer (111) may refer to insulating layers that are integrally penetrated through the second portion (172) of the through-via electrode (170), and the lower build-up insulating layer (112) may refer to insulating layers that are integrally penetrated through the first portion (171) of the through-via electrode (170).
  • the build-up insulating layer (110) as described above may not include a core layer.
  • the circuit board (100) including the build-up insulating layer (110) may be a coreless board.
  • the embodiment is not limited thereto, and the circuit board (100) may be a core board including a core layer.
  • the build-up insulating layer (110) may be disposed on each of the upper and lower surfaces of the core layer.
  • the circuit board (100) is a core board including a core layer
  • the upper build-up insulating layer (111) of the build-up insulating layer (110) may be disposed on the upper surface of the core layer
  • the lower build-up insulating layer (112) of the build-up insulating layer (110) may be disposed on the lower surface of the core layer.
  • the upper build-up insulating layer (111) may include a first insulating layer (113) that is closest to the first protective layer (120) along the vertical direction, a second insulating layer (114) that is further away from the first protective layer (120) along the vertical direction than the first insulating layer (113), and a third insulating layer (115) that is further away from the first protective layer (120) along the vertical direction than the second insulating layer (114).
  • the lower build-up insulating layer (112) may include a fourth insulating layer (116) that is closest to the first protective layer (120) and/or the upper build-up insulating layer (111) along the vertical direction, a fifth insulating layer (117) that is further away from the first protective layer (120) and/or the upper build-up insulating layer (111) along the vertical direction than the fourth insulating layer (116), and a sixth insulating layer (118) that is further away from the first protective layer (120) and/or the upper build-up insulating layer (111) along the vertical direction than the fifth insulating layer (117).
  • the upper build-up insulation layer (111) and the lower build-up insulation layer (112) are described as each including three insulation layers, but are not limited thereto.
  • the upper build-up insulation layer (111) and/or the lower build-up insulation layer (112) may have a structure in which two or fewer insulation layers are laminated.
  • the upper build-up insulation layer (111) and/or the lower build-up insulation layer (112) may have a structure in which four or more insulation layers are laminated.
  • the upper build-up insulation layer (111) and the lower build-up insulation layer (112) have the same number of layers, it is not limited thereto.
  • the upper build-up insulation layer (111) and the lower build-up insulation layer (112) may have an asymmetrical structure.
  • the number of layers of at least one insulation layer among the upper build-up insulation layer (111) and the lower build-up insulation layer (112) may be greater than or less than the number of layers of the other insulation layer among the upper build-up insulation layer (111) and the lower build-up insulation layer (112).
  • the first to sixth insulating layers (113, 114, 115, 116, 117, 118) of the upper build-up insulating layer (111) and the lower build-up insulating layer (112) are arranged to vertically insulate between the pad portions (150) of the wiring portion (140) to be described later.
  • the first to sixth insulating layers (113, 114, 115, 116, 117, 118) may be formed of a thermosetting insulating material containing an inorganic filler in a resin, and Ajinomoto Build-up Film (ABF) may be used.
  • ABSF Ajinomoto Build-up Film
  • the embodiment is not limited thereto, and a photo-curable insulating material (Photo Imageable Dielectric, PID) for forming a fine pattern may be used.
  • At least one of the first to sixth insulating layers may include an insulating material different from at least one other.
  • at least one of the first to sixth insulating layers (113, 114, 115, 116, 117, 118) may include a reinforcing member (not shown).
  • the reinforcing member may mean glass fiber.
  • the reinforcing member may mean GCP (Glass Core Primer). The reinforcing member may be provided in at least one of the first to sixth insulating layers (113, 114, 115, 116, 117, 118) to improve the rigidity of the circuit board (100).
  • the reinforcing member can prevent the circuit board (100) from being significantly bent in a specific direction, thereby improving the vertical positional alignment between the pad portion (150) and the via electrode (160), thereby improving the electrical reliability and/or mechanical reliability of the circuit board (100) and the semiconductor package.
  • the reinforcing member can improve the rigidity of the circuit board (100), thereby improving the processability in the process of mounting a semiconductor device on the circuit board (100), and improving the product yield. Therefore, the reinforcing member can enable the semiconductor device to be stably mounted on the circuit board (100) and can enable the semiconductor device to operate stably. Through this, the operating reliability can be improved by enabling the stable operation of electronic products such as servers to which the semiconductor package is applied.
  • the reinforcing members can be alternately arranged in the vertical direction within the first to sixth insulating layers (113, 114, 115, 116, 117, 118).
  • the reinforcing member may be provided in an odd-numbered insulation layer among the first to sixth insulation layers (113, 114, 115, 116, 117, 118), or may be provided in an even-numbered insulation layer.
  • the lower pad portion of the pad portion (150) may include a first lower pad portion (155) that is further away from the first protective layer (120) than the fourth upper pad portion (154), a second lower pad portion (156) that is further away from the first protective layer (120) than the first lower pad portion (155), and a third lower pad portion (157) that is further away from the first protective layer (120) than the second lower pad portion (156).
  • the pad portion (150) may mean a wiring that overlaps with the via electrode (160) of the wiring portion (140) in a vertical direction or is physically directly connected to the via electrode (160).
  • the wiring portion (140) may further include a trace that overlaps with at least one pad portion among the first to fourth upper pad portions (151, 152, 153, 154) and the first to third lower pad portions (155, 156, 157) in the horizontal direction.
  • the trace may mean a wiring line that electrically connects between a plurality of pads that overlap in the horizontal direction.
  • the pad portion and the via electrode may be distinguished based on a width in the horizontal direction, a thickness in the vertical direction, and a slope of the side surface. For example, the width of the pad portion in the horizontal direction may be greater than the width of the via electrode in the horizontal direction.
  • the thickness of the pad portion in the vertical direction may be less than the thickness of the via electrode in the vertical direction.
  • the slope of the side surface of the pad portion may be closer to perpendicular to the upper or lower surface of the build-up insulating layer (110) than the slope of the side surface of the via electrode.
  • the pad portion and the via electrode can be distinguished using at least one of the width in the horizontal direction, the thickness in the vertical direction, and the slope of the side surface.
  • the trace may mean a signal line that electrically connects between a plurality of pad portions. At this time, the trace and the pad portion can be formed based on the width in the horizontal direction.
  • the width of the trace in the horizontal direction can be smaller than the width of the pad portion in the horizontal direction.
  • the trace and the pad portion can be distinguished by whether or not they overlap with the via electrode in the vertical direction.
  • the pad portion can overlap with the via electrode in the vertical direction and be physically and/or electrically directly connected to the via electrode, and the trace may not overlap with the via electrode in the vertical direction.
  • the trace can electrically connect between the plurality of pad portions in the horizontal direction.
  • first to fourth upper pad portions (151, 152, 153, 154) and the first to third lower pad portions (155, 156, 157) can function to electrically connect with semiconductor elements placed on the circuit board (100).
  • Each of the first to fourth upper pad portions (151, 152, 153, 154) and the first to third lower pad portions (155, 156, 157) can be freely designed in consideration of impedance.
  • the fourth upper pad portion (154) is positioned between the upper build-up insulating layer (111) and the lower build-up insulating layer (112).
  • the base portion (173) of the through via electrode (170) described later may be a part of the fourth upper pad portion (154).
  • the fourth upper pad portions (154) may be arranged in multiple numbers while being spaced apart from each other in the horizontal direction.
  • the pad portions that are physically and/or electrically connected to the first portion (172) and the second portion (171) of the through-via electrode (170) may be referred to as a base portion (173) that electrically connects a portion of the wiring portion (140) described above with the through-via electrode (170).
  • the base portion (173) may electrically connect the other upper pad portions/via electrodes of the wiring portion (140) and the second portion (171) of the through-via electrode in order to simplify the manufacturing process and further improve the product yield while improving the physical reliability and/or electrical reliability of the first portion (172) and the second portion (171) of the through-via electrode (170) described later. Furthermore, the base portion (173) can electrically connect the other lower pad portion/via electrode of the wiring portion (140) and the first portion (172) of the through-via electrode.
  • the wiring portion (140) can include a plurality of pad portions (150) and a plurality of via electrodes (160) as described above.
  • the plurality of pad portions (150) and the plurality of via electrodes (160) can be used as signal wiring for signal transmission.
  • the remaining portions of the plurality of pad portions (150) and the plurality of via electrodes (160) can be electrically connected to the first portion (172) and the second portion (171) of the through-via electrode (170), thereby performing the same function as the function performed by the first portion (172) and the second portion (171).
  • the first portion (172) and the second portion (171) of the through-via electrode (170) perform a heat dissipation function
  • at least some of the plurality of pad portions (150) and the plurality of via electrodes (160) of the wiring portion (140) may be physically and electrically connected to the first portion (172) and/or the second portion (171) of the through-via electrode to perform the heat dissipation function.
  • the pad portions (150) and the via electrodes (160) of the wiring portion (140) that are electrically connected to the first portion (172) and the second portion (171) of the through-via electrode may be used as a seed layer for easy electroplating of the first portion (172) and/or the second portion (171) of the through-via electrode. A detailed structure thereof will be described later.
  • the first to sixth via electrodes (161, 162, 163, 164, 165, 166) can be formed simultaneously in the process of arranging the first to fourth upper pad portions (151, 152, 153, 154) and the first to third lower pad portions (155, 156, 157).
  • a through hole can be formed in the first insulating layer (113) to expose a portion of the second upper pad portion (152), thereby forming the first upper pad portion (151) together with the first via electrode (161) filling the through hole of the first insulating layer (113). Therefore, the first via electrode (161) can be distinguished as a protrusion of the first upper pad portion (151).
  • the inclination angle of the upper through-via electrode (171) may be different from the inclination angles of the first to third via electrodes (161, 162, 163).
  • the upper through-via electrode (171) may be provided so as to integrally penetrate the first to third insulating layers (113, 114, 115) while having a relatively large horizontal width
  • the first to third via electrodes (161, 162, 163) may be provided so as to penetrate the first to third insulating layers (113, 114, 115) respectively while having a relatively small horizontal width. Therefore, the inclination angle of the upper through-via electrode (171) may be closer to vertical than the inclination angles of each of the first to third via electrodes (161, 162, 163).
  • the inclination angle of the side surface of the upper through-via electrode (171) with respect to the upper surface of the upper build-up insulating layer (111) may be closer to vertical than the inclination angle of the side surface of each of the first to third via electrodes (161, 162, 163) with respect to the upper surface of the upper build-up insulating layer (111).
  • the volume of the upper through-via electrode (171) in the upper build-up insulating layer (111) can be increased. Accordingly, the effect according to the function of the upper through-via electrode (171) can be maximized.
  • the heat dissipation characteristics can be further improved by maximizing the volume of the upper through-via electrode (171).
  • the semiconductor device can be operated more stably, and thus the product reliability can be further improved.
  • the lower through-hole via electrode (172) may be provided to integrally penetrate the lower build-up insulating layer (112).
  • the lower through-hole via electrode (172) may integrally penetrate the fourth to sixth insulating layers (116, 117, 118) of the lower build-up insulating layer (112).
  • the lower through-via electrode (172) may have a width that increases horizontally along the direction from the upper surface of the build-up insulating layer (110) toward the lower surface of the build-up insulating layer (110).
  • the inclination angle of the lower through-via electrode (172) may be different from the inclination angles of the fourth to sixth via electrodes (164, 165, 166).
  • the lower through-via electrode (172) may be provided so as to integrally penetrate the fourth to sixth insulating layers (116, 117, 118) while having a relatively large horizontal width
  • the fourth to sixth via electrodes (164, 165, 166) may be provided so as to penetrate the fourth to sixth insulating layers (116, 117, 118) respectively while having a relatively small horizontal width. Therefore, the inclination angle of the lower through-via electrode (172) may be closer to vertical than the inclination angles of each of the fourth to sixth via electrodes (164, 165, 166).
  • the inclination angle of the side surface of the lower through-via electrode (172) with respect to the lower surface of the lower build-up insulating layer (112) may be closer to vertical than the inclination angle of the side surface of each of the fourth to sixth via electrodes (164, 165, 166) with respect to the lower surface of the lower build-up insulating layer (112).
  • the volume of the lower through-via electrode (172) in the lower build-up insulating layer (112) can be increased. Accordingly, the effect according to the function of the lower through-via electrode (172) can be maximized.
  • the heat dissipation characteristics can be further improved by maximizing the volume of the lower through-via electrode (172).
  • the semiconductor device can be operated more stably, and thus the product reliability can be further improved.
  • the first protective layer (120) may be disposed on the upper surface of the upper build-up insulating layer (111), and the second protective layer (130) may be disposed on the lower surface of the lower build-up insulating layer (112).
  • the first protective layer (120) and the second protective layer (130) may protect the upper surface of the first upper pad portion (151) and/or the upper build-up insulating layer (111) from external moisture or contaminants.
  • the first protective layer (120) functions to prevent short circuits between solders due to low wettability with the solder.
  • the first protective layer (120) may use a photocurable insulating material, and for example, a solder resist may be used.
  • the first protective layer (120) may include a thermocurable insulating material that is the same insulating material as the build-up insulating layer (110).
  • the first protective layer (120) may have the same insulating material as the build-up insulating layer (110), and may be provided as, for example, ABF (Ajinomoto Build-up Film) from Ajinomoto Corporation.
  • the circuit board (100) requires a heat dissipation function for stable operation of semiconductor elements.
  • the heat dissipation function may mean easily dissipating heat generated from semiconductor elements placed on the circuit board (100) to the outside of the circuit board.
  • the embodiment can discharge heat generated from a semiconductor element placed on a circuit board toward the lower side of the circuit board by using an upper through-via electrode (171) and a lower through-via electrode (172) provided in an upper build-up insulating layer (111) and a lower build-up insulating layer (112).
  • the wiring section (140) may include a wiring section that is electrically connected to the upper through-via electrode (171) and/or the lower through-via electrode (172) and that applies current for electrolytic plating the upper through-via electrode (171) and/or the lower through-via electrode (172).
  • a comparative example is a process in which a mask (20) having a through hole (TH) and an opening vertically overlapping each other is formed on a build-up insulating layer (10), and then a process of plating a first metal layer (30) and a second metal layer (40) is performed.
  • the first metal layer (30) is a seed layer for forming the second metal layer (40), and may be, for example, a chemical copper plating layer.
  • the second metal layer (40) is an electrolytic plating layer formed by electrolytic plating the first metal layer (30) as a seed layer.
  • the first metal layer (30) is formed on the inner wall of the through hole (TH) and the bottom surface of the through hole (TH) (preferably, the upper surface of the lower pad exposed through the through hole). Accordingly, when the second metal layer (40) is formed by electroplating, plating is performed on the inner wall of the through hole (TH) and the upper surface of the lower pad. For example, in a comparative example, isotropic plating of the second metal layer (40) is performed as electroplating is performed using the first metal layer (30) as a seed layer. At this time, the second metal layer (40) is formed to fill the through hole (TH) and the opening of the mask (20). At this time, the portion of the second metal layer (40) provided in the opening of the mask (20) may exceed the target thickness before the second metal layer (40) is completely filled within the through hole (TH).
  • the comparative example must perform multiple plating processes to completely fill the through hole (TH) with the second metal layer (40). For example, the comparative example performs a process of forming a primary second metal layer (40) in the through hole (TH) and the opening of the mask (20). Thereafter, the comparative example performs a process of removing a portion of the second metal layer (30) that protrudes excessively above the opening of the mask (20) by polishing. Thereafter, the comparative example performs a process of forming a secondary second metal layer (40) in the second through hole (TH) and the opening of the mask (20). At this time, the plating process as described above may be performed repeatedly, and the number of plating processes may increase depending on the depth of the through hole (TH) in the vertical direction.
  • the comparative example has the problem that the time required to completely fill the via hole (TH) with the second metal layer (40) increases and the manufacturing process becomes complicated.
  • the upper surface of the second metal layer (40) that is finally formed is not flat but has a curve.
  • the upper surface of the second metal layer (40) includes a convex portion (40T1) that is convex toward the upper direction and a concave portion (40T2) that is concave toward the lower direction.
  • isotropic plating is performed using the first metal layer (30) formed on the side wall of the via hole (TH) as a seed layer, and accordingly, there is a problem that the difference in flatness between the convex portion (40T1) and the concave portion (40T2) becomes larger.
  • the height difference between the convex portion (40T1) and the concave portion (40T2) exceeds 150 um, or exceeds 180 um, or exceeds 200 um. Therefore, in the comparative example, in order to match the flatness between the convex portion (40T1) and the concave portion (40T2), a polishing process of at least 150 um must be performed.
  • the embodiment forms the upper through-via electrode (171) and the lower through-via electrode (172) without forming a separate seed layer such as a chemical copper plating layer.
  • the upper through-via electrode (171) and the lower through-via electrode (172) may be formed by filling a material such as a conductive paste, but in this case, since they have relatively low heat transfer characteristics, the heat dissipation characteristics of the circuit board and the semiconductor package may be deteriorated.
  • the embodiment forms an upper through-via electrode (171) and a lower through-via electrode (172) having excellent heat dissipation characteristics by performing electrolytic plating. Furthermore, the embodiment enables electrolytic plating of the upper through-via electrode (171) and the lower through-via electrode (172) without forming a seed layer, such as a separate chemical copper plating layer, for electrolytic plating of the upper through-via electrode (171) and the lower through-via electrode (172).
  • the upper through-via electrode (171) and the lower through-via electrode (172) may include only an electrolytic plating layer, and the electrolytic plating layer of the upper through-via electrode (171) and the lower through-via electrode (172) may allow the build-up insulating layer (110) to directly contact the inner wall of the through hole.
  • the embodiment utilizes a portion of the pad portion (150) and the via electrode (160) constituting the wiring portion (140) as a seed layer for electrolytic plating of the upper through-via electrode (171) and the lower through-via electrode (172).
  • the embodiment can form the upper through-via electrode (171) and the lower through-via electrode (172) by electrolytic plating, while allowing the upper through-via electrode (171) and the lower through-via electrode (172) to include only an electrolytic plating layer, and further, can prevent a chemical copper plating layer from being provided between the electrolytic plating layers of the upper through-via electrode (171) and the lower through-via electrode (172) and the inner wall of the through hole of the build-up insulating layer (110).
  • the structure has no separate seed layer disposed between the inner wall of the upper build-up insulating layer (111) and the upper through-via electrode (171), and accordingly, it can be confirmed that the interface (IS) between the inner wall of the upper build-up insulating layer (111) and the upper through-via electrode (171) is clearly distinguishable compared to the comparative example.
  • the embodiment may have a small gap provided at the interface (IS) between the inner wall of the upper build-up insulating layer (111) and the upper through-via electrode (171), through which heat transferred through the upper through-via electrode (171) can be minimized from being transferred to the upper build-up insulating layer (111), and thereby, electrical reliability and/or physical reliability of the circuit board can be further improved.
  • the circuit board of the embodiment includes an upper build-up insulating layer (111).
  • the upper build-up insulating layer (111) includes a plurality of insulating layers (113, 114, 115) stacked along a vertical direction.
  • a wiring portion (140) including a pad portion (150) and a via electrode (160) may be provided on a plurality of insulating layers (113, 114, 115) of the upper build-up insulating layer (111). Additionally, an upper through-via electrode (171) may be provided by integrally penetrating the plurality of insulating layers (113, 114, 115).
  • the wiring section (140) includes a first wiring section (140A) and a second wiring section (140B).
  • each of the first wiring section (140A) and the second wiring section (140B) may include a pad section (151, 152, 153, 154) and a via electrode (161, 162, 163).
  • the pad portions (151, 152, 153, 154) and via electrodes (161, 162, 163) of the first wiring portion (140A) are connected to the upper through-via electrode (171) and the lower through-via electrode (172) through the base portion (173), and the pad portions (151, 152, 153, 154) and via electrodes (161, 162, 163) of the second wiring portion (140B) can be electrically separated from the first wiring portion (140A), the upper through-via electrode (171), the lower through-via electrode (172), and the base portion (173).
  • the first wiring portion (140A) may refer to a wiring portion that is arranged closest to the upper through-via electrode (171).
  • the first wiring portion (140A) may refer to a wiring portion that is closest to the upper through-via electrode (171) along the horizontal direction.
  • the first wiring portion (140A) may refer to a wiring portion that is arranged closer to the upper through-via electrode (171) than the second wiring portion (140B).
  • the first wiring portion (140A) may be electrically connected to the upper through-via electrode (171).
  • the second wiring portion (140B) may be electrically spaced from the upper through-via electrode (171).
  • the second wiring portion (140B) may be electrically spaced from the first wiring portion (140A).
  • the second wiring portion (140B) may refer to a wiring portion that is spaced further away from the upper through-via electrode (171) than the first wiring portion (140A). That is, the first wiring portion (140A) may be positioned between the second wiring portion (140B) and the upper through-via electrode (171).
  • the second wiring section (140B) may be a wiring section that has a different function from the first wiring section (140A).
  • the second wiring unit (140B) may be a signal transmission electrode that transmits a signal.
  • the second wiring unit (140B) may be a communication line that transmits a signal to a semiconductor element placed on a circuit board or receives and transmits a signal transmitted from a semiconductor element.
  • the first wiring unit (140A) may function as a line other than a signal transmission line.
  • the first wiring unit (140A) may be utilized as a heat transfer path that transfers heat.
  • the first wiring unit (140A) may be an electrode that functions as a heat dissipation electrode together with the upper through-via electrode (171), but is not limited thereto.
  • the upper through-via electrode (171) may perform a function other than a heat dissipation function, and accordingly, the first wiring portion (140A) may perform a function corresponding to the other function of the upper through-via electrode (171).
  • the first wiring portion (140A) is electrically connected to the upper through-via electrode (171) and may be utilized as a current transmission path for transmitting a plating current applied to electrolytically plate the upper through-via electrode (171).
  • the upper through-via electrode (171) may be an electrolytically plated layer electrolytically plated through a current flowing through the first wiring portion (140A).
  • the first wiring portion (140A) can be used as a power line for applying a plating current for electrolytic plating the upper through-via electrode (171) and the lower through-via electrode (172).
  • the first wiring portion (140A) can be used as a ground electrode for grounding together with the upper through-via electrode (171), the lower through-via electrode (172), and the base portion (173), or can be used as a heat dissipation line for heat dissipation.
  • the first wiring section (140A) includes a plurality of via electrodes (160A1) each arranged within a plurality of insulating layers (113, 114, 115) along the vertical direction, and pad sections (150A2, 150A3) each arranged between the plurality of via electrodes (160A1).
  • the second wiring portion (140B) includes a plurality of via electrodes (160B) each arranged within a plurality of insulating layers (113, 114, 115) along the vertical direction, and a pad portion (150B) each arranged between the plurality of via electrodes (160B).
  • the plurality of via electrodes (160A1) and pad portions (150A2, 150A3) of the first wiring portion (140A) may have substantially the same shape and/or structure as the plurality of via electrodes (160B) and pad portions (150B) of the second wiring portion (140B).
  • the plurality of via electrodes (160A1) and pad portions (150A2, 150A3) of the first wiring portion (140A) have a structure electrically connected to the upper through-via electrode (171).
  • the plurality of via electrodes (160B) and pad portions (150B) of the second wiring portion (140B) have a structure electrically spaced apart from the first wiring portion (140A) and the upper through-via electrode (171).
  • a plurality of via electrodes (160A1) and pad portions (150A2, 150A3) of the first wiring portion (140A) are electrically connected to the upper through-via electrode (171), and can function as a seed layer that supplies plating current in a process of electroplating the upper through-via electrode (171).
  • a plurality of via electrodes (160B) and pad portions (150B) of the second wiring portion (140B) are electrically spaced apart from the first wiring portion (140A) and the upper through-via electrode (171), and can function as signal wiring that transmits a practical electrically effective signal through this.
  • the base portion (173) of the through-via electrode (170) may mean one of the pad portions of the first wiring portion (140A), and preferably, may mean a base pad that electrically connects the through-via electrode (170) and the first wiring portion (140A).
  • the base portion (173) can electrically connect between the plurality of via electrodes (160A1) of the first wiring portion (140A) and the upper through-via electrode (171).
  • the base portion (173) can be electrically and physically connected to the plurality of via electrodes (160A1) of the first wiring portion (140) while being electrically and physically connected to the upper through-via electrode (171).
  • the base portion (173) can be electrically and physically connected to the plurality of via electrodes (160A1) of the first wiring portion (140) while being electrically and physically connected to the lower through-via electrode (172).
  • the base portion (173) may include a first overlapping portion overlapping a plurality of via electrodes (160A) along the vertical direction, and a second overlapping portion overlapping an upper through-via electrode (171) along the vertical direction.
  • the width of the base portion (173) in the horizontal direction may be greater than the width of the upper through-via electrode (171) in the horizontal direction.
  • the width of the base portion (173) in the horizontal direction may be greater than the width of the lower through-via electrode (172) in the horizontal direction.
  • the width of the base portion (173) in the horizontal direction may be greater than the sum of the widths of the upper through-via electrode (171) and the via electrode (160A1) in the horizontal direction.
  • the base portion (173) may refer to a pad portion that is closest to the lower surface of the upper through-via electrode (171).
  • the base portion (173) may be a pad portion that is in contact with the lower surface of the upper through-via electrode (171).
  • the base portion (173) may be a pad portion that is in contact with the via electrode located at the lowest position among the plurality of via electrodes (160A1) of the first wiring portion (140A).
  • the base portion (173) may be in direct contact with the via electrode (160A1) of the first wiring portion (140A) and may also be in direct contact with the upper through-via electrode (171).
  • direct contact may refer to direct contact with the lower surface of the via electrode located at the lowest position among the upper via electrodes (160A1) of the base portion (173) and the lower surface of the upper through-via electrode (171).
  • the base portion (173) can electrically connect between the via electrode (160A1) of the first wiring portion (140A) and the upper through-via electrode (171).
  • the planar area of the base portion (173) can be larger than the planar area of the upper through-via electrode (171).
  • the base portion (173) can vertically overlap with each of the plurality of via electrodes (160A1) and the upper through-via electrode (171) of the first wiring portion (140A).
  • the base portion (173) electrically connects the first wiring portion (140A) and the upper through-via electrode (171), thereby enabling electrolytic plating of the upper through-via electrode (171) using the first wiring portion (140A). That is, the first wiring portion (140A) can function as a seed layer used for electroplating the upper through-via electrode (171), and further can function as a heat dissipation electrode that releases heat together with the upper through-via electrode.
  • the base portion (173) may overlap with the upper through-via electrode (171) in the vertical direction, but may not overlap with the upper through-via electrode (171) in the horizontal direction. This may mean that the upper through-via electrode (171) is placed on the base portion (173) in a state where the lower surface of the upper through-via electrode (171) is in direct contact with the upper surface of the base portion (173) based on the position where the base portion (173) is placed.
  • the upper surface of the base portion (173) may include a first upper surface that contacts the lower surface of the upper through-via electrode (171) along the vertical direction, and a second upper surface that contacts a plurality of via electrodes (160A1) of the first wiring portion (140A) along the vertical direction.
  • the plurality of via electrodes (160A1) may be provided in plurality and spaced apart from each other along the horizontal direction.
  • the second upper surface may be divided into a plurality of sub-parts that are spaced apart from each other along the circumferential direction of the first upper surface.
  • the base portion (173) may be a reference pad that distinguishes the upper insulating layer from the lower insulating layer.
  • the upper surface of the base portion (173) is in direct contact with the lower surface of the upper through-via electrode (171), and the lower surface of the base portion (173) is in direct contact with the upper surface of the lower through-via electrode (172).
  • the base portion (173) is a plate-shaped single pad, and a plurality of via electrodes (160A1) and an upper through-via electrode (171) of the first wiring portion (140A) are arranged on the upper portion.
  • the base portion (173) can electrically connect a plurality of middle pad portions (150A2), a plurality of upper pad portions (150A3), and a plurality of via electrodes (160A1) of the first wiring portion (140A) that are overlapped with the upper through-via electrodes (171) that are overlapped in the horizontal direction.
  • the base portion (173) can electrically connect the first wiring portion (140A) and the upper through-via electrode (171) described above.
  • the via electrode (160A1) of the first wiring portion (140A) is provided in each of the plurality of insulating layers of the upper build-up insulating layer (111).
  • the via electrodes (160A1) of the first wiring portion (140A) are provided in plurality in the first insulating layer (114) and spaced apart from each other along the circumferential direction of the upper through-via electrode (171).
  • the via electrodes (160A1) of the first wiring portion (140A) are provided in plurality in the second insulating layer (115) and spaced apart from each other along the circumferential direction of the upper through-via electrode (171).
  • the upper pad portion (150A3) may be physically and/or electrically connected to the through-via electrode pad (171P1).
  • the upper pad portion (150A3) and the through-via electrode pad (171P1) may be physically directly connected to each other to form a single pad.
  • the upper pad portion (150A3) and the through-via electrode pad (171P1) may be formed integrally. This may be implemented by adjusting the size of the opening of the mask disposed on the upper build-up insulating layer (111) in the process of forming the upper through-via electrode (171).
  • the base portion is electrically connected to the plurality of via electrodes and is also connected to the through-via electrode.
  • the first wiring portion and the through-via electrode are electrically connected.
  • the through-via electrode includes an upper through-via electrode disposed on the base portion, and a lower through-via electrode disposed under the base portion.
  • the first wiring portion includes an upper wiring portion provided along the circumferential direction of the upper through-via electrode, and a lower wiring portion provided along the circumferential direction of the lower through-via electrode.
  • the upper through-via electrode and the lower through-via electrode in the previous embodiment have shapes that are symmetrical with respect to the base portion.
  • the upper wiring portion and the lower wiring portion have shapes that are symmetrical with respect to the base portion.
  • a circuit board according to an embodiment of FIG. 10 includes an upper build-up insulating layer (211) including a plurality of insulating layers stacked along a vertical direction, and a lower build-up insulating layer (212) including a plurality of insulating layers stacked along a vertical direction.
  • a first protective layer (220) is disposed on the upper build-up insulating layer (211).
  • a second protective layer (230) is disposed under the lower build-up insulating layer (212).
  • the wiring portion of the circuit board has a plurality of via electrodes and pad portions.
  • the wiring portion includes a first wiring portion (242, 243) electrically connected to an upper through-via electrode (250) and/or a lower through-via electrode (260).
  • the wiring portion includes a second wiring portion (244) electrically and physically spaced from the upper through-via electrode (250) and the lower through-via electrode (260).
  • the first wiring portion (242, 243) includes an upper wiring portion (242) provided along the circumferential direction of the upper through-via electrode (250).
  • the first wiring portion (242, 243) includes a lower wiring portion (243) provided along the circumferential direction of the lower through-via electrode (260).
  • the upper through-via electrode (171) and the lower through-via electrode (172) in the previous embodiment had shapes that were symmetrical to each other.
  • the upper through-via electrode (250) and the lower through-via electrode (260) may have an asymmetrical shape with respect to the base portion (241).
  • the width in the horizontal direction and/or the thickness in the vertical direction of the upper through-via electrode (250) may be different from the width in the horizontal direction and/or the thickness in the vertical direction of the lower through-via electrode (260).
  • the width in the horizontal direction of the upper through-via electrode (250) may be different from the width in the horizontal direction of the lower through-via electrode (260).
  • the width in the horizontal direction of the upper through-via electrode (250) may be smaller than the width in the horizontal direction of the lower through-via electrode (260).
  • the embodiment may allow heat to be transferred from the upper through-via electrode (250) having a relatively small width in the horizontal direction to the lower through-via electrode (260) having a relatively large width in the horizontal direction. That is, the embodiment can control the heat transfer direction by varying the width of the upper through-via electrode (250) and the lower through-via electrode (260), thereby providing a more efficient heat dissipation function.
  • a circuit board according to an embodiment of FIG. 11 includes an upper build-up insulating layer (311) including a plurality of insulating layers stacked along a vertical direction, and a lower build-up insulating layer (312) including a plurality of insulating layers stacked along a vertical direction.
  • a first protective layer (320) is disposed on the upper build-up insulating layer (311).
  • a second protective layer (330) is disposed under the lower build-up insulating layer (312).
  • an upper through-via electrode (350) is arranged to integrally penetrate the upper build-up insulating layer (311) on which multiple insulating layers are laminated.
  • a lower through-via electrode (360) is arranged to integrally penetrate the lower build-up insulating layer (312) on which multiple insulating layers are laminated.
  • the upper through-via electrode (350) may be provided in multiple pieces spaced apart along the horizontal direction.
  • the upper through-via electrode (350) may include a first upper through-via electrode (351) that integrally penetrates multiple insulating layers of the upper insulating layer (311), and a second upper through-via electrode (352) that integrally penetrates multiple insulating layers of the upper insulating layer (311) and is spaced apart from the first upper through-via electrode (351) in the horizontal direction.
  • the first upper through-via electrode (351) and the second upper through-via electrode (352) may be referred to as a first sub-through-via electrode and a second sub-through-via electrode of the upper through-via electrode (350) that are spaced apart from each other in the horizontal direction.
  • the first upper through-via electrode (351) and the second upper through-via electrode (352) can transfer heat through mutually branched paths. This allows the embodiment to dissipate heat through multiple paths rather than a single path, thereby further improving heat dissipation characteristics.
  • a plurality of semiconductor elements may be arranged on the circuit board.
  • first and second semiconductor elements spaced apart horizontally may be arranged on the circuit board.
  • first upper through-via electrode (351) may be provided in an area where the first semiconductor element is arranged.
  • second upper through-via electrode (352) may be provided in an area where the second semiconductor element is arranged. That is, the embodiment may provide an upper through-via electrode corresponding to each of a plurality of semiconductor elements arranged on the circuit board. Through this, the embodiment may further maximize the heat dissipation characteristics in a semiconductor package in which a plurality of semiconductor elements are arranged.
  • the wiring portion of the circuit board has a plurality of via electrodes and pad portions.
  • the wiring portion includes a first wiring portion (342, 343) electrically connected to an upper through-via electrode (350) and/or a lower through-via electrode (360).
  • the wiring portion includes a second wiring portion (344) spaced apart from the upper through-via electrode (350) and the lower through-via electrode (360).
  • the first wiring portion (342, 343) includes an upper wiring portion (342) provided along the circumferential direction of the upper through-via electrode (350).
  • the first wiring portion (342, 343) includes a lower wiring portion (343) provided along the circumferential direction of the lower through-via electrode (360).
  • the upper wiring portion (342) may include a first upper wiring portion (342a) provided along the circumferential direction of the first upper through-via electrode (351).
  • the upper wiring portion (342) may include a second upper wiring portion (342b) provided along the circumferential direction of the second upper through-via electrode (352). That is, the embodiment may allow the upper through-via electrode (350) to include a first upper through-via electrode (351) and a second upper through-via electrode (352) spaced apart from each other in the horizontal direction, and the upper wiring portion (342) to include a first upper wiring portion (342a) and a second upper wiring portion (342b) provided along the circumferential direction of each of the upper through-via electrodes. Through this, the embodiment may allow uniform plating of each of the first upper through-via electrode (351) and the second upper through-via electrode (352).
  • a circuit board according to an embodiment of FIG. 12 includes an upper build-up insulating layer (411) including a plurality of insulating layers stacked along a vertical direction, and a lower build-up insulating layer (412) including a plurality of insulating layers stacked along a vertical direction.
  • a first protective layer (420) is disposed on the upper build-up insulating layer (411).
  • a second protective layer (430) is disposed under the lower build-up insulating layer (412).
  • an upper through-via electrode (450) is disposed that integrally penetrates the upper build-up insulating layer (411) on which multiple insulating layers are laminated.
  • a lower through-via electrode (460) is disposed that integrally penetrates the lower build-up insulating layer (412) on which multiple insulating layers are laminated.
  • the wiring portion of the circuit board has a plurality of via electrodes and pad portions.
  • the wiring portion includes a first wiring portion (442, 443) electrically connected to an upper through-via electrode (450) and/or a lower through-via electrode (460).
  • the wiring portion includes a second wiring portion (444) spaced apart from the upper through-via electrode (450) and the lower through-via electrode (460).
  • the first wiring portion (442, 443) includes an upper wiring portion (442) provided on one side of the periphery of the upper through-via electrode (450).
  • the first wiring portion (442, 443) includes a lower wiring portion (443) provided on the other side of the periphery of the lower through-via electrode (460).
  • each of the upper wiring portion and the lower wiring portion in the previous embodiment was provided to surround the periphery of the upper through-via electrode or the lower through-via electrode.
  • the horizontal central axis of the lower through-via electrode (460) and the horizontal central axis of the upper through-via electrode (450) may be misaligned with each other.
  • a semiconductor element (630) may be placed on the first connection portion (610) and the second connection portion (620).
  • the semiconductor element (630) may be electrically connected to the circuit board (600) through the first connection portion (610) and the second connection portion (620).
  • the semiconductor element (630) may be thermally connected to a through-via electrode of the circuit board (600) through the first connection portion (610). Through this, heat generated in the semiconductor element (630) may be dissipated through the through-via electrode of the circuit board (600) through the first connection portion (610).
  • the semiconductor element (630) has a terminal (640), and the terminal (640) of the semiconductor element (630) can be electrically connected to a pad portion of a second wiring portion of the circuit board through a second connection portion (620).
  • the semiconductor package may include at least one circuit board among the circuit boards illustrated in FIGS. 1 to 13.
  • the semiconductor package may include a circuit board (700) as illustrated in FIG. 3.
  • the semiconductor element (730) may be provided with a terminal (740) on the upper surface, and a connecting member (720) such as a wire may electrically connect the terminal (740) of the semiconductor element (730) and the pad portion of the second wiring portion of the circuit board.
  • Figures 16 to 20 are cross-sectional views showing a method for manufacturing a circuit board according to one embodiment in process order.
  • the embodiment may perform a process of forming a build-up insulating layer (110) in which an upper build-up insulating layer (111) and a lower build-up insulating layer (112) are stacked along a vertical direction, and a wiring portion (140) including a plurality of via electrodes and a plurality of pad portions within the build-up insulating layer (110).
  • the wiring portion (140) may include a first wiring portion (140A) and a second wiring portion (140B).
  • the first wiring portion (140) may include a base portion (173) which is a part of a through-via electrode (170).
  • the embodiment may perform a process of forming an upper through hole (VH1) integrally penetrating the upper build-up insulating layer (111). At this time, the embodiment may perform a process of forming the upper through hole (VH1) using the base portion (173) as a stopper. Therefore, as the upper through hole (VH1) is formed, the upper surface of the base portion (173) may be exposed.
  • the embodiment may perform a process of forming a lower through hole (VH2) integrally penetrating the lower build-up insulating layer (112). At this time, the embodiment may perform a process of forming the lower through hole (VH2) using the base portion (173) as a stopper. Therefore, as the lower through hole (VH2) is formed, the lower surface of the base portion (173) may be exposed.
  • the embodiment may perform a process of forming a first mask (M1) on the upper build-up insulating layer (111).
  • the first mask (M1) may include an opening that overlaps the upper through hole (VH1) in a vertical direction.
  • the opening of the first mask (M1) may expose a side surface of the uppermost pad portion of the first wiring portion (140A). Through this, the upper pad portion of the upper through via electrode and the upper pad portion of the first wiring portion (140A) may be physically directly connected to each other later.
  • the embodiment may perform a process of forming a second mask (M2) on the lower build-up insulating layer (112).
  • the second mask (M2) may include an opening that overlaps the lower through hole (VH2) in a vertical direction.
  • the opening of the second mask (M2) may expose a side surface of the lowermost pad portion of the first wiring portion (140A).
  • the embodiment may perform a process of forming an electrolytic plating layer (171A) on the upper surface of the base portion (173) by performing electrolytic plating on the first wiring portion (140A) as a seed layer.
  • the embodiment may form the electrolytic plating layer (171A) using the first wiring portion (140A), and thus, plating growth to a uniform height along the vertical direction may be achieved.
  • the embodiment may perform a process of forming an electrolytic plating layer (172A) on the lower surface of the base portion (173) by performing electrolytic plating on the first wiring portion (140A) as a seed layer.
  • the embodiment may form the electrolytic plating layer (172A) using the first wiring portion (140A), and thus, plating growth to a uniform height along the vertical direction may be achieved.
  • the embodiment may perform a process of forming an upper through-via electrode (171) and an upper pad portion of the upper through-via electrode (171).
  • the embodiment may perform a process of forming a lower through-via electrode (172) and a lower pad portion of the lower through-via electrode (172).
  • the embodiment may perform a process of removing the first mask (M1) and the second mask (M2).
  • the embodiment can proceed with a process of forming a first protective layer (120) and a second protective layer (130).
  • a circuit board having the characteristics of the invention described above when used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply.
  • a circuit board having the characteristics of the invention when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips.
  • problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips.
  • the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

Une carte de circuit imprimé selon un mode de réalisation comprend : une couche isolante à empilement comprenant une pluralité de couches isolantes empilées verticalement ; une partie de câblage comprenant une pluralité d'électrodes traversantes disposées respectivement dans la pluralité de couches isolantes de la couche isolante à empilement ; et une électrode traversante pénétrant dans la couche isolante à empilement. L'électrode traversante comprend : une première partie dont la largeur dans la direction horizontale augmente dans une direction allant de la surface supérieure de la couche isolante à empilement vers la surface inférieure de la couche isolante à empilement ; une seconde partie disposée sur la première partie et dont la largeur dans la direction horizontale diminue dans une direction allant de la surface supérieure de la couche isolante à empilement vers la surface inférieure de la couche isolante à empilement ; et une partie de base disposée entre la première partie et la seconde partie. Au moins une parmi la pluralité d'électrodes traversantes de la partie de câblage est connectée à la partie de base.
PCT/KR2025/003821 2024-03-29 2025-03-25 Carte de circuit imprimé et boîtier pour semi-conducteurs la comprenant Pending WO2025206719A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR20240043703 2024-03-29
KR10-2024-0043703 2024-03-29
KR1020250005306A KR20250146153A (ko) 2024-03-29 2025-01-14 회로 기판 및 이를 포함하는 반도체 패키지
KR10-2025-0005306 2025-01-14

Publications (1)

Publication Number Publication Date
WO2025206719A1 true WO2025206719A1 (fr) 2025-10-02

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Application Number Title Priority Date Filing Date
PCT/KR2025/003821 Pending WO2025206719A1 (fr) 2024-03-29 2025-03-25 Carte de circuit imprimé et boîtier pour semi-conducteurs la comprenant

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Country Link
WO (1) WO2025206719A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011243767A (ja) * 2010-05-19 2011-12-01 Sony Chemical & Information Device Corp 多層配線板とその製造方法
KR20120117456A (ko) * 2011-04-15 2012-10-24 삼성전기주식회사 인쇄회로기판 및 그 제조방법
KR20130139655A (ko) * 2012-06-13 2013-12-23 삼성전기주식회사 인쇄회로기판 및 그 제조방법
KR20160131003A (ko) * 2014-03-10 2016-11-15 마벨 월드 트레이드 리미티드 양측 레이저 공정을 사용하여 비아 구조체를 형성하기 위한 방법
KR20190127254A (ko) * 2018-05-04 2019-11-13 삼성전기주식회사 인쇄회로기판

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011243767A (ja) * 2010-05-19 2011-12-01 Sony Chemical & Information Device Corp 多層配線板とその製造方法
KR20120117456A (ko) * 2011-04-15 2012-10-24 삼성전기주식회사 인쇄회로기판 및 그 제조방법
KR20130139655A (ko) * 2012-06-13 2013-12-23 삼성전기주식회사 인쇄회로기판 및 그 제조방법
KR20160131003A (ko) * 2014-03-10 2016-11-15 마벨 월드 트레이드 리미티드 양측 레이저 공정을 사용하여 비아 구조체를 형성하기 위한 방법
KR20190127254A (ko) * 2018-05-04 2019-11-13 삼성전기주식회사 인쇄회로기판

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