WO2025206789A1 - Circuit board, and semiconductor package comprising same - Google Patents

Abstract

Disclosed in an embodiment of the present invention is a circuit board including: a package substrate including a first core layer; a circuit substrate including a second core layer and arranged on the package substrate; and a semiconductor device mounted on the circuit substrate, wherein the thickness of the package substrate is greater than the thickness of the circuit substrate, and the thickness of the first core layer is greater than the thickness of the second core layer.

Description

Circuit boards and semiconductor packages including the same

Embodiments according to the present invention relate to circuit boards and semiconductor packages.

As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to mount more semiconductor chips on a limited-size substrate. However, because typical packages are based on mounting a single semiconductor chip, achieving desired performance is limited.

A typical circuit board or package substrate consists of a processor package, which houses the processor chip, and a memory package, which houses the memory chips, all connected together. These package substrates integrate the processor and memory chips into a single package, reducing the chip footprint and enabling high-speed signal transmission through short paths. Due to these advantages, these package substrates are widely used in mobile devices and other devices.

Meanwhile, the recent advancements in electronic devices such as mobile devices, servers, and PCs, along with the adoption of High Bandwidth Memory (HBM), have led to larger semiconductor chip areas and the attachment of multiple semiconductor chips to a single package substrate to shorten the electrical connection distance between them, thereby increasing the size of the package. Furthermore, as the functions required for application processors increase, there is a growing need for separate processor chips for each function, and circuit boards capable of mounting these processor chips are required.

At this time, for the above application processor, even when it is separated into two processor chips by function, the number of terminals (Input/Output) provided in each processor chip is increasing.

Furthermore, due to recent trends such as 5G, the Internet of Things (IoT), increased image quality, and faster communication speeds, the number of terminals on processor chips is steadily increasing due to the increase in power and signal capacity. Consequently, the area, thickness, and circuit pattern density of circuit boards are also increasing. Furthermore, increased circuit board area and thickness can make product miniaturization difficult, leading to reliability issues such as board warping and increased product price.

Furthermore, there is a recent trend to prevent problems such as warpage of circuit boards by making the core layer of the circuit board thicker. However, when using a thick core layer, there may be difficulties in yield, density of the spacing between via electrodes, and productivity in forming via electrodes in the core layer. In addition, in order to benefit from the process, components such as bridges are mounted in the build-up layer rather than the core layer to reduce manufacturing difficulty. In addition, in the case of interposers, components such as bridges are embedded in the core layer rather than the build-up layer to prevent degradation of signal integrity by ensuring that signal paths such as wiring paths and wiring structures are regularly formed. However, there is a problem that accuracy is significantly reduced when embedding components such as bridges in the core layer.

In particular, when mounting a circuit board with a bridge mounted on a semiconductor package, there is a problem of warping occurring due to differences in thickness, such as thinning.

An embodiment of the present invention provides a circuit board having improved reliability by controlling the thickness of a core layer of a circuit board (interposer) having different thicknesses as a semiconductor package and a semiconductor package, thereby suppressing the occurrence of warpage due to differences in thermal expansion coefficients, etc.

In addition, the embodiment adjusts the height between the upper surface of the core layer and the connecting member mounted in the circuit board of the semiconductor package, and mounts the connecting member in the cavity of the core layer, so that the connecting member can be easily mounted regardless of whether the size of the connecting member is large or small, and a via penetrating the boundary surface of a plurality of insulating layers for mounting the connecting member is not formed, thereby improving the reliability of the circuit board and a semiconductor package including the same can be provided.

In addition, the embodiment can provide a circuit board and a semiconductor package including the same with improved electrical reliability by easily forming a build-up electrode portion in an upper build-up layer as a micro pattern or electrode pattern by arranging a connecting member in a core layer, thereby reducing an alignment error with an electrode of an upper element.

The problem to be solved in the embodiment is not limited to this, and it can be said that the purpose or effect that can be understood from the solution or implementation form of the problem described below is also included.

A circuit board according to an embodiment of the present invention includes a package substrate including a first core layer; a circuit board disposed on the package substrate including a second core layer; and a semiconductor device mounted on the circuit board; wherein a thickness of the package substrate may be greater than a thickness of the circuit board, and a thickness of the first core layer may be greater than a thickness of the second core layer.

The circuit board may include an upper build-up layer disposed on the second core layer; a lower build-up layer disposed under the second core layer; and a connecting member disposed in an internal cavity.

The cavity can penetrate at least one of the upper build-up layer, the core layer, and the lower build-up layer.

The above connecting member can overlap the second core layer in a horizontal direction.

The first core layer may include a first through hole, and the second core layer may include the second through hole.

The width of the first through hole may be the same on the upper surface, lower surface, and center, and the width of the second through hole may decrease toward the center of the second through hole.

The outer surface of the above connecting member may face the first surface of the cavity in the second core layer.

The above first surface may protrude from the center toward the outer surface of the connecting member in the stacking direction.

The gap between the first surface and the connecting member may be smallest at the center.

The package substrate may include a first core electrode portion including a first core via electrode penetrating the first core layer and a first core wiring portion disposed on the first core layer, and the circuit board may include a second core electrode portion including a second core via electrode penetrating the second core layer and a second core wiring portion disposed on the second core layer.

The width of the first core via electrode may be the same along the stacking direction, and the width of the second core via electrode may increase from the center toward the upper surface or the lower surface along the stacking direction.

The upper surface of the second core wiring portion may be flush with the upper surface of the upper wiring disposed on the upper surface of the connecting member.

An embodiment of the present invention implements a circuit board having improved reliability and a semiconductor package including the same by controlling the thickness of a core layer of a circuit board (interposer) having different thicknesses as a semiconductor package and suppressing the occurrence of warpage due to differences in thermal expansion coefficients.

In addition, the embodiment adjusts the height between the upper surface of the core layer and the connecting member mounted in the circuit board of the semiconductor package, and mounts the connecting member in the cavity of the core layer, so that the connecting member can be easily mounted regardless of whether the size of the connecting member is large or small, and since a via penetrating the boundary surface of a plurality of insulating layers for mounting the connecting member is not formed, a circuit board with improved reliability and a semiconductor package including the same can be implemented.

In addition, the embodiment can easily form a build-up electrode portion in an upper build-up layer into a micro pattern or electrode pattern by arranging a connecting member in a core layer, thereby reducing an alignment error with an electrode of an upper element and thereby implementing a circuit board and a semiconductor package including the same with improved electrical reliability.

The various advantageous and beneficial effects of the present invention are not limited to the above-described contents, and will be more easily understood in the course of explaining specific embodiments of the present invention.

Figure 1 is a plan view of a package according to an embodiment of the present invention;

Figure 2 is a perspective view of a package according to an embodiment of the present invention;

Figure 3 is a drawing taken along line II’ in Figure 1,

Figure 4 is a cross-sectional view of a package according to the first embodiment of the present invention;

Figure 5 is an enlarged view of K1 in Figure 4,

Figure 6 is an enlarged view of K2 in Figure 4,

Fig. 7 is a modified example of Fig. 6,

Figure 8 is an enlarged view of K3 in Figure 4,

FIGS. 9 to 15 are drawings explaining a method for manufacturing a circuit board and a package according to an embodiment of the present invention.

The present invention can be modified in various ways and has various embodiments, and specific embodiments are illustrated and described in the drawings. However, this is not to be construed as a specific embodiment of the present invention.

It is not intended to be limited to the embodiments, and should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

However, the technical idea of the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as “and (and) at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C.

Terms that include ordinal numbers, such as "second," "first," etc., may be used to describe various components, but the components are not limited by the terms. The terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a second component may be referred to as a "first component," and similarly, a first component may also be referred to as a "second component." The terms "and/or" include a combination of multiple related items described herein or any of multiple related items described herein. These terms are only used to distinguish the component from other components and are not limited by the nature, order, or sequence of the component.

And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Also, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

Additionally, the expression that configuration A is positioned between configurations B and C should also include the meaning that configuration A is positioned so that it overlaps configurations B and C at least partially in the horizontal and/or vertical directions.

Expressions referring to directions include horizontal directions, vertical directions, and include a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction. These are referred to as a first horizontal direction (X-axis), a second horizontal direction (Y-axis), and a vertical direction (Z-axis) according to the Cartesian coordinate system, and the meaning of overlapping along the horizontal direction should also include the meaning of overlapping along the first horizontal direction and/or overlapping along the second horizontal direction.

Additionally, the statement that component A is exposed from component B should be understood to mean that component A is exposed from component B, not that component A is exposed from the entire product. That is, when it is stated that component A is exposed from component B, it should be understood to mean that component A is at least partially covered by component C.

Furthermore, when it is described that a component A is in “contact” with a component B, it may include not only cases where that component is in “contact” with the other component directly, but also cases where that component is “contacted” by another component between that component and the other component. Thus, if a component A is to be understood only as being in “direct contact” with a component B, it is described as being in “direct contact.”

In addition, when it is written that configuration A is ‘covered’ by configuration B, it should be understood that configuration A is covered by configuration B, and that the part for the function and purpose to be solved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

Before describing the embodiments, an electronic device to which the circuit board and semiconductor package of the embodiments are applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and/or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. The semiconductor package may include a circuit board and semiconductor elements, and the semiconductor elements may be mounted on the circuit board.

A semiconductor device may include active components and/or passive components. An active component may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of components are integrated into a single chip. A semiconductor chip may be a logic chip, a memory chip, or the like. A logic chip may be a non-memory chip such as a central processor (CPU), a graphics processor (GPU), or a field programmable gate array (FPGA). For example, a logic chip may be an application processor (AP) chip that includes at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chip set that includes a specific combination of the above-mentioned components.

The memory chip may be a stacked memory such as HBM. Additionally, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

Additionally, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the present invention is not limited thereto, and it is to be understood that the electronic device may be any other electronic device that processes data.

FIG. 1 is a plan view of a package according to an embodiment of the present invention, FIG. 2 is a perspective view of a package according to an embodiment of the present invention, and FIG. 3 is a view taken along line II’ in FIG. 1.

Referring to FIGS. 1 to 3, a package (or semiconductor package, 1000) according to an embodiment may include a package substrate (200) in addition to semiconductor elements (DI1, DI2) and a circuit board (100). For example, the package substrate (200) may be an FPGA substrate. In particular, the circuit board (100) according to the embodiment may be a substrate having a built-in connecting member.

The circuit board (100) of the embodiment may include a first semiconductor element (DI1), a second semiconductor element (DI2), and a connecting member (BR). Alternatively, the circuit board (100) may include the connecting member (BR). Furthermore, the first semiconductor element (DI1) and the second semiconductor element (DI2) may be mounted on the circuit board (100).

And the first semiconductor element (DI1) and the second semiconductor element (DI2) may include a logic chip or a memory chip as described above. And the first semiconductor element (DI1) and the second semiconductor element (DI2) may be different types of semiconductor elements as described above. And the connecting member (BR) may be embedded in the circuit board (100). In particular, the connecting member (BR) may be embedded in a cavity of the circuit board (100). The circuit board (100) may be applied with a circuit board described below.

Additionally, the connecting member (BR) may include an upper wiring (BE) that is in contact with an upper electrode portion located on the upper portion of the connecting member on the circuit board. Accordingly, the upper wiring (BE) may be electrically connected to the upper electrode portion. In addition, the upper wiring (BE) may be electrically connected to the first semiconductor element and the second semiconductor element on the upper portion through the upper electrode portion, thereby functioning as a bridge.

In addition, the circuit board may include a conductive member (SB) for connection between the first and second semiconductor elements and the electrode portions disposed on the upper portion of the circuit board (100), particularly on the upper build-up layer, which is the upper build-up layer. In addition, the circuit board may further include a conductive member (SB) disposed between a connection member (BR) other than the build-up layer and the first and second semiconductor elements. In addition, the connection member (BR) may electrically connect between at least two semiconductor elements. However, the following description will be given as performing an electrical connection between two semiconductor elements.

Additionally, an underfill (UF) may be positioned between the circuit board (100) and the first and second semiconductor elements (DI1, DI2). The underfill (UF) may cover the conductive member (SB).

And when the connecting member (BR) does not include a via electrode, the core via electrode located in the core layer of the circuit board (100) may not vertically overlap with the connecting member (BR). However, when the connecting member (BR) includes a via electrode, it may vertically overlap with the via electrode of the core layer of the circuit board (100) and be electrically connected.

Additionally, the via electrode of the build-up layer may overlap vertically with the connecting member (BR). Furthermore, the connecting member (BR) and the via electrode of the build-up layer may be electrically connected. Additionally, the connecting member (BR) may at least partially overlap vertically with the first and second semiconductor elements (DI1, DI2).

In addition, as described above, the connecting member (BR) may be an organic or inorganic connecting member. For example, the connecting member (BR) may be an inorganic connecting member, and when the connecting member (BR) includes a via electrode, it may be advantageous in transmitting power from the circuit board (100) to the first and second semiconductor elements (DI1, DI2).

Furthermore, the aforementioned package substrate (200) may be placed on the lower portion of the circuit substrate (100). The package substrate (200) and the circuit substrate (100) may be electrically connected to each other through a conductive member or the like.

For example, the package substrate (200) may be a FC-BGA (Flip-Chip Ball Grid Array). In addition, the package substrate (200) may be a multilayer structure (multilayer PCB).

And the circuit board (100) is positioned between the semiconductor element and the package board (200) as an interposer, and can transmit signals and power.

FIG. 4 is a cross-sectional view of a package according to a first embodiment of the present invention, FIG. 5 is an enlarged view of K1 in FIG. 4, FIG. 6 is an enlarged view of K2 in FIG. 4, FIG. 7 is a modified example of FIG. 6, and FIG. 8 is an enlarged view of K3 in FIG. 4.

Referring to FIG. 4, a package (1000) according to an embodiment may include a package substrate (200), a circuit substrate (100), and semiconductor elements (DI1, DI2). The package substrate (200), the circuit substrate (100), and the semiconductor elements (DI1, DI2) may be sequentially arranged in a stacking direction. Accordingly, the circuit substrate (100) may be positioned between the semiconductor elements (DI1, DI2) and the package substrate (200).

The package substrate (200) may include a package insulating layer (210) and a package electrode portion. The package insulating layer (210) may include a first core layer (211), an upper insulating layer (212), and a lower insulating layer (213). The upper insulating layer (212) may be positioned above the first core layer (211). The lower insulating layer (213) may be positioned below the first core layer (211).

The package electrode portion may include a first core electrode portion (221), a package upper electrode portion (222), and a package lower electrode portion (223).

The first core electrode portion (221) may include a first core wiring portion (221a) disposed on the first core layer (211) and a first core via electrode (221b) penetrating the first core layer (211). For example, the first core wiring portion (221a) may be disposed on one surface (upper surface and/or lower surface) of the first core layer (211).

The package upper electrode portion (222) may be disposed on the upper insulating layer (212). The package upper electrode portion (222) may include a package upper wiring portion disposed on the upper insulating layer (212) and a package upper via electrode penetrating the upper insulating layer (212).

Additionally, the package lower electrode portion (223) may be disposed on the lower insulating layer (213). The package lower electrode portion (223) may include a package lower wiring portion disposed on the lower insulating layer (213) and a package lower via electrode penetrating the lower insulating layer (213).

Additionally, the circuit board (100) may include an insulating layer (110), an electrode portion (120), and a connecting member (BR).

In an embodiment, the insulating layer (110) may be provided in a structure in which multiple insulating layers are laminated. The electrode portion (120) may be disposed by being embedded in each insulating layer of the multiple insulating layers (110), thereby performing the function of transmitting signals and/or power from a main board (not shown) to a semiconductor element.

Furthermore, when the circuit board includes a core layer, it may include a build-up insulating portion laminated on the core layer. Specifically, as illustrated, the circuit board (100) may include a second core layer (111), a build-up insulating portion (112, 113), a second core electrode portion (121), and a build-up electrode portion (122, 123). Furthermore, the circuit board (100) may further include a protective layer (SR) and a bump portion (BP). In addition, in the following embodiments of the present invention, the build-up insulating portion (112, 113) may include a plurality of insulating layers and may be provided in a structure in which a plurality of insulating layers are laminated. Furthermore, the structure of such an insulating layer may be applied to the package insulating layer of the package substrate described above. The build-up electrode portion (122, 123) may be disposed by being embedded in each layer (e.g., an insulating layer) of the build-up insulating portion (112, 113), thereby functioning to transmit signals and/or power from a main board (not illustrated) to a semiconductor element.

And the insulating layer (110) of the circuit board may include a second core layer (111), an upper build-up layer (112), and a lower build-up layer (113). The upper build-up layer (112) may be located on top of the second core layer (111). And the lower build-up layer (113) may be located on the bottom of the second core layer (111).

And the electrode section (120) can be composed of a via electrode and a wiring section as described later.

As an example, the insulation layer (110) may be formed of a second core layer (111) which is a core layer, and a build-up insulation portion (112, 113) which is formed of at least one insulation layer disposed above and below the second core layer (111). Accordingly, the build-up insulation portion (112, 113) laminated on the core layer may include a plurality of vertically laminated insulation layers. The build-up insulation portion may include an upper build-up layer (112) and a lower build-up layer (113). As illustrated, the upper build-up layer (112) may be disposed above the second core layer (111), and the lower build-up layer (113) may be disposed below the second core layer (111). The upper build-up layer and/or the lower build-up layer may each be formed by laminating a plurality of insulation layers. In addition, the build-up layer (or build-up insulation portion) may be referred to as a build-up structure or a build-up insulation portion, etc. The following description will be based on this.

As an example, the insulating layer (110) may include a second core layer (111), an upper build-up layer (112), and a lower build-up layer (113). In addition, a protective layer (SR) may be further disposed on the outer side of the insulating layer (110).

And the upper build-up layer (112) may be an 'upper build-up structure'. The lower build-up layer (113) may be a 'lower build-up structure'. In the present embodiment, the second core layer (111) may be arranged at the center in the vertical direction of the insulating layer (110). When the build-up layers are laminated on both sides of the second core layer (111), the second core layer (111) may be located at the center of the insulating layer (110). That is, the upper build-up layer (112) may be arranged on the second core layer (111), and the lower build-up layer (113) may be located below the second core layer (111).

And the insulating layer (110) of the circuit board (100) may be rigid or flexible. For example, the insulating layer (110) of the circuit board (100) may include glass or plastic. For example, the insulating layer (110) of the circuit board or each insulating layer constituting the insulating layer (110) may include chemically strengthened/semi-strengthened glass such as soda lime glass or aluminosilicate glass. For example, the insulating layer (110) of the circuit board may include a strengthened or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the insulating layer (110) of the circuit board may include sapphire. For example, the insulating layer (110) of the circuit board may include an optically isotropic film. For example, the insulating layer (110) of the circuit board may include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the insulating layer (110) of the circuit board may be formed of a material including a filler and an insulating resin. For example, the insulating layer (110) of the circuit board may have a structure in which a filler such as silica or alumina is disposed in a thermosetting resin or a thermoplastic resin.

The insulating layer (110) may have a structure in which a plurality of different insulating materials are laminated, and an exemplary arrangement structure will be described in more detail as follows.

In one embodiment, the insulating layer (110) may include a second core layer (111) including a reinforcing member. Here, the second core layer (111) may include the reinforcing member and have a thickness in a vertical direction (Y-axis direction or lamination direction) of several tens of micrometers to several hundreds of micrometers. In addition, the upper build-up layer (112) and the lower build-up layer (113) may be disposed on the upper and lower sides of the second core layer (111), respectively, and may include a plurality of layers that do not include the reinforcing member. The reinforcing member may also be referred to as a reinforcing fiber or glass fiber embedded in the core layer. The reinforcing member may refer to a glass fiber material extending along the horizontal direction (X-axis direction) of the insulating layer, and may have a different meaning from a filler that is spaced apart from each other. For example, the insulating layer (110) may be composed of a resin, a filler, and a reinforcing member (e.g., glass fiber), or may be composed of a resin and a filler.

The second core layer (111) may be made of various insulating materials. For example, the second core layer (111) may be a part of a copper clad laminate (CCL). Alternatively, the core layer may correspond to the copper clad laminate. In addition, the second core layer (111) may be made of a plurality of layers, and the plurality of layers may be made of the same or different materials. Furthermore, the second core layer (111) may include a via electrode penetrating the upper and lower surfaces of the second core layer (111).

And the upper build-up layer (112) or the lower build-up layer (113) can be provided with any insulating resin such as a thermosetting and/or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and a material such as prepreg (PPG) containing glass fiber can be used. As the photocurable resin, any insulating resin such as PID (Photo Imageable Dielectric) resin can be used. The above-mentioned arbitrary insulating resin may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and may include an inorganic filler such as silica. When the insulating resin is used as a core, it may include a reinforcing material or reinforcing member provided with glass fiber or aramid fiber. For example, when manufacturing an insulating layer (110), ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. can be used. For example, when the circuit board (100) is coreless, the insulating layer (110) can be provided by laminating ABF without a core layer.

Furthermore, the upper build-up layer (112) may be formed of a plurality of insulating layers that contact the second core layer (111). The plurality of insulating layers may be formed of fillers of different sizes. For example, the filler size may become smaller as it goes upward among the plurality of insulating layers. In addition, an upper electrode portion having a smaller width or pitch may be arranged as it goes upward among the plurality of insulating layers.

In addition, the wiring or electrode portion (120) according to the embodiment is arranged for electrical connection between a main board, etc. and a chip (or semiconductor element, die), and the electrode portion (120) includes a wiring portion (circuit pattern or circuit pattern layer, pad, pattern portion) and a via portion (or via electrode).

For example, the wiring portion of the electrode portion (120) may include a pattern and a pad on the upper surface of the insulating layer. Hereinafter, the wiring portion is described interchangeably with the terms 'circuit pattern' and 'pattern portion'. In addition, the electrode portion (120) may include a via portion or a via electrode penetrating the insulating layer. Accordingly, in the embodiment, the electrode portion (120) is described below as including a wiring portion (circuit pattern) and a via electrode in each insulating layer. In addition, the wiring portion in the electrode portion (120) may be designed in various forms for transmitting signals and/or power to and from the semiconductor element, and is arranged in each insulating layer of the laminated build-up insulating portions (112, 113).

In the electrode section (120), a via electrode (or via section) is arranged to penetrate at least a portion of each insulating layer for vertical connection between circuit patterns arranged on each insulating layer of the build-up insulating section (112, 113). The via electrode can connect a plurality of circuit patterns (wiring sections) to each other. The via electrode may also be formed in multiple pieces like the wiring section. That is, the insulating layer may include a via hole for arranging the via electrode. In addition, the via electrode may have a wider width than the circuit pattern for impedance optimization or heat dissipation, but is not limited thereto and may be freely designed.

In the electrode portion (120), a wiring portion (circuit pattern) may be arranged on each insulating layer. And the circuit pattern may be electrically connected to the circuit pattern. In addition, the wiring portion (circuit pattern) may be connected to each via electrode. And the circuit patterns arranged on the upper and lower surfaces of the insulating layer in the build-up insulating portion (112, 113) may be electrically connected to a semiconductor element and/or a main board or substrate, etc. For example, the electrode portion (120) may be located on each layer (insulating layer) of the second core layer (111), the upper build-up layer (112), and the lower build-up layer (113).

In an embodiment, the electrode portion (120) may include a second core electrode portion (121), an upper electrode portion (122), and a lower electrode portion (123). The upper electrode portion (122) and the lower electrode portion (123) may be build-up layer electrode portions. In addition, the upper electrode portion (122) is disposed in each insulating layer in the upper build-up layer (112) and may be an 'upper build-up layer electrode portion'. In addition, the lower electrode portion (123) is disposed in each insulating layer in the lower build-up layer (113) and may be a 'lower build-up wiring portion electrode'.

The second core electrode portion (121) may include a second core wiring portion (121a) arranged on the upper and lower surfaces of the second core layer (111) and a second core via electrode (121b) penetrating the second core layer (111).

The upper electrode portion (122) may include an upper wiring portion (122a), which is a wiring portion arranged on the upper and lower surfaces of each insulating layer of the upper build-up layer (112), and an upper via electrode (122b), which is a via electrode. The upper via electrode (122b) may penetrate each insulating layer of the upper build-up layer (112).

Furthermore, the lower electrode portion (123) may include a lower wiring portion (123a), which is a wiring portion arranged on the upper and lower surfaces of the lower build-up layer (113), and a lower via electrode (123b), which is a via electrode. In addition, the lower via electrode (123b) may penetrate each insulating layer of the lower build-up layer (113).

And in the embodiment, the wiring portion of the upper electrode portion (and/or the lower electrode portion) may include a wiring portion (first wiring portion) having a fine pitch and a wiring portion (second wiring portion) having a pitch larger than the first wiring portion.

The second wiring portion may refer to a wiring having the same width and spacing as a circuit pattern used in a conventional circuit board, and the first wiring portion may refer to a fine wiring having a width and spacing narrower than the width and spacing of a pattern used in a conventional circuit board for interconnection between semiconductor devices, impedance matching, or formation of an inductor. For example, the line width of the first wiring portion may be several micrometers (㎛) or less, or the pitch may be several tens of ㎛ or less. For example, the width of the first wiring portion may be 30 ㎛ or less. For example, the pitch of the first wiring portion may be 55 ㎛ or less. A detailed description thereof will be provided later.

Additionally, the circuit board (100) according to the first embodiment may further include a protective layer (SR) and a bump portion (BP).

Specifically, the protective layer (SR) can have the function of protecting the pad from external moisture or contaminants, and to prevent a short circuit problem when bonding between the semiconductor element and/or the main board and the circuit board, the protective layer (SR) can be provided with a solder resist, for example. Specifically, the semiconductor element and/or the main board, etc. have a plurality of terminals for connecting the circuit board. In addition, the plurality of terminals can be arranged at a high density. When the plurality of terminals and the pads of the circuit board are bonded, solder can be used, for example. When solder is used, a solder short circuit problem may occur between terminals having a high density, and thus, a solder resist that does not have good wettability with the solder can be arranged to solve this short circuit problem. In addition, the protective layer (SR) can be formed of a material having insulating properties for electrical connection. The protective layer (SR) can include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. Additionally, the protective layer (SR) may include any one of a photo solder resist layer, a cover-lay, and a polymer material. The protective layer (SR) may have at least one opening for connection between a terminal of a semiconductor device and a pad of a circuit board. For example, in an embodiment, the protective layer (SR) may be formed of a filler and a resin, which are reinforcing members.

A protective layer (SR) may be disposed on an insulating layer (110). The protective layer (SR) may include a plurality of fillers. Specifically, the protective layer (SR) may include a first protective layer (SR1) disposed on an upper build-up layer (112) and a second protective layer (SR2) disposed under a lower build-up layer (113). The first protective layer (SR1) and the second protective layer (SR2) may be disposed spaced apart from each other along a stacking direction and may have different thicknesses in consideration of warpage of the circuit board. Hereinafter, the protective layer will be described based on the first protective layer (SR1).

The bump portion (BP) may be disposed on the protective layer (SR). For example, the bump portion (BP) may be disposed on the upper surface of the protective layer (SR). The bump portion (BP) may be located outside the build-up electrode portions (122, 123). For example, in the upper build-up layer (112), the bump portion (BP) may be located on the upper surface of the build-up electrode portions (122, 123). In addition, the bump portion (BP) may include a protrusion portion (PP) disposed on the upper surface of the protective layer (SR) and a via portion (TP) penetrating the protective layer (SR). In an embodiment, the via portion (TP) and the protrusion portion (PP) may each include a plurality of protrusions or convex portions protruding toward the adjacent protective layer (SR). For example, on the first protective layer (SR1), the via portion (TP) and the protrusion portion (PP) may include a plurality of protrusions (or convex portions) protruding toward the first protective layer (SR1).

Furthermore, a metal layer may be additionally disposed on the bump portion (BP) and electrically connected. Accordingly, the durability and reliability of the bump portion (BP) may be further improved. For example, the metal layer may be formed of at least one metal layer. The metal layer may be formed of copper (Cu), gold (Au), nickel (Ni), palladium (Pd), tungsten (W), titanium (Ti), or a combination thereof. Accordingly, the bonding strength between the metal layer and the bump portion (BP) is improved, the corrosion resistance and durability of the bump portion (BP) are improved, and the loss of electrical signals may be minimized. The metal layer may be formed on the bump portion (BP) by deposition, electroplating, or the like of various metals.

In addition, a semiconductor element may be arranged on the upper build-up layer (112). The semiconductor element may be electrically connected to the first wiring portion, which is the aforementioned micro-pattern. The circuit board may be arranged to have a high wiring density for connecting the semiconductor element and signals. In addition, the first wiring portion, which is the micro-pattern, may provide a function of a line for signal connection between the semiconductor elements, or may perform signal connection (e.g., provision to the lower substrate) for each semiconductor element. Accordingly, it may be provided to prevent the semiconductor element from becoming unnecessarily large, thereby improving the yield of the semiconductor element.

In addition, circuit boards can be divided into package substrates and interposers according to their function. The package substrate functions to mount semiconductor devices and/or interposers. As data increases, the circuit board area increases or the number of laminated insulating layers increases, which can significantly reduce the yield of the circuit board. Therefore, in order to improve the yield of circuit boards with a high number of laminated layers, the yield of the circuit board can be improved by separating them into an interposer and a package substrate. In addition, as the terminal density of semiconductor devices increases, it may be difficult to implement pads on the package substrate with an area corresponding to the terminals of the semiconductor devices. Therefore, the interposer can act as a buffer between the pad size of the package substrate and the fine pattern size of the terminals of the semiconductor devices.

The package substrate and interposer described above can be classified into core substrates and coreless substrates, respectively, depending on the composition of the insulating layer. In the case of a core substrate, the insulating layer may include a core layer, and the core layer may refer to a layer among the laminated insulating layers that includes a reinforcing member. The reinforcing member may refer to glass fiber. The core layer may have the function of preventing warpage of the circuit board during the process by being arranged thicker than other insulating layers. However, the core layer may cause problems such as voltage drop and signal loss, or may be difficult to thin. Therefore, depending on the application, the insulating layer of the circuit board may use a coreless substrate that does not include a core layer.

In addition, in the embodiment, the second core layer (111) in the circuit board (100) may include a cavity (CV). That is, the circuit board (100) may include a second core layer (111) having a cavity (CV). The cavity (CV) may penetrate at least one of the upper build-up layer (112), the second core layer (111), and the lower build-up layer (113). In the embodiment, the cavity (CV) may be expressed in various ways, such as a ‘groove’, a ‘recess’, a hole, a ‘via’, etc. Furthermore, the cavity (CV) may have various shapes, such as a flat surface, a circle, a square shape, etc. Furthermore, the inner wall of the cavity (CV) or the inner side of the second core layer (111) may have a structure in which the width or diameter increases from the center or central portion toward the upper surface of the second core layer (111) and the width or diameter increases toward the lower surface of the second core layer (111). Alternatively, the inner wall of the cavity (CV) or the inner side of the second core layer (111) may have a structure in which the width or diameter increases from the center or central portion toward the upper surface of the second core layer (111), or only the width or diameter increases toward the lower surface of the second core layer (111).

The cavity (CV) may have various shapes depending on the shape of the component (e.g., connecting member) mounted therein. For example, the shape of the connecting member may generally be rectangular with respect to a plane perpendicular to the stacking direction. Correspondingly, the cavity (CV) may also have a rectangular shape with respect to a plane perpendicular to the stacking direction. However, for easy mounting of the connecting member (BR), it may have various shapes.

The circuit board (100) may include a connecting member (BR). The connecting member (BR) may be positioned within a cavity (CV). That is, a mounting space for the connecting member (BR) and the like can be easily secured in the upper build-up layer (112) through the cavity (CV). In addition, a lower electrode portion (123) having a smaller line width than the upper electrode portion (122) outside the cavity (CV) can be easily arranged on the upper portion of the cavity (CV). Accordingly, the circuit board according to the embodiment can provide easy connection between semiconductor elements and an improved input/output (I/O) count.

According to an embodiment, the connecting member (BR) may be embedded in the cavity (CV) of the second core layer (111). That is, according to an embodiment, the second core layer (111) may be provided to prevent warpage while the circuit board (100) is thinned, and at this time, the connecting member (BR) may be embedded in the second core layer (111). In addition, as described above, since the connecting member (BR) is arranged in the second core layer (111), the reliability of the circuit board is maintained by the mounting of the connecting member, and various connecting members (BR) can be mounted.

Additionally, the connecting member (BR) may be positioned within the second core layer (111) of the circuit board (100) and may overlap with the second core layer (111) in the horizontal direction (X-axis direction). For example, the connecting member (BR) may not be positioned in the upper build-up layer (112) or the lower build-up layer (113) of the circuit board (100).

In addition, when the connecting member (BR) is embedded in at least a portion of the upper build-up layer (112), the connecting member (BR) can be mounted within a limited height within the upper build-up layer (112). Furthermore, when the length (thickness) of the connecting member (BR) increases in the stacking direction, problems such as peeling or cracking occurring at the boundary surface between the plurality of insulating layers may exist as cavities are formed in the upper build-up layer (112), which is a plurality of insulating layers. Therefore, by mounting the connecting member (BR) as much as possible within the second core layer (111) as in the embodiment, the connecting member (BR) can be easily mounted regardless of whether the size of the connecting member (BR) is large or small, and since a via penetrating the boundary surface of the plurality of insulating layers for mounting the connecting member is not formed, the reliability of the circuit board can be improved.

Since the circuit board (100) according to the embodiment can be used as an interposer, thinning is required, so that a connecting member (BR) can be embedded in the second core layer (111).

In addition, the upper build-up layer (112) may be disposed on the second core layer (111), and a portion thereof may be disposed within the cavity (CV) of the second core layer (111). Accordingly, a portion of the lower surface of the upper build-up layer (112) may be in contact with the upper surface of the lower build-up layer (113), and may form the same surface. This may be implemented within the cavity (CV).

Referring further to FIGS. 5 and 6, in an embodiment, the thickness (ta) of the package substrate (200) may be different from the thickness (tb) of the circuit substrate (100). For example, the thickness (ta) of the package substrate (200) may be greater than the thickness (tb) of the circuit substrate (100).

Additionally, the thickness (t1) of the first core layer (211) of the package substrate (200) may be different from the thickness (t2) of the second core layer (111) of the circuit substrate (100). For example, the thickness (t1) of the first core layer (211) of the package substrate (200) may be greater than the thickness (t2) of the second core layer (111) of the circuit substrate (100).

This configuration can enhance the mechanical strength and stability of the overall structure of the semiconductor package. Furthermore, the semiconductor device can be mounted on the circuit board, facilitating efficient electrical connection. Furthermore, heat dissipation can be efficiently achieved within the semiconductor package, with the relatively thick package substrate, and structural support can be improved.

As described above, the cavity (CV) may penetrate at least a portion of the circuit board (100). For example, the cavity (CV) may penetrate the second core layer (111). A connecting member (BR) may be positioned within the cavity (CV).

In this way, when cavities are designed to penetrate multiple layers, electrical connection paths in multilayer structures can be shortened, improving signal transmission speed. Specifically, by placing connecting elements within the cavities, space utilization within the circuit board can be improved, and the connecting elements can efficiently implement electrical connections between upper (or lower) layers. This can increase circuit density and enhance design flexibility.

Furthermore, in the embodiment, the connecting member (BR) may overlap the second core layer (111) in a horizontal direction. According to various examples, at least a portion of the connecting member (BR) may be positioned above the upper surface of the second core layer (111), or at least a portion of the connecting member (BR) may be positioned below the lower surface of the second core layer (111).

Additionally, the first core layer (211) may include a first through hole (211h). And the second core layer (111) may include a second through hole (211h). Accordingly, by forming through holes in the first and second core layers, interlayer electrical connections (vias) may be implemented.

In an embodiment, the first through hole (211h) and the second through hole (111h) may have different shapes. The width (Wa) of the first through hole (211h) may be the same on the upper surface, lower surface, and center of the first core layer (211).

In contrast, the width (Wb) of the second through hole (111h) may decrease toward the center of the second core layer (111) or the second through hole (111h).

With this configuration, the first core electrode portion of the first through-hole (211h) has a constant impedance, facilitating high-speed signal transmission. Furthermore, the second through-hole (111h) has a wider connection area on both sides, reducing reliability issues such as solder cracks and interface delamination. In other words, mechanical fixation and heat/stress dissipation effects can be improved.

In particular, a first core via electrode (221b) may be positioned in a first through hole (211h). And a second core via electrode (121b) may be positioned in a second through hole (111h).

The first core via electrode (211b) is positioned along the inner surface of the first through hole (211h), and the first core via electrode (211b) may not completely fill the inside of the first through hole (211h). That is, an empty space (VC) may be formed inside the first through hole (211h).

And since the width (Wa) of the first core via electrode (221b) is maintained thin, the stress relief effect can be improved. The second core via electrode (121b) can be fully filled within the second through hole (211h), so that the thermal and electrical characteristics can be significantly improved.

Furthermore, the outer surface (ES) of the connecting member (BR) may face the first surface (S1), which is the inner surface of the cavity (CV) in the second core layer (111). The first surface (S1) may protrude from the center toward the outer surface of the connecting member (BR) in the stacking direction or the vertical direction (Y-axis direction).

In other words, the gap between the first surface (S1) and the connecting member (BR) may be smallest at the center of the cavity along the stacking direction (Y-axis direction). In addition, the gap between the first surface (S1) and the connecting member (BR) may increase from the center toward the upper or lower surface of the cavity (CV).

For example, when the first surface (S1) of the cavity (CV) and the outer surface (ES) of the connecting member (BR) are adjacent or in contact, the connecting member (BR) can be easily aligned within the cavity (CV). Furthermore, the connecting member (BR) can be easily mounted within the cavity (CV).

In addition, due to the shape of the first surface of the cavity (CV), stresses due to external forces or thermal expansion may not be concentrated at one point depending on the mounting of connecting members (BR), etc. Accordingly, the stress flow may be smoothly continued, effectively reducing the possibility of cracks or peeling occurring at a specific location. In other words, the stress is not concentrated in the center, but is distributed and transmitted along the first surface of the cavity, thereby improving the durability of the circuit board and semiconductor package against thermal expansion or mechanical shock.

Additionally, the thickness (t2) of the second core layer (111) and the thickness (t3) of the connecting member (BR) may be the same or different. In an embodiment, the thickness (t2) of the second core layer (111) may be greater than the thickness (t3) of the connecting member (BR).

And the upper surface of the second core wiring portion (121a) can be flush with the upper surface of the upper wiring (BE) disposed on the upper surface of the upper wiring (BE). In this way, the thickness (tc) of the second core wiring portion (121a) can be formed corresponding to the thickness (td) of the upper wiring (BE) disposed on the upper surface of the upper wiring (BE).

This configuration simplifies the electrical connection between the upper wiring and the second core wiring, optimizing the signal transmission path and reducing electrical loss. Furthermore, it facilitates the planarization (CMP, Chemical Mechanical Polishing) process during the manufacturing process, such as the formation of the upper build-up layer, thereby increasing production efficiency and potentially contributing to a reduction in the thickness of the overall circuit board. Furthermore, by minimizing the height difference between wiring layers, signal delays and impedance mismatches can be prevented, thereby improving the performance of high-speed signal transmission.

Referring further to FIG. 7, the upper surface of the second core layer (111) may or may not have the same surface as the upper surface of the connecting member (BR). For example, the upper surface of the second core layer (111) may have the same height from the lower surface of the second core layer (111) as the upper surface of the connecting member (BR).

Additionally, the upper surface of the second core layer (111) may be positioned lower than the upper surface of the connecting member (BR). Additionally, the upper surface of the second core layer (111) may be positioned higher than the upper surface of the connecting member (BR).

In addition, the height from the upper surface of the second core layer (111) to the upper surface of the second core wiring portion (121a) and the height from the upper surface of the second core layer (111) to the upper surface of the upper wiring (BE) may be different from or the same as each other. For example, the height from the upper surface of the second core layer (111) to the upper surface of the second core wiring portion (121a) and the height from the upper surface of the second core layer (111) to the upper surface of the upper wiring (BE) may correspond to each other through the manufacturing method. The height from the upper surface of the second core layer (111) to the upper surface of the second core wiring portion (121a) may be greater than the height from the upper surface of the second core layer (111) to the upper surface of the upper wiring (BE).

In this way, the thickness and height of the upper wiring (BE) and the like can be adjusted in response to the second core wiring portion (121a) depending on the thickness of the connecting member (BR). As a result, the mounting of the connecting member within the second core layer (111) can be implemented more easily.

Referring further to Fig. 8, the bump portion (BP) may be formed of a protrusion (PP) positioned on the upper surface of the protective layer (SR) and a via portion (TP) penetrating the protective layer (SR). Furthermore, the bump portion (BP) may include a first layer (L1) and a second layer (L2).

The first layer (L1) may be positioned below the second layer (L2). Furthermore, the first layer (L1) may protrude at least partially above the upper surface of the protective layer (SR). Accordingly, at least a portion of the first layer (L1) may not horizontally overlap the protective layer (SR).

Furthermore, the edge of the first layer (L1) may include a groove formed downward. Now, the second layer (L2) may extend downward along the edge of the first layer (L1). The second layer (L2) may include a first region (AR1) and a second region (AR2). The first region (AR1) may overlap the protective layer (SR) in a horizontal direction. In addition, the first region (AR1) may be located below the upper surface of the first protective layer (SR1).

And the second region (AR2) may not overlap horizontally with the first protective layer (SR1). The second region (AR2) may be located on the upper surface of the first protective layer (SR1).

The first region (AR1) may be a groove structure extending downward along the edge of the first layer (L1). The second region (AR2) may extend upward, corresponding to a region extending horizontally toward the center or upward of the first layer (L1). The second layer (L2) may have a larger width in the horizontal direction than the first layer (L1).

Furthermore, the first layer (L1) may include a third region (AR3) that horizontally overlaps the first protective layer (SR1) and a fourth region (AR4) on the upper surface of the first protective layer (SR1). The fourth region (AR4) may be surrounded by the second region (AR2). And the first region (AR1) may be located at the edge of the third region (AR3).

And the first layer (L1) and the second layer (L2) can be made of different materials. For example, the first layer (L1) can include copper (Cu), and the second layer (L2) can include nickel (Ni).

In addition, the first layer (L1) may be positioned in the through hole of the first protective layer (SR1). The inner wall of the through hole in the first protective layer (SR1) may be in contact with the first layer (L1) and the second layer (L2). At this time, the thickness (d4) at which the first layer (L1) and the inner wall of the through hole are in contact may be different from the thickness (d3) at which the second layer (L2) and the inner wall of the through hole are in contact. For example, the thickness (d4) at which the first layer (L1) and the inner wall of the through hole are in contact may be smaller than the thickness (d3) at which the second layer (L2) and the inner wall of the through hole are in contact. The ratio between the thickness (d4) at which the first layer (L1) and the inner wall of the through hole are in contact and the thickness (d3) at which the second layer (L2) and the inner wall of the through hole are in contact may be 0.6:1 to 0.95:1. At this time, if the second layer (L2) is outside the above range of the inner wall of the through hole, there is a risk of cracks or breakage at the connection between the bump and the die due to the brittleness of nickel, and the thermal conductivity is lower than that of copper, so the adaptability to thermal changes may be low.

Furthermore, due to the aforementioned characteristics, nickel is harder and more durable than copper, providing circuit boards with greater resistance to mechanical stress and impact. Furthermore, nickel is more resistant to oxidation than copper, facilitating long-term use of bumps adjacent to the exterior. This translates to improved reliability.

FIGS. 9 to 15 are drawings explaining a method for manufacturing a circuit board and a package according to an embodiment of the present invention.

It should be noted that one or more steps may be combined to simplify and/or clarify the steps for providing or manufacturing a circuit board. In some implementations, the order of the processes may be changed or modified. Furthermore, in some implementations, one or more of the manufacturing methods may be replaced or substituted without departing from the spirit of the present disclosure. Different implementations may manufacture the board differently.

Referring to Fig. 9, a second core layer (111) can be provided. The second core layer (111) may be an insulating layer having a predetermined thickness or greater as described above. In addition, the second core layer (111) may include glass or glass fiber having a resin. However, the second core layer (111) may also include different materials.

Referring to Fig. 10, a via hole or through hole (111h) can be formed in the second core layer (111). The through hole can be formed through the upper and lower surfaces of the second core layer (111). The through hole or via hole can be formed by a method such as laser drilling.

Referring to Fig. 10, a second core electrode portion (121) can be formed on a second core layer (111). The electrode portion can be formed by a patterning process based on mask formation (exposure, curing, etc.), a stripping process, and/or a plating process.

For example, a plating process may be performed on a via hole formed in the second core layer (111) to form a through electrode. In addition, a core wiring portion may be formed on the upper and lower surfaces of the second core layer (111). The core wiring portion may have a pattern using a mask or the like. Furthermore, the core wiring portion may be formed using an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP), which are manufacturing processes for printed circuit boards. This may be equally applied to other wiring portions.

Referring to Fig. 11, a cavity (CV) can be formed in a region of the second core layer (111) by various methods, such as a laser method. The cavity (CV) can penetrate the second core layer (111). The cavity (CV) can penetrate up to a part of the second core layer (111). That is, the cavity (CV) can be a hole or a groove.

Referring further to Fig. 12, a connecting member (BR) can be mounted in a cavity (CV) of a second core layer (111). When a cavity (CV), which is a through hole, is formed in the second core layer (111), the connecting member (BR) can be mounted in the cavity (CV) through a stopper portion (not shown).

And the position of the connecting member (BR) can be easily adjusted by a stopper (not shown) or the like. For example, a mark (e.g., an alignment mark) for aligning the connecting member (BR) can be formed on the stopper (not shown). By this configuration, the connecting member (BR) can be positioned at a more accurate position according to the design within the cavity (CV). For example, the position of the connecting member (BR) can be adjusted so that the center of the connecting member (BR) is in the center of the cavity (CV).

Referring to FIG. 13, an upper build-up layer (112) can be formed above the second core layer (111) and within the cavity (CV). Additionally, a lower build-up layer (113) can be formed below the second core layer (111).

Additionally, before forming the upper build-up layer (112), underfilling may be performed to fix the position of the connecting member (BR) in the cavity (CV). For example, a filling material may be further applied within the cavity (CV). Accordingly, the filling material may improve the bonding strength between the second core layer (111) and the connecting member (BR). As a result, the circuit board may be protected from impact, dropping, and vibration. In addition, deformation due to differences in thermal expansion between other components, such as the connecting member (BR) and the second core layer (111), may be reduced. This filling material (F1) may include epoxy, etc.

Additionally, as described above, the upper build-up layer (112) can be applied within the cavity (CV). Accordingly, the upper build-up layer (112) is placed within the cavity (CV) so that the connecting member (BR) can be mounted within the cavity (CV).

Referring to FIG. 14, a via hole or through hole may be formed in the upper build-up layer (112) and/or the lower build-up layer (113). The via hole may be formed by a laser drilling method, a punching method, an etching method (mechanical drilling, chemical etching, or any suitable mechanism), etc.

Additionally, an upper electrode portion (122) may be formed on the upper build-up layer (112). And a lower electrode portion (123) may be formed on the lower build-up layer (113). The upper electrode portion (122) and the lower electrode portion (123) may be formed by a patterning process based on mask formation (exposure, curing, etc.), a stripping process, and/or a plating process.

And the upper wiring part of the upper electrode part (122) may be formed on the upper surface of the upper build-up layer (112), and the lower wiring part of the lower electrode part (123) may be formed on the lower surface of the lower build-up layer (113). Each wiring part may have a pattern by a mask or the like. Furthermore, the wiring part may be formed by an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP), which are manufacturing processes of a printed circuit board.

Thereafter, a first protective layer (SR1) may be formed on the upper build-up layer (112). A second protective layer (SR2) may be formed under the lower build-up layer (113). Furthermore, a via (TP) penetrating the protective layer (SR) may be formed.

Referring to FIG. 15, when a circuit board (100) is formed as described above, a package board (200) may be placed underneath and semiconductor elements (DI1, DI2) may be mounted on top. For example, after the semiconductor elements (DI1, DI2) are mounted on the circuit board (100), the circuit board (100) on which the semiconductor elements (DI1, DI2) are mounted may be mounted on the package board (200).

Specifically, individual semiconductor devices (dies) can be diced from a wafer. At this time, dicing can be implemented using a laser or a dicing blade.

And semiconductor elements can be mounted on the interposer. The semiconductor elements (DI1, DI2) can be accurately positioned on the circuit board (100). And the semiconductor elements (DI1, DI2) can be fixed to the circuit board (100) using various bonding materials.

And the semiconductor elements (DI1, DI2) and the circuit board (100) as an interposer can be attached to the package board (200). Afterwards, molding, etc. can be additionally performed.

Furthermore, reflow, etc., can be performed on the circuit board (100) and package board (200) of the semiconductor device (DI1, DI2). In addition, electrical performance tests can be performed on the manufactured semiconductor package. Additionally, appearance inspection and mechanical inspection can also be performed simultaneously.

Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

Although the above description focuses on examples, these are merely examples and are not intended to limit the examples. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present examples. For example, each component specifically shown in the examples can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims (10)

A package substrate comprising a first core layer; A circuit board disposed on the package substrate including a second core layer; and A semiconductor device mounted on the circuit board; The thickness of the above package substrate is greater than the thickness of the above circuit substrate, A circuit board wherein the thickness of the first core layer is greater than the thickness of the second core layer. In the first paragraph, The above circuit board, An upper build-up layer disposed on the second core layer; A lower build-up layer disposed below the second core layer; and A circuit board comprising a connecting member arranged in an internal cavity. In the second paragraph, A circuit board wherein the cavity penetrates at least one of the upper build-up layer, the core layer, and the lower build-up layer. In the second paragraph, A circuit board in which the above connecting member overlaps the second core layer in a horizontal direction. In the second paragraph, The first core layer includes a first through hole; A circuit board wherein the second core layer includes a second through hole. In paragraph 5, The width of the first through hole is the same on the upper surface, lower surface and center, A circuit board in which the width of the second through hole decreases toward the center of the second through hole. In the second paragraph, A circuit board in which the outer surface of the above connecting member faces the first surface of the cavity in the second core layer. In paragraph 7, The above first surface is a circuit board that protrudes from the center toward the outer surface of the connecting member in the stacking direction. In paragraph 7, The circuit board having the smallest gap between the first surface and the connecting member at the center. In the second paragraph, The package substrate includes a first core electrode portion including a first core via electrode penetrating the first core layer and a first core wiring portion disposed on the first core layer, The circuit board includes a second core electrode portion including a second core via electrode penetrating a second core layer and a second core wiring portion disposed on the second core layer.