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WO2025204321A1 - Dispositif d'imagerie, procédé de commande de dispositif d'imagerie et programme de commande de dispositif d'imagerie - Google Patents

Dispositif d'imagerie, procédé de commande de dispositif d'imagerie et programme de commande de dispositif d'imagerie

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Publication number
WO2025204321A1
WO2025204321A1 PCT/JP2025/005743 JP2025005743W WO2025204321A1 WO 2025204321 A1 WO2025204321 A1 WO 2025204321A1 JP 2025005743 W JP2025005743 W JP 2025005743W WO 2025204321 A1 WO2025204321 A1 WO 2025204321A1
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WO
WIPO (PCT)
Prior art keywords
row
pixel
pixel row
error
reference signal
Prior art date
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Pending
Application number
PCT/JP2025/005743
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English (en)
Japanese (ja)
Inventor
真実 青木
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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Filing date
Publication date
Application filed by Sony Semiconductor Solutions Corp filed Critical Sony Semiconductor Solutions Corp
Publication of WO2025204321A1 publication Critical patent/WO2025204321A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/68—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to defects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/779—Circuitry for scanning or addressing the pixel array

Definitions

  • This technology relates to an imaging device equipped with a CMOS (Complementary Metal Oxide Semiconductor) image sensor, an imaging device control method, and an imaging device control program.
  • CMOS Complementary Metal Oxide Semiconductor
  • the row scanning unit outputs pixel control signals such as reset, accumulation, and transfer for the intended pixels in the pixel array, and selects the address of the row to be read out.
  • the pixel signals output from the pixel array are then converted into digital data by a column-parallel analog-to-digital converter. For this reason, if an accidental failure occurs in the row scanning unit or the pixel control signal wiring output from the row scanning unit, incorrect pixel control or incorrect readout row selection will occur, causing abnormalities in the image data captured by the image sensor.
  • the ability to detect whether the image sensor has performed pixel control and readout row selection as intended is particularly useful for camera systems equipped with image sensors.
  • row-specific binary data is created by combining two potentials input to a reference pixel from outside the pixel array for each row, and fault detection is performed by comparing this reference pixel digital data with an expected value.
  • This technology can detect faults in the row scanning unit and the pixel control signal wiring output from the row scanning unit.
  • Patent Document 2 which is similar to Patent Document 1 in that reference pixels are given row-specific binary data and fault detection is performed by comparing the digital data of the reference pixels with an expected value, discloses technology in which the presence or absence of a fault in the reference pixel is stored in advance in memory within the image sensor or input from outside the image sensor.
  • the objective of this technology is to provide an imaging device, an imaging device control method, and an imaging device control program that are highly efficient and capable of accurate fault detection.
  • an imaging device includes a plurality of pixel rows, an error detection unit, and a failure determination unit.
  • the plurality of pixel rows form a pixel array in which pixels made of CMOS (Complementary Metal Oxide Semiconductor) are arranged, and each pixel row is configured by connecting, via wiring, imaging pixels that output pixel signals corresponding to incident light, row-specific value reference pixels that output row-specific reference signals, and correction code reference pixels that output error correction codes for the reference signals.
  • CMOS Complementary Metal Oxide Semiconductor
  • the error detection unit detects an error in the reference signal based on a reference signal output from a row-specific value reference pixel constituting a specific pixel row among the plurality of pixel rows and an error correction code output from a correction code reference pixel constituting the pixel row.
  • the failure determination unit determines whether or not there is a failure in the pixel row based on the reference signal and the detection result by the error detection unit.
  • the error detection unit may supply the reference signal to the fault detection and determination unit as a reference signal for the pixel row, and if it detects an error in the reference signal output from the row-specific value reference pixels that make up the pixel row, it may supply a reference signal obtained by correcting the reference signal to the fault determination unit as a reference signal for the pixel row.
  • the fault determination unit may compare the reference signal supplied from the error detection unit with an expected value set for the pixel row, and if the reference signal and the expected value do not match, determine that there is a fault in the pixel row.
  • the failure determination unit may notify that there is an abnormality in the captured image generated based on the output of the imaging pixel.
  • the fault determination unit may not need to determine whether or not there is a fault in the pixel row.
  • the error detection unit may detect an error in the reference signal output from the row-specific value reference pixels that make up the pixel row, and if the reference signal cannot be corrected, may notify that an abnormality exists in the captured image generated based on the output of the imaging pixels.
  • the plurality of pixel rows include a first pixel row and a second pixel row that are simultaneously read out and have the same reference signal and the same error correction code;
  • the error detection unit detects an error in the first reference signal based on a first reference signal output from row-specific value reference pixels constituting the first pixel row and a first error correction code output from correction code reference pixels constituting the first pixel row, and when an error is detected from the first reference signal, detects an error in the second reference signal based on a second reference signal output from row-specific value reference pixels constituting the second pixel row and a second error correction code output from correction code reference pixels constituting the second pixel row;
  • the failure determination section may determine the presence or absence of a failure in the first pixel row and the second pixel row based on the first reference signal, the second reference signal, and a detection result by the error detection section.
  • the error detection unit may supply the first reference signal to the fault determination unit as a reference signal for the first pixel row and the second pixel row; if the error detection unit detects an error in the first reference signal output from the row-specific value reference pixels that make up the first pixel row and does not detect an error in the second reference signal output from the row-specific value reference pixels that make up the second pixel row, it may supply the second reference signal to the fault determination unit as a reference signal for the first pixel row and the second pixel row.
  • the fault determination unit may compare the reference signal supplied from the error detection unit with expected values set for the first pixel row and the second pixel row, and if the reference signal and the expected value do not match, determine that there is a fault in the first pixel row and the second pixel row.
  • the failure determination unit determines that there is a failure in the first pixel row and the second pixel row, it may notify that there is an abnormality in the captured image generated based on the output of the imaging pixels.
  • the failure determination unit may not need to determine whether or not there is a failure in the first pixel row and the second pixel row.
  • the error correction unit may notify that an abnormality exists in the captured image generated based on the output of the imaging pixels.
  • an imaging device control program causes an information processing device to operate as an error detection unit and a failure determination unit.
  • the error detection unit forms a pixel array in which pixels made of CMOS (Complementary Metal Oxide Semiconductor) are arranged, and detects an error in the reference signal based on the reference signal output from the row-specific value reference pixels constituting a specific pixel row and the error correction code output from the correction code reference pixels constituting the pixel row, among a plurality of pixel rows in which each pixel row is configured by connecting by wiring imaging pixels that output pixel signals corresponding to incident light, row-specific value reference pixels that output row-specific reference signals, and correction code reference pixels that output error correction codes for the reference signals.
  • the failure determination unit determines whether or not there is a failure in the pixel row based on the reference signal and the detection result by the error detection unit.
  • an imaging device control method includes:
  • the error detection unit forms a pixel array in which pixels made of CMOS (Complementary Metal Oxide Semiconductor) are arranged, and each pixel row is formed by connecting, via wiring, imaging pixels that output pixel signals corresponding to incident light, row-specific value reference pixels that output row-specific reference signals, and correction code reference pixels that output error correction codes for the reference signals, and detects an error in the reference signal based on the reference signal output from the row-specific value reference pixels that constitute a specific pixel row and the error correction code output from the correction code reference pixels that constitute the pixel row.
  • a failure determination unit determines whether or not there is a failure in the pixel row based on the reference signal and the detection result by the error detection unit.
  • FIG. 1 is a schematic diagram of an imaging device according to a first embodiment of the present technology
  • 4 is a flowchart showing the operation of the imaging device.
  • 3A and 3B are schematic diagrams illustrating reference signals output by row eigenvalue reference pixels of the imaging device.
  • FIG. 1 is a schematic diagram of a pixel array in a conventional imaging device.
  • FIG. 10 is a schematic diagram of an imaging device according to a second embodiment of the present technology.
  • 4 is a flowchart showing the operation of the imaging device.
  • FIG. 1 is a block diagram showing a hardware configuration of an information processing device capable of realizing the functional configuration of an imaging device according to a first embodiment and a second embodiment of the present technology.
  • Fig. 1 is a block diagram of an image pickup device 100 according to the first embodiment.
  • Fig. 2 is a flowchart showing the operation of the image pickup device 100.
  • the image pickup device 100 includes a pixel array 101, an A/D converter array 102, a row scanning unit 103, a control unit 104, a signal processing unit 105, a voltage supply unit 106, a ramp signal supply unit 107, an error detection unit 108, and a failure determination unit 109.
  • the pixel array 101 is an array in which pixels made of CMOS (Complementary Metal Oxide Semiconductor) are arranged. Specifically, the pixel array 101 includes imaging pixels 121, row-specific value reference pixels 122, and correction code reference pixels 123. In Figure 1, the row-specific value reference pixels 122 are indicated by hatching with diagonal lines, and the correction code reference pixels 123 are indicated by hatching with dots.
  • CMOS Complementary Metal Oxide Semiconductor
  • the pixel array 101 is composed of rows and columns of pixels.
  • Figure 1 shows pixel rows R and pixel columns L made up of pixels.
  • the pixel array 101 is composed of multiple pixel rows R and multiple pixel columns L.
  • Each pixel row R is composed of one or more imaging pixels 121, row-specific value reference pixels 122, and correction code reference pixels 123.
  • the pixels that make up each pixel row R are connected to each other by row wiring 131, and the pixels that make up each pixel column L are connected to each other by column wiring 132.
  • the imaging pixels 121 photoelectrically convert incident light and accumulate electric charges.
  • the imaging pixels 121 output a pixel signal corresponding to the amount of accumulated electric charge to the column wiring 132.
  • the row-specific value reference pixels 122 output row-specific reference signals.
  • the row-specific value reference pixels 122 are supplied with a fixed voltage V0 or V1 from the voltage supply unit 106 and receive a row selection signal from the row wiring 131, the row-specific value reference pixels 122 output a reference signal in accordance with either the fixed voltage V0 or V1 .
  • the reference signal output from the row-specific value reference pixels 122 supplied with the fixed voltage V0 is defined as "0”
  • the reference signal output from the row-specific value reference pixels 122 supplied with the fixed voltage V1 is defined as "1.”
  • Figure 1 shows only one row-specific value reference pixel 122 for each pixel row R, in reality, a number of pixels are arranged that are sufficient to generate a unique reference signal for each pixel row R.
  • Figure 3 is a schematic diagram showing a unique reference signal for each pixel row R. As shown in the figure, if there are four pixel rows R, using two row-specific value reference pixels 122 generates four different reference signals: "00", "01", "10", and "11".
  • each pixel row R with two row-specific value reference pixels 122, a reference signal specific to each pixel row R is generated. For example, if the number of pixel rows R is 1536, 2 ⁇ 10 ⁇ 1536 ⁇ 2 , and therefore, by configuring each pixel row R with 11 row-specific value reference pixels 122, a reference signal specific to each pixel row R can be generated.
  • the correction code reference pixels 123 output an error correction code for the reference signal output by the row-specific value reference pixels 122.
  • error correction code There are no particular limitations on the type of error correction code, and it can be a parity code, checksum, cyclic redundancy check (CRC), Hamming code, or the like.
  • CRC cyclic redundancy check
  • a number of correction code reference pixels 123 are arranged that are sufficient to generate an error correction code for the reference signal of each pixel row R. For example, if each pixel row R contains 11 row-specific value reference pixels 122 and the error correction code type is CRC-4, an error correction code can be generated by setting the number of correction code reference pixels 123 that make up each pixel row R to five.
  • the A/D converter array 102 is an array of A/D converters 141.
  • Each A/D converter 141 is connected to a column wiring 132 and converts the analog signals input from the column wiring 132, specifically the pixel signals, reference signals, and error correction codes, into digital signals.
  • the row scanning unit 103 selects a pixel row R from which to read out a signal.
  • the row scanning unit 103 applies a voltage to the row wiring 131 of the pixel row R to be read out, signals are output from the imaging pixels 121, row-specific value reference pixels 122, and correction code reference pixels 123 connected to this row wiring 131 to the column wiring 132 connected to each, and are read out.
  • the row scanning unit 103 sequentially selects pixel rows R to be read out.
  • the control unit 104 is connected to and controls the row scanning unit 103 and A/D converter 141.
  • the signal processing unit 105 is connected to the imaging pixels 121 and A/D converter 141 via the column wiring 132, and generates image data based on the pixel signals output from the imaging pixels 121.
  • the voltage supply unit 106 supplies a reference potential for generating a reference signal and an error correction code to the row-specific value reference pixels 122 and the correction code reference pixels 123.
  • the ramp signal supply unit 107 supplies a ramp signal for A/D conversion to the A/D converter 141.
  • the error detection unit 108 detects an error in the reference signal based on the reference signal output from the row-specific value reference pixels 122 that make up a specific pixel row R and the error correction code output from the correction code reference pixels 123 that make up that pixel row R. Specifically, the error detection unit 108 reads out the reference signal output from the row-specific value reference pixels 122 that make up the pixel row R selected by the row scanning unit 103 (Step 101, see Figure 2).
  • the error detection unit 108 performs an error detection process using the error correction code output from the correction code reference pixels 123 that make up the pixel row R, and detects an error in the reference signal output from the row-specific value reference pixels 122 (St102).
  • the error in the reference signal is due to a failure in the row-specific value reference pixels 122.
  • the error detection unit 108 If the error detection unit 108 does not detect an error in the reference signal output from the row-specific value reference pixels 122 that make up the pixel row R (St103; No), it supplies this reference signal to the fault determination unit 109 as the reference signal for the pixel row R. On the other hand, if the error detection unit 108 detects an error in the reference signal output from the row-specific value reference pixels 122 that make up the pixel row R (St103; Yes), it corrects this reference signal through error correction processing using an error correction code.
  • the error detection unit 108 can correct the reference signal (St104; Yes), it corrects the reference signal (St105) and supplies the corrected reference signal to the fault determination unit 109 as the reference signal for the pixel row R. If the error detection unit 108 cannot correct the reference signal (St104; No), it notifies the outside, for example, the device in which the imaging device 100 is installed, that there is an abnormality in the captured image generated based on the output of the imaging pixels 121 (St106), and ends imaging.
  • the fault determination unit 109 determines whether or not a fault exists in pixel row R based on the reference signal and the determination result by the error detection unit 108. Specifically, if the error detection unit 108 detects no error in the reference signal output from the row-specific value reference pixels 122 that make up pixel row R (St103; No), the fault determination unit 109 compares the reference signal supplied from the error detection unit 108 with an expected value that is set in advance for that pixel row R (St107). If the two match (St108; Yes), the fault determination unit 109 determines that no fault has occurred in that pixel row R. On the other hand, if the two do not match (St108; No), the fault determination unit 109 determines that a fault has occurred in that pixel row R.
  • the failure determination unit 109 does not determine whether there is a failure due to the reference signal. If there is an error in the reference signal, it is presumed that a failure has occurred in the row-specific value reference pixels 122. Therefore, if failure determination is performed, it will be determined that a failure has occurred in pixel row R, even if no failure has occurred in pixels other than the row-specific value reference pixels 122 of pixel row R. By the failure determination unit 109 not performing failure determination, it is possible to prevent failure determination due to a failure in the row-specific value reference pixels 122.
  • the fault determination unit 109 compares the reference signal corrected by the error detection unit 108 with an expected value that is set in advance for that pixel row R (St107) to perform fault determination. In this case, since the error in the reference signal due to a fault in the row-specific value reference pixels 122 has been eliminated by the correction, fault determination due to a fault in the row-specific value reference pixels 122 can be prevented.
  • the failure determination unit 109 may not perform failure determination based on the reference signal, regardless of whether the error detection unit 108 has successfully corrected the error. In this case, too, by having the failure determination unit 109 not perform failure determination, it is possible to prevent failure detection due to a failure in the row-specific value reference pixels 122.
  • the imaging device 100 detects an error in the reference signal output by the row eigenvalue reference pixels 122 using the error correction code output by the correction code reference pixels 123. Furthermore, if there is no error in the reference signal or if the error in the reference signal has been corrected, the reference signal is used to determine whether or not there is a fault in the pixel row. This prevents an erroneous determination of a fault in the pixel row due to an error in the reference signal caused by a fault in the row eigenvalue reference pixels 122, and enables accurate fault determination of the pixel row.
  • FIG. 4 is a schematic diagram of a pixel array using this method.
  • the pixel array 501 shown in the figure includes imaging pixels 521, reference pixels 522a, and reference pixels 522b.
  • Each pixel row R of the pixel array 501 is made up of imaging pixels 521, reference pixels 522a, and reference pixels 522b.
  • the reference pixels 522a are pixels that output a reference signal specific to the pixel row R.
  • the reference pixels 522b are pixels that output the same reference signal as the reference pixels 522a, and the same number as the reference pixels 522a are required.
  • Another method for suppressing the effects of reference pixel failure involves storing information about whether or not a reference pixel is faulty in an information storage mechanism built into the imaging device, or obtaining the information from outside the imaging device. However, in this case, it is necessary to provide an information storage mechanism either inside or outside the imaging device. In contrast, the imaging device 100 according to the present technology does not require such an information storage mechanism.
  • the imaging device 100 has excellent pixel area efficiency, is able to suppress the effects of reference pixel failures without requiring an information retention mechanism, and is able to accurately detect pixel row failures. For this reason, the imaging device 100 is well suited to applications where imaging is performed continuously, such as in-vehicle sensors, factory use, traffic monitoring, and biometric authentication.
  • the imaging device 100 can also be used in any application where a CMOS image sensor can be used.
  • FIG. 5 is a block diagram of an imaging device 200 according to the second embodiment.
  • Fig. 6 is a flowchart showing the operation of the imaging device 200.
  • the imaging device 200 includes a pixel array 201, an A/D converter array 202, a row scanning unit 203, a control unit 204, a signal processing unit 205, a voltage supply unit 206, a ramp signal supply unit 207, an error detection unit 208, and a failure determination unit 209.
  • the pixel array 201 is an array in which pixels made of CMOS (Complementary Metal Oxide Semiconductor) are arranged. Specifically, the pixel array 201 includes imaging pixels 221, row-specific value reference pixels 222, and correction code reference pixels 223. In Figure 5, the row-specific value reference pixels 222 are indicated by hatching with diagonal lines, and the correction code reference pixels 223 are indicated by hatching with dots.
  • CMOS Complementary Metal Oxide Semiconductor
  • the pixel row R includes a first pixel row R1 and a second pixel row R2.
  • the row wiring 231 of the first pixel row R1 and the row wiring 231 of the second pixel row R2 are connected, and the first pixel row R1 and the second pixel row R2 are read out simultaneously.
  • the other pixel rows R also include a first pixel row R1 and a second pixel row R2 that are read out simultaneously.
  • the imaging pixels 221 photoelectrically convert incident light and accumulate electric charges.
  • the imaging pixels 221 output a pixel signal corresponding to the amount of accumulated electric charge to the column wiring 232.
  • the row-specific value reference pixel 222 outputs a row-specific reference signal.
  • the row-specific value reference pixel 222 receives a fixed voltage V0 or V1 from the voltage supply unit 206 and receives a row selection signal from the row wiring 231, the row-specific value reference pixel 222 outputs a reference signal in accordance with either the fixed voltage V0 or V1 .
  • the reference signals output by the row-specific value reference pixels 222 are the same between the first pixel row R1 and the second pixel row R2.
  • the reference signals output by the row-specific value reference pixels 222 constituting the first pixel row R1 will be referred to as the "first reference signal”
  • the reference signals output by the row-specific value reference pixels 222 constituting the second pixel row R2 will be referred to as the "second reference signal.” If there are no failures in the row-specific value reference pixels 222 in the first pixel row R1 and the second pixel row R2, the first reference signal and the second reference signal will be the same. Note that while Figure 5 shows only one row-specific value reference pixel 222 in each pixel row R, in reality, a number of row-specific value reference pixels 222 sufficient to generate a unique reference signal are arranged in each pixel row R (see Figure 3).
  • the A/D converter array 202 is an array in which A/D converters 241 are arranged. Each A/D converter 241 is connected to a column wiring 232 and converts the analog signals input from the column wiring 232, specifically the pixel signal, first reference signal, second reference signal, first error correction code, and second error correction code, into digital signals.
  • the error detection unit 208 detects an error in the reference signal based on the reference signal output from the row-specific value reference pixels 122 that make up a specific pixel row R and the error correction code output from the correction code reference pixels 123 that make up that pixel row R. Specifically, the error detection unit 208 reads out the first reference signal output from the row-specific value reference pixels 122 that make up the first pixel row R1 of the pixel row pair selected by the row scanning unit 203, and the second reference signal output from the row-specific value reference pixels 122 that make up the second pixel row R2 of the same pixel row pair (St201, see Figure 6).
  • the error detection unit 208 performs an error detection process using the first error correction code output from the correction code reference pixels 223 that make up the first pixel row R1, and detects an error in the first reference signal (St202).
  • the error detection unit 208 If the error detection unit 208 does not detect an error in the second reference signal (St205; No), it supplies this second reference signal to the fault determination unit 209 as a reference signal for the first pixel row R1 and the second pixel row R2. On the other hand, if the error detection unit 208 detects an error in the second reference signal (St205; Yes), it notifies the outside, for example, the device in which the imaging device 200 is installed, that there is an abnormality in the captured image generated based on the output of the imaging pixels 221 (St206), and terminates imaging.
  • the programs executed by the information processing device 300 may be programs that are processed chronologically in the order described in this disclosure, or may be programs that are processed in parallel or at the required timing, such as when called.
  • the entire hardware configuration of the information processing device 300 does not have to be installed in a single device; the information processing device 300 may be made up of multiple devices. Furthermore, part of the hardware configuration of the information processing device 300 may be installed in multiple devices connected via a network.
  • This technology can also be configured as follows:
  • a pixel array in which pixels made of CMOS (Complementary Metal Oxide Semiconductor) are arranged, each pixel row being configured by connecting imaging pixels that output pixel signals corresponding to incident light, row-specific value reference pixels that output row-specific reference signals, and correction code reference pixels that output error correction codes for the reference signals by wiring; an error detection unit that detects an error in the reference signal based on a reference signal output from row-specific value reference pixels that configure a specific pixel row among the plurality of pixel rows and an error correction code output from a correction code reference pixel that configures the pixel row; a failure determination unit that determines whether or not there is a failure in the pixel row based on the reference signal and a detection result by the error detection unit.
  • CMOS Complementary Metal Oxide Semiconductor
  • the error detection unit When the error detection unit does not detect an error in the reference signals output from the row-eigenvalue reference pixels that constitute the pixel row, the error detection unit supplies the reference signals to the fault detection and determination unit as the reference signals for the pixel row, and when the error detection unit detects an error in the reference signals output from the row-eigenvalue reference pixels that constitute the pixel row, the error detection unit corrects the reference signals and supplies the corrected reference signals to the fault determination unit as the reference signals for the pixel row.
  • the failure determination unit compares the reference signal supplied from the error detection unit with an expected value set for the pixel row, and determines that the pixel row has a failure if the reference signal does not match the expected value.
  • the failure determination unit determines that the pixel row has a failure
  • the failure determination unit notifies that an abnormality exists in a captured image generated based on outputs of the imaging pixels.
  • the imaging device according to any one of (1) to (4) above When the error detection unit detects an error in the reference signals output from row-specific value reference pixels that configure the pixel row, the failure determination unit does not determine whether or not there is a failure in the pixel row.
  • the error detection unit detects an error in a reference signal output from row-specific value reference pixels that configure the pixel row, and if the reference signal cannot be corrected, notifies that an abnormality exists in an image generated based on outputs from the imaging pixels.
  • the error detection unit When the error detection unit does not detect an error in first reference signals output from row-eigenvalue reference pixels constituting the first pixel row, the error detection unit supplies the first reference signals to the failure determination unit as reference signals for the first pixel row and the second pixel row; when the error detection unit detects an error in the first reference signals output from the row-eigenvalue reference pixels constituting the first pixel row and does not detect an error in second reference signals output from the row-eigenvalue reference pixels constituting the second pixel row, the error detection unit supplies the second reference signals to the failure determination unit as reference signals for the first pixel row and the second pixel row.
  • the failure determination unit compares the reference signal supplied from the error detection unit with expected values set for the first pixel row and the second pixel row, and determines that there is a failure in the first pixel row and the second pixel row when the reference signal and the expected value do not match.
  • the failure determination unit determines that the first pixel row and the second pixel row have a failure, the failure determination unit notifies that there is an abnormality in a captured image generated based on outputs of the imaging pixels.
  • a pixel array in which pixels made of CMOS (Complementary Metal Oxide Semiconductor) are arranged, each pixel row outputting a pixel signal corresponding to incident light, row-specific value reference pixels outputting a row-specific reference signal, and correction code reference pixels outputting an error correction code for the reference signal, among a plurality of pixel rows connected by wiring, an error detection unit that detects an error in the reference signal based on the reference signal output from the row-specific value reference pixels constituting a specific pixel row and the error correction code output from the correction code reference pixels constituting the pixel row; an imaging device control program that causes an information processing device to operate as a failure determination unit that determines whether or not there is a failure in the pixel row based on the reference signal and a detection result by the error detection unit; (14) the error detection unit forms a pixel array in which pixels made of CMOS (Complementary Metal Oxide Semiconductor) are arranged, and each pixel row is formed by connecting imaging pixels that output pixel signals
  • REFERENCE SIGNS LIST 100 200... Imaging device 101, 201... Pixel array 102, 202... A/D converter array 103, 203... Row scanning unit 104, 204... Control unit 105, 205... Signal processing unit 106, 206... Voltage supply unit 107, 207... Ramp signal supply unit 108, 208... Error detection unit 109, 209... Fault determination unit 121, 221... Imaging pixels 122, 222... Row eigenvalue reference pixels 123, 223... Correction code reference pixels 131, 231... Row wiring 132, 232... Column wiring

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  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

Un dispositif d'imagerie selon la présente invention est pourvu d'une pluralité de lignes de pixels, d'une unité de détection d'erreur et d'une unité de détermination de défaillance. La pluralité de lignes de pixels constitue un réseau de pixels dans lequel sont disposés des pixels comprenant des CMOS, et chaque ligne de pixels est configurée par connexion, par le biais d'un câblage, de pixels d'imagerie qui délivrent en sortie des signaux de pixel correspondant à une lumière incidente, un pixel de référence de valeur spécifique à une ligne, qui délivre un signal de référence spécifique à la rangée, et un pixel de référence de code de correction qui délivre un code de correction d'erreur pour le signal de référence. Sur la base du signal de référence émis par le pixel de référence de valeur spécifique à la ligne constituant une ligne de pixels spécifique parmi la pluralité de lignes de pixels et du code de correction d'erreur délivré par le pixel de référence de code de correction constituant la ligne de pixels, l'unité de détection d'erreur détecte une erreur dans le signal de référence. L'unité de détermination de défaillance détermine si une défaillance s'est produite ou non dans la ligne de pixels sur la base du signal de référence et du résultat de détection par l'unité de détection d'erreur.
PCT/JP2025/005743 2024-03-26 2025-02-20 Dispositif d'imagerie, procédé de commande de dispositif d'imagerie et programme de commande de dispositif d'imagerie Pending WO2025204321A1 (fr)

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WO2006120815A1 (fr) * 2005-05-11 2006-11-16 Matsushita Electric Industrial Co., Ltd. Dispositif de lecture d’images a semi-conducteurs, camera, vehicule et dispositif de surveillance
JP2009118427A (ja) * 2007-11-09 2009-05-28 Panasonic Corp 固体撮像装置およびその駆動方法
JP2018107747A (ja) * 2016-12-28 2018-07-05 キヤノン株式会社 撮像装置、故障検知方法、撮像システム、及び移動体
JP2019012752A (ja) * 2017-06-29 2019-01-24 キヤノン株式会社 撮像装置、撮像システム、移動体
JP2021087143A (ja) * 2019-11-28 2021-06-03 キヤノン株式会社 光電変換装置、光電変換システム、移動体、光電変換装置の検査方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006120815A1 (fr) * 2005-05-11 2006-11-16 Matsushita Electric Industrial Co., Ltd. Dispositif de lecture d’images a semi-conducteurs, camera, vehicule et dispositif de surveillance
JP2009118427A (ja) * 2007-11-09 2009-05-28 Panasonic Corp 固体撮像装置およびその駆動方法
JP2018107747A (ja) * 2016-12-28 2018-07-05 キヤノン株式会社 撮像装置、故障検知方法、撮像システム、及び移動体
JP2019012752A (ja) * 2017-06-29 2019-01-24 キヤノン株式会社 撮像装置、撮像システム、移動体
JP2021087143A (ja) * 2019-11-28 2021-06-03 キヤノン株式会社 光電変換装置、光電変換システム、移動体、光電変換装置の検査方法

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