WO2025244851A1

WO2025244851A1 - Methods and apparatus for controlling power converters

Info

Publication number: WO2025244851A1
Application number: PCT/US2025/028416
Authority: WO
Inventors: Michael J. Harrison; Donald Richard Zimmanck
Original assignee: Enphase Energy Inc
Current assignee: Enphase Energy Inc
Priority date: 2024-05-22
Filing date: 2025-05-08
Publication date: 2025-11-27
Anticipated expiration: 2026-11-22

Abstract

A ripple rejection resonant inverter configured for use with a power conversion system is provided and comprises a first circuit connected to a primary winding of a transformer, a second circuit connected to a secondary winding of the transformer and to a DC input side of the power conversion system, and a controller connected to the first circuit and the second circuit and configured to determine when a power ripple is equal to or above a predetermined value, calculate a ripple control voltage, and apply a correction offset based on the ripple control voltage to regulate the power ripple.

Description

METHODS AND APPARATUS FOR CONTROLLING POWER CONVERTERS

BACKGROUND

Field of the Disclosure

[0001] Embodiments of the present disclosure relate generally to power conversion systems and, in particular, to methods and apparatus for controlling series ripple rejection using a resonant inverter.

Description of the Related Art

[0002] Conventional power converters suitable for use with power conversion systems are known. For example, in some instances, single phase power converters can create a two time (2x) grid frequency power ripple at an input of the power converter. Some devices, such as batteries, do not tolerate or allow such large ripple current, necessitating some sort of ripple rejection. Classic approaches sometimes use a dual-stage inverter which can create a DC-link that can absorb the power ripple, but such approaches can be expensive and inefficient because two converters in series are, typically, required to manage the full power. Alternatively, a voltage source inverter (VSI), which is a converter that converts a constant DC voltage to AC voltage with variable frequency and magnitude, can be connected in series with one of the input legs of the VSI to cancel the ripple, while running at much lower power levels as the VSI only needs to process the ripple voltage. Such methods/apparatus, however, also can be expensive.

[0003] Thus, there is a need for improved methods and apparatus for controlling series ripple rejection using a resonant inverter.

SUMMARY

[0004] In accordance with at least some embodiments, there is provided a ripple rejection resonant inverter configured for use with a power conversion system. The ripple rejection resonant inverter comprises a first circuit connected to a primary winding of a transformer, a second circuit connected to a secondary winding of the transformer and to a DC input side of the power conversion system, and a controller connected to the first circuit and the second circuit and configured to determine when a power ripple is equal to or above a predetermined value, calculate a ripple control voltage, and apply a correction offset based on the ripple control voltage to regulate the power ripple.

[0005] In accordance with at least some embodiments, there is provided a power conversion system. The power conversion system comprises a converter, a DC side of the converter, and a ripple rejection resonant inverter comprising a first circuit connected to a primary winding of a transformer, a second circuit connected to a secondary winding of the transformer and to a DC input side of the power conversion system, and a controller connected to the first circuit and the second circuit and configured to determine when a power ripple is equal to or above a predetermined value, calculate a ripple control voltage, and apply a correction offset based on the ripple control voltage to regulate the power ripple.

[0006] In accordance with at least some embodiments, there is provided a method for controlling a ripple rejection resonant inverter configured for use with a power conversion system. The method comprises determining, using a first circuit connected to a primary winding of a transformer and a second circuit connected to a secondary winding of the transformer, when a power ripple at a DC input side of the power conversion system is equal to or above a predetermined value, calculating a ripple control voltage, and applying a correction offset based on the ripple control voltage to regulate the power ripple.

[0007] Various advantages, aspects, and novel features of the present disclosure may be appreciated from a review of the following detailed description of the present disclosure, along with the accompanying figures in which like reference numerals refer to like parts throughout.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments. [0009] Figure 1 is a schematic diagram of a power conversion system comprising a switched mode power converter, in accordance with embodiments of the present disclosure;

[0010] Figure 2 is a schematic diagram of a power conversion system comprising a switched mode power converter, in accordance with embodiments of the present disclosure;

[0011] Figure 3 is a schematic diagram of two types of ripple rejection inverters, in accordance with embodiments of the present disclosure;

[0012] Figure 4 is a schematic diagram of a behavior model of the ripple rejection inverters of Figure 3, in accordance with embodiments of the present disclosure;

[0013] Figure 5 is a simulation of the operation of the ripple rejection inverters of Figure 3, in accordance with embodiments of the present disclosure; and

[0014] Figure 6 is a schematic diagram of two types of ripple rejection inverters, in accordance with embodiments of the present disclosure; and

[0015] Figure 7 is a flowchart of a method for controlling a ripple rejection resonant inverter configured for use with a power conversion system, in accordance with embodiments of the present disclosure.

DETAILED DESCRIPTION

[0016] Embodiments of the present disclosure are directed to improved methods and apparatus for controlling series ripple rejection using a resonant inverter. For example, a ripple rejection resonant inverter can be configured for use with a power conversion system and comprises a first circuit connected to a primary winding of a transformer, a second circuit connected to a secondary winding of the transformer and to a DC input side of the power conversion system, and a controller connected to the first circuit and the second circuit and configured to determine when a power ripple is equal to or above a predetermined value, calculate a ripple control voltage, and apply a correction offset based on the ripple control voltage to regulate the power ripple. Compared to conventional methods and apparatus, the methods and apparatus described herein are relatively simple, efficient, and cost effective for counteracting series ripple reaction. [0017] The foregoing description of embodiments of the disclosure comprises a number of elements, devices, circuits and/or assemblies that perform various functions as described. These elements, devices, circuits, and/or assemblies are exemplary implementations of means for performing their respectively described functions.

[0018] Figure 1 is a schematic diagram of a power conversion system 100 comprising a converter 102 (e.g., a switched mode power converter), in accordance with embodiments of the present disclosure. This diagram only portrays one variation of the myriad of possible system configurations. The present disclosure can function in a variety of power generation environments and systems.

[0019] The power conversion system 100 comprises a DC component 120, such as a PV module or a battery, coupled to a DC side of the converter 102 (referred to herein as “converter 102”). In other embodiments the DC component 120 may be any suitable type of DC components, such as another type of renewable energy source (e.g., wind farms, hydroelectric systems, and the like), other types of energy storage components, and the like.

[0020] The converter 102 comprises a capacitor 122 coupled across the DC component 120 as well as across an H-bridge 104 formed from switches S-1 , S-2, S-3 and S-4. The switches S-1 and S-2 are coupled in series to form a left leg of the H-bridge 104, and the switches S-3 and S-4 are coupled in series to form a right leg of the H-bridge 104.

[0021] The output of the H-bridge 104 is coupled across a series combination of a capacitor Cr and inductor L, which form a resonant tank, and the primary winding of a transformer 108. In other embodiments, the resonant tank may be formed by a different configuration of the capacitor Cr and the inductor Lr (e.g., the capacitor Cr and the inductor L may be coupled in parallel); in some embodiments, Lr may represent a leakage inductance from the transformer 108 rather than a physical inductor.

[0022] A series combination of the secondary winding of the transformer 108 and an inductor L is coupled across a bridge which produces a three-phase AC output, although in other embodiments the bridge may produce one or two phases of AC at its output. The bridge can be a half-bridge, full-bridge, Hex-bridge, etc. formed using switches that are arranged to enable current flow to be alternated. For example, the switches can comprise one or more semiconductor (or vacuum tube) devices, e.g., Field Effect Transistor (FET), Junction FET (JFET), Metal Oxide Semiconductor FET (MOSFET), High Electron Mobility Transistor (HEMT), etc. The switches can be used for AC-DC conversion and/or DC-AC conversion (e.g., switches that are controllable). The bridge can be a Bi-directional bridge (sometimes referred to as a cycloconverter bridge or cycloconverter for short) that uses two Uni-Directional switches connected in series (back-to-back, which can be referred to as Bidirectional switches) -which can conduct current in either direction (when turned on), can block a voltage of either polarity (when turned off), and can also block a voltage in both polarities (e.g., block polar voltage). For illustrative purposes, the secondary winding of the transformer 108 and the inductor L are assumed coupled across a cycloconverter 110. The cycloconverter 110 comprises three 4Q bidirectional switches Q-1, Q-2, and Q-3 (which may be collectively referred to as switches Q) respectively in a first leg, a second leg, and a third leg coupled in parallel to one another. In accordance with embodiments of the present disclosure, each of the switches Q-1 , Q-2, and Q-3 is a native four quadrant bi-directional switch comprising one or more of the aforementioned semiconductor (or vacuum tube) devices. Alternatively or additionally, the cycloconverter 110 can comprise three monolithically formed switches (e.g., a Monolithic Bi-Directional Switch (MBDS)) - Gallium-Nitride (GaN) based on a HEMT structure, as described in greater detail below. That is, the MBDS refers to the fact that this Bi-Directional Switch (BDS) can be built in a single semiconductor die. In at least some embodiments, each of the switches Q-1 , Q-2, and Q-3 comprises a pair of Gallium-Nitride (GaN) High Electron Mobility Transistors. In at least some embodiments, each of the switches Q-1 , Q-2, and Q-3 comprises a first pair of Gallium-Nitride (GaN) High Electron Mobility Transistors and a second pair of Gallium-Nitride (GaN) High Electron Mobility Transistors connected in series.

[0023] The first cycloconverter leg comprises the 4Q switch Q-1 coupled to a capacitor C1 , the second cycloconverter leg comprises the 4Q switch Q-2 coupled to a capacitor C2, and the third cycloconverter leg comprises a 4Q switch Q-3 coupled to a capacitor 03. A first AC output phase line is coupled between the switch Q-1 and the capacitor C1 , a second AC output phase line is coupled between the switch Q-2 and the capacitor C2, and a third AC output phase line is coupled between the switch Q-3 and the capacitor C3. The converter 102 may also include additional circuitry not shown, such as voltage and/or current monitors, for obtaining data for power conversion, data reporting, and the like.

[0024] The converter 102 additionally comprises a controller 106 coupled to the Id- bridge switches (S-1 , S-2, S-3, and S-4) and the cycloconverter switches (Q-1 , Q-2, and Q-3) for operatively controlling the switches to generate the desired output power. In some embodiments, the converter 102 may function as a bi-directional converter.

[0025] The controller 106 comprises a CPU 184 coupled to each of support circuits

183 and a memory 186. The CPU 184 may comprise one or more conventionally available microprocessors or microcontrollers. Additionally or alternatively, the CPU

184 may include one or more application specific integrated circuits (ASICs). The support circuits 183 are well known circuits used to promote functionality of the CPU 184. Such circuits include, but are not limited to, a cache, power supplies, clock circuits, buses, input/output (I/O) circuits, and the like. The controller 106 may be implemented using a general purpose computer that, when executing particular software, becomes a specific purpose computer for performing various embodiments of the present disclosure.

[0026] The memory 186 is a non-transitory computer readable storage medium such as random access memory, read only memory, removable disk memory, flash memory, and various combinations of these types of memory. The memory 186 is sometimes referred to as main memory and may, in part, be used as cache memory or buffer memory. The memory 186 generally stores the OS 187 (operating system), if necessary, of the controller 106 that can be supported by the CPU capabilities. In some embodiments, the OS 187 may be one of a number of commercially available operating systems such as, but not limited to, LINUX, Real- Time Operating System (RTOS), and the like.

[0027] The memory 186 may store various forms application software (e.g., instructions), such as a conversion control module 189 for controlling power conversion by the converter 102, for example maximum power point tracking (MPPT), switching, performing the methods described herein, and the like. The memory 186 may further store a database 199 for storing various data. The controller 106 further processes inputs and outputs to external communications 194 (i.e., gateway) and a grid interface 188.

[0028] Figure 2 is a schematic diagram of a power conversion system 200 comprising a converter 202 (e.g., a switched mode power converter), in accordance with embodiments of the present disclosure.

[0029] The power conversion system 200 comprises the DC component 120 coupled to a DC side of the converter 202. The converter 202 comprises the capacitor 122 coupled across the DC component 120 and the H-bridge 104, as described above with respect to the converter 102. The output of the H-bridge 104 is coupled across a series combination of the capacitor Cr and the inductor Lr, which form a resonant tank, and the primary winding of the transformer 108, as described above with respect to the converter 102. In other embodiments, the resonant tank may be formed by a different configuration of the capacitor Cr and the inductor Lr (e.g., the capacitor Cr and the inductor L may be coupled in parallel); in some embodiments, Lr may represent a leakage inductance of the transformer 108 rather than a physical inductor.

[0030] A series combination of the secondary winding of the transformer 108 and the inductor L can be coupled across a bridge as described above with respect to Figure 1. For example, the secondary winding of the transformer 108 and the inductor L can be coupled across a cycloconverter 210 which produces a single-phase AC output. For example, the cycloconverter 210 comprises two bi-directional switches Q-1 and Q-2, (collectively referred to as switches Q) respectively in a first leg and a second leg coupled in parallel to one another. In accordance with embodiments of the present disclosure, each of the switches Q-1 and Q-2 is a native four quadrant bi-directional switch comprising one or more of the aforementioned semiconductor (or vacuum tube) devices. Alternatively or additionally, the cycloconverter 210 can comprise two monolithically formed switches (e.g., a Monolithic Bi-Directional Switch (MBDS)) -Gallium-Nitride (GaN) based on a HEMT structure, as described in greater detail below. In at least some embodiments, each of the switches Q-1 and Q-2 comprises a pair of Gallium-Nitride (GaN) High Electron Mobility Transistors. In at least some embodiments, each of the switches Q-1 and Q-2 comprises a first pair of Gallium-Nitride (GaN) High Electron Mobility Transistors and a second pair of Gallium-Nitride (GaN) High Electron Mobility Transistors connected in series.

[0031] The first cycloconverter leg comprises the 4Q switch Q-1 coupled to the capacitor C1 , and the second cycloconverter leg comprises the 4Q switch Q-2 coupled to the capacitor C2. A first AC output phase line is coupled between the switch Q-1 and the capacitor C1 , and a second AC output phase line is coupled between the switch Q-2 and the capacitor C2. The converter 202 may also include additional circuitry not shown, such as voltage and/or current monitors, for obtaining data for power conversion, data reporting, and the like.

[0032] The converter 202 additionally comprises a controller 206 coupled to the H- bridge switches (S-1 , S-2, S-3, and S-4), and the cycloconverter switches (Q-1 and Q-2) for operatively controlling the switches to generate the desired output power. In some embodiments, the converter 202 may function as a bi-directional converter.

[0033] The controller 206 comprises a CPU 284 coupled to each of support circuits

283 and a memory 286. The CPU 284 may comprise one or more conventionally available microprocessors or microcontrollers. Alternatively or additionally, the CPU

284 may include one or more application specific integrated circuits (ASICs). The support circuits 283 are well known circuits used to promote functionality of the CPU 284. Such circuits include, but are not limited to, a cache, power supplies, clock circuits, buses, input/output (I/O) circuits, and the like. The controller 206 may be implemented using a general purpose computer that, when executing particular software, becomes a specific purpose computer for performing various embodiments of the present disclosure.

[0034] The memory 286 is a non-transitory computer readable medium such as random access memory, read only memory, removable disk memory, flash memory, and various combinations of these types of memory. The memory 286 is sometimes referred to as main memory and may, in part, be used as cache memory or buffer memory. The memory 286 generally stores the OS 287 (operating system), if necessary, of the controller 206 that can be supported by the CPU capabilities. In some embodiments, the OS 287 may be one of a number of commercially available operating systems such as, but not limited to, LINUX, Real-Time Operating System (RTOS), and the like.

[0035] The memory 286 may store various forms of application software, such as a conversion control module 289 for controlling power conversion by the converter 202, for example maximum power point tracking (MPPT), switching, and the like. The memory 286 may further store a database 299 for storing various data. The controller 206 further processes inputs and outputs to external communications 194 (i.e., gateway) and the grid interface 188.

[0036] As noted above, embodiments of the present disclosure are directed to improved methods and apparatus for controlling series ripple rejection using a resonant inverter. The inventive concepts described herein provide flexibility on where a cancellation of the series ripple occurs (e.g., high side, low side, or both) due to isolation, provide multiple cancellation nodes, which can provide cancellation on both inputs with one rejection converter, provide step up or step-down capabilities so that a user can optimize device selection, and because the DC voltage for the ripple inverter is isolated from the ripple port, the ripple inverter can share a ground with a controller. For illustrative purposes, the ripple inverter is described for use with the cycloconverter 210 which produces a single-phase AC output. The ripple converter can be used, however, with the cycloconverter 110, such as, when there is a significant voltage imbalance on a three-phase supply, which can result in a small amount of ripple which ripple converter can remedy. Additionally, another reason for using a ripple converter with a three-phase converter is if one wants the three-phase converter to be fault tolerant and able to operate correctly if one phase voltage is missing, e g., due to a grid fault condition or on the basis of designing a converter that can be powered from either three-phase or single-phase. In the latter instance, the ripple converter power rating can be determined by the single-phase operational condition.

[0037] Continuing with reference to Figure 3, which is a schematic diagram of two types of ripple rejection inverters (converters), in accordance with embodiments of the present disclosure, a single output ripple rejection inverter 300 (single output inverter) comprises a capacitor Cn_PPie_i that is connected across two legs each comprising two switches. For example, a first leg comprises switch Sri_PPie_i and switch Sri_PPie_2 and a second leg comprises switch Sn_PPie_3 and switch Sn_PPie_4. The switch S ripple_1 , switch S ripple_2, switch S ripple_3, and switch Sn_PPie_4 can be the same as or similar to the switches described above, e.g., S-1 , S-2, S-3, S-4, Q-1 , Q-2, or Q-3. The first leg and the second leg connect to a primary winding of a transformer Trippie and a secondary winding of the transformer Tn_PPie connects to a pair of switches (switch Sri_PPie_5 and switch Sn_PPie_6) and to a pair of capacitors (capacitor Cri_PPie_2 and capacitor Crippie s). The switch Sn_PPie_5 and switch Sri_PPie_6 can be the same as or similar to the switches described above, e.g., S-1 , S-2, S-3, S-4, Q-1 , Q-2, or Q-3. An inductor Lrippie can be connected to the transformer Trippie between the switch Sri_PPie_5 and switch Sn_PPie_6. During operation, when a DC voltage and a ripple is present on the capacitor 122, the single output ripple rejection inverter 300 provides a ripple rejection waveform that counteracts DC voltage and the ripple on the capacitor 122.

[0038] A dual output ripple rejection inverter 302 (dual output inverter) is substantially identical to the single output ripple rejection inverter 300, except that the dual output ripple rejection inverter 302 comprises two secondary windings on the transformer Thppie and each one of the two secondary windings connects to the pair of switches (switch Sri_PPie_5 and switch Sri_PPie_6) and to the pair of capacitors (capacitor Cn_PPie_2 and capacitor Cri_PPie_3) that provide input bypass capacitance. Each secondary winding on the transformer Trippie comprises an inductor Lrippie that can be connected between the switch Sri_PPie_5 and switch Sri_PPie_6. During operation, when a DC voltage and a ripple is present on the capacitor 122, the dual output ripple rejection inverter 302 provides a ripple rejection waveform that counteracts DC voltage and the ripple on the capacitor 122.

[0039] Figure 4 is a schematic diagram 400 of a behavior model circuit of the ripple rejection inverters of Figure 3, and Figure 5 is a simulation 500 of the operation of the ripple rejection inverters of Figure 3, in accordance with embodiments of the present disclosure. In Figure 4, a control algorithm 401 is reliant upon the controller 402 having an accurate value for the main converter ripple capacitor (e.g., capacitor Cri_PPie_i ), which can degrade over the lifetime of the converter. F3 is a mathematical functional block that performs a division operation. The voltage across the capacitor Cri_Ppie_i is fed into the 'y' input of the divider and the demanded ac power signal is fed into the 'x' input of this divider. The demanded ac power is divided by the voltage across the capacitor Cri_PPie_i resulting in a ripple current output signal, which is then used to generate the ripple current imposed across the ripple capacitor. The schematic diagram 400 of the behavior model circuit creates a realistic set of signals to drive the controller 402. During operation, when a converter input has a ripple voltage 502 and a converter current 504 (e.g., with two times power ripple) is present, using either of the ripple rejection inverters of Figure 3, a ripple rejection inverter input voltage 506 (e.g., of about 50 V) is controlled/maintained and a ripple rejection converter output voltage 508 (see ripple rejection waveform of Figure 3) is generated (e.g., anti-ripple), which provides an input current 510 (e.g., with two times power ripple removed).

[0040] In at least some embodiments, a power level of the ripple rejection inverters can be proportional to a percentage of ripple designed on an input bypass capacitance. For example, if the capacitors re selected to provide 10% ripple at Pmax, the ripple rejection inverter can manage about 1/10^th the power level of the main converter (e.g., the cycloconverter 110 or the cycloconverter 210). For example, with a 400 V input, 2 kW inverter and a 440pF input capacitor, the calculations used can comprise:

> 2 W

^{Idc =} 400

- 10 A * - - - — —— - - - and

2n * 2 * 120 Hz * 440 .F p = Vrippie * Idc = 30.1 V * 54 = 150 W.

[0041] Thus, the ripple inverters only need to process 150 W of power when the main converter is at 2 kW, which is not only cost effective, but is also incredibly efficient, e.g., assuming the ripple rejection inverter is 96% efficient, at full power the ripple rejection inverter would only have 6 W of loss, which translates to only 0.3% efficiency loss in the overall power conversion.

[0042] Figure 6 is a schematic diagram of two types of ripple rejection inverters, in accordance with embodiments of the present disclosure. The two types of ripple rejection inverters of Figure 6 can be used instead of the control shown in Figure 4 and are not reliant on knowing the correct value for the main capacitor ripple capacitor. Alternatively, in at least some embodiments, combining one or more attributes of the control methods of Figures 4 and 6 is also a possible to create a more robust control architecture. A ripple rejection inverter 602 is configured to filter the AC ripple voltage using a HPF (High-Pass Filter) to generate the anti-ripple control signal. In such embodiments, the High-Pass Filter can be a sophisticated digital filter that is synchronized to the main converter AC mains phase-locked loop (PLL). A ripple rejection inverter 604 uses a simple PI (Proportional-Integral) control loop that aims to generate an anti-ripple control signal that results in no load ripple. Both the ripple rejection inverter 602 and the ripple rejection inverter 604 may require additional control loops to maintain regulation of the DC storage capacitor voltage.

[0043] In at least some embodiments, a bypass mode/state that shorts the output of the ripple rejection inverters described herein can also be used. For example, the bypass mode can use one or more mechanical relays across the output, or the bypass mode can comprise turning both AC port Bi-Directional Switches (BDS) devices on. In at least some embodiments, at start-up of the main converter, the ripple rejection inverter can be held in the bypass mode. Accordingly, if the ripple rejection inverter should fail, the main converter can still operate (albeit with increased output ripple).

[0044] Figure 7 is a flowchart of a method 700 for controlling a ripple rejection resonant inverter configured for use with a power conversion system, in accordance with embodiments of the present disclosure. For illustrative purposes, the method 700 is described in terms of use with the single output ripple rejection inverter and the cycloconverter 210 of Figure 2.

[0045] At 702, the method 700 comprises determining, using a first circuit connected to a primary winding of a transformer and a second circuit connected to a secondary winding of the transformer, when a power ripple at a DC input side of the power conversion system is equal to or above a predetermined value. For example, the controller 402 is configured to determine when a power ripple at the capacitor 122 is equal to or above a predetermined value (e.g., converter input has the ripple voltage 502 and the converter current 504 (e.g., with two times power ripple (AC power)). [0046] Next, at 704, the method 700 comprises calculating a ripple control voltage. For example, the controller 402 is configured to calculate ripple control voltage using the control algorithm 401 and using F3 (e.g., using phase-locked loop output).

[0047] Next, at 706, the method 700 comprises applying a correction offset based on the ripple control voltage to regulate the power ripple. For example, the controller 402 is configured to apply and generate ripple rejection converter output voltage 508 (e.g., anti-ripple) to regulate the power ripple, e.g., the input current 510 has two times power ripple removed.

[0048] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is defined by the claims that follow.

Claims

CLAIMS:

1. A ripple rejection resonant inverter configured for use with a power conversion system, comprising: a first circuit connected to a primary winding of a transformer; a second circuit connected to a secondary winding of the transformer and to a DC input side of the power conversion system; and a controller connected to the first circuit and the second circuit and configured to determine when a power ripple is equal to or above a predetermined value, calculate a ripple control voltage, and apply a correction offset based on the ripple control voltage to regulate the power ripple.

2. The ripple rejection resonant inverter of claim 1 , wherein the second circuit is connected in series with the DC input side.

3. The ripple rejection resonant inverter of claim 1 , wherein the first circuit comprises a first leg of switches, a second leg of switches, and a capacitor connected across the first leg of switches and the second leg of switches, the first leg of switches and the second leg of switches connect to the primary winding of the transformer, and wherein the second circuit comprises a third leg of switches and a first leg of capacitors, the third leg of switches and the first leg of capacitors connect to the secondary winding of the transformer.

4. The ripple rejection resonant inverter of claim 1 , wherein the correction offset is applied to at least one of a high side or a low side of the DC input side.

5. The ripple rejection resonant inverter of claim 1 , wherein the ripple rejection resonant inverter is one of a single output inverter or a dual output inverter.

6. The ripple rejection resonant inverter of claim 1 , wherein the ripple control voltage is calculated using a phase-locked loop output.

7. The ripple rejection resonant inverter of claim 1 , wherein the predetermined value is two times an AC power.

8. The ripple rejection resonant inverter as in any of claims 1 to 7, wherein the ripple rejection resonant inverter is configured to manage 1/10^th a power level of a main converter of the power conversion system.

9. A power conversion system, comprising: a converter; a DC side of the converter; and a ripple rejection resonant inverter, comprising: a first circuit connected to a primary winding of a transformer; a second circuit connected to a secondary winding of the transformer and to a DC input side of the power conversion system; and a controller connected to the first circuit and the second circuit and configured to determine when a power ripple is equal to or above a predetermined value, calculate a ripple control voltage, and apply a correction offset based on the ripple control voltage to regulate the power ripple.

10. The power conversion system of claim 9, wherein the second circuit is connected in series with the DC input side.

11 . The power conversion system of claim 9, wherein the first circuit comprises a first leg of switches, a second leg of switches, and a capacitor connected across the first leg of switches and the second leg of switches, the first leg of switches and the second leg of switches connect to the primary winding of the transformer, and wherein the second circuit comprises a third leg of switches and a first leg of capacitors, the third leg of switches and the first leg of capacitors connect to the secondary winding of the transformer.

12. The power conversion system of claim 9, wherein the correction offset is applied to at least one of a high side or a low side of the DC input side.

13. The power conversion system of claim 9, wherein the ripple rejection resonant inverter is one of a single output inverter or a dual output inverter.

14. The power conversion system of claim 9, wherein the ripple control voltage is calculated using a phase-locked loop output.

15. The power conversion system of claim 9, wherein the predetermined value is two times an AC power.

16. The power conversion system as in any of claims 9 to 15, wherein the ripple rejection resonant inverter is configured to manage 1/10^th a power level of a main converter of the power conversion system.

17. A method of controlling a ripple rejection resonant inverter configured for use with a power conversion system, comprising: determining, using a first circuit connected to a primary winding of a transformer and a second circuit connected to a secondary winding of the transformer, when a power ripple at a DC input side of the power conversion system is equal to or above a predetermined value; calculating a ripple control voltage; and applying a correction offset based on the ripple control voltage to regulate the power ripple.

18. The method of claim 17, wherein the second circuit of the ripple rejection resonant inverter is connected in series with the DC input side.

19. The method of claim 17, wherein the first circuit comprises a first leg of switches, a second leg of switches, and a capacitor connected across the first leg of switches and the second leg of switches, the first leg of switches and the second leg of switches connect to the primary winding of the transformer, and wherein the second circuit comprises a third leg of switches and a first leg of capacitors, the third leg of switches and the first leg of capacitors connect to the secondary winding of the transformer.

20. The method as in any of claims 17 to 19, wherein the correction offset is applied to at least one of a high side or a low side of the DC input side.