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WO2025139322A1 - Procédé et système de détection de défaut de puce - Google Patents

Procédé et système de détection de défaut de puce Download PDF

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Publication number
WO2025139322A1
WO2025139322A1 PCT/CN2024/128016 CN2024128016W WO2025139322A1 WO 2025139322 A1 WO2025139322 A1 WO 2025139322A1 CN 2024128016 W CN2024128016 W CN 2024128016W WO 2025139322 A1 WO2025139322 A1 WO 2025139322A1
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Prior art keywords
skip
algorithm
probability
neural architecture
nas
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English (en)
Chinese (zh)
Inventor
明雪飞
李可
宿磊
于成昊
孙钰
顾杰斐
赵新维
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Jiangnan University
CETC 58 Research Institute
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Jiangnan University
CETC 58 Research Institute
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/045—Combinations of networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/047—Probabilistic or stochastic networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0495—Quantised networks; Sparse networks; Compressed networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G06N3/096—Transfer learning
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G06N3/0985—Hyperparameter optimisation; Meta-learning; Learning-to-learn
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis

Definitions

  • Deep learning technology has gradually entered the field of engineering. There are many reasons for its successful application in the field of fault detection.
  • deep learning can solve a variety of problems such as classification, prediction, and decision-making.
  • the technical problem to be solved by the present invention is to overcome the problems in the prior art of deep technology, such as high degree of manual intervention, vague engineering application directionality, redundant and bloated models, and inconvenience in edge device deployment.
  • the method for constructing the neural architecture search algorithm model ASNDARTS is as follows: inputting the two-dimensional image data of the chip into the neural architecture search algorithm NAS for training, and optimizing the neural architecture search algorithm NAS during the training process, and obtaining the neural architecture search algorithm model ASNDARTS when the neural architecture search algorithm NAS reaches Nash equilibrium;
  • the construction method of the knowledge distillation algorithm model DPSKD is: using the neural architecture search algorithm model ASNDARTS as a teacher network for knowledge distillation, and taking a single cell in the neural architecture search algorithm model ASNDARTS as a student network for knowledge distillation, wherein the neural architecture search algorithm model ASNDARTS includes a plurality of cells connected in series, and each of the cells is a result obtained by searching the neural architecture search algorithm model ASNDARTS in the search space;
  • the knowledge transfer method between the teacher network and the student network is decoupled, and the hyperparameters of the student network are optimized.
  • the knowledge distillation algorithm model DPSKD is obtained;
  • the one-dimensional vibration signal of the chip to be detected is obtained and converted into two-dimensional image data.
  • the two-dimensional image data of the chip to be detected is detected by the knowledge distillation algorithm model DPSKD to determine the Is the chip defective?
  • the optimization of the neural architecture search algorithm NAS during the training process includes a first optimization method, specifically:
  • the probability of the original skip_connect operation of the neural architecture search algorithm NAS being selected is band-limited.
  • the optimization of the neural architecture search algorithm NAS during the training process includes a second optimization method, specifically:
  • the optimization of the neural architecture search algorithm NAS during the training process includes a third optimization method, specifically:
  • the number of operation modes OP of the node is adaptively expanded according to the model contribution rate of each operation mode OP.
  • the method of performing band-limited correction on the probability of selection of the original skip_connect operation of the neural architecture search algorithm NAS during the training process includes:
  • the selected probability value ⁇ skip of the skip_connect operation during the training of the neural architecture search algorithm NAS is recorded in real time.
  • the selected probability distribution of ⁇ skip is P skip .
  • the point when P skip shows a gradient rise phenomenon is defined as the algorithm NAS crash starting point epoch_break.
  • the difference between ⁇ skip and ⁇ correct_skip at the algorithm NAS crash starting point is defined as ⁇ .
  • the band-limited corrected probability is obtained according to ⁇ skip , ⁇ correct_skip and ⁇ . The formula is as follows:
  • k skip represents the restriction on the probability of skip_connect operation in the algorithm NAS search process
  • the first half of k skip , k skip(tanh) is the limit on the number of early skip_connect operations at the epoch level based on the tanh activation function
  • the second half of k skip, k skip(sigmoid) is the limit on the number of skip_connect operations at the edge level based on the sigmoid activation function
  • the preset criterion includes:
  • the preset criteria include, in order of judgment, the algorithm accuracy trend under equal training epoch intervals, whether there is an abnormal accuracy value under equal training epoch intervals, the OP contribution value trend of each operation mode under equal training epoch intervals, and the OP frequency of each node selected operation mode under equal training epoch intervals, wherein:
  • the algorithm accuracy trend under the equal training epoch interval is as follows: a preset number of equal training epoch intervals are obtained, the algorithm accuracy value of each equal training epoch interval is counted, and the algorithm accuracy values of all equal training epoch intervals are linearly fitted to obtain a first linear fitting value. If the first linear fitting value is greater than 0, it indicates that the algorithm accuracy is on an upward trend; if the first linear fitting value is less than 0, This indicates that the accuracy of the algorithm is on a downward trend;
  • the contribution value trend of each operation mode OP under the equal training epoch interval is as follows: a preset number of equal training epoch intervals are obtained, and at the same time, the selection probability of each operation mode OP in each equal training epoch interval is obtained, and the selection probability of OP in all equal training epoch intervals is linearly fitted to obtain a second linear fitting value, and if the second linear fitting value is greater than 0, it indicates that the contribution value of the operation mode OP is in an upward trend; if the second linear fitting value is less than 0, it indicates that the contribution value of the operation mode OP is in a downward trend;
  • the method for adaptively expanding the number of operation modes OP of a node according to the model contribution rate of each operation mode OP includes:
  • the current node selects the operation mode OP whose contribution value is an upward trend, ignores the operation mode OP whose contribution value is a downward trend, and completes the adaptive expansion of the number of operation mode OPs of the current node.
  • the search space of the algorithm NAS includes several optional operation modes OP
  • the search space of the algorithm NAS includes several optional operation modes OP, including several max_pool_nxn, several avg_pool_nxn, skip_connect, several sep_conv_nxn, several dil_conv_nxn, and none, wherein max_pool represents maximum pooling, avg_pool represents average pooling, skip_connect represents skip connection, sep_conv represents depthwise separable convolution, dil_conv represents hole convolution, none represents no operation, and n takes an odd number in the value range ⁇ [1,9].
  • the method for decoupling the knowledge transfer between the teacher network and the student network based on the probability space includes:
  • the model ASNDARTS is probability reassigned and divided into three hierarchical category probability spaces, namely target space t, target class space O and overall space C.
  • the symbol P [p t , p O ⁇ t , p ⁇ O ] is defined, where p t represents the probability of target space t, p O ⁇ t represents the probability of excluding target t in the target class space O, and p ⁇ O represents the probability of excluding O in the overall space C.
  • zt represents the soft probability of the target class
  • zj represents the soft probability of all classes
  • zk represents the soft profile of the non-target class
  • k represents the in-class index of the non-target class
  • j represents the out-class index of the non-target class
  • ⁇ represents the correction symbol of the final skip_connect, It means that in the target class space O, other independent similar probabilities of the target space t are excluded; similarly, represents the probability of other independent similar objects in the overall space C after excluding the target class space O, where
  • the knowledge distillation KD is decoupled into three-level category probability spaces, and the formula is:
  • KL divergence TKD, KL divergence CKD and KL divergence OKD of the three-level category probability space are reorganized, and the knowledge transfer between the teacher network and the student network is realized based on the reorganization results.
  • the present invention provides a chip defect detection system, comprising:
  • Acquisition module used to acquire the one-dimensional vibration signal of the chip and convert it into two-dimensional image data
  • Construction module used to construct a neural architecture search algorithm model ASNDARTS, and to construct a knowledge distillation algorithm model DPSKD based on the neural architecture search algorithm model ASNDARTS;
  • the method for constructing the neural architecture search algorithm model ASNDARTS is as follows: inputting the two-dimensional image data of the chip into the neural architecture search algorithm NAS for training, and optimizing the neural architecture search algorithm NAS during the training process, and obtaining the neural architecture search algorithm model ASNDARTS when the neural architecture search algorithm NAS reaches Nash equilibrium;
  • the construction method of the knowledge distillation algorithm model DPSKD is: using the neural architecture search algorithm model ASNDARTS as a teacher network for knowledge distillation, and taking a single cell in the neural architecture search algorithm model ASNDARTS as a student network for knowledge distillation, wherein the neural architecture search algorithm model ASNDARTS includes a plurality of cells connected in series, and each of the cells is a result obtained by searching the neural architecture search algorithm model ASNDARTS in the search space;
  • the knowledge transfer method between the teacher network and the student network is decoupled, and the hyperparameters of the student network are optimized.
  • the knowledge distillation algorithm model DPSKD is obtained;
  • Detection module used to obtain the one-dimensional vibration signal of the chip to be detected and convert it into two-dimensional image data, and detect the two-dimensional image data of the chip to be detected through the knowledge distillation algorithm model DPSKD to determine whether the chip to be detected has defects.
  • the present invention selects the neural architecture search algorithm NAS as the basic network model, effectively solves the time-consuming problem of manually designing models, and designs a lightweight network model with excellent performance that can effectively target specific engineering application backgrounds;
  • the present invention performs band-limited correction on the skip_connect operation in the NAS algorithm to solve the NAS algorithm
  • the present invention proposes the concept of alternative search space, which solves the problem of excessive GPU usage of NAS algorithm on the basis of expanding the diversity of search space; the present invention introduces a contribution discrimination mechanism to the predecessor connection edge of each node in the NAS algorithm, obtains a variable number of node structures, and constitutes diversified cells; the present invention greatly improves the training stability and detection accuracy of the neural architecture search algorithm NAS, and reduces the consumption of hardware resources;
  • the present invention uses the network model ASNDARTS obtained by neural architecture search as the basic teacher model, further lightweights the network structure through knowledge distillation technology to obtain the student model, and decouples the knowledge transfer logic between the teacher and student models, effectively improving the ability to obtain information from the teacher model, and reducing the computing resource loss of the model without reducing the prediction accuracy;
  • the present invention can adaptively design deep neural networks under different industrial backgrounds, improve the prediction accuracy of model data while lightweighting the model structure, making it easy to deploy on edge devices to realize chip defect detection.
  • FIG1 is a flow chart of a chip defect detection method according to the present invention.
  • FIG2 is a flow chart of a skip_connect operation band limit correction in an embodiment of the present invention.
  • FIG3 is a logic diagram of a skip_connect operation band limit correction in an embodiment of the present invention.
  • FIG. 4 is a logic diagram of the decoupling of the teacher-student knowledge transfer logic in the DPSKD model according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram of a result structure (ie, a cell) searched by the model ASNDARTS in an embodiment of the present invention.
  • the present invention relates to a chip defect detection method, comprising:
  • the one-dimensional vibration signal of the chip to be detected is obtained and converted into two-dimensional image data, and the two-dimensional image data of the chip to be detected is detected by the knowledge distillation algorithm model DPSKD to determine whether the chip to be detected has defects.
  • the optimization of the neural architecture search algorithm NAS during the training process includes a first optimization method, specifically: performing a band-limited correction on the original skip_connect operation selection probability of the neural architecture search algorithm NAS during the training process.
  • the method for adaptively expanding the number of operation modes OP of a node according to the model contribution rate of each operation mode OP includes:
  • the deep learning soft probability model ASNDARTS is probability reassigned and divided into three hierarchical category probability spaces, namely target space t, target class space O and overall space C.
  • the symbol P [p t , p O ⁇ t , p ⁇ O ] is defined, where p t represents the probability of target space t, p O ⁇ t represents the probability of excluding target t in the target class space O, and p ⁇ O represents the probability of excluding O in the overall space C.
  • Figure 4 shows the decoupling logic of knowledge transfer logic using three-level category probability space.
  • A1, A2, A3, A4, and A5 in Figure 4 are as follows:
  • Step S1 Obtain a one-dimensional vibration signal from the faulty chip, sample the data with equal steps using a window width of n*n length; reconstruct the sampled signal into an n*n matrix after Fourier transformation, and concatenate three layers of n*n matrices to form a three-channel image data.
  • Each sample is of uniform size n*n and is A one-hot type label of the corresponding category is produced for each sample (since it is a prior art, it will not be described in detail in this embodiment). All samples are divided into a training set and a test set according to a certain ratio.
  • Step S3 Based on the original model NAS, a skip_connect operation correction value is introduced, which is combined with the original skip_connect operation selection probability value. Based on the accuracy convergence trend and model structure convergence trend during the algorithm training process, the skip_connect operation selection probability is corrected to solve the algorithm crash.
  • the specific workflow and usage logic are shown in Figure 2.
  • the selected probability value ⁇ skip and the correction value ⁇ correct_skip of the skip_connect operation in the search space are recorded in real time.
  • the distribution of ⁇ skip is P skip ; the point where the gradient rise phenomenon occurs in P skip is defined as the algorithm crash starting point epoch_break.
  • the corrected coefficient ⁇ correct_skip will tend to be stable.
  • the probability of ⁇ skip taking values after the crash point is taken as Get the final band-limited corrected probability
  • k skip represents the control of the probability of skip_connect operation during the algorithm search process.
  • data features can be fully extracted without using skip_connect for skip connection.
  • the first half of k skip is based on the tanh activation function to limit the number of early skip_connect operations at the epoch level.
  • the second half is based on the sigmoid activation function to limit the number of skip_connect operations at the edge level.
  • the criteria include: (1) the trend of model accuracy under equal training epoch intervals, (2) the abnormal situation of model accuracy value under equal training epoch intervals, (3) the trend of contribution value of each operation mode under equal training epoch intervals, and (4) the frequency of operation mode selected by each node under equal training epoch intervals.
  • the specific judgment logic is shown in Table 1 below.
  • Step S5 Introduce the operation mode op contribution discrimination mechanism for each node predecessor connection edge, and adaptively expand the number of node operations according to the op model contribution rate to obtain a variable number of node nodes. structure;
  • Figure 5 shows the result structure of the search by the model ASNDARTS, i.e., a cell.
  • Blocks 1 to 4 in Figure 5 represent four nodes, and the input predecessor edge of each node corresponds to an operation mode OP.
  • model_V1.0 is formed by multiple cells in series/parallel, and is also the structure of model_V2.0 (i.e., model DPSKD).
  • Step S8 Construct a new information transfer logic of the teacher-student network in the knowledge distillation algorithm, combine the chip fault category and fault degree to achieve the decoupling of the target class, target family class and all classes into three probability spaces, and obtain the knowledge transfer logic formula under different probability spaces.
  • the specific workflow and usage logic are shown in Figure 3.
  • This embodiment provides a computer-readable storage medium on which a computer program is stored.
  • the computer program is executed by a processor, the steps of the chip defect detection method described in the first embodiment are implemented.
  • These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

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Abstract

La présente invention se rapporte à un procédé et un système de détection de défaut de puce. Le procédé consiste à : acquérir un signal de vibration unidimensionnel d'une puce et convertir celui-ci en données d'image bidimensionnelle ; entraîner un algorithme NAS au moyen des données d'image bidimensionnelle, et optimiser l'algorithme NAS pour obtenir un modèle d'algorithme de recherche d'architecture neuronale ASNDARTS ; construire un modèle d'algorithme de distillation de connaissances DPSKD sur la base du modèle d'algorithme de recherche d'architecture neuronale ASNDARTS ; et acquérir un signal de vibration unidimensionnel d'une puce testée et le convertir en données d'image bidimensionnelle, et détecter les données d'image bidimensionnelle de la puce testée au moyen du modèle d'algorithme de distillation de connaissances DPSKD, de façon à déterminer si la puce testée présente un défaut. Dans la présente invention, l'algorithme NAS est optimisé, le procédé de transfert de distillation de connaissances est optimisé, et le modèle obtenu DPSKD améliore efficacement la précision de détection de défaut de puce tout en ayant une redondance de modèle réduite.
PCT/CN2024/128016 2023-12-28 2024-10-29 Procédé et système de détection de défaut de puce Pending WO2025139322A1 (fr)

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