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WO2025138007A1 - Power switching semiconductor device and method of packaging at least one power switching semiconductor device die in a package - Google Patents

Power switching semiconductor device and method of packaging at least one power switching semiconductor device die in a package Download PDF

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Publication number
WO2025138007A1
WO2025138007A1 PCT/CN2023/142816 CN2023142816W WO2025138007A1 WO 2025138007 A1 WO2025138007 A1 WO 2025138007A1 CN 2023142816 W CN2023142816 W CN 2023142816W WO 2025138007 A1 WO2025138007 A1 WO 2025138007A1
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WO
WIPO (PCT)
Prior art keywords
package
semiconductor device
power switching
switching semiconductor
electrode
Prior art date
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Pending
Application number
PCT/CN2023/142816
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French (fr)
Inventor
On Bon Peter Chan
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Tr Semiconductor Hk Ltd
Original Assignee
Tr Semiconductor Hk Ltd
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Filing date
Publication date
Application filed by Tr Semiconductor Hk Ltd filed Critical Tr Semiconductor Hk Ltd
Priority to PCT/CN2023/142816 priority Critical patent/WO2025138007A1/en
Priority to CN202420287146.8U priority patent/CN222355136U/en
Priority to CN202410172664.XA priority patent/CN120237011A/en
Publication of WO2025138007A1 publication Critical patent/WO2025138007A1/en
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material

Definitions

  • This invention relates to a power switching semiconductor device or module and a method of packaging at least one power switching semiconductor device die in a package.
  • Discrete power switching semiconductor device product normally is being packaged by conductive die-attachment of a power switching semiconductor device die substrate (back side) to a die pad (metal island) on a metal lead-frame structure which is being connected in the metal lead-frame to the pin out connecting ports of the package corresponding to the substrate of the power switching semiconductor device die.
  • the other two electrodes at the other (front) side of the power switching semiconductor device die are being connected to the other two corresponding pin out ports in the metal lead-frame by wire, foil, or clip bonding, with all three pin out connecting ports being short circuited by the metal lead-frame due to mechanical strength requirement of the structure.
  • molding of electronic molding compound (EMC) to form the insulating body is performed, followed by separating multiple package units into individual units, trim and form of metal pins of pin out connecting ports, if necessary, and final testing.
  • Figure 1 is a TOLL type package of a single MOSFET, which illustrate concept as discussed.
  • substrate (back side) 101 is connected to the die substrate by conductive die attachment while the other two contacts 102 and 103 are connected to the front side electrodes of the power semiconductor die by wire, foil or clip bonding.
  • the thermal resistance of the package is the limiting factor that limits the maximum power dissipation that can be tackled by the same power switching semiconductor device die.
  • a packaging method with reduced thermal is always preferred due to it mean improving the maximum power handling capability in actual applications.
  • a method of packaging at least one power switching semiconductor device die in a package comprising the following steps:
  • step (C) includes forming a hole through the insulating portion of the package for accessing at least one other electrode; step (D) includes forming a conductive path via the hole for connection of said at least one other electrode; and step (E) includes forming a conductive connection of said at least one other electrode to a respective pin out connecting port on the bottom side of the package.
  • the method includes step (H) of cutting the resulting package into a plurality of smaller packages each including one or more of the power switching semiconductor device dies.
  • the insulating portion includes at least one other layer of electronic molding compound encapsulating the power switching semiconductor device die and the preceding layer, with a said hole and a said conductive path via the hole associated with each layer.
  • Figures 3 (a) to 3 (d) show, each by way of a bottom view and four progressive cross-sectional side views, a first design embodiment of the invention to package a single power switching semiconductor device into product;
  • Figures 4 (a) to 4 (c) disclose, each by way of a circuit diagram and a bottom view, packaging of multiple power switching power semiconductor dies into various module products using the first design embodiment of the invention
  • Figure 5 is a circuit diagram of a three-phase bridge driver that can be packaged as a module product using the invention.
  • Figures 6 (a) to 6 (d) show, each by way of a bottom view and a cross-sectional side view, a second design embodiment of using the invention to package the circuit as shown in figure 5 as module product.
  • NPN bipolar device 201 N type MOSFET device 202
  • IGBT device 203 IGBT device 203
  • PNP bipolar device 204 P type MOSFET device 205. It should be noted that the list is just serving as examples and by no means to be exhaustive.
  • FIG. 3 (a) to 6 (d) of the drawings there are illustrated embodiments of a method of packaging at least one power switching semiconductor device die in a single package, and a resulting packaged power switching semiconductor device, all in accordance with the invention.
  • Figures 3 (a) to 3 (d) show a first preferred embodiment of a method using the invention to package at least one or in this particular instance a single power switching semiconductor device die 301.
  • the packaging method flow commences with attaching the substrate (back side) 302 of the power switching semiconductor device die 301 to an inner metal surface 309 of substrate of the package 30301, or 30302, or 30303 by conductive die attachment compound 304.
  • PCB without blind vias can also be used with increase in thermal resistance while electrical isolation between the die attachment pad and the exposed metal surface 309 (a) of the package is achieved.
  • PCB using ceramic as dielectric or ceramic insert 306 between the die attachment pad and the exposed metal surface 309 (a) may also be used to improve thermal conductivity while electrical isolation is also achieved.
  • the front side electrodes of the power switching semiconductor device die 301 namely control electrode 307 and switch electrode 308, together with the inner metal surface 309 of the package substrate 30301, or 30302, or 30303, can then be used in further processes according to the invention. Bottom view and cross-sectional side views of a package after this processing step are as illustrated in Figure 3 (a) .
  • an insulated portion 310 of the body of the package is formed by application of Electronic Molding Compound (EMC) .
  • EMC Electronic Molding Compound
  • injection molding process is used for this processing step.
  • Alternative processing methods such as dispensing followed by thermal curing may also be applied.
  • the metal interconnections between the three electrodes 302, 307 and 308 of the power switching semiconductor device die 301 and the corresponding pin out connecting ports of the package is then performed preferably by a process similar to bare PCB manufacturing. Processing steps involved may include, but not limited to, combinations of electroless metal plating, photographic process and metal etching to define electrical connective paths within the package as required. Bottom view and cross-sectional side views of a package up to the aforementioned processing steps are illustrated in Figure 3 (c) .
  • metal patterns 312, 313 and 314 are the connection metals from the bottom side of the package to respective switch electrode 308, control electrode 307 and substrate electrode 302 of the switching power semiconductor device die 301 via respective holes 311 in Figure 3 (b) underneath such metal patterns 312, 313 and 314. Further processing steps will then be taken to define the pin out connecting ports on these metal connecting patterns.
  • Pin out connecting ports surface processing similar to bare PCB manufacturing process such as solder mask, gold/silver plating, or solder tin hot air levelling, etc.
  • Bottom view and cross-sectional side views of a package up to the aforementioned processing steps are as illustrated in Figure 3 (d) .
  • 316, 317 and 318 are pin out connecting ports for the switch electrode 308, substrate electrode 302 and control electrode 307 respectively.
  • Solder mask 315 covers the area other than the pin out connecting ports 316-318 and dotted line shapes 312, 313 and 314 in the bottom view are metal traces underneath the solder mask as in Figure 3 (c) .
  • isolating polymer similar to solder mask in bare PCB manufacturing may be deposited to the top side of the package to cover exposed metal for heat transfer to the environment.
  • the method of packaging at least one power switching semiconductor device die in a package may be summarized to comprise at least the following steps:
  • step (C) may include forming a hole through the insulating portion of the package for accessing at least one other, e.g. back side, electrode.
  • step (D) includes forming a conductive path within the package via the hole for connection of said at least one other electrode
  • step (E) includes forming a conductive connection of said at least one other electrode to a respective pin out connecting port on the bottom side of the package.
  • the subject method of packaging may include step (F) of processing a surface of the pin out connecting port or ports of the package, and step (G) of testing the power switching semiconductor device die via the pin out connecting port or ports of the package.
  • the subject method of packaging includes, after step (D) and before step (E) , repeating steps (B) , (C) and (D) as steps (B' ) , (C’ ) and (D’ ) respectively one or more times, depending on the number of additional layer of insulting portion of the package is desired.
  • the power switching semiconductor device packaged by the described method may be summarized to comprise at least a power switching semiconductor device die having three electrodes that are a substrate electrode and two front side electrodes, and a package having a substrate with an island to which the power switching semiconductor device die is conductive die-attached, with the back side electrode facing a top side of the package.
  • the package has an insulating portion of electronic molding compound encapsulating the power switching semiconductor device die.
  • a conductive connection of the electrode or electrodes of the power switching semiconductor device die to a respective pin out connecting port on a bottom side of the package.
  • the power switching semiconductor device may include a hole through the insulating portion of the package for accessing at least one other, e.g. back side, electrode, a conductive path within the package via the hole for connection of said at least one other electrode, and a conductive connection of said at least one other electrode to a respective pin out connecting port on the bottom side of the package.
  • all three pin out connecting ports 316, 317, and 318 of each package are insulated by nature.
  • the two pin out connecting ports connected to the front side electrodes of the power switching semiconductor device die 301 for each individual package device are isolated from all other such pin out connecting ports of other packages manufactured in multiple packages as a single pass, with only the substrate pin out connecting ports of multiple packages connected. For these reasons, concurrent testing of multiple package units is made possible.
  • final testing of the packaged device is preferably carried out by concurrent testing of multiple package units in panel form, before it is separated into individual units.
  • final testing is preferably carried out by concurrent testing of multiple package units in panel form, before it is separated into individual units.
  • the normal process of separating into individual units prior to final testing remains possible.
  • FIG. 4 (a) to 4 (c) show some typical examples of semiconductor circuits that can be packaged using the subject invention.
  • FIG. 4 (a) a circuit diagram of three N type MOSFET devices 401, 402 and 403 with common drain (substrate) electrodes connecting to VDD and the corresponding bottom view of the package are shown as a potential candidate for using the invention with multiple die packaging.
  • N type MOSFET device dies 401, 402 and 403, namely G1, G2, G3, S1, S2 and S3, are connected to the respective pin out connecting ports of the package, and the substrate electrodes of the N type MOSFET device dies 401, 402 and 403 are connected to the VDD pin out connecting port of the package using processing steps as described in the previous embodiment.
  • the corresponding bottom view with pin out connecting ports of the package is also shown in Figure 4 (a) , with the dotted line shapes representing metal patterns underneath the solder mask.
  • the three packaged power switching semiconductor device dies can be used as the three high side devices in a three-phase bridge for various applications such as BLDC or induction motor drivers.
  • FIG. 4 (c) a circuit diagram of two N type MOSFET devices 406 and 407 with common drain (substrate) electrodes and the corresponding bottom view of the package are shown as yet another potential candidate for using the invention with multiple die packaging.
  • N type MOSFET devices 406 and 407 namely G6, G7, S6 and S7
  • the corresponding bottom view with pin out connecting ports of the package are also shown with the dotted line shapes representing metal patterns underneath the solder mask.
  • the target application for this packaged module is over-charging and over-discharging protection of lithium batteries. Since external pin out connection to the substrate node is not required, drilling of holes to reach the substrate may be eliminated during selective hole drilling process.
  • the N type MOSFET devices 501, 502 and 503 have a common drain (substrate) connection to the pin out connecting pad VDD, and hence sharing a common die-attach island in the package substrate.
  • each of N type MOSFET devices 504, 505 and 506 all require individual die-attach islands in package substrate that are isolated to fulfil the electrical circuit connections. Therefore, a package substrate with multiple (in this case, four) isolated die-attach islands will be required.
  • the packaging method flow of this second embodiment commences with attaching the substrates of the power switching semiconductor device dies 501-506 to respective die-attach islands of the package substrate by conductive die-attach compound.
  • Reference numerals 612-617 correspond to gate electrodes GUU, GUV, GUW, GLU, GLV and GLW respectively of the N type MOSFET device dies 501-506 of Figure 5.
  • Reference numerals 618-623 correspond to the source electrodes of the N type MOSFET device dies 501-506 respectively.
  • a metal pattern 639 is connected to the metal island 602 of Figure 6(a) via the holes 626 of Figure 6 (b) underneath the metal pattern 639. Since the drain (substrate) electrodes of the N type MOSFET device dies 501, 502 and 503 are all conductive die-attached to the metal island 602, which means that the metal pattern 639 is the equivalent circuit node VDD shown in Figure 5.
  • Metal patterns 627-632 are connected to the gate electrodes of the N type MOSFET device dies 501-506 respectively via the holes 625 of Figure 6 (b) underneath the metal patterns 627-632.
  • the electrical equivalent circuit nodes for the metal patterns 633-635 are U, V and W respectively of Figure 5.
  • Metal patterns 636-638 are connected to the source electrodes of the N type MOSFET device dies 504-506 via the holes 625 of Figure 6 (b) underneath the metal patterns 636-638.
  • the electrical equivalent circuit nodes for the metal patterns 636-638 are VSU, VSV and VSW respectively of Figure 5.
  • the equivalent circuit nodes for the pin out connecting ports 640-645 are GUU, GUV, GUW, GLU, GLV and GLW respectively of Figure 5.
  • the equivalent circuit nodes for the pin out connecting ports 646-651 are U, V, W, VSU, VSV and VSW respectively of Figure 5.
  • the equivalent circuit node for the pin out connecting port 652 is VDD of Figure 5.
  • Final testing of the packaged module is preferably carried out by concurrent testing of multiple package units in panel form, before the package units are separated into individual power switching units in the situation where a PCB substrate is used.
  • the normal process of separating the package units into individual units before final testing is applicable when a metal lead-frame substrate is used.
  • the subject method of packaging may include step (H) of cutting the resulting package into a plurality of smaller packages to form separate power switching units, each including one or more of the power switching semiconductor device dies.
  • the method involves packaging a plurality of power switching semiconductor device dies in the same package having a common package substrate, with each power switching semiconductor device die being subject to steps (A) to (G) .
  • the method may include step (H) , subsequent to step (G) , of cutting the resulting package into a plurality of smaller packages each including one or more of the power switching semiconductor device dies.
  • the invented packaging method replaces electrical connections between pin out connecting ports of the package and the corresponding metal connection pads of the power switching semiconductor device die (s) normally made by bonding process by a process similar to PCB manufacturing.
  • the substrate side (back side) of power switching semiconductor device die (s) attached to the metal island of package substrate of the package is facing upwards while pin out connecting ports of the package is facing downwards.
  • the die attachment metal island thermally conducted to environment (air) .
  • such packaging design provides a direct thermal dissipation path from the exposed metal surface of the package directly to the environment for reduction of thermal resistance.
  • such packaging method isolates other pin out connecting ports other than the substrate of the power switching device die (s) from each other when packaging is performed in batch of multiple packaged units. Hence, concurrent testing before separating multiple packaged devices into individual units is possible.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A power switching semiconductor device comprises a power switching semiconductor device die having three electrodes that are a substrate electrode and two front side electrodes, and a package having a substrate with an island to which the power switching semiconductor device die is conductive die-attached, with the back side electrode facing a top side of the package. The package has an insulating portion of electronic molding compound encapsulating the power switching semiconductor device die. There is a hole through the insulating portion of the package for accessing at least one electrode of the power switching semiconductor device die, and a conductive path via the hole connects said at least one electrode of the power switching semiconductor device die. Included is a conductive connection of the electrode or electrodes of the power switching semiconductor device die to a respective pin out connecting port on a bottom side of the package.Also disclosed is a method of packaging at least one power switching semiconductor device die in a package, comprising the following steps (A) conductive die-attaching the power switching semiconductor device die to an island of a substrate of the package, with the back side electrode facing a top side of the package; (B) encapsulating the power switching semiconductor device die with electronic molding compound to form an insulating portion of the package; (C) forming a hole through the insulating portion of the package for accessing at least one electrode of the power switching semiconductor device die; (D) forming a conductive path via the hole for connection of said at least one electrode of the power switching semiconductor device die; and (E) forming a conductive connection of the electrode or electrodes of the power switching semiconductor device die to a respective pin out connecting port on a bottom side of the package.

Description

POWER SWITCHING SEMICONDUCTOR DEVICE AND METHOD OF PACKAGING AT LEAST ONE POWER SWITCHING SEMICONDUCTOR DEVICE DIE IN A PACKAGE TECHNICAL FIELD
This invention relates to a power switching semiconductor device or module and a method of packaging at least one power switching semiconductor device die in a package.
BACKGROUND
Discrete power switching semiconductor device product normally is being packaged by conductive die-attachment of a power switching semiconductor device die substrate (back side) to a die pad (metal island) on a metal lead-frame structure which is being connected in the metal lead-frame to the pin out connecting ports of the package corresponding to the substrate of the power switching semiconductor device die. The other two electrodes at the other (front) side of the power switching semiconductor device die are being connected to the other two corresponding pin out ports in the metal lead-frame by wire, foil, or clip bonding, with all three pin out connecting ports being short circuited by the metal lead-frame due to mechanical strength requirement of the structure. After bonding process, molding of electronic molding compound (EMC) to form the insulating body is performed, followed by separating multiple package units into individual units, trim and form of metal pins of pin out connecting ports, if necessary, and final testing.
The difference in coefficient of thermal expansion (CTE) between metal bonding wires and the EMC insulating package body is a major concern in reliability of packaging process. Thermal cycling due to temperature rise happened during operation in actual application, and cooling down after power off will happened during the operating life of the packaged power switching semiconductor device. As the result of the thermal cycling and the difference in CTEs between metal and the CTE insulating body, mechanical stress between bonding wires and the plastic package body will be created during daily operations.
Various package designs of power switching semiconductor devices normally have the substrate side of the power switching semiconductor device die facing downwards such that pin out port of the substrate electrode of the power switching semiconductor device die will be on the same plane as the other two pin out connecting ports. Heat generated during the operation of such packaged power switching semiconductor device therefore needs to go through the body of the package, or a long distance to near the perimeter of the metal substrate, before heat can be conducted to the environment, or air. Hence, thermal resistance of the package is increased. Figure 1 is a TOLL type package of a single MOSFET, which illustrate concept as discussed. In Figure 1, substrate (back side) 101 is connected to the die substrate by conductive die attachment while the other two  contacts 102 and 103 are connected to the front side electrodes of the power semiconductor die by wire, foil or clip bonding.
In actual application, the thermal resistance of the package is the limiting factor that limits the maximum power dissipation that can be tackled by the same power switching semiconductor device die. For the same power switching semiconductor die, a packaging method with reduced thermal is always preferred due to it mean improving the maximum power handling capability in actual applications.
In addition, short circuit of pin out connecting ports of the packaged power switching semiconductor device during packaging prohibits testing of multiple units concurrently before separating multiple packaged devices into individual units, and hence limits the manufacturing efficiency. Thus, it is also desirable to devise a method to enable the possibility of concurrent testing of multiple packaged devices before separating into individual package units.
Therefore, solving or alleviating these known issues in packaging of power switching semiconductor device improves device reliability, power handling capability, and efficiency in packaging operations.
SUMMARY OF THE INVENTION
It is a first object of the invention to eliminate packaging reliability issue of power switching semiconductor device (s) due to use of bonding processes. It is a second object of the invention to reduce the thermal resistance for packaging of power switching semiconductor device (s) . It is a third object of the invention to enable the possibility of concurrent testing of multiple package units of power switching semiconductor device (s) before separating into individual package units. This invention aims to mitigate or at least to alleviate problems relating to at least one or more of the aforesaid issues.
According to one aspect of the invention, there is provided a method of packaging at least one power switching semiconductor device die in a package, the power switching semiconductor device die having three electrodes that are a back side electrode and two front side electrodes, the method comprising the following steps:
(A) conductive die-attaching the power switching semiconductor device die to an island of a substrate of the package, with the back side electrode facing a top side of the package;
(B) encapsulating the power switching semiconductor device die with electronic molding compound to form an insulating portion of the package;
(C) forming a hole through the insulating portion of the package for accessing at least one electrode of the power switching semiconductor device die;
(D) forming a conductive path via the hole for connection of said at least one electrode of the power switching semiconductor device die; and
(E) forming a conductive connection of the electrode or electrodes of the power switching semiconductor device die to a respective pin out connecting port on a bottom side of the package.
In a preferred embodiment, step (C) includes forming a hole through the insulating portion of the package for accessing at least one other electrode; step (D) includes forming a conductive path via the hole for connection of said at least one other electrode; and step (E) includes forming a conductive connection of said at least one other electrode to a respective pin out connecting port on the bottom side of the package.
Preferably, the method includes step (F) of processing a surface of the pin out connecting port or ports of the package.
More preferably, in step (F) the surface of the pin out connecting port or ports is processed by way of a relevant process as generally known in bare PCB manufacturing, such as solder mask, gold/silver plating, or tin solder hot air levelling.
It is preferred that the method includes step (G) of testing the power switching semiconductor device die via the pin out connecting port or ports of the package. In a preferred embodiment, the method involves packaging a plurality of said power switching semiconductor device dies in the same package having a common package substrate, with each power switching semiconductor device die being subject to the aforesaid steps.
More preferably, the method includes step (H) of cutting the resulting package into a plurality of smaller packages each including one or more of the power switching semiconductor device dies.
In another preferred embodiment, the method involves packaging a plurality of said power switching semiconductor device dies in the same package having a common package substrate, with each power switching semiconductor device die being subject to the aforesaid steps, and the method includes step (H) , subsequent to step (G) , of cutting the resulting package into a plurality of smaller packages each including one or more of the power switching semiconductor device dies.
Preferably, the substrate of the package is selected from a lead-frame and a bare PCB.
More preferably, the substrate of the package comprises a bare PCB selected from a double-sided or multi-layer PCB and a metal-based PCB for enhancing heat dissipation.
Further more preferably, the substrate of the package comprises a PCB with blind vias for heat transfer from the power switching semiconductor device die or dies to metal on the top side of the package.
Further more preferably, the substrate of the package comprises a PCB with ceramic insulation between the power switching semiconductor device die or dies and metal on the top side of the package for reduction of junction-to-case thermal resistance.
It is preferred that in step (B) the electronic molding compound is applied by way of a process selected from injection molding, and dispensing and high temperature hardening.
It is preferred that in step (C) the hole or holes are formed by way of laser drilling. It is preferred that in step (E) the conductive connection or connections are formed by way of a relevant process as generally known in bare PCB manufacturing, such as electroless plating, or patterning of conductive paths.
In a further preferred embodiment, the method includes, after step (D) and before step (E) , repeating steps (B) , (C) and (D) as steps (B') , (C’ ) and (D’ ) respectively at least one time as follows:
(B') encapsulating the resulting assembly with electronic molding compound to form another layer of insulating portion of the package;
(C’ ) forming a hole through all the insulating portions of the package for accessing at least one further electrode of the power switching semiconductor device die; and
(D’ ) forming a conductive path via the hole for connection of said at least one further electrode of the power switching semiconductor device die.
According to another aspect of the invention, there is provided a power switching semiconductor device comprising:
a power switching semiconductor device die having three electrodes that are a back side electrode and two front side electrodes;
a package having a substrate with an island to which the power switching semiconductor device die is conductive die-attached, with the back side electrode facing a top side of the package, the package having an insulating portion of electronic molding compound encapsulating the power switching semiconductor device die;
a hole through the insulating portion of the package for accessing at least one electrode of the power switching semiconductor device die;
a conductive path via the hole for connection of said at least one electrode of the power switching semiconductor device die; and
a conductive connection of the electrode or electrodes of the power switching semiconductor device die to a respective pin out connecting port on a bottom side of the package.
In a preferred embodiment, the power switching semiconductor device includes a hole through the insulating portion of the package for accessing at least one other electrode, a conductive path via the hole for connection of said at least one other electrode, and a conductive connection of said at least one other electrode to a respective pin out connecting port on the bottom side of the package.
Preferably, the pin out connecting port or ports of the package have a processed surface.
In another preferred embodiment, the power switching semiconductor device includes a plurality of said power switching semiconductor device dies packaged in the same package, with each power switching semiconductor device die being conductive die-attached to the same substrate and the back side electrode facing a top side of the package.
More preferably, the package has respective said insulating portions encapsulating the power switching semiconductor device dies, each insulating portion having a said hole and a said conductive path via the hole.
Preferably, the substrate of the package is selected from a lead-frame and a bare PCB.
More preferably, the substrate of the package comprises a bare PCB selected from a double-sided or multi-layer PCB and a metal-based PCB for enhancing heat dissipation.
Further more preferably, the substrate of the package comprises a PCB with blind vias for heat transfer from the power switching semiconductor device die or dies to metal on the top side of the package.
Further more preferably, the substrate of the package comprises a PCB with ceramic insulation between the power switching semiconductor device die or dies and metal on the top side of the package for reduction of junction-to-case thermal resistance.
In a further preferred embodiment, the insulating portion includes at least one other layer of electronic molding compound encapsulating the power switching semiconductor device die and the preceding layer, with a said hole and a said conductive path via the hole associated with each layer.
BRIEF DESCRIPTION OF DRAWINGS
Embodiments of the invention will now be described, by examples, with reference to the accompanying drawings, in which:
Figure 1 shows, by way of a top, a bottom and two side views, a TOLL type package of a single power MOSFET device product;
Figure 2 shows, by way of five schematic diagrams, some typical power switching semiconductor devices that can be packaged into products in accordance with the invention;
Figures 3 (a) to 3 (d) show, each by way of a bottom view and four progressive cross-sectional side views, a first design embodiment of the invention to package a single power switching semiconductor device into product;
Figures 4 (a) to 4 (c) disclose, each by way of a circuit diagram and a bottom view, packaging of multiple power switching power semiconductor dies into various module products using the first design embodiment of the invention;
Figure 5 is a circuit diagram of a three-phase bridge driver that can be packaged as a module product using the invention; and
Figures 6 (a) to 6 (d) show, each by way of a bottom view and a cross-sectional side view, a second design embodiment of using the invention to package the circuit as shown in figure 5 as module product.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
In Figure 2, there are shown some typical power switching semiconductor devices that can be packaged using this invention, namely NPN bipolar device 201, N type MOSFET device 202, IGBT device 203, PNP bipolar device 204, and P type MOSFET device 205. It should be noted that the list is just serving as examples and by no means to be exhaustive.
Common characteristics for all such power switching semiconductor devices are all of them have three electrodes, namely a substrate electrode serving as one side of the switching terminal at the substrate (normally referred as the back side) of the power switching semiconductor device die, and two other electrodes at the other side (normally referred to as the front side) of the power switching semiconductor device die, namely a control electrode that controls the on/off state of the power switching semiconductor device die, and another switching electrode for the power switching semiconductor device die.
Referring now to Figures 3 (a) to 6 (d) of the drawings, there are illustrated embodiments of a method of packaging at least one power switching semiconductor device die in a single package, and a resulting packaged power switching semiconductor device, all in accordance with the invention.
Figures 3 (a) to 3 (d) show a first preferred embodiment of a method using the invention to package at least one or in this particular instance a single power switching semiconductor device die 301. The packaging method flow commences with attaching the substrate (back side) 302 of the power switching semiconductor  device die 301 to an inner metal surface 309 of substrate of the package 30301, or 30302, or 30303 by conductive die attachment compound 304.
The substrate of the package is preferably metal lead-frame 30301 for achieving lower thermal resistance. Both thermal and electrical conduction between the power switching semiconductor device die 301 and the metal surface 309 (a) of the package at opposite side to the power switching semiconductor device die are achieved. The substrate of the package may also be various types of bare PCB 30302 (metal-based PCB such as aluminum or copper based, or normal PCB) with one exposed metal surface 309 (a) serving as the heat conduction media to outside environment such as air, and the other (inner) metal side 309 as the die attachment surface, being inter-linked through blind vias 305. As a particular example, PCB without blind vias can also be used with increase in thermal resistance while electrical isolation between the die attachment pad and the exposed metal surface 309 (a) of the package is achieved. PCB using ceramic as dielectric or ceramic insert 306 between the die attachment pad and the exposed metal surface 309 (a) may also be used to improve thermal conductivity while electrical isolation is also achieved. The front side electrodes of the power switching semiconductor device die 301, namely control electrode 307 and switch electrode 308, together with the inner metal surface 309 of the package substrate 30301, or 30302, or 30303, can then be used in further processes according to the invention. Bottom view and cross-sectional side views of a package after this processing step are as illustrated in Figure 3 (a) .
Subsequent to the die attachment process, an insulated portion 310 of the body of the package is formed by application of Electronic Molding Compound (EMC) . Preferably, injection molding process is used for this processing step. Alternative processing methods such as dispensing followed by thermal curing may also be applied.
Selective hole drilling through the insulated body of the package to reach the three electrodes 302, 307 and 308 of the power switching semiconductor device die 301 is then performed, preferably by laser drilling. Normally, holes 311 drilled will reach directly to the two electrodes 307 and 308 at bonding pads at the front side of the power switching semiconductor device die 301, and indirectly to the substrate electrode 302 of the power switching semiconductor device die 301 via the metal connection along the inner metal surface 309 within the substrate of the package 30301, or 30302, 30303. Bottom view and cross-sectional side views of a package up to the aforementioned processing steps are illustrated in Figure 3 (b) .
The metal interconnections between the three electrodes 302, 307 and 308 of the power switching semiconductor device die 301 and the corresponding pin out connecting ports of the package is then performed preferably by a process similar to bare PCB manufacturing. Processing steps involved may include, but not limited to, combinations of electroless metal plating, photographic process and metal etching to define electrical connective paths within the package as required. Bottom view and cross-sectional side views of a package up to the aforementioned processing steps are illustrated in Figure 3 (c) . In Figure 3 (c) , metal patterns 312, 313 and 314 are the connection metals from the bottom side of the package to  respective switch electrode 308, control electrode 307 and substrate electrode 302 of the switching power semiconductor device die 301 via respective holes 311 in Figure 3 (b) underneath such metal patterns 312, 313 and 314. Further processing steps will then be taken to define the pin out connecting ports on these metal connecting patterns.
Pin out connecting ports surface processing similar to bare PCB manufacturing process such as solder mask, gold/silver plating, or solder tin hot air levelling, etc. Bottom view and cross-sectional side views of a package up to the aforementioned processing steps are as illustrated in Figure 3 (d) . In Figure 3 (d) , 316, 317 and 318 are pin out connecting ports for the switch electrode 308, substrate electrode 302 and control electrode 307 respectively. Solder mask 315 covers the area other than the pin out connecting ports 316-318 and dotted line shapes 312, 313 and 314 in the bottom view are metal traces underneath the solder mask as in Figure 3 (c) .
Optionally, isolating polymer similar to solder mask in bare PCB manufacturing may be deposited to the top side of the package to cover exposed metal for heat transfer to the environment.
Based on the forgoing description, the method of packaging at least one power switching semiconductor device die in a package may be summarized to comprise at least the following steps:
(A) conductive die-attaching the power switching semiconductor device die to an island of a substrate of the package, with the back side or substrate electrode facing a top side of the package;
(B) encapsulating the power switching semiconductor device die with electronic molding compound to form an insulating portion of the package;
(C) forming a hole through the insulating portion of the package for accessing at least one, e.g. front side, electrode of the power switching semiconductor device die;
(D) forming a conductive path within the package via the hole for connection of said at least one electrode of the power switching semiconductor device die; and
(E) forming a conductive connection of the electrode or electrodes of the power switching semiconductor device die to a respective pin out connecting port on a bottom side of the package.
It is noted that step (C) may include forming a hole through the insulating portion of the package for accessing at least one other, e.g. back side, electrode. In this case, step (D) includes forming a conductive path within the package via the hole for connection of said at least one other electrode, and step (E) includes forming a conductive connection of said at least one other electrode to a respective pin out connecting port on the bottom side of the package.
The subject method of packaging may include step (F) of processing a surface of the pin out connecting port or ports of the package, and step (G) of testing the power switching semiconductor device die via the pin out connecting port or ports of the package.
As a variant of the described embodiment, after processing steps arriving at the resulting assembly of Figure 3 (c) , package body molding, selective drilling and internal connectivity realization may be repeated until arriving at the final layer of pin out connecting ports (i.e. bottom side of the package) , before performing solder mask and pin out connecting ports surface processing. It is envisaged that this and similar variants fall within the scope of the subject invention.
Referring to the repeated steps, they are:
· package body molding -step (B') encapsulating the resulting assembly with electronic molding compound to form another layer of insulating portion of the package;
· selective drilling -step (C’ ) forming a hole through all the insulating portions of the package for accessing at least one further electrode of the power switching semiconductor device die; and
· internal connectivity realization -step (D’ ) forming a conductive path within the package via the hole for connection of said at least one further electrode of the power switching semiconductor device die.
Taking these repeated steps into account, the subject method of packaging includes, after step (D) and before step (E) , repeating steps (B) , (C) and (D) as steps (B' ) , (C’ ) and (D’ ) respectively one or more times, depending on the number of additional layer of insulting portion of the package is desired.
Based on the forgoing description, the power switching semiconductor device packaged by the described method may be summarized to comprise at least a power switching semiconductor device die having three electrodes that are a substrate electrode and two front side electrodes, and a package having a substrate with an island to which the power switching semiconductor device die is conductive die-attached, with the back side electrode facing a top side of the package. The package has an insulating portion of electronic molding compound encapsulating the power switching semiconductor device die. There is a hole through the insulating portion of the package for accessing at least one, e.g. front side, electrode of the power switching semiconductor device die, and a conductive path within the package via the hole connects said at least one electrode of the power switching semiconductor device die. Also included is a conductive connection of the electrode or electrodes of the power switching semiconductor device die to a respective pin out connecting port on a bottom side of the package.
For some circuits, the power switching semiconductor device may include a hole through the insulating portion of the package for accessing at least one other, e.g. back side, electrode, a conductive path within the package via the hole for connection of said at least one other electrode, and a conductive connection of said at least one other electrode to a respective pin out connecting port on the bottom side of the package.
As all interconnections between the electrodes 302, 307 and 308 of the power switching semiconductor device die 301 and the respective pin out connecting  ports 316, 317, and 318 of the package are integrated within the package, bonding process has been eliminated, so bonding related packaging reliability issues do not exist in the packaged power switching semiconductor device of the subject invention.
In addition, since the substrate side die pad, which is thermally linked to the top side metal 309 (a) of the package, will be facing upwards and exposed to the environment (air or via additional heat sink) after soldering in PCBA, thermal resistance will be reduced compared to the existing packaging method with the substrate electrode facing downwards.
Furthermore, all three pin out connecting ports 316, 317, and 318 of each package are insulated by nature. In addition, the two pin out connecting ports connected to the front side electrodes of the power switching semiconductor device die 301 for each individual package device are isolated from all other such pin out connecting ports of other packages manufactured in multiple packages as a single pass, with only the substrate pin out connecting ports of multiple packages connected. For these reasons, concurrent testing of multiple package units is made possible.
As discussed, final testing of the packaged device is preferably carried out by concurrent testing of multiple package units in panel form, before it is separated into individual units. Of course, the normal process of separating into individual units prior to final testing remains possible.
Another variant of the described embodiment is the packaging of multiple power switching semiconductor device dies with common substrate electrodes for applications in a single package using the same aforesaid processing steps. In this regard, Figures 4 (a) to 4 (c) show some typical examples of semiconductor circuits that can be packaged using the subject invention.
In Figure 4 (a) , a circuit diagram of three N type MOSFET devices 401, 402 and 403 with common drain (substrate) electrodes connecting to VDD and the corresponding bottom view of the package are shown as a potential candidate for using the invention with multiple die packaging.
The corresponding gate and source electrodes of N type MOSFET device dies 401, 402 and 403, namely G1, G2, G3, S1, S2 and S3, are connected to the respective pin out connecting ports of the package, and the substrate electrodes of the N type MOSFET device dies 401, 402 and 403 are connected to the VDD pin out connecting port of the package using processing steps as described in the previous embodiment. The corresponding bottom view with pin out connecting ports of the package is also shown in Figure 4 (a) , with the dotted line shapes representing metal patterns underneath the solder mask. The three packaged power switching semiconductor device dies (N type MOSFETs) can be used as the three high side devices in a three-phase bridge for various applications such as BLDC or induction motor drivers.
In Figure 4 (b) , a circuit diagram and bottom view of corresponding package for one P type MOSFET device 404 and one N type MOSFET device 405 with  common drain (substrate) electrodes connecting to the output pin out of the package are shown as another potential candidate for using the invention with multiple die packaging.
The source electrode of the P type MOSFET device 404 and the source electrode of the N type MOSFET 405 device are connected to the VDD and VSS pinout connecting ports of the package respectively. The gate electrode of the P type MOSFET device 404 and the gate electrode of the N type MOSFET 405 device are connected to the pinout connecting ports G4 and G5 of the package respectively. The substrate electrode of the P type MOSFET device 404 and the substrate electrode of the N type MOSFET 405 device are connected to the output pinout connecting port of the package. Processing steps for such packaging are as described in the previous embodiment. The corresponding bottom view with pin out connecting ports of the package is also shown with the dotted line shapes representing metal patterns underneath the solder mask. This packaged circuit can be used as a half-bridge driver for power switching conversion, or motor drivers.
In Figure 4 (c) , a circuit diagram of two N type MOSFET devices 406 and 407 with common drain (substrate) electrodes and the corresponding bottom view of the package are shown as yet another potential candidate for using the invention with multiple die packaging.
The corresponding gate and source electrodes of N type MOSFET devices 406 and 407, namely G6, G7, S6 and S7, are connected to the respective pin out connecting ports of the package using processing steps as described in the previous embodiment. The corresponding bottom view with pin out connecting ports of the package are also shown with the dotted line shapes representing metal patterns underneath the solder mask. The target application for this packaged module is over-charging and over-discharging protection of lithium batteries. Since external pin out connection to the substrate node is not required, drilling of holes to reach the substrate may be eliminated during selective hole drilling process.
In general, for multiple die packaging, the method involves packaging a plurality of power switching semiconductor device dies in the same package having a common package substrate, with each power switching semiconductor device die being subject to at least steps (A) to (E) and optionally steps (F) and (G) . In the packaged product, the substrate has respective portions or islands to which the power switching semiconductor device dies are conductive die-attached. Each power switching semiconductor device die is conductive die-attached to the same substrate, with its back side electrode facing a top side of the package. The package has respective insulating portions encapsulating the power switching semiconductor device dies, each insulating portion having a said hole of step (C) and a said conductive path via the hole of step (D) .
For more complicated circuits, more layers for routing of interconnections will be required. Use of an additional or more layers sandwiched between the PCB package substrate can be used to solve the routing problem. Alternatively,  repeated uses of EMC molding, selective hole drilling, and conductive path making using processes similar to bare PCB making as described previously can also be used. Thus, in the resulting power switching semiconductor device product, the insulating portion includes at least one other layer of electronic molding compound encapsulating the power switching semiconductor device die and the preceding layer, with a said hole of step (C) and a said conductive path via the hole of step (D) associated with each layer.
It should be noted that the examples described are given merely as typical examples and are by no means exhaustive.
In the description so far, there is a limitation of common substrate connections within the package for packaging of multiple switching semiconductor device dies. This may limit the adoption of the invention as separation of substrate electrodes is quite usual in many application circuits.
It is disclosed herein a second embodiment of the invention in which the limitation of common substrate can be avoided. Figure 5 is a circuit diagram of a three-phase bridge driver with six N type MOSFET device dies 501-506 having substrate electrodes that cannot be short circuited together. Typical applications of this semiconductor circuit are power drivers for BLDC or induction motors. This semiconductor circuit is now used as a candidate to illustrate the second embodiment of this invention to package the circuit as a module.
In Figure 5, the N type MOSFET devices 501, 502 and 503 have a common drain (substrate) connection to the pin out connecting pad VDD, and hence sharing a common die-attach island in the package substrate. However, each of N type MOSFET devices 504, 505 and 506 all require individual die-attach islands in package substrate that are isolated to fulfil the electrical circuit connections. Therefore, a package substrate with multiple (in this case, four) isolated die-attach islands will be required.
As to the first embodiment, using a metal lead-frame with multiple die-attach islands as the package substrate is possible provided that there is no need for concurrent testing of multiple packaged modules before separating into individual modules. With the use of a PCB substrate, the advantage of such concurrent testing can also be taken.
Figures 6 (a) to 6 (d) show a preferred embodiment of using the method of the invention to package six N type MOSFET device dies 501-506 according to the circuit of Figure 5 into a package module. In these figures, although only the use of PCB with blind vias in between die-attach islands and exposed metal surfaces of the package as package substrate is disclosed, it should be understood that the use of other types of package substrate are equally possible.
The packaging method flow of this second embodiment commences with attaching the substrates of the power switching semiconductor device dies 501-506 to respective die-attach islands of the package substrate by conductive die-attach compound.
The substrate of the package is preferably one selected from various types of bare PCB (metal-based PCB such as aluminum or copper based, or normal PCB) with multiple exposure metal surfaces serving as the heat conduction media to outside environment such as air, and the other side as the die attachment surfaces, being inter-linked through blind vias.
As a particular example, PCB without blind vias can also be used with increase in thermal resistance while electrical isolation between the die attachment pad and the exposed metal surface of the package is achieved. PCB using ceramic as dielectric or ceramic inserts between the die attachment islands and the exposed metal surfaces side may also be used to improve thermal conductivity while electrical isolation is also achieved.
Bottom view and cross-sectional side view of a package produced by the subject method using a metal-based PCB with blind vias connecting top metal islands for heat dissipation to environment and inner die-attach islands are as illustrated in Figure 6 (a) . In Figure 6 (a) , N type MOSFET device dies 501, 502 and 503 are attached to an inner metal island 602 of a package substrate 601 using conductive die attachment compound 606. N type MOSFET device dies 504, 505 and 506 are attached to respective inner metal islands 603, 604 and 605 of the package substrate 601 using conductive die attachment compound 606. Thermal and electrical conductions between the inner metal island 602 and an exposed metal surface 608 at top of the package substrate 601 are established through blind vias 607. Thermal and electrical conductions between the inner metal islands 603, 604 and 605 and exposed metal surfaces 609, 610, and 611 respectively at top of the package substrate 601 are established through blind vias 607. Reference numerals 612-617 correspond to gate electrodes GUU, GUV, GUW, GLU, GLV and GLW respectively of the N type MOSFET device dies 501-506 of Figure 5. Reference numerals 618-623 correspond to the source electrodes of the N type MOSFET device dies 501-506 respectively.
The substrate of the package may also be a metal lead-frame for achieving lower thermal resistance. Both thermal and electrical conductions between the power switching semiconductor device dies and the exposed top metal surfaces of the package at opposite side to the power switching semiconductor device dies are achieved. After the die attachment process, an insulated portion of the body of the package is formed by application of Electronic Molding Compound (EMC) 624. Preferably, injection molding process is used for this processing step. Alternative processing methods such as dispensing followed by thermal curing may also be used.
Selective hole drilling through the insulated body 624 of the package to reach the respective three electrodes of the six N type MOSFET device dies 501-506 is then performed, preferably by laser drilling. Bottom view and cross-sectional side view of a package up to the aforementioned processing steps are illustrated in Figure 6(b) . In Figure 6 (b) , there are two types of holes, namely holes 625 and holes 626. Holes 625 drilled will arrive directly at the two electrodes at bonding pads on the front side of the six N type MOSFET device dies 501-506. Holes 626 drilled will  reach the substrate electrode (back side) of the six N type MOSFET device dies 501-506 indirectly via inner metal islands 602-605 in Figure 6 (a) of the package substrate.
Metal interconnections between the electrodes of the six N type MOSFET device dies 501-506 and the corresponding locations of pin out connecting ports at the perimeter of the package are then made preferably by a process similar to bare PCB manufacturing.
The processing steps involved may include, but not limited to, combinations of electroless metal plating, photographic process and metal etching to define electrical connectivity paths required. Bottom view and cross-sectional side view of a package module subsequent to the making of metal connections between the electrodes of the six N type MOSFET device dies 501-506 and the corresponding locations of pin out connecting ports at the perimeter of the package are illustrated in Figure 6 (c) .
In Figure 6 (c) , a metal pattern 639 is connected to the metal island 602 of Figure 6(a) via the holes 626 of Figure 6 (b) underneath the metal pattern 639. Since the drain (substrate) electrodes of the N type MOSFET device dies 501, 502 and 503 are all conductive die-attached to the metal island 602, which means that the metal pattern 639 is the equivalent circuit node VDD shown in Figure 5. Metal patterns 627-632 are connected to the gate electrodes of the N type MOSFET device dies 501-506 respectively via the holes 625 of Figure 6 (b) underneath the metal patterns 627-632. The electrical equivalent circuit nodes for the metal patterns 627-632 are GUU, GUV, GUW, GLU, GLV and GLW respectively shown in Figure 5. Metal patterns 633-635 are connected to the source electrodes of the N type MOSFET device dies 501-503 via the holes 625 of Figure 6 (b) underneath the metal patterns 633-635, as well as to the metal islands 603-605 respectively of Figure 6 (a) vis the holes 626 of Figure 6 (b) underneath the metal patterns 633-635. The metal patterns 633-635 are also connected to the die attachment metal islands 603-605 of Figure 6 (a) via the holes 626 of Figure 6 (b) , and hence electrically connected to the substrate electrodes (drains) of the N type MOSFET device dies 504-506 respectively. The electrical equivalent circuit nodes for the metal patterns 633-635 are U, V and W respectively of Figure 5. Metal patterns 636-638 are connected to the source electrodes of the N type MOSFET device dies 504-506 via the holes 625 of Figure 6 (b) underneath the metal patterns 636-638. The electrical equivalent circuit nodes for the metal patterns 636-638 are VSU, VSV and VSW respectively of Figure 5.
Pin out connecting ports surface processing such as solder mask, gold/silver plating, or solder tin hot air levelling, etc, are then carried out. Bottom view and cross-sectional side view of a packaged module subsequent to pin out connecting ports surface processing are shown in Figure 6 (d) . In Figure 6 (d) , the patterns shown in dotted lines in the bottom view are the same as the metal patterns in the bottom view of Figure 6 (c) . Solder mask processing is applied so that an isolating solder mask 653 covers the whole bottom side of the package except the pin out connecting ports 613-652. Further surface processing such as gold/silver plating or tin solder hot air levelling is then applied to the pin out connecting ports 613- 652. The equivalent circuit nodes for the pin out connecting ports 640-645 are GUU, GUV, GUW, GLU, GLV and GLW respectively of Figure 5. The equivalent circuit nodes for the pin out connecting ports 646-651 are U, V, W, VSU, VSV and VSW respectively of Figure 5. The equivalent circuit node for the pin out connecting port 652 is VDD of Figure 5.
As a variant of this embodiment, subsequent to the processing steps resulting in the assembly of Figure 6 (c) , package body molding, selective drilling and internal connectivity realization may be repeated until arriving at the final layer of pin out connecting ports, before pin out connecting ports surface processing, such as solder mask, is performed. It is envisaged that this and similar variants fall within the scope of the subject invention.
Final testing of the packaged module is preferably carried out by concurrent testing of multiple package units in panel form, before the package units are separated into individual power switching units in the situation where a PCB substrate is used. The normal process of separating the package units into individual units before final testing is applicable when a metal lead-frame substrate is used.
Thus, for multiple die packaging, the subject method of packaging may include step (H) of cutting the resulting package into a plurality of smaller packages to form separate power switching units, each including one or more of the power switching semiconductor device dies. In general, the method involves packaging a plurality of power switching semiconductor device dies in the same package having a common package substrate, with each power switching semiconductor device die being subject to steps (A) to (G) . The method may include step (H) , subsequent to step (G) , of cutting the resulting package into a plurality of smaller packages each including one or more of the power switching semiconductor device dies.
The foregoing description so far only covers packaging of power switching semiconductor device (s) . It is envisaged that co-packaging of power switching semi-conductor device (s) together with other semiconductor device (s) using the same basic concept of this invention obviously falls within the scope of the invention.
The invented packaging method replaces electrical connections between pin out connecting ports of the package and the corresponding metal connection pads of the power switching semiconductor device die (s) normally made by bonding process by a process similar to PCB manufacturing. In addition, the substrate side (back side) of power switching semiconductor device die (s) attached to the metal island of package substrate of the package is facing upwards while pin out connecting ports of the package is facing downwards. With the die attachment metal island thermally conducted to environment (air) . such packaging design provides a direct thermal dissipation path from the exposed metal surface of the package directly to the environment for reduction of thermal resistance. Furthermore, such packaging method isolates other pin out connecting ports other than the substrate of the power switching device die (s) from each other when packaging is performed in batch of multiple packaged units. Hence, concurrent  testing before separating multiple packaged devices into individual units is possible.

Claims (26)

  1. A method of packaging at least one power switching semiconductor device die in a package, the power switching semiconductor device die having three electrodes that are a back side electrode and two front side electrodes, the method comprising the following steps:
    (A) conductive die-attaching the power switching semiconductor device die to an island of a substrate of the package, with the back side electrode facing a top side of the package;
    (B) encapsulating the power switching semiconductor device die with electronic molding compound to form an insulating portion of the package;
    (C) forming a hole through the insulating portion of the package for accessing at least one electrode of the power switching semiconductor device die;
    (D) forming a conductive path via the hole for connection of said at least one electrode of the power switching semiconductor device die; and
    (E) forming a conductive connection of the electrode or electrodes of the power switching semiconductor device die to a respective pin out connecting port on a bottom side of the package.
  2. The method as claimed in claim 1, wherein:
    step (C) includes forming a hole through the insulating portion of the package for accessing at least one other electrode;
    step (D) includes forming a conductive path via the hole for connection of said at least one other electrode; and
    step (E) includes forming a conductive connection of said at least one other electrode to a respective pin out connecting port on the bottom side of the package.
  3. The method as claimed in claim 1 or claim 2, wherein the method includes step (F) of processing a surface of the pin out connecting port or ports of the package.
  4. The method as claimed in claim 3, wherein in step (F) the surface of the pin out connecting port or ports is processed by way of a relevant process as generally known in bare PCB manufacturing, such as solder mask, gold/silver plating, or tin solder hot air levelling.
  5. The method as claimed in claim 3 or claim 4, wherein the method includes step (G) of testing the power switching semiconductor device die via the pin out connecting port or ports of the package.
  6. The method as claimed in any one of claims 1 to 5, wherein the method involves packaging a plurality of said power switching semiconductor device dies in the same package having a common package substrate, with each power switching semiconductor device die being subject to the aforesaid steps.
  7. The method as claimed in claim 6, wherein the method includes step (H) of cutting the resulting package into a plurality of smaller packages each including one or more of the power switching semiconductor device dies.
  8. The method as claimed in claim 5, wherein the method involves packaging a plurality of said power switching semiconductor device dies in the same package having a common package substrate, with each power switching semiconductor device die being subject to the aforesaid steps, and wherein the method includes step (H) , subsequent to step (G) , of cutting the resulting package into a plurality of smaller packages each including one or more of the power switching semiconductor device dies.
  9. The method as claimed in any one of claims 1 to 8, wherein the substrate of the package is selected from a lead-frame and a bare PCB.
  10. The method as claimed in claim 9, wherein the substrate of the package comprises a bare PCB selected from a double-sided or multi-layer PCB and a metal-based PCB for enhancing heat dissipation.
  11. The method as claimed in claim 10, wherein the substrate of the package comprises a PCB with blind vias for heat transfer from the power switching semiconductor device die or dies to metal on the top side of the package.
  12. The method as claimed in claim 10, wherein the substrate of the package comprises a PCB with ceramic insulation between the power switching semiconductor device die or dies and metal on the top side of the package for reduction of junction-to-case thermal resistance.
  13. The method as claimed in any one of claims 1 to 12, wherein in step (B) the electronic molding compound is applied by way of a process selected from injection molding, and dispensing and high temperature hardening.
  14. The method as claimed in any one of claims 1 to 13, wherein in step (C) the hole or holes are formed by way of laser drilling.
  15. The method as claimed in any one of claims 1 to 14, wherein in step (E) the conductive connection or connections are formed by way of a relevant process as generally known in bare PCB manufacturing, such as electroless plating, or patterning of conductive paths.
  16. The method as claimed in any one of claims 1 to 15, wherein the method includes, after step (D) and before step (E) , repeating steps (B) , (C) and (D) as steps (B') , (C’) and (D’) respectively at least one time as follows:
    (B') encapsulating the resulting assembly with electronic molding compound to form another layer of insulating portion of the package;
    (C’) forming a hole through all the insulating portions of the package for accessing at least one further electrode of the power switching semiconductor device die; and
    (D’) forming a conductive path via the hole for connection of said at least one further electrode of the power switching semiconductor device die.
  17. A power switching semiconductor device comprising:
    a power switching semiconductor device die having three electrodes that are a back side electrode and two front side electrodes;
    a package having a substrate with an island to which the power switching semiconductor device die is conductive die-attached, with the back side electrode facing a top side of the package, the package having an insulating portion of electronic molding compound encapsulating the power switching semiconductor device die;
    a hole through the insulating portion of the package for accessing at least one electrode of the power switching semiconductor device die;
    a conductive path via the hole for connection of said at least one electrode of the power switching semiconductor device die; and
    a conductive connection of the electrode or electrodes of the power switching semiconductor device die to a respective pin out connecting port on a bottom side of the package.
  18. The power switching semiconductor device as claimed in claim 17, including a hole through the insulating portion of the package for accessing at least one other electrode, a conductive path via the hole for connection of said at least one other electrode, and a conductive connection of said at least one other electrode to a respective pin out connecting port on the bottom side of the package.
  19. The power switching semiconductor device as claimed in claim 17 or claim 18, wherein the pin out connecting port or ports of the package have a processed surface.
  20. The power switching semiconductor device as claimed in any one of claims 17 to 19, including a plurality of said power switching semiconductor device dies packaged in the same package, with each power switching semiconductor device die being conductive die-attached to the same substrate and the back side electrode facing a top side of the package.
  21. The power switching semiconductor device as claimed in 20, wherein the package has respective said insulating portions encapsulating the power switching semiconductor device dies, each insulating portion having a said hole and a said conductive path via the hole.
  22. The power switching semiconductor device as claimed in any one of claims 17 to 21, wherein the substrate of the package is selected from a lead-frame and a bare PCB.
  23. The power switching semiconductor device as claimed in claim 22, wherein the substrate of the package comprises a bare PCB selected from a double-sided or multi-layer PCB and a metal-based PCB for enhancing heat dissipation.
  24. The power switching semiconductor device as claimed in claim 23, wherein the substrate of the package comprises a PCB with blind vias for heat transfer from the power switching semiconductor device die or dies to metal on the top side of the package.
  25. The power switching semiconductor device as claimed in claim 23, wherein the substrate of the package comprises a PCB with ceramic insulation between the power switching semiconductor device die or dies and metal on the top side of the package for reduction of junction-to-case thermal resistance.
  26. The power switching semiconductor device as claimed in any one of claims 17 to 25, wherein the insulating portion includes at least one other layer of electronic molding compound encapsulating the power switching semiconductor device die and the preceding layer, with a said hole and a said conductive path via the hole associated with each layer.
PCT/CN2023/142816 2023-12-28 2023-12-28 Power switching semiconductor device and method of packaging at least one power switching semiconductor device die in a package Pending WO2025138007A1 (en)

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PCT/CN2023/142816 WO2025138007A1 (en) 2023-12-28 2023-12-28 Power switching semiconductor device and method of packaging at least one power switching semiconductor device die in a package
CN202420287146.8U CN222355136U (en) 2023-12-28 2024-02-07 Power switch semiconductor device
CN202410172664.XA CN120237011A (en) 2023-12-28 2024-02-07 Power switching semiconductor device and method of packaging at least one power switching semiconductor device die in a package

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110118332A (en) * 2010-04-23 2011-10-31 엘지이노텍 주식회사 Light emitting device, light emitting device package and manufacturing method
CN107591452A (en) * 2017-10-10 2018-01-16 无锡新洁能股份有限公司 A kind of wafer scale power semiconductor and preparation method thereof
CN110571153A (en) * 2018-06-05 2019-12-13 宁波比亚迪半导体有限公司 Semiconductor power device and preparation method thereof
CN113937006A (en) * 2020-06-29 2022-01-14 英飞凌科技奥地利有限公司 Power module with metal substrate
CN115274599A (en) * 2021-04-30 2022-11-01 英飞凌科技奥地利有限公司 Semiconductor module having wire loops exposed from molded body and method of manufacturing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110118332A (en) * 2010-04-23 2011-10-31 엘지이노텍 주식회사 Light emitting device, light emitting device package and manufacturing method
CN107591452A (en) * 2017-10-10 2018-01-16 无锡新洁能股份有限公司 A kind of wafer scale power semiconductor and preparation method thereof
CN110571153A (en) * 2018-06-05 2019-12-13 宁波比亚迪半导体有限公司 Semiconductor power device and preparation method thereof
CN113937006A (en) * 2020-06-29 2022-01-14 英飞凌科技奥地利有限公司 Power module with metal substrate
CN115274599A (en) * 2021-04-30 2022-11-01 英飞凌科技奥地利有限公司 Semiconductor module having wire loops exposed from molded body and method of manufacturing the same

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