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WO2025134548A1 - Dispositif à semi-conducteur et appareil électronique - Google Patents

Dispositif à semi-conducteur et appareil électronique Download PDF

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Publication number
WO2025134548A1
WO2025134548A1 PCT/JP2024/038579 JP2024038579W WO2025134548A1 WO 2025134548 A1 WO2025134548 A1 WO 2025134548A1 JP 2024038579 W JP2024038579 W JP 2024038579W WO 2025134548 A1 WO2025134548 A1 WO 2025134548A1
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Prior art keywords
layer
semiconductor
gate electrode
semiconductor device
semiconductor layer
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Japanese (ja)
Inventor
竜舞 斎藤
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]

Definitions

  • This disclosure relates to semiconductor devices and electronic devices.
  • a semiconductor device has been proposed that includes a barrier layer having a negative ion region.
  • Semiconductor devices are required to suppress increases in leakage current.
  • a semiconductor device includes a channel layer including a first nitride semiconductor, a semiconductor layer including a second nitride semiconductor and stacked with the channel layer, a gate electrode and a drain electrode provided above the semiconductor layer, a first insulating film provided above the semiconductor layer between the gate electrode and the drain electrode, and a second insulating film including silicon and stacked with the first insulating film.
  • the semiconductor layer includes a halogen element below the gate electrode.
  • the silicon content of the semiconductor layer below the gate electrode and the drain electrode is 2 atomic % or less.
  • An electronic device includes a circuit having a channel layer including a first nitride semiconductor, a semiconductor layer including a second nitride semiconductor and stacked with the channel layer, a gate electrode and a drain electrode provided above the semiconductor layer, a first insulating film provided above the semiconductor layer between the gate electrode and the drain electrode, and a second insulating film including silicon and stacked with the first insulating film.
  • the semiconductor layer includes a halogen element below the gate electrode.
  • the silicon content of the semiconductor layer below the gate electrode and the drain electrode is 2 atomic % or less.
  • FIG. 1 is a diagram for explaining a configuration example of a semiconductor device according to an embodiment of the present disclosure.
  • FIG. 2 is a diagram for explaining an example of a composition distribution in a semiconductor device according to an embodiment of the present disclosure.
  • FIG. 3A is a diagram showing an example of the composition of each layer of the semiconductor device of the present disclosure.
  • FIG. 3B is a diagram showing an example of the composition of each layer of the semiconductor device of the present disclosure.
  • FIG. 4 is a diagram showing a leak path in a semiconductor device according to a comparative example.
  • FIG. 5 is a diagram for explaining a configuration example of a semiconductor device according to an embodiment of the present disclosure.
  • FIG. 6 is a diagram for explaining a configuration example of a semiconductor device according to an embodiment of the present disclosure.
  • FIG. 7 is a diagram for explaining a configuration example of a semiconductor device according to the first modification of the present disclosure.
  • FIG. 8 is a diagram illustrating an example of the configuration of a wireless communication device according to
  • Fig. 1 is a diagram for explaining a configuration example of a semiconductor device according to an embodiment of the present disclosure.
  • Fig. 1 shows an example of a cross-sectional configuration of the semiconductor device 1.
  • the semiconductor device 1 is configured, for example, using a compound semiconductor, and can be applied to a device (circuit) that processes high-frequency signals.
  • the semiconductor device 1 is configured, for example, using a III-V group compound semiconductor, and can be applied to a communication device as a high-frequency circuit.
  • the semiconductor device 1 is formed using a nitride semiconductor, for example, GaN (gallium nitride).
  • GaN gallium nitride
  • GaN gallium nitride
  • GaN is a wide-gap semiconductor material and has a wide band gap.
  • GaN also has characteristics such as high voltage resistance, high heat resistance, and high saturated drift velocity.
  • the two-dimensional electron gas (2DEG) formed in GaN-based heterojunctions has the characteristics of high mobility and high sheet electron density. Due to these characteristics, GaN-based heterojunction FETs (HFETs: Hetero Field Effect Transistors) have low resistance and are capable of high-speed operation and high-voltage operation.
  • HFETs Hetero Field Effect Transistors
  • Schottky HEMTs with a Schottky structure are characterized by small characteristic fluctuations (e.g., fluctuations in threshold voltage during operation, drain lag, etc.).
  • GaN-based HFETs can be suitably used in power devices, RF devices, etc.
  • GaN-based HFETs may be applied to high-frequency devices for fifth-generation mobile communications (5G).
  • the semiconductor device 1 may be applied to an integrated circuit such as an MMIC (Monolithic Microwave Integrated Circuit).
  • the semiconductor device 1 can be used in electronic devices that use frequency bands such as the microwave band and the millimeter wave band.
  • the semiconductor device 1 can be applied to, for example, a switch circuit for RF signals, a power amplifier circuit, a filter circuit, etc.
  • the semiconductor device 1 is configured as a field effect transistor (FET) having gate, source, and drain terminals.
  • FET field effect transistor
  • the semiconductor device 1 is, for example, a heterojunction FET (HFET) and is configured using compound semiconductors.
  • HFET heterojunction FET
  • the semiconductor device 1 may have a two-dimensional electron gas (two-dimensional electron gas layer) formed using a heterojunction.
  • the semiconductor device 1 includes, for example, a gate using a Schottky junction, and is configured as a transistor having a Schottky gate.
  • the semiconductor device 1 has a Schottky-type gate structure, and may also be called a Schottky FET.
  • the semiconductor device 1 has a substrate 10, a buffer layer 21, a channel layer 22, a spacer layer 23, a barrier layer 24, a protective layer 25, a semiconductor region 26a, and a semiconductor region 26b.
  • the semiconductor device 1 also has an insulating film 31, an insulating film 32, a gate electrode 40, a source electrode 50a, and a drain electrode 50b.
  • the substrate 10 is made of a semiconductor material, for example, a III-V compound semiconductor material.
  • the substrate 10 may be made of GaN.
  • the substrate 10 may be another substrate, such as a SiC (silicon carbide) substrate, a sapphire substrate, or a Si (silicon) substrate.
  • the lattice constant can be controlled by providing a buffer layer 21, which will be described later, and the substrate 10 may be a SiC substrate, a sapphire substrate, a Si substrate, or the like.
  • the buffer layer 21 is provided so as to be laminated on the substrate 10.
  • the buffer layer 21 is provided on the substrate 10 and is located between the substrate 10 and the channel layer 22.
  • the buffer layer 21 is made of, for example, AlN, AlGaN, GaN, etc.
  • the buffer layer 21 can be made of a compound semiconductor layer epitaxially grown on the substrate 10.
  • the lattice constant of the substrate 10 differs from that of the channel layer 22, the lattice constant can be controlled (adjusted) by the buffer layer 21 to improve the crystal state of the channel layer 22 and suppress warping (warping of the substrate 10, channel layer 22, etc.).
  • the buffer layer 21 may be used as the buffer layer 21.
  • the channel layer 22 is made of a compound semiconductor, for example, a nitride semiconductor.
  • the channel layer 22 is a semiconductor layer containing a nitride semiconductor, and is made of, for example, GaN.
  • the channel layer 22 is provided so as to be stacked above the substrate 10. In the example shown in FIG. 1, the channel layer 22 is formed on the buffer layer 21, and is located between the buffer layer 21 and the spacer layer 23.
  • the channel layer 22 and the barrier layer 24 may be composed of different compound semiconductors.
  • the channel layer 22 and the barrier layer 24 may be composed of, for example, different nitride semiconductors.
  • the channel layer 22 and the barrier layer 24 may be configured to have different bandgaps.
  • the channel layer 22 is, for example, an epitaxially grown layer of GaN, and is a region in which carriers (signal charges) are accumulated due to polarization in the channel layer 22 and the barrier layer 24.
  • the channel layer 22 can generate and accumulate charges due to the difference in polarization with the barrier layer 24.
  • the channel layer 22 forms part of the current path between the source electrode 50a and the drain electrode 50b.
  • the semiconductor device 1 carriers are induced by polarization in the channel layer 22 and the barrier layer 24, and a two-dimensional electron gas (2DEG) is formed at the interface between the channel layer 22 and the barrier layer 24.
  • the semiconductor device 1 is, for example, a semiconductor device (semiconductor element) in which a two-dimensional electron gas is formed, and can be configured as a high electron mobility transistor (HEMT).
  • HEMT high electron mobility transistor
  • the channel layer 22 may be made of u-GaN with no added impurities (undoped). In this case, impurity scattering of carriers in the channel layer 22 is suppressed, and high carrier mobility can be achieved.
  • the channel layer 22 may also be made of other semiconductor materials. Also, impurities may be added to the channel layer 22 for band engineering.
  • the spacer layer 23 is provided between the channel layer 22 and the barrier layer 24.
  • the spacer layer 23 is made of, for example, a material having a band gap larger than the band gap of the channel layer 22.
  • the spacer layer 23 is made of a nitride semiconductor, for example, an epitaxially grown layer of AlN, and is located on the channel layer 22.
  • the spacer layer 23 may be made of Al x In y Ga 1-x-y N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x+y ⁇ 1).
  • the spacer layer 23 may be made of a ternary material (e.g., AlGaN) or a quaternary material (e.g., AlGaInN).
  • the spacer layer 23 is provided, which reduces the effect of alloy scattering caused by the barrier layer 24 on carriers (i.e., two-dimensional electron gas) induced at the interface between the spacer layer 23 and the channel layer 22. This increases carrier mobility.
  • the barrier layer 24 is made of, for example, a compound semiconductor material, and is provided so as to be laminated on the channel layer 22.
  • the barrier layer 24 is formed on the spacer layer 23 and is located between the spacer layer 23 and the protective layer 25.
  • the barrier layer 24 can be made of, for example, a material having a band gap larger than the band gap of the channel layer 22.
  • the barrier layer 24 is composed of an epitaxially grown layer of a nitride semiconductor, for example, Al x In 1-x N (0 ⁇ x ⁇ 1), and is located on the spacer layer 23.
  • a nitride semiconductor for example, Al x In 1-x N (0 ⁇ x ⁇ 1)
  • polarization occurs in the barrier layer 24 and the channel layer 22, and a two-dimensional electron gas layer 60 can be generated at the heterojunction interface, as in the example shown by the dotted line in FIG.
  • the barrier layer 24 may be an undoped u-Al x In 1-x N layer. In this case, the barrier layer 24 can suppress impurity scattering of carriers in the channel layer 22, and can further increase carrier mobility.
  • the barrier layer 24 may be made of a compound semiconductor material capable of accumulating carriers according to the difference in polarization charge amount at the interface between the channel layer 22 and the spacer layer 23.
  • the channel layer 22 may be made of Al, In, etc.
  • the barrier layer 24 may be made of an epitaxially grown layer of Al1 -x- yInxGayN ( 0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, x+y ⁇ 1).
  • the barrier layer 24 may be made of Al 1-x-y In x Ga y N with no doping.
  • the barrier layer 24 is a nitride semiconductor layer made of a nitride semiconductor, and may also be called a carrier supply layer (or an electron supply layer).
  • the barrier layer 24 may also be called a carrier transport layer (or an electron transport layer).
  • the protective layer 25 is provided on the barrier layer 24.
  • the protective layer 25 is made of, for example, GaN, SiN, etc.
  • the provision of the protective layer 25 suppresses, for example, oxidation of the surface (upper surface) of the barrier layer 24.
  • the protective layer 25 may be made of a single layer, or may be made of a laminate of multiple layers (films).
  • the protective layer 25 may be composed of a composite layer of, for example, GaN and SiN. Also, for example, the protective layer 25 may have a structure in which the composition gradually changes in the thickness direction. The protective layer 25 is also called a cap layer.
  • the protective layer 25 may be made of a compound semiconductor material, for example, Al1 -x- yInxGayN (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, x+ y ⁇ 1). In this case, for example, the barrier layer 24 made of an epitaxially grown layer can be effectively protected. Note that the protective layer 25 may not be provided depending on the desired device characteristics, mass productivity, and the like.
  • the semiconductor region 26a and the semiconductor region 26b are, for example, n+ type semiconductor regions formed using n-type impurities (dopants).
  • the semiconductor region 26a and the semiconductor region 26b are, for example, formed using GaN.
  • the semiconductor regions 26a and 26b can be made using the same material as the channel layer 22.
  • the semiconductor regions 26a and 26b are also called contact layers.
  • the semiconductor regions 26a and 26b may be formed using In x Ga 1-x N (0 ⁇ x ⁇ 1) or other materials. As n-type impurities (dopants), Si (silicon), Ge (germanium), etc. are used. The impurity concentration is, for example, 1 ⁇ 10 18 cm ⁇ 3 or more, or 1 ⁇ 10 19 cm ⁇ 3 or more.
  • the semiconductor regions 26a and 26b are each a high-concentration n+ layer.
  • the semiconductor regions 26a and 26b are formed, for example, so as to contact the channel layer 22 in which the two-dimensional electron gas layer 60 is formed.
  • the semiconductor region 26a is provided from the source electrode 50a to the channel layer 22.
  • the semiconductor region 26b is provided from the drain electrode 50b to the channel layer 22.
  • the semiconductor regions 26a and 26b can be formed in the barrier layer 24 and in the channel layer 22.
  • the semiconductor regions 26a and 26b may be formed in a region of the channel layer 22 deeper than the vicinity of the barrier layer 24 where the two-dimensional electron gas layer 60 is formed.
  • the semiconductor regions 26a and 26b form part of the current path between the source electrode 50a and the drain electrode 50b.
  • One of the semiconductor regions 26a and 26b constitutes a part of the source of the transistor.
  • the other of the semiconductor regions 26a and 26b constitutes a part of the drain of the transistor.
  • the semiconductor region 26a is the source region, and the semiconductor region 26b can also be called the drain region.
  • the semiconductor regions 26a and 26b are provided, so that the two-dimensional electron gas layer 60 in the channel layer 22 can be electrically connected to the source electrode 50a (and the drain electrode 50b) with low resistance.
  • the semiconductor regions 26a and 26b do not have to be in contact with the two-dimensional electron gas layer 60.
  • the semiconductor region 26a (or semiconductor region 26b) does not have to be in direct contact with the two-dimensional electron gas layer 60.
  • the semiconductor regions 26a and 26b may be formed, for example, by partially removing the barrier layer 24 and the channel layer 22 by etching, and selectively performing epitaxial growth in the removed areas.
  • the semiconductor regions 26a and 26b may also be formed, for example, by ion implantation.
  • the source electrode 50a and the drain electrode 50b are each made of, for example, titanium (Ti), aluminum (Al), nickel (Ni), gold (Au), or the like.
  • the source electrode 50a is provided for the semiconductor region 26a
  • the drain electrode 50b is provided for the semiconductor region 26b. Note that each of the source electrode 50a and the drain electrode 50b may be formed using other metal materials.
  • the source electrode 50a is electrically connected to the semiconductor region 26a, and the drain electrode 50b is electrically connected to the semiconductor region 26b.
  • the source electrode 50a is in ohmic junction with the semiconductor region 26a
  • the drain electrode 50b is in ohmic junction with the semiconductor region 26b.
  • the source electrode 50a and the drain electrode 50b can also be called ohmic electrodes.
  • the insulating film 31 is provided on the protective layer 25 and is located between the protective layer 25 and the insulating film 32.
  • the insulating film 31 is made of an insulating material that does not contain Si (silicon), such as aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), or the like.
  • the insulating film 31 may be made of AlN, TiO 2 , NbO, Nb 2 O 5 or Ta 2 O 5.
  • the insulating film 31 may be formed using other materials having insulating properties.
  • the insulating film 31 may be made of a single film or may be made by stacking a plurality of films.
  • the insulating film 32 is provided so as to be laminated on the insulating film 31.
  • the insulating film 32 is formed on the insulating film 31 between the source electrode 50a and the gate electrode 40, and between the drain electrode 50b and the gate electrode 40.
  • the insulating film 32 is made of an insulating material containing Si (silicon).
  • the insulating film 32 is, for example, a single layer film made of one of silicon nitride (SiN or Si 3 N 4 ), silicon oxide (SiO 2 ), silicon oxynitride (SiON), etc., or a laminated film made of two or more of these.
  • the insulating film 32 may be made of a SiN film having excellent insulating properties and stress controllability. Also, two or more layers of SiN films may be laminated in multiple steps depending on the manufacturing process. Furthermore, it may be configured by laminating two or more SiN layers with different refractive indices.
  • the insulating film 32 may be made of AlSiO, or may be formed using other insulating materials.
  • the insulating film 32 can be provided, for example, as an interlayer insulating film in a wiring layer in which multiple wirings are provided. As an example, the insulating film 32 is formed between multiple wirings, between an electrode (e.g., a via) and a wiring, between multiple electrodes, etc. Note that the insulating film 32 may be formed of a single film, or may be formed by stacking multiple films.
  • the insulating films 31 and 32 have a gate opening 35.
  • the gate opening 35 is an opening (opening) formed by, for example, removing the portions of the insulating films 31 and 32 between the source electrode 50a and the drain electrode 50b by etching.
  • a gate electrode 40 is provided within the gate opening 35.
  • the gate electrode 40 is provided so as to fill the gate opening 35, and may have, for example, a T-shaped cross-sectional shape.
  • the gate electrode 40 is made of a metal material such as nickel (Ni) or gold (Au).
  • the gate electrode 40 is formed so as to be embedded in the gate opening 35. In the example shown in FIG. 1, the bottom (lower end) of the gate electrode 40 is disposed on the protective layer 25.
  • the gate electrode 40 may be made of other conductive materials.
  • the semiconductor device 1 is configured to contain a halogen group element below the gate electrode 40.
  • the semiconductor device 1 is configured to contain fluorine (F) as a halogen group element in the region below the gate electrode 40.
  • the protective layer 25, the barrier layer 24, the spacer layer 23, and the like below the gate electrode 40 may be configured to contain fluorine.
  • the semiconductor device 1 may also be configured to contain oxygen (O) below the gate electrode 40.
  • oxygen oxygen
  • the protective layer 25, the barrier layer 24, the spacer layer 23, and the like below the gate electrode 40 may contain oxygen.
  • fluorine and oxygen may be introduced into the region (position) below the gate electrode 40 by dry etching, wet etching, or the like, as described below.
  • FIG. 2 is a diagram for explaining an example of a composition distribution in a semiconductor device according to an embodiment.
  • the peak position of the fluorine (F) content and the peak position of the oxygen (O) content in the semiconductor device 1 are shown as schematic rectangles.
  • FIGS. 3A and 3B are diagrams showing an example of the composition of each layer of a semiconductor device.
  • FIG. 3B shows an enlarged view of a portion of FIG. 3A.
  • XPS X-ray photoelectron spectroscopy
  • EDX energy dispersive X-ray spectroscopy
  • SIMS secondary ion mass spectroscopy
  • the semiconductor device 1 is configured to contain fluorine and oxygen at the interface between the gate electrode 40 and the protective layer 25.
  • the semiconductor device 1 is also configured to contain fluorine and oxygen at the interface between the protective layer 25 and the barrier layer 24.
  • the semiconductor device 1 can also be configured to contain fluorine and oxygen at the interface between the barrier layer 24 and the spacer layer 23.
  • the semiconductor device 1 has a peak (maximum part) of fluorine content and a peak of oxygen content near the interface between the protective layer 25 and the barrier layer 24.
  • the semiconductor device 1 may also have a peak of fluorine content and a peak of oxygen content near the interface between the barrier layer 24 and the spacer layer 23.
  • the semiconductor device 1 is configured to contain at least one of fluorine and oxygen below the gate electrode 40.
  • fluorine as negative ions (negative fixed charges) below the gate electrode 40, for example, in the protective layer 25, the barrier layer 24, the spacer layer 23, etc., it becomes possible to reduce the electric field (potential gradient) in each layer of the semiconductor device 1.
  • the semiconductor device 1 it is possible to suppress the occurrence of electric field concentration (strong electric field) between the gate electrode 40 and the drain electrode 50b. In addition, it is possible to reduce the electric field between the gate electrode 40 and the source electrode 50a. It is possible to reduce the gate end electric field and reduce the leakage current.
  • strong electric field strong electric field
  • oxygen is injected into the protective layer 25, the barrier layer 24, the spacer layer 23, etc., below the gate electrode 40, making it possible to effectively suppress leakage current.
  • the trap levels in each layer formed by oxygen injection capture unnecessary carriers leaking from the two-dimensional electron gas layer 60, thereby reducing the leakage current.
  • the maximum fluorine content in each of the protective layer 25, the barrier layer 24, and the spacer layer 23 below the gate electrode 40 may be 0.5 atomic % (atomic percent) or more.
  • the maximum oxygen content in each of the protective layer 25, the barrier layer 24, and the spacer layer 23 below the gate electrode 40 may be 1 atomic % or more.
  • an insulating film 31 is provided below the insulating film 32 that contains silicon.
  • the insulating film 31 is made of an insulating material that does not contain silicon, such as aluminum oxide. This makes it possible to prevent the silicon contained in the insulating film 32 from diffusing (mixing) into the region below the insulating film 31 (protective layer 25, barrier layer 24, etc.). For example, it becomes possible to prevent the silicon in the insulating film 32 from diffusing into the barrier layer 24 during the manufacturing process (e.g., heat treatment process).
  • the insulating film 31 is provided, so that the resistance of the protective layer 25 and the like can be prevented from decreasing due to the diffusion of silicon from the insulating film 32. This makes it possible to effectively suppress the leakage current (off-leak current) between the gate electrode 40 and the drain electrode 50b (or the source electrode 50a).
  • the silicon content in each of the protective layer 25 and the barrier layer 24 below the gate electrode 40 and the drain electrode 50b may be, for example, 2 atomic % or less. In this case, it is possible to effectively suppress the leakage current between the gate electrode 40 and the drain electrode 50b (or the source electrode 50a).
  • the composition ratio of silicon in the protective layer 25 etc. may be a magnitude (value) below the detection limit.
  • a leak path may be formed between the two-dimensional electron gas layer 60 and the gate electrode 40, causing an increase in the leak current, as shown in the example diagrammatically by the arrow in Figure 4.
  • the electric field is alleviated by implanting fluorine and oxygen, and the diffusion of silicon is suppressed by the insulating film 31, so that the leakage current between the two-dimensional electron gas layer 60 and the gate electrode 40 can be effectively suppressed, as shown by the "X" mark in FIG. 5.
  • an electronic device e.g., a mobile terminal
  • FIG. 6 is a diagram for explaining an example of the configuration of a semiconductor device according to an embodiment.
  • the insulating film 31 has a thickness smaller than that of the insulating film 32, for example.
  • the thickness Th1 of the insulating film 31 may be greater than 1 nm.
  • the thickness Th1 of the insulating film 31 may be greater than 2 nm, or greater than 3 nm.
  • the thickness Th1 of the insulating film 31 may be in the range of 2 nm to 15 nm.
  • the thickness Th2 of the insulating film 32 may be, for example, within the range of 40 nm to 150 nm.
  • the insulating films 31 and 32 may be formed to satisfy, for example, Th1/Th2>0.005.
  • the substrate 10 is prepared.
  • single crystal Si is used for the substrate 10.
  • the substrate 10 is, for example, a semiconductor wafer having a region for forming a plurality of transistors before the dicing process.
  • a buffer layer 21, a channel layer 22, a spacer layer 23, a barrier layer 24, and a protective layer 25 are sequentially stacked on the substrate 10.
  • Each of the buffer layer 21, the channel layer 22, the spacer layer 23, the barrier layer 24, and the protective layer 25 will be further described.
  • the buffer layer 21 is formed on the substrate 10 using an epitaxial growth method (e.g., MOCVD).
  • the buffer layer 21 is formed of one or more compound semiconductor layers selected from, for example, AlN, AlGaN, and GaN.
  • the channel layer 22 is formed on the buffer layer 21 using an epitaxial growth method.
  • the channel layer 22 is formed using, for example, GaN as a compound semiconductor layer.
  • the spacer layer 23 is formed on the channel layer 22 by epitaxial growth.
  • the spacer layer 23 is formed as a compound semiconductor layer using, for example, a nitride semiconductor material including AlN.
  • the barrier layer 24 is formed on the spacer layer 23 by epitaxial growth.
  • the barrier layer 24 is formed as a compound semiconductor layer using, for example, a nitride semiconductor material.
  • the protective layer 25 is formed on the barrier layer 24 using one deposition method selected from the group consisting of epitaxial growth, ALD (Atomic Layer Deposition), and CVD (Chemical Vapor Deposition). Then, the semiconductor regions 26a and 26b are formed by, for example, a regrowth method. The semiconductor regions 26a and 26b may be formed after the gate electrode 40 is formed.
  • An insulating film 31 and an insulating film 32 are sequentially laminated between the gate electrode 40 and the source electrode 50a, and between the gate electrode 40 and the drain electrode 50b.
  • the insulating film 31 is formed on the protective layer 25 by, for example, the ALD method or the CVD method.
  • the insulating film 31 is formed of, for example, Al 2 O 3.
  • the insulating film 32 is formed on the insulating film 31 by, for example, the ALD method, the CVD method, or the sputtering method.
  • the insulating film 32 is formed as a single layer or a composite layer by, for example, using an insulating material such as SiN.
  • a gate opening 35 is formed in the insulating film 32 in the region where the gate electrode 40 is to be formed.
  • the gate opening 35 in the insulating film 32 is formed by, for example, dry etching or wet etching.
  • etching is performed in the thickness direction of the insulating film 31 by an etching method.
  • the etching method used may be dry etching or wet etching.
  • the gate opening 35 in the insulating film 31 is formed by an etching method using a mask formed by, for example, photolithography technology.
  • an anisotropic dry etching method is used as the etching method to effectively suppress the expansion of the opening dimensions.
  • fluorine supplied from the etching gas (SF6, CF4)
  • oxygen contained in the Al2O3 insulating film 31 also diffuses into the protective layer 25 and the barrier layer 24 together with fluorine.
  • fluorine and oxygen may be introduced (diffused) into the protective layer 25, the barrier layer 24, and the spacer layer 23 by wet etching and heat treatment using a solution containing fluorine, oxygen, etc.
  • fluorine, etc. can be effectively injected into the protective layer 25, etc., using dry etching or wet etching while preventing damage.
  • the insulating film 31 suppresses the diffusion of Si contained in the insulating film 32 in a high-temperature environment (e.g., annealing) during the manufacturing process.
  • the insulating film 31 can effectively suppress or prevent the diffusion of Si into the surface of the semiconductor layer (e.g., protective layer 25) when forming a gate opening 35 in the insulating film 32.
  • the gate electrode 40 is formed. A portion of the gate electrode 40 is electrically connected to and mechanically joined to the protective layer 25 through the gate opening 35.
  • the gate electrode 40 is formed, for example, by using a mask deposition method.
  • the gate electrode 40 is formed, for example, by sequentially stacking Ni and Au.
  • the source electrode 50a and the drain electrode 50b are formed on the semiconductor region 26a (and the semiconductor region 26b) by sequentially depositing Ti, Al, Ni, and Au, for example, using a mask deposition method.
  • the source electrode 50a is electrically connected to and mechanically joined to the semiconductor region 26a.
  • the drain electrode 50b is electrically connected to and mechanically joined to the semiconductor region 26b.
  • the semiconductor device 1 can be manufactured by the manufacturing method described above. Through a series of processes, it is possible to diffuse fluorine and oxygen into the semiconductor layer (protective layer 25, barrier layer 24, etc.) below the gate electrode 40, while suppressing the diffusion of Si from the insulating film 32 into the protective layer 25. It is possible to obtain the desired composition profile of fluorine, oxygen, and silicon. Note that the manufacturing method described above is merely one example, and other manufacturing methods may be adopted.
  • the semiconductor device includes a channel layer (channel layer 22) containing a first nitride semiconductor, a semiconductor layer (e.g., barrier layer 24) that is laminated with the channel layer and contains a second nitride semiconductor, a gate electrode (gate electrode 40) and a drain electrode (drain electrode 50b) that are provided above the semiconductor layer, a first insulating film (insulating film 31) that is provided above the semiconductor layer between the gate electrode and the drain electrode, and a second insulating film (insulating film 32) that is laminated with the first insulating film and contains silicon.
  • the semiconductor layer contains a halogen element below the gate electrode.
  • the silicon content of the semiconductor layer below the gate electrode and the drain electrode is 2 atomic % or less.
  • the semiconductor layer for example the barrier layer 24, contains fluorine as a halogen element below the gate electrode 40.
  • the silicon content of the semiconductor layer below between the gate electrode 40 and the drain electrode 50b is 2 atomic % or less. This makes it possible to suppress leakage current in the semiconductor device 1. It is possible to realize a semiconductor device capable of reducing leakage current.
  • Fig. 7 is a diagram for explaining a configuration example of a semiconductor device according to a first modified example of the present disclosure.
  • the semiconductor device 1 may have an underlayer 28 and a back barrier layer 29, as in the example shown in Fig. 7.
  • the underlayer 28 is provided, for example, so as to be laminated on the buffer layer 21.
  • the underlayer 28 is provided on the buffer layer 21 and is located between the buffer layer 21 and the back barrier layer 29.
  • the underlayer 28 may be made of GaN.
  • the underlayer 28 may be made of u-GaN to which no impurities have been added (undoped). Note that the underlayer 28 may be formed by laminating multiple layers (films).
  • the back barrier layer 29 is provided so as to be laminated above the buffer layer 21.
  • the back barrier layer 29 is formed on the base layer 28 and is located between the base layer 28 and the channel layer 22.
  • the back barrier layer 29 is made of, for example, a compound semiconductor material.
  • the back barrier layer 29 may be formed using a semiconductor material that is bonded with the channel layer 22 with band bending.
  • the back barrier layer 29 may be composed of Al x Ga 1-x N (0 ⁇ x ⁇ 1), an epitaxially grown layer of u-AlGaN with no doping, or the like.
  • the back barrier layer 29 may be composed of a plurality of films stacked together.
  • the semiconductor device 1 includes fluorine (F) as a halogen group element in the region below the gate electrode 40.
  • the semiconductor device 1 may include another halogen group element (e.g., chlorine (Cl)) in the region below the gate electrode 40.
  • Fig. 8 is a diagram showing a configuration example of a wireless communication device 200 according to the present disclosure.
  • the wireless communication device 200 includes an antenna ANT, an antenna switch circuit 201, a high power amplifier HPA, a radio frequency integrated circuit RFIC (Radio Frequency Integrated Circuit), a baseband unit BB, an audio output unit MIC, a data output unit DT, and an interface unit I/F.
  • RFIC Radio Frequency Integrated Circuit
  • the interface section I/F is, for example, an interface circuit that uses a wireless LAN (W-LAN: Wireless Local Area Network), Bluetooth (registered trademark), etc.
  • the wireless communication device 200 is, for example, a mobile phone system with multiple functions such as voice and data communication and LAN connection.
  • the wireless communication device 200 is configured by applying any of the semiconductor devices according to the above-mentioned embodiments or modifications to the antenna switch circuit 201, the high power amplifier HPA, the radio frequency integrated circuit RFIC, the baseband section BB, etc.
  • the technology according to this disclosure to the antenna switch circuit 201, the baseband section BB, etc., it is possible to effectively suppress leakage current.
  • a semiconductor device includes a channel layer including a first nitride semiconductor, a semiconductor layer including a second nitride semiconductor and stacked with the channel layer, a gate electrode and a drain electrode provided above the semiconductor layer, a first insulating film provided above the semiconductor layer between the gate electrode and the drain electrode, and a second insulating film including silicon and stacked with the first insulating film.
  • the semiconductor layer includes a halogen element below the gate electrode.
  • the silicon content of the semiconductor layer below between the gate electrode and the drain electrode is 2 atomic % or less. This makes it possible to realize a semiconductor device capable of reducing leakage current.
  • the present disclosure may have the following configurations. (1) a channel layer including a first nitride semiconductor; a semiconductor layer including a second nitride semiconductor, the semiconductor layer being stacked on the channel layer; a gate electrode and a drain electrode provided above the semiconductor layer; a first insulating film provided above the semiconductor layer between the gate electrode and the drain electrode; a second insulating film including silicon and provided so as to be stacked on the first insulating film; the semiconductor layer contains a halogen element below the gate electrode, a silicon content of the semiconductor layer below and between the gate electrode and the drain electrode is 2 atomic % or less.
  • a protective layer provided between the semiconductor layer and the gate electrode; the semiconductor layer is a barrier layer containing a second nitride semiconductor,
  • a maximum value of an oxygen content in the protective layer and the semiconductor layer below the gate electrode is 1 atomic % or more.
  • a protective layer provided between the semiconductor layer and the gate electrode; a spacer layer provided between the semiconductor layer and the channel layer, the semiconductor layer is a barrier layer containing a second nitride semiconductor, the protective layer, the semiconductor layer, and the spacer layer contain fluorine below the gate electrode;
  • the semiconductor device according to any one of (1) to (11), wherein a maximum value of a fluorine content in the protective layer, the semiconductor layer and the spacer layer below the gate electrode is 0.5 atomic % or more.
  • the protective layer, the semiconductor layer, and the spacer layer contain oxygen below the gate electrode;
  • the semiconductor device according to (12), wherein a maximum value of an oxygen content in the protective layer, the semiconductor layer, and the spacer layer below the gate electrode is 1 atomic % or more.
  • the semiconductor layer and the spacer layer have a peak of fluorine content and a peak of oxygen content in the vicinity of an interface between the semiconductor layer and the spacer layer.
  • the first insulating film has a thickness greater than 1 nm.
  • the electronic device wherein a silicon content of the semiconductor layer below and between the gate electrode and the drain electrode is 2 atomic % or less.

Landscapes

  • Junction Field-Effect Transistors (AREA)

Abstract

Un dispositif à semi-conducteur selon un mode de réalisation de la présente divulgation comprend : une couche de canal qui comprend un premier semi-conducteur au nitrure ; une couche semi-conductrice qui est placée de façon à être stratifiée avec la couche de canal et comprend un second semi-conducteur au nitrure ; une électrode de grille et une électrode de drain qui sont placées au-dessus de la couche semi-conductrice ; un premier film isolant qui est placé au-dessus de la couche semi-conductrice entre l'électrode de grille et l'électrode de drain ; et un second film isolant qui est placé de façon à être stratifié avec le premier film isolant et comprend du silicium. La couche semi-conductrice comprend un élément halogène sous l'électrode de grille. La teneur en silicium de la couche semi-conductrice sous l'espace entre l'électrode de grille et l'électrode de drain n'est pas supérieure à 2 % atomique.
PCT/JP2024/038579 2023-12-18 2024-10-29 Dispositif à semi-conducteur et appareil électronique Pending WO2025134548A1 (fr)

Applications Claiming Priority (2)

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JP2023-213294 2023-12-18
JP2023213294 2023-12-18

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008172055A (ja) * 2007-01-12 2008-07-24 Sharp Corp 窒化物半導体装置及びそれを用いた電力変換装置
JP2012018961A (ja) * 2010-07-06 2012-01-26 Sanken Electric Co Ltd 半導体装置
JP2012124442A (ja) * 2010-12-10 2012-06-28 Fujitsu Ltd 半導体装置及び半導体装置の製造方法
JP2016046413A (ja) * 2014-08-25 2016-04-04 ルネサスエレクトロニクス株式会社 半導体装置
US20190081167A1 (en) * 2017-09-08 2019-03-14 Wavetek Microelectronics Corporation Nitride semiconductor device
JP2020205449A (ja) * 2018-03-06 2020-12-24 株式会社東芝 半導体装置、電源回路、及び、コンピュータ

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008172055A (ja) * 2007-01-12 2008-07-24 Sharp Corp 窒化物半導体装置及びそれを用いた電力変換装置
JP2012018961A (ja) * 2010-07-06 2012-01-26 Sanken Electric Co Ltd 半導体装置
JP2012124442A (ja) * 2010-12-10 2012-06-28 Fujitsu Ltd 半導体装置及び半導体装置の製造方法
JP2016046413A (ja) * 2014-08-25 2016-04-04 ルネサスエレクトロニクス株式会社 半導体装置
US20190081167A1 (en) * 2017-09-08 2019-03-14 Wavetek Microelectronics Corporation Nitride semiconductor device
JP2020205449A (ja) * 2018-03-06 2020-12-24 株式会社東芝 半導体装置、電源回路、及び、コンピュータ

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