WO2025134376A1 - Gate drive control device and power conversion device - Google Patents

Abstract

This gate drive control device drives a gate of a first semiconductor element and comprises: a mirror clamp circuit for retaining a gate voltage of the first semiconductor element at a low level when the gate voltage has fallen to less than a predetermined control threshold value; and a gate monitor circuit for sensing that the gate voltage of the first semiconductor element has fallen below a predetermined sensing threshold value for positive potential. In the gate drive control device, when the first semiconductor element is turned off, the gate monitor circuit senses that the gate voltage of the first semiconductor element has fallen below the sensing threshold value either at the same time as the start of operation of the mirror clamp circuit or later than the start of operation.

Description

Gate drive control device and power conversion device

The present invention relates to a gate drive control device that drives the gate of a semiconductor element, and a power conversion device that uses the same.

Power conversion devices have functions such as AC-DC conversion, DC-AC conversion, or frequency conversion of AC power and voltage conversion of DC power. To perform these conversion functions, power conversion devices have a power conversion circuit that converts power by the on/off operation of a power semiconductor module with a switching function. The power semiconductor module is turned on by the gate drive circuit controlling the gate voltage between the gate terminal and source terminal (or emitter terminal) to High (positive voltage), and turned off by controlling it to Low (0V or negative voltage). The gate drive circuit is further controlled by a higher-level controller.

Power semiconductor modules include 1-in-1 modules that are equipped with single or multiple semiconductor switching elements (hereafter referred to as "switching elements") connected in parallel, and 2-in-1 modules that connect two switching elements in series inside the module to form a half-bridge circuit in one module.

Patent document 1 describes a power semiconductor drive circuit. It describes that the power semiconductor drive circuit includes "a parallel circuit composed of at least two transistors connected to the gate side of a power semiconductor element and setting the gate resistance of the power semiconductor element, and a gate voltage monitoring circuit connected to the gate side of the power semiconductor element and the parallel circuit and set to a predetermined monitoring voltage for monitoring the gate voltage of the power semiconductor element," and "a signal delay circuit that delays the output signal from the gate voltage monitoring circuit, and a gate control circuit that switches the magnitude of the combined resistance of the parallel circuit based on the output signal output from the signal delay circuit."

　Si (silicon) elements have been used for switching elements up until now. In recent years, SiC (silicon carbide) elements, which offer low on-resistance, high-speed switching, and high-temperature operation, have become more popular in order to improve the performance of power conversion circuits. Hereinafter, semiconductor elements that use SiC will be referred to as "SiC elements."

In order to shorten the dead time by supporting high-speed SiC drive, an active dead time configuration has been proposed in which the dead time is controlled by a gate driver IC (GDIC). In an active dead time configuration, the gate monitor signal of the GDIC is input to the GDIC of the opposing arm, which determines that the SiC element of the opposing arm is off and turns on the SiC element of the own arm.

JP 2019-080359 A

In the active dead time configuration, each arm is connected to a Miller clamp circuit that controls the gate with low impedance, and a gate voltage monitoring circuit that monitors the gate voltage of the semiconductor element. The Miller clamp circuit is a circuit that holds the gate voltage of the semiconductor element at a low level when the gate voltage falls below a predetermined control threshold. The gate voltage monitoring circuit is a circuit that determines that the gate is off when the gate voltage of the semiconductor element falls below the off detection threshold, and that the gate is on when it exceeds the on detection threshold. The off detection threshold of a conventional GDIC is set higher than the operating threshold of the Miller clamp circuit. With this setting, the gate monitor signal may be detected as off even if the SiC element of the own arm is in a half-on state. Also, if switching noise of the other phase arm is superimposed on the gate voltage in the half-on state, the SiC element of the own arm may turn on again. For this reason, there was a risk of short-circuiting the upper and lower arms in the active dead time configuration.

The present invention was made in consideration of the above situation, and aims to prevent short circuits between the upper and lower arms in a gate drive control device equipped with a Miller clamp circuit and a gate voltage monitoring circuit, while driving the semiconductor elements that make up the arms at high speed.

In order to solve the above problem, one aspect of the present invention is a gate drive control device that drives the gate of a first semiconductor element, and includes a Miller clamp circuit that holds the gate voltage of the first semiconductor element at a low level when the gate voltage falls below a predetermined control threshold, and a gate monitor circuit that detects that the gate voltage of the first semiconductor element has fallen below a predetermined detection threshold of positive potential. In the gate drive control device, when the first semiconductor element is turned off, the gate monitor circuit is configured to detect that the gate voltage of the first semiconductor element has fallen below the detection threshold simultaneously with or after the Miller clamp circuit starts operating.

According to at least one aspect of the present invention, the gate monitor circuit detects gate off after the Miller clamp circuit operates to confirm that the semiconductor element of the arm is gate off. This operation makes it possible to obtain a more accurate gate off detection result. If the control computer generates dead time using the gate off detection result, it is possible to prevent short circuits between the upper and lower arms while driving the semiconductor elements that make up the arms at high speed.
Problems, configurations and effects other than those described above will become apparent from the following description of the embodiments.

1 is a block diagram showing an example of a configuration of an inverter device equipped with a gate drive control device according to a first embodiment of the present invention. FIG. 2 is a diagram illustrating an example of a configuration of a gate monitor unit in the first embodiment of the present invention. 4 is an example of a timing chart illustrating an outline of a gate detection operation by a gate monitor unit in the first embodiment of the present invention. FIG. 4 is a diagram illustrating an example of a minimum configuration of a gate monitor unit in the first embodiment of the present invention. FIG. 11 is a diagram showing an example of the configuration of an inverter device according to a second embodiment of the present invention. 10 is an example of a timing chart illustrating a gate drive operation of an inverter device according to a second embodiment of the present invention. FIG. 11 is a diagram showing an example (part 1) of the configuration of an inverter device according to a third embodiment of the present invention. FIG. 13 is a diagram showing an example (part 2) of the configuration of an inverter device according to the third embodiment of the present invention. 13 is an example of a timing chart illustrating a gate driving operation according to a third embodiment of the present invention. FIG. 13 is a diagram showing an example of a configuration of a gate monitor unit in a fourth embodiment of the present invention. FIG. 13 is a diagram illustrating an example of a timing chart that roughly illustrates a threshold value changing operation in the fourth embodiment of the present invention. 13 is a diagram showing a modified example (separate configuration) of the configuration of the gate monitor unit according to the embodiment of the present invention. FIG. FIG. 13 is a diagram showing a modified example of the configuration of the gate monitor unit according to the embodiment of the present invention (a configuration in which some thresholds are shared);

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, examples of modes for carrying out the present invention (hereinafter, referred to as "embodiments") will be described with reference to the accompanying drawings.
In this specification and the accompanying drawings, identical or similar components are given the same reference numerals, and duplicate explanations may be omitted, or only differences may be explained. In addition, when there are multiple identical or similar components, they may be explained with different subscripts added to the same reference numerals. In addition, when it is not necessary to distinguish between these multiple components, the subscripts may be omitted. The number of each component may be singular or plural, unless otherwise specified.

Before explaining the present invention, we will provide additional explanation as to why the off-detection threshold of the GDIC was previously set higher than the operating threshold of the Miller clamp circuit. Conventional gate monitor results were used only for monitoring purposes in diagnostic applications. In order to reduce the error between the on/off detection timing of the real power device and the on/off operation timing of the real power device, the conventional off-detection threshold was set to a value close to the gate threshold of the real power device.

However, in the active dead time configuration of the present invention described below, the gate monitor result needs to be used not only as a monitor function but also as a gate input signal for the opposing arm. Therefore, if a power device is turned off once and then erroneously turned on again due to noise or the like generated when the gate is turned off, the opposing arm will turn on as a result of the first gate off, and a short circuit will occur between the upper and lower arms with the own arm being erroneously turned on. To avoid this, in the present invention, the gate is determined to be off after the Miller clamp operation (gate completely off).

Also, traditionally, it has been assumed that the device will be driven by an IGBT (Insulated Gate Bipolar Transistor). SiC, which can be driven at high speed, has a shorter gate voltage transition time (delay time) than an IGBT, and the impact of the difference between the actual gate threshold and the off detection threshold is smaller.

In inverters, large currents are intermittently passed through power devices (semiconductor elements), which generates large noise when the gates of the self-phase and other-phase arms are turned on and off. In fact, common mode noise that occurs when the gate of the other-phase arm is driven can cause the gate of the self-phase arm to erroneously turn on again after having been turned off once. If the aforementioned erroneous on occurs in an inverter with an active dead time configuration, the first gate off will turn on the power device of the opposing arm, causing the power device of the self-arm to erroneously turn on, resulting in a short circuit between the upper and lower arms.

If the gate drive control device can detect gate off more reliably, it will be possible to avoid short circuits in the upper and lower arm circuits as described above in inverters with active dead time configurations. This will improve the reliability of the inverter, leading to greater safety for automobiles.

First Embodiment
First, a gate drive control device and a power conversion device according to a first embodiment of the present invention will be described.

[Configuration of inverter device]
FIG. 1 is a block diagram showing an example of the configuration of an inverter device equipped with a gate drive control device according to a first embodiment of the present invention.
An inverter device 100 (an example of a power conversion device) shown in Fig. 1 includes a first semiconductor element 31 that functions as an upper arm and a second semiconductor element 32 that functions as a lower arm. In Fig. 1, the first semiconductor element 31 and the second semiconductor element 32 are n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) made of SiC. However, the first semiconductor element 31 and the second semiconductor element 32 are not limited to this example. For example, the inverter device 100 is suitable for use in transistors with excellent high-speed switching properties, such as transistors made of SiC.

The inverter device 100 supplies power to a load by controlling the switching operation of a first semiconductor element 31 and a second semiconductor element 32 based on instructions from an MCU (Micro-Control Unit) 1. One example of the load is a motor. The MCU 1 is a microcontroller and an example of a control computer. In the MCU 1, an arithmetic processing device (e.g., a CPU), a memory device (RAM and ROM), an input/output circuit (I/O), a timer circuit, etc. are implemented in a single integrated circuit.

The inverter device 100 includes a gate drive control device 10 that controls the switching operation of the first semiconductor element 31, and a gate drive control device 20 that controls the switching operation of the second semiconductor element 32. The gate drive control device 10 controls the gate voltage supplied to the first semiconductor element 31, and the gate drive control device 20 controls the gate voltage supplied to the second semiconductor element 32.

The MCU1 and the gate drive control device 10 are electrically insulated by the signal transmission unit 2_1. The input side and output side of the signal transmission unit 2_1 are magnetically coupled, and transmit signals while maintaining an electrically insulated state between the input side and the output side. Signals are exchanged between the MCU1 and the gate drive control device 10 via the signal transmission unit 2_1. Examples of the signal transmission unit 2_1 include a signal transmission unit that uses magnetic coupling using a transformer, and a signal transmission unit that uses light using a photocoupler.

The gate drive controller 10 will be described below, but the same applies to the gate drive controller 20.
The gate drive control device 10 includes a gate state determination circuit 14, a Miller clamp circuit 15, and a reference voltage generation circuit 13. The gate state determination circuit 14 detects gate-off of the first semiconductor element 31 simultaneously with or after the Miller clamp circuit 15 starts operating. The configuration and operation of the gate drive control device 10 will be described.

The gate drive control device 10 is composed of a gate drive unit 11 and a gate monitor unit 12 .
The gate driver 11 controls the gate G1 of the first semiconductor element 31 based on a drive command cmd1 input from the MCU 1 via the signal transmission unit 2_1.
The gate monitor unit 12 determines the gate state from the gate G1 voltage and outputs the gate state determination result as a gate monitor signal Mon_g1. The gate monitor unit 12 also controls the gate G1 with low impedance based on the gate state determination result.

(Gate driver)
The gate driver 11 includes a transistor Mp1, a transistor Mn1, and a NOT circuit INV1_1. The transistor Mp1 is a p-channel MOSFET, and the transistor Mn1 is an n-channel MOSFET. The NOT circuit INV1_1 inverts the logical level of a drive command cmd1 and outputs it. The output signal of the NOT circuit INV1_1 is input to the gates of the transistors Mp1 and Mn1 as a switching control signal cnt1.

When the drive command cmd1 becomes a logical high level (hereinafter referred to as "High"), the NOT circuit INV1_1 causes the switching control signal cnt1 to become a logical low level (hereinafter referred to as "Low"). This turns on the transistor Mp1 and turns off the transistor Mn1. The gate G1 is High and the first semiconductor element 31 turns on.

On the other hand, when the drive command cmd1 goes low, the NOT circuit INV1_1 causes the switching control signal cnt1 to go high. This turns the transistor Mp1 off and the transistor Mn1 on. The gate G1 is low, and the first semiconductor element 31 is off.

Resistor Ron1, which is provided between the drain and gate G1 of transistor Mp1, and resistor Roff1, which is provided between the drain and gate G1 of transistor Mn1, are provided to adjust the charging and discharging speed of the gate G1 voltage.

(Gate monitor section)
The gate monitor unit 12 includes a gate state determination circuit 14 , a Miller clamp circuit 15 , and a reference voltage generation circuit 13 .

The gate state determination circuit 14 (an example of a gate monitor circuit) compares the gate G1 voltage with a gate state determination threshold (hereinafter referred to as "Vth_mon") to determine the on/off state of the first semiconductor element 31 and output the result as a gate monitor signal Mon_g1. The gate state determination threshold corresponds to the above-mentioned on determination threshold. In addition, since this embodiment relates to the timing of detecting the off state of the semiconductor element, the gate state determination threshold can also be considered as an off determination threshold.
The Miller clamp circuit 15 controls the gate G1 with low impedance when the gate G1 voltage is less than a Miller clamp operation threshold (hereinafter referred to as "Vth_mc". In other words, the Miller clamp circuit 15 is a circuit that holds the gate voltage of a semiconductor element at a low level when the gate voltage falls below a predetermined control threshold.
The reference voltage generating circuit 13 generates a reference voltage that determines Vth_mon and Vth_mc.

The gate monitor signal Mon_g1, which includes the gate state determination result, is input to the MCU1 via the signal transmission unit 2_1. Then, since the gate state determination result of the first semiconductor element 31 is an OFF determination, the MCU1 outputs an ON command to the gate drive control device 20 in the opposite arm via the signal transmission unit 2_2. The gate state determination result of the first semiconductor element 31 input to the MCU1 is used to adjust the drive timing of the second semiconductor element 32, etc.

The gate drive control device 20, like the gate drive control device 10, includes a gate drive unit 21 and a gate monitor unit 22. The operation of the gate drive control device 20 is the same as that of the gate drive control device 10, so a description thereof will be omitted.

In the present embodiment, the gate driver 11 shows an example configuration in which the output terminal of the transistor Mp1 and the output terminal of the transistor Mn1 are divided into two, but the outputs of the transistors Mp1 and Mn1 may be a single terminal. The gate driver 11 may have a p-channel MOS-p-channel MOS configuration or an n-channel MOS-n-channel MOS configuration, as well as a p-channel MOS-p-channel MOS configuration. When a negative voltage is not generated, the source potential (VSS1_1) of the transistor Mn1 is connected to the same potential as the source potential. When a negative voltage is generated, the source potential (VSS1_1) of the transistor Mn1 is connected to the same potential as the source potential or to a potential lower than the source potential (for example, a negative power supply voltage).

[Gate monitor configuration]
The gate monitor unit 12 according to this embodiment will be described in further detail with reference to FIG.
FIG. 2 is a diagram showing an example of the configuration of the gate monitor unit 12. As shown in FIG.

(Reference voltage determination circuit)
The reference voltage generating circuit 13 generates a voltage of Vth_mon (gate state determination threshold) and a voltage of Vth_mc (Miller clamp operation threshold). In this embodiment, it is assumed that Vth_mon and Vth_mc have the same value. FIG. 2 shows a configuration in which a common reference voltage is used for Vth_mon and Vth_mc. Note that, when Vth_mon and Vth_mc have different values, a configuration in which the reference voltages are generated separately may be used, as shown in FIG. 12 and FIG. 13 described later.

(Gate state determination circuit)
The gate state determination circuit 14 includes a comparator CMP1_1 having two inputs, a voltage of Vth_mon and a voltage of the gate G1, and a NOT circuit INV1_2 that inverts the logic output from CMP1_1. As an example, the comparator CMP1_1 receives the voltage of Vth_mon at a non-inverting input terminal and the voltage of the gate G1 at an inverting input terminal, and outputs a gate state determination result to the NOT circuit INV1_2. If the voltage of the gate G1 is less than Vth_mon, the comparator CMP1_1 outputs an OFF determination (Low in this embodiment) indicating that the gate is in an OFF state to the gate monitor signal Mon_g1 via INV1_2. If the gate G1 voltage is equal to or greater than Vth_mon, the comparator CMP1_1 outputs an ON determination (High in this embodiment) indicating that the gate is in an ON state to the gate monitor signal Mon_g1 via INV1_2.

It is also possible to connect gate G1 to the non-inverting input terminal of CMP1_1 and Vth_mon to the inverting input terminal. In that case, the NOT circuit INV1_2 is not necessary.

(Miller clamp circuit)
The Miller clamp circuit 15 includes a comparator CMP2_1 and a Miller clamp transistor Q1.

Comparator CMP2_1 is a comparator that has two inputs, the voltage of Vth_mc and the voltage of gate G1. As an example, the voltage of Vth_mc is input to the non-inverting input terminal, and the voltage of gate G1 is input to the inverting input terminal. If the gate G1 voltage is less than Vth_mc, comparator CMP2_1 outputs a low impedance control command (High in this embodiment) to the mirror clamp control signal cnt1_mc. If the gate G1 voltage is equal to or greater than Vth_mc, comparator CMP2_1 outputs a high impedance control command (Low in this embodiment) to the mirror clamp control signal cnt1_mc.

The reference potential (VSS3_1) of Vth_mon and Vth_mc is connected to the same potential as the source potential.
The source potential (VSS2_1) of the Miller clamp transistor Q1 is connected to a potential equal to the source potential or a potential lower than the source potential (for example, a negative power supply voltage).

The Miller clamp transistor Q1 controls the gate G1 of the first semiconductor element 31 at low impedance based on the Miller clamp control signal cnt1_mc, which is the output of the comparator CMP2_1. The Miller clamp transistor Q1 is turned on when the Miller clamp control signal cnt1_mc is a low impedance control command (High). Conduction between the drain and source of the Miller clamp transistor Q1 creates a low impedance between the gate G1 and the source (VSS2_1). This holds the voltage of the gate G1 at a low level. As an example, the Miller clamp transistor Q1 can be an n-channel MOSFET, but is not limited to this.

[Gate detection operation]
Next, the gate detection operation in the gate drive control device 10 having the gate monitor unit 12 will be described with reference to FIG.

FIG. 3 is an example of a timing chart that illustrates the gate detection operation by the gate monitor unit 12. In FIG.
At time t1: while an OFF command is input to the drive command cmd1, an OFF command (Low) is input to the drive command cmd2. The transistor Mp2 (not shown) in the gate drive control device 20 turns OFF and the transistor Mn2 (not shown) turns ON, causing the gate G2 potential of the second semiconductor element 32 to start decreasing. The transistors Mp2 and Mn2 correspond to the transistors Mp1 and Mn1 in the gate drive control device 10, respectively.

Time t2: The gate G2 voltage reaches the mirror voltage of the second semiconductor element 32, and the gate G2 potential becomes constant.
Time t3: After the drain D2 voltage of the second semiconductor element 32 rises, the gate G2 potential begins to decrease.

Time t4: The gate G2 potential falls below Vth_mc, and the Miller clamp circuit 15 starts operating to control the gap between gate G2 and VSS2_2 with low impedance, causing the gate G2 potential to fall to the VSS2_2 potential. At the same time, the gate G2 potential falls below Vth_mon, causing an off determination (Low) result to be output to the gate monitor signal Mon_g2. During the period from time t1 when the gate G2 potential starts to fall to time t4 when the gate G2 potential has completely fallen to VSS2_2, the second semiconductor element 32 is in a half-on state.

At time t5: When the gate monitor signal Mon_g2 goes low, the MCU1 outputs an on command (high) to the drive command cmd1. The period from time t4, when the gate monitor signal Mon_g2 goes low, to the time Tdelay has elapsed when the gate G1 starts to rise is the dead time. When the on command (high) is input to the drive command cmd1, after a delay time (Tdelay), the transistor Mp1 in the gate drive control device 10 turns on and the transistor Mn1 turns off. As a result, the potential of the gate G1 of the first semiconductor element 31 starts to rise.

At time t6: When the potential of the gate G1 of the second semiconductor element 32 becomes equal to or higher than Vth_mon, an on-state determination (High) is output to the gate monitor signal Mon_g1. At the same time, the Miller clamp transistor Q1 stops operating.

At time t7: The potential of the gate G1 of the first semiconductor element 31 rises to VCC1 (Figure 1), and the first semiconductor element 31 enters the ON state.

In the gate monitor unit 12 according to the present embodiment described above, the detection threshold (Vth_mon) of the gate state determination circuit 14 is set to the same value as the control threshold (Vth_mc) of the Miller clamp circuit 15.

With this configuration, in this embodiment, gate off is detected simultaneously with or after the Miller clamp circuit starts operating, making it possible to increase the accuracy of gate off detection compared to conventional techniques.
Furthermore, by sharing the reference voltage as shown in FIG. 2, the circuit area can be reduced compared to the conventional art, resulting in low cost and miniaturization.

The Miller clamp circuit may be configured to stop operating simultaneously with the input of an ON command to the gate driver of the arm in question.

[Minimum configuration of gate monitor section]
Here, an example of the minimum configuration of the gate monitor unit in this embodiment will be described with reference to FIG.

FIG. 4 is a diagram showing an example of a minimum configuration of the gate monitor unit.
In the gate monitor unit 12A shown in Fig. 4, the comparator CMP1_1 and the comparator CMP2_1 shown in Fig. 2 are shared, thereby making it possible to reduce the number of comparators by one. Note that the following description of the gate monitor unit 12A will focus on the configuration that differs from the gate monitor unit 12 shown in Fig. 2.

Focusing on the differences from the configuration shown in FIG. 2 described above, the gate monitor unit 12A includes a comparator CMP3_1 instead of the comparators CMP1_1 and CMP2_1. Furthermore, the gate monitor unit 12A includes a buffer circuit BUF1 on the output line of the comparator CMP3_1. A NOT circuit INV3_1 is connected between the input side of the buffer circuit BUF1 and the output side of the comparator CMP3_1.

Comparator CMP3_1 compares two inputs, the voltage of gate G1 and the voltage of Vth_mon (=Vth_mc), and outputs the comparison result to the Miller clamp control signal cnt1A_mc. Comparator CMP3_1 operates in the same way as comparator CMP2_1, so a detailed explanation of its operation is omitted. Also, NOT circuit INV3_1 operates in the same way as NOT circuit INV1_2, so a detailed explanation of its operation is omitted.

The buffer circuit BUF1 adjusts the logic level output by the NOT circuit INV3_1 to the desired logic level (a voltage level whose logic can be determined by the signal transmission unit 2_1) and outputs it as the gate monitor signal Mon_g1.

Here, it is assumed that the logic determination threshold (Vdet_st1) for determining the logic level of the signal transmission unit 2_1 and the High output voltage (Vinv_h) of the NOT circuit INV3_1 have the relationship shown in the following formula (1). Furthermore, the High output voltage (Vbuf1_h) of the buffer circuit BUF1 is set so as to satisfy the following formula (1).

Vinv_h<Vdet_st1<Vbuf1_h...(1)

When the potential of the high voltage (Vinv_h) of the NOT circuit INV3_1 is less than the logic determination threshold (Vdet_buf1) for determining the logic level of the buffer circuit BUF1, the buffer circuit BUF1 outputs a low monitor signal Mon_g1. The low-level gate monitor signal Mon_g1 transmits information (that it is at a low level) to the MCU1 via the signal transmission unit 2_1.

On the other hand, if the potential of the High voltage (Vinv_h) of the NOT circuit INV3_1 is equal to or higher than Vdet_buf1, High (Vbuf1_h) is output to the gate monitor signal Mon_g1. Therefore, the signal transmission unit 2_1 identifies the signal transmitted from the gate monitor unit 12A as High and transmits the signal to the MCU1.

Note that if Vdet_st1 and Vinv_h satisfy the following formula (2), the High output voltage (Vinv_h) of the NOT circuit INV3_1 is sufficiently large. In this case, the buffer circuit BUF1 may not be provided.

Vdet_st1<Vinv_h...(2)

The gate monitor unit 12A shown in FIG. 4 allows the terminals and some of the internal circuits to be shared, making the circuit size smaller and reducing costs.

(Modification of Gate Monitor Section (Separate Configuration))
Here, a modification of the configuration of the gate monitor unit in this embodiment will be further described.

FIG. 12 shows a modified example (separate configuration) of the configuration of the gate monitor unit in this embodiment.
The gate monitor unit 12C shown in FIG. 12 is configured to generate reference voltages individually for Vth_mon (gate state determination threshold) and Vth_mc (Miller clamp operation threshold).

The comparator CMP1_1 receives two inputs, a voltage of Vth_mon and a voltage of the gate G1. A reference voltage generating circuit 1310 generates a voltage of Vth_mon and inputs it to an input terminal (for example, a non-inverting input terminal) of the comparator CMP1_1.
The comparator CMP2_1 receives two inputs, a voltage of Vth_mc and a voltage of the gate G1. A reference voltage generating circuit 1320 generates a voltage of Vth_mc and inputs it to an input terminal (for example, a non-inverting input terminal) of the comparator CMP2_1.

(Modification of the gate monitor unit (some thresholds shared configuration))
FIG. 13 shows a modified example of the configuration of the gate monitor unit in this embodiment (a configuration in which some thresholds are shared).
13 is configured to generate reference voltages individually for Vth_mon (gate state determination threshold) and Vth_mc (Miller clamp operation threshold), although some threshold voltages are common.

A series circuit of the reference voltage generating circuit 1410 and the reference voltage generating circuit 1420 is connected between the reference potential (VSS3_1) and the input terminal (e.g., the non-inverting input terminal) of the comparator CMP2_1. The connection point between the reference voltage generating circuit 1410 and the reference voltage generating circuit 1420 is connected to the input terminal (e.g., the non-inverting input terminal) of the comparator CMP1_1.

The comparator CMP1_1 receives two inputs, a voltage of Vth_mon and a voltage of the gate G1. A reference voltage generating circuit 1410 generates a voltage of Vth_mon and inputs it to an input terminal (for example, a non-inverting input terminal) of the comparator CMP1_1.
The comparator CMP2_1 receives two inputs, a voltage Vth_mc and a voltage at the gate G1. The voltage Vth_mc is a voltage obtained by adding the voltage generated by the reference voltage generation circuit 1420 to the voltage Vth_mon generated by the reference voltage generation circuit 1410.

In the gate monitor unit shown in Figures 12 and 13, the gate state determination threshold (Vth_mon) of the gate state determination circuit 14 is set to the same value as the mirror clamp operation threshold (Vth_mc) of the mirror clamp circuit 15, or to a value smaller than the mirror clamp operation threshold (Vth_mc).

As described above, the gate drive device (gate drive control device 10) according to this embodiment is a gate drive control device that drives the gate of a first semiconductor element (first semiconductor element 31). This gate drive control device includes a Miller clamp circuit (Miller clamp circuit 15) that holds the gate voltage at a low level when the gate voltage of the first semiconductor element falls below a predetermined control threshold (Vth_mc), and a gate monitor circuit (gate state determination circuit 14) that detects that the gate voltage of the first semiconductor element has fallen below a predetermined detection threshold (Vth_mon) of positive potential. In this gate drive control device, when the first semiconductor element is turned off, the gate monitor circuit is configured to detect that the gate voltage of the first semiconductor element has fallen below the detection threshold simultaneously with or after the Miller clamp circuit starts operating.

According to the present embodiment described above, the gate monitor circuit detects gate off after the Miller clamp circuit operates to confirm that the semiconductor element of its own arm is gate off. This makes it possible to obtain a more accurate gate off detection result, and more accurate gate information can be used for gate drive control. If the gate off detection result is used to generate dead time in an MCU or the like, it is possible to drive the semiconductor elements that make up the arms at high speed while preventing short circuits between the upper and lower arms.

In addition, by setting the detection threshold (Vth_mon) to a positive potential with respect to GND (FIG. 3), the gate potential can be determined to be at a low level more quickly and gate off can be detected more quickly. Accordingly, the dead time by the active dead time control unit described later can be shortened.
Moreover, by setting each threshold value to a positive potential, it is possible to eliminate the generation circuitry involved in generating a negative potential and the diagnosis circuitry for the negative potential, thereby reducing costs.

Second Embodiment
Next, the configuration of an inverter device according to a second embodiment of the present invention will be described with reference to FIG.

[Configuration of inverter device]
Fig. 5 is a diagram showing an example of the configuration of an inverter device according to a second embodiment of the present invention. The following describes an inverter device 600 shown in Fig. 5, focusing on the configuration different from the inverter device 100 according to the first embodiment shown in Fig. 1.

The inverter device 600 includes an active dead time control unit 40 in addition to the configuration of the inverter device 100 according to the first embodiment. The active dead time control unit 40 corresponds to the active dead time configuration described in the Background section. The active dead time control unit 40 is provided between the signal transmission units 2_1 and 2_2 and the gate drive control devices 10 and 20. The active dead time control unit 40 uses the gate state determination results from the gate monitor units 12 and 22 in the gate drive control devices 10 and 20 to turn one semiconductor element off and then turn the other semiconductor element on, thereby generating dead times for the first semiconductor element 31 and the second semiconductor element 32.

The active dead time control unit 40 includes a NOT circuit INV2, a NOT circuit INV3, an AND circuit 41, and an AND circuit 42.

The NOT circuit INV 2 outputs the inverted logic of the gate monitor signal Mon_g 2 to the AND circuit 41 .
The NOT circuit INV3 outputs the inverted logic of the gate monitor signal Mon_g1 to the AND circuit 42.

The AND circuit 41 receives two inputs, the drive command cmd1 and the inverted logic of the gate monitor signal Mon_g2, and outputs the logical product of the two inputs to the gate driver 11 as the drive command cmd3.
The AND circuit 42 receives two inputs, the drive command cmd2 and the inverted logic of the gate monitor signal Mon_g1, and outputs the logical product of the two inputs to the gate driver 21 as the drive command cmd4.

The operation of the AND circuit 41 will be described. When the drive command cmd1 is an ON command (High) and the inverted logic of the gate monitor signal Mon_g2 is an OFF judgment (High), the AND circuit 41 outputs an ON command (High) as the drive command cmd3. On the other hand, when at least one of the drive command cmd1 or the inverted logic of the gate monitor signal Mon_g2 is Low, the AND circuit 41 outputs an OFF command (Low) as the drive command cmd3.

Note that the operation of AND circuit 42 is the same as that of AND circuit 41, except that the signal lines connected to it are different, so a description of its operation will be omitted.

[Gate detection operation]
Next, the gate drive operation of the inverter device 600 including the active dead time control unit 40 will be described with reference to FIG.

FIG. 6 is an example of a timing chart that shows an outline of the gate drive operation of an inverter device 600 equipped with an active dead time control unit 40. The following describes the timing chart shown in FIG. 6, focusing on the differences from the timing chart of the first embodiment shown in FIG. 3.

Time t1: When an OFF command (Low) is input to the drive command cmd2 while an OFF command is input to the drive command cmd1, the drive command cmd4 also becomes an OFF command (Low) via the AND circuit 42.

Time t5: The amount of processing in MCU1 increases, MCU1 is unable to secure dead time, and when the second semiconductor element 32 is half-on, an ON command (High) is input to the drive command cmd1. However, the gate monitor signal Mon_g2 is determined to be ON (High), and the operation of the AND circuit 41 causes the drive command cmd3 to maintain an OFF command (Low).

At time t4: The gate G2 potential falls below Vth_mc, and the Miller clamp circuit 15 starts operating to control the gap between the gate G2 and VSS2_2 with low impedance, causing the gate G2 potential to fall to the VSS2_2 potential. At the same time, the gate G2 potential falls below Vth_mon, causing an off determination (Low) to be output to the gate monitor signal Mon_g2. As a result, the AND circuit 41 determines that the drive command cmd1 is an on command (High), and the gate monitor signal Mon_g2 is inverted by the NOT circuit INV2, and outputs an on command (High) to the drive command cmd3. Then, after a delay time (Tdelay), the transistor Mp2 in the gate drive control device 20 turns on, and the transistor Mn2 turns off. As a result, the potential of the gate G1 of the first semiconductor element 31 begins to rise, and the first semiconductor element 31 begins to transition to the on state.

The first semiconductor element 31 is in a half-on state during the period from when the gate G1 potential starts to rise after the delay time Tdelay has elapsed from time t4 until time t7 when the gate G1 has fully risen.

As described above, the gate driving device according to this embodiment includes an active dead time control unit (active dead time control unit 40) that turns on the second semiconductor element (second semiconductor element 32) of the paired arm connected in series with the first semiconductor element after the gate monitor circuit (gate state determination circuit 14) detects that the gate voltage of the first semiconductor element (first semiconductor element 31) has fallen below the detection threshold (Vth_mon).

According to the present embodiment described above, the active dead time control unit 40 uses the gate state determination results from the gate monitor units 12, 22 in the gate drive control devices 10, 20 to turn off one semiconductor element before turning on the other semiconductor element. As a result, in this embodiment, it is possible to drive the semiconductor elements that make up the arms at a higher speed than in the first embodiment while preventing short circuits between the upper and lower arms.

In addition, according to this embodiment, even if the MCU1 (microcontroller) cannot ensure sufficient dead time, the gate drive control device (GDIC) can ensure the dead time.

For example, according to the inverter device 600 according to the present embodiment described above, in the active dead time configuration, it is possible to avoid vehicle failure due to a short circuit between the upper arm and the lower arm.
Furthermore, it is possible to detect with higher accuracy that the gate of a semiconductor element has been turned off without adding any additional circuitry to the conventional circuit.

Third Embodiment
Next, the configuration of an inverter device according to a third embodiment of the present invention will be described with reference to FIG.

[Configuration of inverter device]
Fig. 7 is a diagram showing an example (part 1) of the configuration of an inverter device according to a third embodiment of the present invention. Fig. 8 is a diagram showing an example (part 2) of the configuration of an inverter device according to a third embodiment of the present invention. The difference between Fig. 7 and Fig. 8 is the difference in the logical level of the signal flowing through the signal line. The following describes the inverter device 800 shown in Figs. 7 and 8, focusing on the configuration that is different from the configuration of the inverter device 600 according to the second embodiment shown in Fig. 5.

The inverter device 800 includes a simultaneous on prevention circuit 50 in addition to the configuration of the inverter device 600 according to the second embodiment. The simultaneous on prevention circuit 50 is provided between the signal transmission units 2_1 and 2_2 and the active dead time control unit 40.

The simultaneous on prevention circuit 50 is a circuit that prevents simultaneous on in response to a simultaneous on command from the MCU 1 in the gate drive control devices 10 and 20. The simultaneous on prevention circuit 50 prevents the upper and lower arms from being turned on simultaneously by masking the on command that comes in the other drive command when an on command (High) comes in one drive command.

The simultaneous on-prevention circuit 50 includes a resistor R1, a resistor R2, a diode Di1, and a diode Di2.
The resistor R1 transmits the drive command cmd1 as a simultaneous on-prevention command c2_onp to the NOT circuit INV3.
The resistor R2 transmits the drive command cmd2 as a simultaneous-on prevention command c1_onp to the NOT circuit INV2.
The diode Di1 transmits the gate monitor signal Mon_g1 as a simultaneous-on prevention command c2_onp to the NOT circuit INV3.
The diode Di2 transmits the gate monitor signal Mon_g2 as a simultaneous-on prevention command c1_onp to the NOT circuit INV2.

Here, resistor R1 and diode Di1 determine which logic level is output as the simultaneous on prevention command c2_onp when the logic levels of drive command cmd1 and gate monitor signal Mon_g1 differ. For example, if the gate monitor signal Mon_g1 is low and drive command cmd1 is high, diode Di1 will have a reverse voltage. Therefore, the logic level of drive command cmd1 is output as the simultaneous on prevention command c2_onp.

On the other hand, if the gate monitor signal Mon_g1 is High and the drive command cmd1 is Low, the diode Di1 will have a forward voltage. Therefore, the logic of the gate monitor signal Mon_g1 is output as the simultaneous on prevention command c2_onp.

Resistor R1 is provided to give priority to the logic of either the drive command cmd1 or the gate monitor signal Mon_g1, whichever is High. When the drive command cmd1 is High and the gate monitor signal Mon_g1 is Low, diode Di1 is reverse biased and turns OFF, and the simultaneous on prevention command c2_onp goes High (Figure 7). Even if a High signal (simultaneous on control) is input to the drive command cmd2, simultaneous on is prevented because the simultaneous on prevention command c2_onp is High (prohibition command).

On the other hand, as shown in FIG. 8, when the drive command cmd1 is Low and the gate monitor signal Mon_g1 is High, the diode Di1 is forward biased and turned ON, and the simultaneous on prevention command c2_onp is High. Even if a High signal is input to the drive command cmd2, simultaneous on is prevented in the same manner as in the operation of the inverter device 600 shown in FIG. 5.

The resistor R1 is set to a value that maintains the logic of the simultaneous on prevention command c2_onp and the drive command cmd1 even if their logic differs. For example, if the value of resistor R1 is too large, the logic may be inverted. Note that resistor R2 and diode Di2 are connected to different signal lines, and their operation is the same as resistor R1 and diode Di1, so an explanation of their operation will be omitted.

In this way, in the inverter device 800 according to this embodiment, the gate monitor circuit (e.g., gate state determination circuit 14) detects that the gate voltage of the first semiconductor element 31 and the gate voltage of the second semiconductor element 32 have fallen below a predetermined detection threshold. The inverter device 800 also includes gate drivers (gate drivers 11, 12) that drive the gates of the first semiconductor element 31 and the second semiconductor element 32, and a simultaneous-on prevention circuit (simultaneous-on prevention circuit 50) that prohibits the gate driver from driving the gate of the other semiconductor element when the gate monitor circuit has not detected that the gate voltage of one semiconductor element has fallen below the predetermined detection threshold.

With the above configuration, this embodiment can achieve active dead time that can prevent the upper and lower arms from turning on simultaneously with a small number of parts.

[Gate drive operation]
Next, the gate drive operation of the inverter device 800 including the simultaneous-on prevention circuit 50 will be described with reference to FIG.

FIG. 9 is an example of a timing chart that shows the gate drive operation of an inverter device 800 equipped with a simultaneous on prevention circuit 50. The following describes the timing chart shown in FIG. 9, focusing on the differences from the timing chart of the second embodiment shown in FIG. 6. In FIG. 9, only the semiconductor element that is driven is different from time t8 to time t11, and the operation itself is the same as time t4 to time t7, so a description of the operation will be omitted. Note that the example in FIG. 9 assumes a case where the drive commands cmd1 and cmd2 mistakenly become on commands (High) at the same time.

Time t1: When the inverted logic of the simultaneous on prevention command c1_onp is in the on-permitted state (High) and an on command (High) is input to the drive command cmd1, the drive command cmd3 becomes an on command (High). This causes the gate G1 voltage to start rising. At the same time, the inverted logic of the simultaneous on prevention command c2_onp becomes on-prohibited (Low) via resistor R1.

At time t2: Even if an ON command (High) is input to the drive command cmd2, ON prohibition (Low) is input via resistor R1 as the inverted logic of the simultaneous ON prevention command c2_onp. Therefore, the AND circuit 42 maintains the OFF command (Low) of the drive command cmd4.

Time t3: When the potential of gate G1 becomes equal to or higher than Vth_mon, the gate monitor signal Mon_g1 is determined to be ON. In the example of FIG. 9, an OFF command (Low) is input to the drive command cmd2 before time t4.

At time t4: After the above-mentioned OFF command, an ON command (High) is input to the drive command cmd2, but ON prohibition (Low) is input to the inverted logic of the simultaneous ON prevention command c2_onp via the diode Di1. Therefore, the AND circuit 42 maintains the OFF command (Low) of the drive command cmd4.

At time t5: An OFF command (Low) is input to the drive command cmd1, and the potential of gate G1 begins to decrease.

At time t6: The potential of gate G1 becomes less than Vth_mc, the Miller clamp circuit 15 starts operating, and the potential of gate G1 drops to the VSS2_1 potential. At the same time, the potential of gate G1 becomes less than Vth_mon, and an off judgment (Low) result is output to the gate monitor signal Mon_g1. As a result, the inverted logic of the simultaneous on prevention command c2_onp becomes on permitted (High). At this point, because an on command has been input to the drive command cmd2, the gate G2 potential begins to rise. At the same time, the inverted logic of the simultaneous on prevention command c1_onp becomes on prohibited (Low) via the diode Di2.

Time t7: The gate G2 potential becomes equal to or greater than Vth_mon, and the gate monitor signal Mon_g2 is determined to be on.

In this way, in the inverter device 800 according to this embodiment, the simultaneous on prevention circuit 50 is connected to the gate drive control device 10 via the active dead time control unit 40. In this embodiment, by providing the simultaneous on prevention circuit 50, when the gate state determination circuit 14 does not detect that the gate voltage of one semiconductor element has fallen below a predetermined detection threshold, the other semiconductor element is prohibited from being turned on.

According to this embodiment with the above configuration, even if a command to turn on the upper and lower arms simultaneously is input due to a software abnormality in the microcontroller (MCU1), the simultaneous on prevention circuit 50 (GDIC) can prevent the upper and lower arms from turning on simultaneously.

Fourth Embodiment
Next, the configuration of an inverter device according to a fourth embodiment of the present invention will be described with reference to FIG.

Fig. 10 shows an example of the configuration of a gate monitor unit included in an inverter device according to a fourth embodiment of the present invention. The gate monitor unit 12B shown in Fig. 10 is an example of a configuration in which the values of Vth_mon and Vth_mc can be rewritten via SPI communication.
The following describes the gate monitor unit 12B, focusing on the configuration that differs from the configuration of the gate monitor unit 12 according to the first embodiment shown in Fig. 2. The gate monitor unit 12B includes a buffer circuit BUF1, but as described with reference to Fig. 4, the buffer circuit BUF1 does not need to be provided if the conditions are met.

The gate monitor unit 12A includes an SPI communication circuit 1100 and a memory 1110 in addition to the configuration of the gate monitor unit 12 according to the first embodiment. SPI (Serial Peripheral Interface) is one of the standards for data transmission paths. SPI is a bus-type connection method in which multiple devices share a single transmission path, and employs a serial communication method that uses a single signal line for one-way communication.

The SPI communication circuit 1100 operates according to a command input via the SPI communication Com_s1. For example, the SPI communication circuit 1100 rewrites the value of Vth_mon stored in the memory 1110 by inputting a command to change the value of Vth_mon via the SPI communication Com_s1. Furthermore, the SPI communication circuit 1100 may use the SPI communication Com_s1 to transmit information on whether or not the gate is being driven (the state of the drive command cmd1 and the drive command cmd2). Note that the SPI communication may be configured to allow bidirectional data exchange by adding a signal line.

Memory 1110 reflects the stored information in Vth_mon or Vth_mc. When the gate drive of the semiconductor element is stopped (when drive command cmd1 and drive command cmd2 are both in the off command state), memory 1110 changes the value of Vth_mon based on the value recorded inside memory 1110. Non-volatile storage such as ROM, RAM, or SSD (Solid State Drive) can be used as memory 1110.

[Threshold change operation]
Next, the threshold value changing operation of the gate monitor unit 12B will be described with reference to FIG.
11 is a timing chart showing an example of a threshold change operation of the gate monitor unit 12B. In FIG. 11, an example of a start-up operation of the gate drive control device 10 including the gate monitor unit 12B shown in FIG.

At time t1: Power supply from power supply VCC1 (Figure 1) begins, and the potential of power supply VCC1 begins to rise.

At time t2: After the potential of the power supply VCC1 rises, the SPI communication circuit 1100 sets the memory rewrite permission signal to the memory 1110 to permission (High in this embodiment). The memory 1110 reflects the initial value (Vth_L) of Vth_mon recorded in the memory 1110 in Vth_mon.

At time t3: Command 1 is input via SPI communication Com_s1 to change the Vth_mon value to the Vth_H value. In accordance with command 1, the SPI communication circuit 1100 rewrites the initial value (Vth_L) in the memory 1110 to the SPI write value (Vth_H).

At time t4: Memory 1110 reflects the newly recorded Vth_H in Vth_mon.

At time t5: A drive command cmd1 is input from MCU1 to the SPI communication circuit 1100, and gate driving is started based on the on/off command of the drive command cmd1. At this time, the SPI communication circuit 1100 receives command 2 (gate driving) via SPI communication Com_s1. In accordance with command 2, the SPI communication circuit 1100 sets the memory rewrite permission signal to prohibited (Low in this embodiment).

The gate monitor unit 12B according to the present embodiment described above includes a reference voltage that determines the control threshold (Vth_mc) and the detection threshold (Vth_mon). The reference voltage can be set before gate driving starts. The reference voltage can be generated, for example, by the reference voltage generation circuit 13 (Figure 2).

In this embodiment with such a configuration, the mirror clamp operation and gate-off detection can be performed at optimal timing according to the control threshold (Vth_mc) and detection threshold (Vth_mon) of the power device to be driven (first semiconductor element 31, second semiconductor element 32).

Furthermore, in this embodiment, an example has been shown in which Vth_mon is changed via SPI communication Com_s1 when the gate drive control device is started, but Vth_mon may be changed according to the system state during the period in which gate drive is stopped even after startup. For example, consider a case in which the gate voltage threshold of the power devices (first semiconductor element 31, second semiconductor element 32) has decreased due to long-term use. In such a case, a microcontroller such as MCU1 may detect deterioration of the power device and change Vth_mon to an appropriate value at any time via SPI communication Com_s1.

In the gate monitor unit 12B according to this embodiment, at least one of the control threshold (Vth_mc) and the detection threshold (Vth_mon) can be set by an external signal. After being set before gate driving starts, they can be changed according to the system state.

In this embodiment of the configuration, the control threshold and detection threshold are set using the SPI or an external port (not shown) when the inverter device is started, making it possible to set optimal thresholds for the power device to be driven without changing the circuit configuration.

As described above, the present invention is not limited to the above-described embodiment, and it goes without saying that various other modified examples and application examples are possible without departing from the gist of the invention described in the claims.
For example, the above-mentioned embodiments have been described in detail and specifically in order to clearly explain the present invention, and are not necessarily limited to those including all of the components described. In addition, it is possible to replace a part of the configuration of one embodiment with a component of another embodiment. It is also possible to add a component of another embodiment to the configuration of one embodiment. It is also possible to add, replace, or delete other components from part of the configuration of each embodiment.

For example, the configurations of the gate monitor units 12, 12A, 12C, and 12D shown in Figures 2, 4, 12, and 13 can be applied not only to the first embodiment, but also to the second to fourth embodiments. Also, the gate monitor unit 12B in the fourth embodiment can be applied to the first to third embodiments.

Furthermore, in order to reduce delay time due to signal transmission, some of the configurations, circuits, and functions shown in each embodiment may be integrated into one semiconductor device. That is, one or more of the gate driver, Miller clamp circuit, gate monitor circuit (e.g., gate state determination circuit 14), active dead time control unit (active dead time control unit 40), and simultaneous on prevention circuit may be integrated into one semiconductor device. The semiconductor device may be configured to output to the outside that the gate voltage of either the first semiconductor element or the second semiconductor element has fallen below a predetermined detection threshold.

When configured in this way, integration can shorten the length of the wiring that transmits each signal, thereby reducing the delay time in signal transmission.

Furthermore, the above-mentioned configurations, functions, processing units, etc. can be realized in part or in whole in hardware, for example by designing them as integrated circuits. As hardware, broad processor devices such as FPGAs (Field Programmable Gate Arrays) and ASICs (Application Specific Integrated Circuits) may be used.

In addition, in the above-described embodiment, the control lines and information lines are those that are considered necessary for the explanation, and not all control lines and information lines in the product are necessarily shown. In reality, it can be considered that almost all components are connected to each other.

10, 20...gate drive control device, 11...gate drive unit, 12, 12A-12D...gate monitor unit, 13...reference voltage generation circuit, 14...gate state determination circuit, 15...Miller clamp circuit, 21...gate drive unit, 22...gate monitor unit, 31...first semiconductor element, 32...second semiconductor element, 40...active dead time control unit, 50...simultaneous on prevention circuit, 100, 600, 800...inverter device, G1, G2...gate

Claims (9)

A gate drive control device that drives a gate of a first semiconductor element,
a Miller clamp circuit that holds a gate voltage of the first semiconductor element at a low level when the gate voltage of the first semiconductor element becomes less than a predetermined control threshold;
a gate monitor circuit that detects when a gate voltage of the first semiconductor element falls below a predetermined detection threshold of a positive potential;
When the first semiconductor element is turned off, the gate monitor circuit is configured to detect that the gate voltage of the first semiconductor element has fallen below the detection threshold simultaneously with or after the Miller clamp circuit starts to operate. 2. The gate drive control device according to claim 1, further comprising: an active dead time control unit that turns on a second semiconductor element of a paired arm connected in series with the first semiconductor element after the gate monitor circuit detects that the gate voltage of the first semiconductor element has fallen below the detection threshold. The gate drive control device according to claim 2 , wherein the detection threshold of the gate monitor circuit is set to a value equal to or smaller than the control threshold of the Miller clamp circuit. 4. The gate drive control device according to claim 3, wherein when the gate monitor circuit does not detect that the gate voltage of one of the semiconductor elements has fallen below a predetermined detection threshold, the other semiconductor element is inhibited from being turned on. the gate monitor circuit detects that a gate voltage of the first semiconductor element and a gate voltage of the second semiconductor element fall below a predetermined detection threshold;
a gate driver for driving a gate of the first semiconductor device and a gate of the second semiconductor device;
5. The gate drive control device according to claim 4, further comprising: a simultaneous-on prevention circuit that, when the gate monitor circuit does not detect that the gate voltage of one of the semiconductor elements has fallen below a predetermined detection threshold, prohibits the gate drive unit from driving the gate of the other semiconductor element. a reference voltage for determining the control threshold and the detection threshold;
The gate drive control device according to claim 3 , wherein the reference voltage is set before gate drive starts. 4. The gate drive control device according to claim 3, wherein at least one of the detection threshold and the control threshold is configured to be set by information of an external signal, and is set before gate drive starts, and then changed by the information of the external signal depending on the state of the first semiconductor element. Integrating one or more of the gate driver, the Miller clamp circuit, the gate monitor circuit, the active dead time control circuit, and the simultaneous on prevention circuit into one semiconductor device;
The gate drive control device according to claim 1 , further comprising: an output that indicates that the gate voltage of either the first semiconductor element or the second semiconductor element has fallen below a predetermined detection threshold, the output being sent to an external device of the semiconductor device. a gate driver that drives a gate of a first semiconductor element and a gate of a second semiconductor element that configure the upper arm and the lower arm;
a Miller clamp circuit that holds the gate voltage of the first semiconductor element and the gate voltage of the second semiconductor element at a low level when the gate voltage of the first semiconductor element and the gate voltage of the second semiconductor element become less than a predetermined control threshold value;
a gate monitor circuit that detects when a gate voltage of the first semiconductor element and a gate voltage of the second semiconductor element fall below a predetermined detection threshold value of a positive potential;
When one of the semiconductor elements is turned off, the gate monitor circuit is configured to detect that the gate voltage of the one of the semiconductor elements has fallen below the detection threshold simultaneously with or after the Miller clamp circuit starts to operate.

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