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WO2025127740A1 - Carte de circuit imprimé flexible, module cof et dispositif électronique les comprenant - Google Patents

Carte de circuit imprimé flexible, module cof et dispositif électronique les comprenant Download PDF

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Publication number
WO2025127740A1
WO2025127740A1 PCT/KR2024/020364 KR2024020364W WO2025127740A1 WO 2025127740 A1 WO2025127740 A1 WO 2025127740A1 KR 2024020364 W KR2024020364 W KR 2024020364W WO 2025127740 A1 WO2025127740 A1 WO 2025127740A1
Authority
WO
WIPO (PCT)
Prior art keywords
thickness
pad portion
circuit pattern
metal layer
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/KR2024/020364
Other languages
English (en)
Korean (ko)
Inventor
윤형규
채성민
박지효
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LG Innotek Co Ltd
Original Assignee
LG Innotek Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LG Innotek Co Ltd filed Critical LG Innotek Co Ltd
Publication of WO2025127740A1 publication Critical patent/WO2025127740A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0263—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
    • H05K1/0265—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board characterized by the lay-out of or details of the printed conductors, e.g. reinforced conductors, redundant conductors, conductors having different cross-sections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/147—Structural association of two or more printed circuits at least one of the printed circuits being bent or folded, e.g. by using a flexible printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings

Definitions

  • the present invention relates to a flexible circuit board, a COF module and an electronic device including the same.
  • a COF Chip On Film
  • the substrate is flexible. That is, the COF is a flexible circuit board. Accordingly, the COF is applied to a flexible display.
  • the COF can be applied to various wearable electronic devices.
  • the COF has a fine pitch. Accordingly, the COF is applied to a display having a high resolution.
  • the chip includes a semiconductor chip.
  • the chip may be an integrated circuit (IC) chip or a large scale integrated circuit (LSI) chip.
  • IC integrated circuit
  • LSI large scale integrated circuit
  • the chip is connected to an external circuit board and a display panel through a circuit pattern.
  • pad parts are arranged at one end and the other end of the circuit pattern, respectively.
  • One pad part is electrically connected to a terminal of the chip.
  • the other pad part is connected to a terminal of the circuit board and the display panel. Accordingly, the chip, the circuit board, and the display panel are electrically connected through the COF. Accordingly, a signal is transmitted to the display panel through the circuit pattern.
  • the flexible circuit board is connected to the display panel. Accordingly, the circuit pattern may be damaged by the high current. As a result, the reliability of the COF module may decrease.
  • Korean registered patent KR10-0618898 (2006.09.01) is disclosed.
  • the invention provides a flexible circuit board having improved reliability and a COF module including the same.
  • a flexible circuit board includes: a substrate; a plurality of circuit patterns arranged on the substrate; and a protective layer arranged on the circuit patterns, wherein each of the plurality of circuit patterns has a thickness exceeding 8 ⁇ m and not more than 25 ⁇ m, and a thickness deviation between the plurality of circuit patterns is 0.5 ⁇ m to 3 ⁇ m.
  • each of the plurality of circuit patterns includes a buffer layer disposed on the substrate, a metal layer disposed on the buffer layer, and a bonding layer disposed on the metal layer.
  • the bonding layer is arranged to cover a side surface of the buffer layer, a side surface of the metal layer, and an upper surface of the metal layer.
  • the thickness deviation between the metal layers of the plurality of circuit patterns is 0.5 ⁇ m to 3 ⁇ m.
  • the metal layer includes a first metal layer and a second metal layer on the first metal layer, and a thickness of the second metal layer is greater than a thickness of the first metal layer.
  • the thickness deviation between the second metal layers of the plurality of circuit patterns is 0.5 ⁇ m to 3 ⁇ m.
  • the substrate includes a first side end and a second side end
  • the protective layer includes a first open area overlapping a region between the first side end and the second side end along a thickness direction, a second open area spaced apart from the first open area and closest to the first side end, and a third open area spaced apart from the first open area and the second open area and closest to the second side end.
  • the circuit pattern includes a first circuit pattern including a first pad portion arranged in the first open area; a second pad portion arranged in the second open area, and a first wiring portion connecting between the first pad portion and the second pad portion; and a second circuit pattern including a third pad portion arranged in the first open area; a fourth pad portion arranged in the third open area, and a second wiring portion connecting between the third pad portion and the fourth pad portion.
  • the thickness deviation of the first circuit pattern is 0.3 ⁇ m to 2.5 ⁇ m.
  • the thickness deviation of the second circuit pattern is 0.3 ⁇ m to 5 ⁇ m.
  • the thickness deviation between the first pad portion and the third pad portion is 0.3 ⁇ m to 0.9 ⁇ m.
  • the thickness deviation of the second pad portion is 0.5 ⁇ m to 3 ⁇ m.
  • the thickness deviation of the fourth pad portion is 1 ⁇ m to 5 ⁇ m.
  • the circuit pattern further includes a third circuit pattern including a fifth pad portion arranged in the second open area, a sixth pad portion arranged in the third open area, and a third wiring portion connecting the fifth pad portion and the sixth pad portion.
  • the thickness deviation of the first circuit pattern, the second circuit pattern, and the third circuit pattern is 1 ⁇ m to 5 ⁇ m.
  • the first circuit pattern is arranged on one surface of the substrate
  • the third circuit pattern is arranged on the other surface of the substrate
  • the second circuit pattern is arranged on each of the one surface and the other surface of the substrate and connected through a via.
  • a flexible circuit board includes a plurality of circuit patterns.
  • the circuit patterns have a set thickness.
  • the circuit patterns have a thickness exceeding 8 ⁇ m.
  • the circuit patterns have a uniform line width.
  • the above flexible circuit board is connected to a display panel.
  • the above display panel may have high performance. Accordingly, a high current may flow through the display panel.
  • the above high current is transmitted to the flexible circuit board. Since the circuit pattern is formed within a set thickness range, the circuit pattern can be prevented from being damaged by the high current.
  • the above circuit pattern has a uniform thickness. That is, the thickness deviation of the above circuit pattern is small.
  • the plating process for forming the circuit pattern is controlled.
  • a shielding layer can be placed in an area where the plating thickness is thick so as to have a uniform thickness compared to the plating thickness of other areas.
  • the thickness deviation of the circuit pattern is reduced.
  • the thickness deviation of each circuit pattern is reduced.
  • the thickness deviation of each pad portion is reduced.
  • Figure 1 is a top view of a flexible circuit board according to an embodiment.
  • Figures 2 and 3 are cross-sectional views taken along the A-A' section of Figure 1.
  • Figure 4 is a cross-sectional view taken along the B-B' section of Figure 1.
  • Figures 5 and 6 are drawings illustrating a first process for forming a circuit pattern.
  • Figure 7 is a scanning electron microscope (SEM) image of a circuit pattern formed by the first process.
  • Figures 8 to 16 are drawings illustrating a second process for forming a circuit pattern.
  • Figure 17 is a scanning electron microscope (SEM) image of a circuit pattern formed by the second process.
  • Fig. 18 is a drawing for explaining the connection of a COF module and other members according to an embodiment.
  • FIGS. 19 to 21 are drawings of electronic devices including flexible circuit boards according to embodiments.
  • the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.
  • the singular may also include the plural unless specifically stated in the phrase, and when it is described as “and (and) at least one (or more than one) of B, C,” it may include one or more of all combinations that can be combined with A, B, C.
  • a component when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.
  • each component when it is described as being formed or arranged "above or below" each component, above or below includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components.
  • the first direction (1D) is the direction in which the pad portion of the display panel and the pad portion of the circuit board face each other.
  • the second direction (2D) is the direction perpendicular to the first direction (1D).
  • a flexible circuit board (1000) includes a substrate (100), a circuit pattern, and a protective layer (300).
  • the above-described substrate (100) includes a first surface (1S) and a second surface (2S) opposite to the first surface (1S).
  • the circuit pattern and the protective layer (300) are arranged on the first surface (1S).
  • the above substrate (100) includes a cutting line (CL).
  • the flexible circuit board (1000) is cut along the cutting line (CL).
  • the circuit pattern, the metal pattern, the protective layer, and the chip are arranged on the substrate (100).
  • the substrate (100) is cut along the cutting line (CL). Accordingly, a COF module is manufactured. Accordingly, the edge of the COF module becomes the cutting line (CL).
  • the above description (100) includes a valid area (AA) and an ineffective area (UA).
  • the first surface (1S) includes the valid area (AA) and the ineffective area (UA).
  • the above valid area (AA) and the above non-valid area (UA) are separated by the cutting line (CL).
  • the above valid area (AA) is an inner area of the cutting line (CL).
  • the above non-valid area (UA) is an outer area of the cutting line (CL).
  • the circuit pattern, the protective layer, and the chip are arranged on the effective area (AA).
  • a dummy pattern and a sprocket hole (SH) are arranged on the ineffective area (UA).
  • the dummy pattern increases the strength of the substrate (100).
  • the flexible circuit board (1000) is rolled or unrolled in a roll-to-roll manner by the sprocket hole (SH).
  • the above-described substrate (100) includes a chip mounting area (CHA).
  • the chip mounting area (CHA) is disposed on the first surface (1S).
  • the chip mounting area (CHA) is disposed on the effective area (AA).
  • the chip (CH) is disposed on the chip mounting area (CHA).
  • pad portions of the circuit pattern are disposed inside the chip mounting area (CHA).
  • the protective layer (300) is not disposed on the chip mounting area (CHA).
  • the substrate (100) includes a flexible material.
  • the substrate (100) may include polyimide (PI).
  • PI polyimide
  • the substrate (100) may include a polymer material including polyethylene terephthalate (PET) or polyethylene naphthalate (PEN). Accordingly, the flexible circuit board can be applied to various electronic devices including a curved display device.
  • the substrate (100) may have a thickness of 20 ⁇ m to 100 ⁇ m.
  • the substrate (100) may have a thickness of 25 ⁇ m to 50 ⁇ m.
  • the substrate (100) may have a thickness of 30 ⁇ m to 40 ⁇ m.
  • the thickness of the substrate (100) exceeds 100 ⁇ m, the overall thickness of the flexible circuit board increases. Accordingly, the flexible characteristic of the flexible circuit board may be reduced.
  • the thickness of the substrate (100) is less than 20 ⁇ m, the substrate (100) may be damaged by heat and pressure applied to the substrate (100) when mounting the chip on the flexible circuit board.
  • the circuit pattern and the protective layer (300) are disposed on the substrate (100). In detail, the circuit pattern and the protective layer (300) are disposed on the first surface (1S). In detail, the circuit pattern and the protective layer (300) are disposed on at least one of the effective area (AA) and the uneffective area (UA).
  • the above circuit pattern includes a first circuit pattern (210), a second circuit pattern (220), and a third circuit pattern (230).
  • the first circuit pattern (210) includes a first wiring portion (211), a first pad portion (212a), and a second pad portion (212b).
  • the first wiring portion (211), the first pad portion (212a), and the second pad portion (212b) may include the same material.
  • the first wiring portion (211), the first pad portion (212a), and the second pad portion (212b) may be formed integrally.
  • the first pad portion (212a) is positioned inside the chip mounting area (CHA). Accordingly, the first pad portion (212a) is connected to the terminal of the chip. As a result, the first circuit pattern (210) and the chip are connected.
  • the second pad portion (212b) is positioned outside the chip mounting area (CHA).
  • the second pad portion (212b) is connected to the pad portion of the circuit board (3000).
  • the first circuit pattern (210) and the circuit board (3000) are connected.
  • the first wiring portion (211) is arranged between the first pad portion (212a) and the second pad portion (212b).
  • the first wiring portion (211) connects the first pad portion (212a) and the second pad portion (212b). Accordingly, the chip (CH) and the circuit board (3000) are connected. Accordingly, a signal generated from the chip (CH) is transmitted to the circuit board (3000).
  • the first circuit pattern (210) may further include a test pad portion.
  • a first test pad portion (TP1) is arranged in the non-valid area (UA).
  • the first wiring portion (211), the first pad portion (212a), the second pad portion (212b), and the first test pad portion (TP1) may be formed integrally.
  • the first circuit pattern (210) Before connecting the circuit board and the second pad portion (212b), the first circuit pattern (210) can be tested by the first test pad portion (TP1). For example, whether the first circuit pattern is open or shorted can be checked through the first test pad portion (TP1).
  • the second circuit pattern (220) includes a second wiring portion (221), a third pad portion (222a), and a fourth pad portion (222b).
  • the second wiring portion (221), the third pad portion (222a), and the fourth pad portion (222b) may include the same material.
  • the second wiring portion (221), the third pad portion (222a), and the fourth pad portion (222b) may be formed integrally.
  • the third pad portion (222a) is positioned inside the chip mounting area (CHA). Accordingly, the third pad portion (222a) is connected to the terminal of the chip. As a result, the second circuit pattern (220) and the chip (CH) are connected.
  • the fourth pad portion (222b) is positioned outside the chip mounting area (CHA).
  • the fourth pad portion (222b) is connected to the pad portion of the external display panel (4000).
  • the second circuit pattern (220) and the display panel (4000) are connected.
  • the second wiring section (221) is arranged between the third pad section (222a) and the fourth pad section (222b).
  • the second wiring section (221) connects the third pad section (222a) and the fourth pad section (222b). Accordingly, the chip (CH) and the display panel (4000) are connected. Accordingly, a signal generated from the chip (CH) is transmitted to the display panel (4000).
  • the second circuit pattern (220) may further include a test pad portion.
  • a second test pad portion (TP2) is arranged in the non-effective area (UA).
  • the second test pad portion (TP2) is arranged outside the cutting line (CL).
  • the second test pad portion (TP2) is arranged on the non-effective area (UA).
  • the second wiring portion (221), the third pad portion (222a), the fourth pad portion (222b), and the second test pad portion (TP2) may be formed integrally.
  • the second circuit pattern (220) Before connecting the circuit board and the fourth pad portion (222b), the second circuit pattern (220) can be tested by the second test pad portion (TP2). For example, whether the second circuit pattern is open or shorted can be checked through the second test pad portion (TP2).
  • the third circuit pattern (230) includes a third wiring portion (231), a fifth pad portion (232a), and a sixth pad portion (232b).
  • the third wiring portion (231), the fifth pad portion (232a), and the sixth pad portion (232b) may include the same material.
  • the third wiring portion (231), the fifth pad portion (232a), and the sixth pad portion (232b) may be formed integrally.
  • the fifth pad portion (232a) and the sixth pad portion (232b) are arranged outside the chip mounting area (CHA).
  • the fifth pad portion (232a) can be connected to the pad portion of the circuit board (2000).
  • the sixth pad portion (232b) can be connected to the pad portion of the display panel (4000).
  • the third wiring section (231) is arranged between the fifth pad section (232a) and the sixth pad section (232b).
  • the third wiring section (231) connects the fifth pad section (232a) and the sixth pad section (232b). Accordingly, the circuit board (3000) and the display panel (4000) are connected.
  • the third circuit pattern (230) may be a bypass circuit.
  • the third circuit pattern (230) may be a power supply pattern. Accordingly, the circuit board and the display panel may be supplied with power by the third circuit pattern (230).
  • the third circuit pattern (230) may include a plurality of third circuit patterns spaced apart in the second direction (2D).
  • the line width and spacing of the third circuit pattern (230) may be larger than the line width and spacing of the first circuit pattern (210).
  • the line width and spacing of the third circuit pattern (230) may be larger than the line width and spacing of the second circuit pattern (220).
  • At least one dummy pattern may be placed on the effective area (AA).
  • the above dummy pattern can prevent the flexible circuit board (1000) from bending.
  • the spacing and line width of the circuit pattern can be made uniform by the dummy pattern.
  • the above dummy pattern may include the same material as the circuit pattern.
  • the line width of the dummy pattern may be the same as or different from the circuit pattern.
  • the dummy pattern is not connected to the chip (CH), the circuit board (3000), and the display panel (4000).
  • At least one of the third circuit pattern and the dummy pattern may be an outermost pattern.
  • the outermost pattern in the second direction (2D) of the substrate (100) may be at least one of the third circuit pattern and the dummy pattern.
  • the protective layer (300) is disposed on the first surface (1S). Accordingly, the protective layer (300) is disposed on the first circuit pattern (210), the second circuit pattern (220), and the third circuit pattern (230). The protective layer (300) is disposed on the first wiring portion (211), the second wiring portion (221), and the third wiring portion (231). The protective layer (300) is not disposed on the first pad portion (212a), the second pad portion (212b), the third pad portion (222a), the fourth pad portion (222b), the fifth pad portion (232a), and the sixth pad portion (232b). In addition, the protective layer (300) is not disposed on the chip mounting area (CHA).
  • FIGS. 2 and 3 the circuit pattern is formed in a multilayer structure.
  • FIGS. 2 and 3 are described with reference to the first circuit pattern. The following description applies equally to the second and third circuit patterns.
  • the first circuit pattern is formed in multiple layers.
  • the first wiring portion (211), the first pad portion (212a), and the second pad portion (212b) include a buffer layer (205), a metal layer (201), and a bonding layer (203).
  • the above buffer layer (205) may include multiple layers.
  • the buffer layer (205) includes a first buffer layer (205a) and a second buffer layer (205b).
  • the first buffer layer (205a) is disposed on the substrate (100).
  • the second buffer layer (205b) is disposed on the first buffer layer (205a).
  • the first buffer layer (205a) includes a material having good adhesion to the substrate (100).
  • the first buffer layer (205a) may include nickel (Ni).
  • the second buffer layer (205b) includes a material having good adhesion to the circuit pattern.
  • the second buffer layer (205b) may include chromium (Cr).
  • the above buffer layer (205) may have a thin film thickness in nanometer units.
  • the above buffer layer (205) may have a thickness of 20 nm or less.
  • the adhesion between the substrate (100) and the circuit pattern is improved by the buffer layer (205).
  • the metal layer (201) is disposed on the buffer layer (205).
  • the metal layer (201) is disposed on the second buffer layer (205b).
  • the metal layer (201) includes a metal material.
  • the metal layer (201) may include copper (Cu).
  • the above metal layer (201) can be formed by electroplating using the buffer layer as a seed layer. That is, the above metal layer (201) can be a plating layer.
  • the thickness of the above metal layer (201) may be 10 ⁇ m to 30 ⁇ m.
  • the above bonding layer (203) is placed on the metal layer (201).
  • the above bonding layer (203) is arranged on the side and upper surface of the metal layer (201).
  • the bonding layer (203) may be arranged to surround the metal layer (201).
  • the above bonding layer (203) includes a metal.
  • the above bonding layer (203) may include tin (Sn).
  • the above bonding layer (203) is formed by a plating process.
  • the above bonding layer (203) may be a plating layer.
  • the thickness of the above bonding layer (203) may be 0.3 ⁇ m to 0.7 ⁇ m.
  • the tin content may increase as it extends from the lower surface to the upper surface of the above bonding layer (203).
  • the bonding layer (203) is in contact with the metal layer (201). Therefore, the tin content increases from the lower surface of the bonding layer (203) toward the upper surface. Additionally, the copper content decreases from the lower surface of the bonding layer (203) toward the upper surface.
  • pure tin may remain in a thickness range of 0.1 ⁇ m to 0.3 ⁇ m from the upper surface of the bonding layer (203).
  • the above pad portion can be easily bonded to the terminals of the chip, the circuit board, and the display panel by the bonding layer (203). For example, when heat and pressure are applied to the pad portion, the upper surface of the bonding layer melts. Pure tin remains on the upper surface of the bonding layer. Therefore, the pad portion can be easily bonded to the terminals of the chip, the circuit board, and the display panel.
  • the metal layer (201) may include a first metal layer (201a) and a second metal layer (201b).
  • the first metal layer (201a) is disposed on the buffer layer (205).
  • the second metal layer (201b) is disposed on the first metal layer (201a).
  • the second metal layer (201b) may be formed by electroplating using the first metal layer (201a) as a seed layer. That is, the second metal layer (201b) may be a plating layer.
  • the thickness of the first metal layer (201a) may be smaller than the thickness of the second metal layer (201b).
  • the thickness of the first metal layer (201a) may be 0.7 ⁇ m to 2 ⁇ m, and the thickness of the second metal layer (201b) may be 6 ⁇ m to 25 ⁇ m.
  • the first metal layer (201a) and the second metal layer (201b) may include the same metal material.
  • the first metal layer (201a) and the second metal layer (201b) may include copper (Cu).
  • the above bonding layer (203) may include a first bonding layer (203a) and a second bonding layer (203b).
  • the first bonding layer (203a) is disposed on the metal layer (201).
  • the first bonding layer (203a) is disposed on the second wiring portion (221), the third pad portion (222a), and the fourth pad portion (222b).
  • the second bonding layer (203b) is disposed on the first bonding layer (203a).
  • the second bonding layer (203b) is disposed on the third pad portion (222a) and the fourth pad portion (222b).
  • the second wiring portion (221) includes the buffer layer (205), the metal layer (201), and the first bonding layer (203a).
  • the third pad portion (222a) and the fourth pad portion (222b) include the buffer layer (205), the metal layer (201), the first bonding layer (203a), and the second bonding layer (203b).
  • the layer structure of the second wiring portion (221) is different from the layer structures of the first pad portion (212a) and the second pad portion (212b).
  • the first bonding layer (203a) and the second bonding layer (203b) contain metal.
  • the first bonding layer (203a) and the second bonding layer (203b) may contain tin (Sn).
  • the first bonding layer (203a) and the second bonding layer (203b) are arranged with different thicknesses.
  • the thickness of the second bonding layer (203b) is greater than the thickness of the first bonding layer (203a).
  • the first bonding layer (203a) has a thickness of 0.02 ⁇ m to 0.06 ⁇ m.
  • the second bonding layer (203b) has a thickness of 0.2 ⁇ m to 0.6 ⁇ m.
  • the flexible circuit board includes a bending area (BA) that is bent in one area.
  • the wiring portion is arranged on the bending area (BA). Accordingly, the thickness of the bonding layer on the wiring portion is formed small. Accordingly, when the flexible circuit board is bent, cracks can be prevented from being formed in the first wiring portion (211).
  • the thickness of the circuit pattern may be greater than 8 ⁇ m and less than or equal to 25 ⁇ m. In detail, the thickness of the circuit pattern may be from 9 ⁇ m to 20 ⁇ m. In detail, the thickness of the circuit pattern may be from 10 ⁇ m to 15 ⁇ m.
  • the thickness of the circuit pattern is less than 8 ⁇ m, the resistance of the circuit pattern may increase. In addition, when a high current flows through the display panel, the circuit pattern may be damaged. If the thickness of the circuit pattern exceeds 25 ⁇ m, it becomes difficult to implement a fine pattern.
  • Figure 4 is a cross-sectional view taken along the B-B' section of Figure 1.
  • the first wiring portion (211) includes a buffer layer (205), a first metal layer (201a), a second metal layer (201b), and a bonding layer (203).
  • the buffer layer (205) and the bonding layer (203) are formed with a thin film thickness. Accordingly, the total thickness (T3) of the first wiring portion (211) is determined by the thickness (T2) of the metal layers (201a, 201b) or the thickness (T2) of the second metal layer (201b).
  • the above metal layer may be formed as one metal layer as shown in Fig. 2.
  • the metal layer may be formed as two metal layers as shown in Fig. 3.
  • Figures 5 to 7 are drawings for explaining a first process for forming a circuit pattern.
  • the first process is a process for forming a circuit pattern with a single metal layer, as shown in Figure 2.
  • a buffer layer (205) is disposed on the substrate (100).
  • the metal layer (201) is disposed on the buffer layer (205).
  • a photosensitive layer (400) is placed on the metal layer (201).
  • the photosensitive layer (4000) forms a plurality of photosensitive patterns (DP) through exposure and development processes.
  • the photosensitive patterns (DP) are placed on an area where the circuit pattern is formed. Accordingly, an area between the photosensitive patterns (DP) becomes an etching area.
  • the etching area is etched.
  • the etching area is etched by spraying an etching solution onto the etching area.
  • a bonding layer (205) is formed on the metal layer (201) to form a circuit pattern.
  • the etching uniformity of the circuit pattern may decrease.
  • the thickness of the metal layer (201) exceeds 8 ⁇ m, the uniformity of the line width of the circuit pattern may decrease. That is, the thickness of the metal layer (201) may be uniform, but the line width may be uneven.
  • the line width (W) of the circuit pattern (210) is uneven. That is, as shown in FIG. 7(a), the line width of the circuit pattern (210) increases as it approaches the substrate (100). Accordingly, the line widths of the upper and lower surfaces of the circuit pattern (210) become different. As the thickness of the circuit pattern (210) increases, the line width difference between the upper and lower surfaces of the circuit pattern increases. Accordingly, the line width (W) of the circuit pattern (210) becomes uneven at each location. Accordingly, it becomes difficult to form a circuit pattern with a fine line width.
  • the embodiment forms a circuit pattern by a second process that is different from the first process.
  • FIGS. 8 to 17 are drawings illustrating the second process.
  • the buffer layer (205) is placed on the substrate (100).
  • the first metal layer (201a) is placed on the buffer layer (205).
  • the first metal layer (201a) can be formed by electrolytic or electroless plating.
  • the photosensitive layer (400) is disposed on the first metal layer (201a).
  • the photosensitive layer (400) forms a plurality of photosensitive patterns (DP) by exposure and development processes.
  • the photosensitive patterns (DP) are disposed on an area where the circuit pattern is not formed. Accordingly, the circuit pattern is formed on an area between the photosensitive patterns (DP). Accordingly, the area between the photosensitive patterns (DP) becomes a plating area. Accordingly, a plurality of plating areas are formed.
  • a second metal layer (201b) is plated on the plating area.
  • a plating solution is sprayed onto the plating area.
  • the plating thickness of the plating areas may vary. Accordingly, the thickness deviation of multiple circuit patterns may increase.
  • the thickness of one plating layer may be greater than the thickness of the plating layer in another region.
  • the shielding layer (500) may be arranged on the plating region where the plating layer has a large thickness.
  • the plating layer may have a large thickness in a wide region (W2).
  • W2 wide region
  • the shielding layer (500) may be formed on the plating region where the plating layer has a large thickness. No plating is performed on the plating region that overlaps with the shielding layer (500). In addition, plating is performed on the plating region that does not overlap with the shielding layer (500). Accordingly, the plating thicknesses of the plating layers in the large and small regions can be uniformly controlled.
  • the shielding layer (500) is placed until the thickness of the plating layer of multiple plating areas becomes uniform.
  • the chip layer is removed.
  • the photosensitive pattern (DP) is removed. Then, the first metal layer (201a) and the buffer layer (205) disposed under the photosensitive pattern (DP) are etched to separate a plurality of circuit patterns. When the first metal layer (201a) and the buffer layer (205) are etched, the second metal layer (201b) is etched together. Therefore, the thickness of the second metal layer (201b) can be slightly reduced compared to the thickness after the plating process is completed. Therefore, the plating process can be performed to a thickness slightly higher than the set circuit pattern thickness.
  • the second process plates a second metal layer on the plating area. Accordingly, the line width of the circuit patterns can be made uniform.
  • the widths of the upper and lower portions of the circuit pattern may be similar. Accordingly, the line width (W) of the circuit pattern may be uniform. In addition, the line width deviation of multiple circuit patterns may be reduced.
  • the second process controls the plating thickness.
  • the thickness deviation of the plurality of plating areas is controlled by the shield layer (500). Accordingly, the thickness of the circuit pattern can be made uniform. In addition, the thickness deviation of the plurality of circuit patterns can be reduced.
  • Tables 1 and 2 are data on the thickness of the circuit pattern formed by the second process. Tables 1 and 2 above are results after the plating process was performed with the set thickness set to 12 ⁇ m. Table 1 is comparative example data for plating without using the shielding layer. Table 2 is example data for plating using the shielding layer.
  • the average thickness of the circuit pattern exceeds the set thickness.
  • the thickness deviation of the circuit pattern is large.
  • the thickness deviation of the second pad portion and the fourth pad portion is large. Accordingly, the thickness deviations of the first pad portion, the second pad portion, the third pad portion, and the fourth pad portion also increase.
  • the average thickness of the circuit pattern is similar to the set thickness.
  • the thickness deviation of the circuit pattern is small.
  • the first to fourth pad portions have a thickness deviation of 3 ⁇ m or less. Accordingly, the thickness deviations of the first pad portion, the second pad portion, the third pad portion, and the fourth pad portion also decrease.
  • the thickness of the above circuit pattern is determined by the thickness of the second metal layer.
  • the thickness of the second metal layer is controlled by the shielding layer.
  • the thickness deviation of the second metal layer of the circuit patterns is reduced.
  • the thickness deviation of the second metal layer may be 3 ⁇ m or less.
  • the thickness deviation of the second metal layer may be 0.5 ⁇ m to 3 ⁇ m, 0.6 ⁇ m to 2.5 ⁇ m, or 0.5 ⁇ m to 2 ⁇ m.
  • the thickness deviation of the metal layer of the circuit patterns is reduced.
  • the thickness deviation of the metal layer may be 3 ⁇ m or less.
  • the thickness deviation of the metal layer may be 0.5 ⁇ m to 3 ⁇ m, 0.6 ⁇ m to 2.5 ⁇ m, or 0.5 ⁇ m to 2 ⁇ m.
  • the thickness deviation of the circuit patterns is reduced.
  • the thickness deviation of the circuit pattern may be 3 ⁇ m or less.
  • the thickness deviation of the circuit pattern may be 0.5 ⁇ m to 3 ⁇ m, 0.6 ⁇ m to 2.5 ⁇ m, or 0.5 ⁇ m to 2 ⁇ m.
  • the thickness deviation of the first circuit pattern may be 0.3 ⁇ m to 2.5 ⁇ m, 0.4 ⁇ m to 2 ⁇ m, or 0.5 ⁇ m to 1.5 ⁇ m.
  • the thickness deviation of the second circuit pattern may be 0.3 ⁇ m to 5 ⁇ m, 0.4 ⁇ m to 4 ⁇ m, or 0.5 ⁇ m to 2 ⁇ m.
  • the thickness deviation between the first pad portion and the third pad portion can be 0.3 ⁇ m to 0.9 ⁇ m.
  • the thickness deviation of the second pad portion may be 0.5 ⁇ m to 3 ⁇ m, 0.8 ⁇ m to 2 ⁇ m, or 1 ⁇ m to 1.5 ⁇ m.
  • the thickness deviation of the fourth pad portion may be 1 ⁇ m to 5 ⁇ m, 1.2 ⁇ m to 3 ⁇ m, or 1.5 ⁇ m to 2 ⁇ m.
  • the thickness deviation of the first circuit pattern, the second circuit pattern, and the third circuit pattern is reduced.
  • the thickness deviation of the first circuit pattern, the second circuit pattern, and the third circuit pattern is a difference between a largest thickness and a smallest thickness of the circuit patterns.
  • the thickness deviation of the first circuit pattern, the second circuit pattern, and the third circuit pattern may be 5 ⁇ m or less.
  • the thickness deviation of the first circuit pattern, the second circuit pattern, and the third circuit pattern may be 1 ⁇ m to 5 ⁇ m, 1.2 ⁇ m to 4 ⁇ m, or 1.4 ⁇ m to 2 ⁇ m.
  • the flexible circuit board according to the embodiment includes circuit patterns having uniform thickness and width.
  • the circuit patterns have a thickness exceeding 8 ⁇ m.
  • the circuit pattern can be prevented from being damaged by the high current of the display panel.
  • the line width and thickness of the circuit patterns become uniform, the current and signal moving in each channel can become uniform. Accordingly, the electrical characteristics of the flexible circuit board and COF module are improved.
  • one end of the COF module (2000) is connected to the display panel (4000), and the other end is connected to the circuit board (3000).
  • the display panel (4000) and the circuit board (3000) are disposed on one surface of the COF module (2000).
  • the display panel (4000) and the circuit board (3000) may be disposed on different surfaces of the COF module (2000).
  • the COF module (2000) may have circuit patterns disposed on each of both surfaces.
  • the COF module (2000) may include a first circuit pattern and a second circuit pattern disposed on a first surface, and a second circuit pattern and a third circuit pattern disposed on the second surface.
  • the second circuit patterns may be connected to each other through vias.
  • the COF module (2000) since the COF module (2000) includes a flexible substrate, it has a rigid shape and a bent shape between the display panel (3000) and the circuit board (4000). That is, the COF module (2000) may include a bending area (BA).
  • BA bending area
  • the COF module (2000) connects the display panel (4000) and the circuit board (3000), which are arranged opposite each other, in a bent form. Accordingly, the thickness of the electronic device is reduced. In addition, the design freedom of the electronic device is improved. In addition, the COF module (2000) does not have wiring break even in a bent form. Accordingly, the reliability of the electronic device is improved.
  • COF module Since the above COF module is flexible, it can be used in various electronic devices.
  • the COF module can be applied to a flexible touch window that can be bent.
  • a touch device device including the same can be a flexible touch device device. Accordingly, a user can bend or fold it by hand.
  • Such a flexible touch window can be applied to a wearable touch, etc.
  • the COF module can be applied to various wearable touch devices including a curved display. Accordingly, an electronic device including the COF module can be slimmed down or made lightweight.
  • the COF module can be used in various electronic devices having a display portion, such as a TV, a monitor, and a laptop.
  • the COF module can also be used in an electronic device having a curved display portion.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

La présente invention concerne une carte de circuit imprimé flexible comprenant : un substrat ; une pluralité de motifs de circuit disposés sur le substrat ; et une couche de protection disposée sur les motifs de circuit : l'épaisseur de chacun de la pluralité de motifs de circuit étant inférieure ou égale à 25 µm et supérieure à 8 µm ; et l'écart d'épaisseur entre la pluralité de motifs de circuit étant de 0,5 à 3 µm. Lorsque la carte de circuit imprimé flexible est connectée à un écran d'affichage, l'écran d'affichage peut avoir une performance élevée et permet à un courant élevé de circuler à travers celui-ci. Des motifs de circuit ayant les caractéristiques selon la présente invention sont empêchés d'être endommagés par le courant élevé.
PCT/KR2024/020364 2023-12-14 2024-12-16 Carte de circuit imprimé flexible, module cof et dispositif électronique les comprenant Pending WO2025127740A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020230181877A KR20250091683A (ko) 2023-12-14 2023-12-14 연성 회로기판, cof 모듈 및 이를 포함하는 전자 디바이스
KR10-2023-0181877 2023-12-14

Publications (1)

Publication Number Publication Date
WO2025127740A1 true WO2025127740A1 (fr) 2025-06-19

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PCT/KR2024/020364 Pending WO2025127740A1 (fr) 2023-12-14 2024-12-16 Carte de circuit imprimé flexible, module cof et dispositif électronique les comprenant

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KR (1) KR20250091683A (fr)
WO (1) WO2025127740A1 (fr)

Citations (5)

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Publication number Priority date Publication date Assignee Title
KR20180125350A (ko) * 2017-05-15 2018-11-23 엘지이노텍 주식회사 올인원 칩 온 필름용 연성 회로기판 및 이를 포함하는 칩 패키지, 및 이를 포함하는 전자 디바이스
KR20220002219A (ko) * 2019-11-01 2022-01-06 주식회사 에이맵플러스 디스플레이 패널 및 이의 패턴 형성 방법
KR20220054102A (ko) * 2020-10-23 2022-05-02 엘지이노텍 주식회사 연성 인쇄회로기판, cof 모듈 및 이를 포함하는 전자디바이스
KR20220055759A (ko) * 2020-10-27 2022-05-04 엘지이노텍 주식회사 연성 인쇄회로기판, cof 모듈 및 이를 포함하는 전자디바이스
KR20220082480A (ko) * 2020-12-10 2022-06-17 주식회사 원탑플레이팅 연성인쇄회로기판의 제조방법 및 이를 이용하여 형성된연성 인쇄회로기판의 금속 배선패턴

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180125350A (ko) * 2017-05-15 2018-11-23 엘지이노텍 주식회사 올인원 칩 온 필름용 연성 회로기판 및 이를 포함하는 칩 패키지, 및 이를 포함하는 전자 디바이스
KR20220002219A (ko) * 2019-11-01 2022-01-06 주식회사 에이맵플러스 디스플레이 패널 및 이의 패턴 형성 방법
KR20220054102A (ko) * 2020-10-23 2022-05-02 엘지이노텍 주식회사 연성 인쇄회로기판, cof 모듈 및 이를 포함하는 전자디바이스
KR20220055759A (ko) * 2020-10-27 2022-05-04 엘지이노텍 주식회사 연성 인쇄회로기판, cof 모듈 및 이를 포함하는 전자디바이스
KR20220082480A (ko) * 2020-12-10 2022-06-17 주식회사 원탑플레이팅 연성인쇄회로기판의 제조방법 및 이를 이용하여 형성된연성 인쇄회로기판의 금속 배선패턴

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