WO2025122588A1

WO2025122588A1 - Systems and methods for power and noise configurable analog to digital converters

Info

Publication number: WO2025122588A1
Application number: PCT/US2024/058423
Authority: WO
Inventors: Echere Iroaga; Michael D. Scott
Original assignee: Encharge Ai Inc
Current assignee: Encharge Ai Inc
Priority date: 2023-12-04
Filing date: 2024-12-04
Publication date: 2025-06-12
Anticipated expiration: 2026-06-04
Also published as: TW202531233A

Abstract

A circuit can include a compute in-memory (CIM) array of multiplying bit-cells with analog to digital converters (ADCs) coupled with the array, each ADC including a reference voltage terminal receiving a reference voltage with a full-scale range of each ADC being a function of the reference voltage, an analog voltage input receiving a result analog voltage, and a set of programmable capacitors having a capacitance value based on a capacitance input where a noise performance of the ADC is a function of the capacitance input. Each ADC provides a digital output that is a representation of the result analog voltage received at the analog voltage input. The circuit can include programmable reference voltage generators receiving reference voltage configuration bits, and generating the reference voltage for a respective ADC based on the reference voltage configuration bits.

Description

SYSTEMS AND METHODS FOR POWER AND NOISE CONFIGURABLE ANALOG TO DIGITAL CONVERTERS

CROSS-REFERENCE TO RELATED APPLICATION

This Application claims priority to and the benefit of United States Provisional Application Number 63/606,022, filed December 4, 2023.

TECHNICAL FIELD

[0001] This disclosure relates to in-memory computing arrays, and in particular to power and noise configurable analog to digital converters.

DESCRIPTION OF THE RELATED TECHNOLOGY

[0002] Using in-memory computing for neural network acceleration is an emerging and innovative approach that leverages the unique properties of memory devices to enhance the speed and efficiency of neural network computations. Traditional neural network training and inference processes involve moving data back and forth between memory (RAM) and processing units (CPUs or GPUs), which can be a significant bottleneck in terms of speed and energy consumption. In-memory computing seeks to overcome these limitations by processing data directly within the memory itself.

SUMMARY

[0003] In some aspects, the techniques described herein relate to a circuit, including: a compute in-memory (CIM) array of multiplying bit-cells, the array generating a plurality of result analog voltages resulting from a multiplication of data stored in the multiplying bit-cells and input voltages; a plurality of analog to digital converters (ADCs) coupled with the CIM array, each ADC of the plurality of ADCs including: a reference voltage terminal receiving a reference voltage, wherein a full-scale range of each ADC is a function of the reference voltage, an analog voltage input of a plurality of analog voltage inputs receiving a result analog voltage of a plurality of result analog voltages, a set of programmable capacitors configured to have a capacitance value based on a capacitor configuration input, wherein a noise performance of the ADC is a function of the capacitance value, and a digital output providing a digital representation of the result analog voltage received at the analog voltage input; and a plurality of programmable reference voltage generators coupled with a plurality of reference voltage terminals of the plurality of ADCs, each programmable reference voltage generator of the plurality of programmable reference voltage generators receiving one or more reference voltage configuration bits, and generating the reference voltage for a respective ADC of the plurality of ADCs based on the one or more reference voltage configuration bits.

[0004] In some aspects, the techniques described herein relate to a circuit, wherein the capacitor configuration input and the one or more reference voltage configuration bits are based on data stored in the multiplying bit-cells of the CIM array of multiplying bit-cells. [0005] In some aspects, the techniques described herein relate to a circuit, wherein the capacitor configuration input and the one or more reference voltage bits are configured such that for a respective ADC a decrease in the reference voltage corresponds to an increase in the capacitance value of the set of programmable capacitors.

[0006] In some aspects, the techniques described herein relate to a circuit, wherein the capacitor configuration input is configured to be independent of the reference voltage.

[0007] In some aspects, the techniques described herein relate to a circuit, wherein each ADC of the plurality of ADCs is a successive-approximation-register ADC including at least one comparator, wherein the at least one comparator includes: a pre-amplifier stage coupled with the input terminals of the comparator, and a latch stage coupled with the pre-amplifier stage, wherein the set of programmable capacitors is positioned at the output of the pre-amplifier stage.

[0008] In some aspects, the techniques described herein relate to a circuit, wherein the set of programmable capacitors is positioned at an input of each ADC.

[0009] In some aspects, the techniques described herein relate to a circuit, further including: a controller configured to: receive as input at least a portion of the data stored in the multiplying bit-cells, determine the full-scale range of each ADC of the plurality of ADCs, determine a recommended reference voltage for each ADC of the plurality of ADCs, determine a recommended capacitance for each ADC of the plurality of ADCs, and set the one or more reference voltage configuration bits and the capacitor configuration input for each ADC of the plurality of ADCs, respectively, based on the recommended reference voltage and the recommended capacitance.

[0010] In some aspects, the techniques described herein relate to a circuit, wherein the controller is configured to: determine the recommended reference voltage based on a reference voltage look-up table, and determine the recommended capacitance based on a capacitance look-up table.

[0011] In some aspects, the techniques described herein relate to a circuit, wherein the controller is configured to: determine the recommended reference voltage and the recommended capacitance based on a desired signal to noise ratio (SNR). [0012] In some aspects, the techniques described herein relate to a circuit, further including: a plurality of capacitor configuration registers storing capacitor configuration inputs corresponding to the plurality of ADCs; and a plurality of reference voltage configuration registers storing one or more reference voltage configuration bits corresponding to the plurality of programmable reference voltage generators.

[0013] In some aspects, the techniques described herein relate to a circuit, wherein the plurality of capacitor configuration registers and the plurality of reference voltage configuration registers are loaded at a time of loading the data stored in the multiplying bit-cells.

[0014] In some aspects, the techniques described herein relate to a circuit, wherein each programmable capacitor of the set of programmable capacitors includes a plurality of switched capacitor, wherein states of switches of the plurality of switched capacitors are controlled based on the plurality of capacitor configuration registers.

[0015] In some aspects, the techniques described herein relate to a method for configuring a plurality of analog to digital converters (ADCs) coupled with a compute in-memory (CIM) array of multiplying bit-cells, the array generating a plurality of result analog voltages resulting from a multiplication of data stored in the multiplying bit-cells and input voltages, each of the plurality of ADCs including: a reference voltage terminal receiving a reference voltage, wherein a full-scale range of each ADC is a function of the reference voltage, an analog voltage input receiving a result analog voltage or a plurality of result analog voltages, a set of programmable capacitors configured to have a capacitance value based on a capacitor configuration input, wherein a noise performance of the ADC is a function of the capacitance value, and a digital output providing a digital representation of the result analog voltage received at the analog voltage input, the method including: generating a reference voltage for each ADC of the plurality of ADCs based on a respective reference voltage configuration bits.

[0016] In some aspects, the techniques described herein relate to a method, including: generating the capacitor configuration input and the reference voltage configuration bits based on data stored in the multiplying bit-cells of the CIM array of multiplying bit-cells. [0017] In some aspects, the techniques described herein relate to a method, including: responsive to a decrease in the reference voltage, generating the capacitor configuration input to increase the capacitance value of the set of programmable capacitors.

[0018] In some aspects, the techniques described herein relate to a method, including: generating the capacitor configuration input to change the capacitance value of the set of programmable capacitors independently of the reference voltage.

[0019] In some aspects, the techniques described herein relate to a method, wherein each ADC of the plurality of ADCs is a successive-approximation-register ADC including at least one comparator, wherein the at least one comparator includes: a pre-amplifier stage coupled with the input terminals of the comparator, and a latch stage coupled with the pre-amplifier stage, wherein the set of programmable capacitors is positioned at the output of the pre-amplifier stage.

[0020] In some aspects, the techniques described herein relate to a method, wherein the set of programmable capacitors is positioned at an input of each ADC.

[0021] In some aspects, the techniques described herein relate to a method, including: receiving as input at least a portion of the data stored in the multiplying bit-cells; determining the full-scale range of each ADC of the plurality of ADCs; determining a recommended reference voltage for each ADC of the plurality of ADCs; determining a recommended capacitance for each ADC of the plurality of ADCs; and setting the reference voltage configuration bits and the capacitor configuration input for each ADC of the plurality of ADCs, respectively, based on the recommended reference voltage and the recommended capacitance.

[0022] In some aspects, the techniques described herein relate to a method, including: determining the recommended reference voltage based on a reference voltage look-up table, and determining the recommended capacitance based on a capacitance look-up table.

[0023] In some aspects, the techniques described herein relate to a method, including: determining the recommended reference voltage and the recommended capacitance based on a desired signal -to-noise ratio (SNR).

[0024] In some aspects, the techniques described herein relate to a method, including: storing capacitor configuration inputs corresponding to the plurality of ADCs in a plurality of capacitor configuration registers; and storing the reference voltage configuration bits corresponding to the plurality of programmable reference voltage generators in a plurality of reference voltage configuration registers.

[0025] In some aspects, the techniques described herein relate to a method, including: storing capacitor configuration inputs and the reference voltage configuration bits at a time of loading the data stored in the multiplying bit-cells.

[0026] In some aspects, the techniques described herein relate to a successive- approximation-register (SAR) analog to digital converter (ADC) including: a reference voltage terminal receiving a reference voltage, wherein a full-scale range of the SAR ADC is a function of the reference voltage, an analog voltage input receiving an input analog voltage for digital conversion, a set of programmable capacitors configured to have a capacitance value based on a capacitor configuration input, wherein a noise performance of the ADC is a function of the capacitance value, and a digital output providing a digital representation of the input analog voltage received at the analog voltage input.

[0027] In some aspects, the techniques described herein relate to a SAR ADC, wherein the capacitor configuration input is based, in part, on a value of the reference voltage.

[0028] In some aspects, the techniques described herein relate to a SAR ADC, wherein the set of programmable capacitors includes a plurality of switched capacitors connected in parallel, and wherein an on or off state of switches of each of the plurality of switched capacitors is determined based on the capacitor configuration input.

[0029] In some aspects, the techniques described herein relate to a SAR ADC, wherein the reference voltage is based on an expected input analog voltage swing.

[0030] In some aspects, the techniques described herein relate to a SAR ADC, wherein the reference voltage and the capacitance configuration input are based on a desired signal-to-noise ratio (SNR).

[0031] In some aspects, the techniques described herein relate to a SAR ADC, wherein the reference voltage and the capacitance configuration input are based on a desired input analog voltage swing and a desired signal-to-noise ratio (SNR).

[0032] In some aspects, the techniques described herein relate to a SAR ADC, wherein the reference voltage and the capacitance configuration input are based on a desired power dissipation of the SAR ADC.

BRIEF DESCRIPTION OF THE DRAWINGS

[0033] FIG. 1 depicts a block diagram of an example in-memory computing architecture. [0034] FIG. 2 shows a block diagram of a compute in-memory array.

[0035] FIG. 3 shows an example circuit diagram of the computing cells discussed above in relation to FIG. 2.

[0036] FIG. 4 depicts a block diagram of an example successive-approximation-register (SAR) analog to digital converter (ADC) architecture.

[0037] FIG. 5 depicts a block diagram of a SAR ADC comparator example architecture. [0038] FIG. 6 is a schematic circuit diagram of a programmable capacitor bank for implementation as programmable capacitors. [0039] FIG. 7 shows simulated results of SAR ADC comparator noise and power in response to changes in pre-amplifier stage capacitance.

[0040] FIG. 8 is a block diagram of an analog bias generator.

[0041] FIG. 9 is a schematic circuit diagram of bias generator.

[0042] FIG. 10 is a schematic circuit diagram of ADC reference voltage generator.

[0043] FIG. 11 is a block diagram of an example controller.

[0044] Like reference numbers and designations in the various drawings indicate like elements.

DETAILED DESCRIPTION

[0045] The various concepts introduced above and discussed in greater detail below can be implemented in any of numerous ways, as the described concepts are not limited to any particular manner of implementation. Examples of specific implementations and applications are provided primarily for illustrative purposes.

[0046] As will be apparent to those of skill in the art upon reading this disclosure, each of the individual aspects described and illustrated herein has discrete components and features which can be readily separated from or combined with the features of any of the other several aspects without departing from the scope or spirit of the present disclosure. [0047] Any recited method can be carried out in the order of events recited or in any other order that is logically possible. That is, unless otherwise expressly stated, it is in no way intended that any method or aspect set forth herein be construed as requiring that its steps be performed in a specific order. Accordingly, where a method claim does not specifically state in the claims or descriptions that the steps are to be limited to a specific order, it is no way intended that an order be inferred, in any respect. This holds for any possible nonexpress basis for interpretation, including matters of logic with respect to arrangement of steps or operational flow, plain meaning derived from grammatical organization or punctuation, or the number or type of aspects described in the specification.

[0048] All publications mentioned herein are incorporated herein by reference to disclose and describe the methods and/or materials in connection with which the publications are cited. All such publications and patents are herein incorporated by references as if each individual publication or patent were specifically and individually indicated to be incorporated by reference. Such incorporation by reference is expressly limited to the methods and/or materials described in the cited publications and patents and does not extend to any lexicographical definitions from the cited publications and patents. Any lexicographical definition in the publications and patents cited that is not also expressly repeated in the instant specification should not be treated as such and should not be read as defining any terms appearing in the accompanying claims. The publications discussed herein are provided solely for their disclosure prior to the filing date of the present application. Nothing herein is to be construed as an admission that the present invention is not entitled to antedate such publication by virtue of prior invention. Further, the dates of publication provided herein can be different from the actual publication dates, which can require independent confirmation.

[0049] While aspects of the present disclosure can be described and claimed in a particular statutory class, such as the system statutory class, this is for convenience only and one of skill in the art will understand that each aspect of the present disclosure can be described and claimed in any statutory class.

[0050] It is also to be understood that the terminology used herein is for the purpose of describing particular aspects only and is not intended to be limiting. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosed compositions and methods belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0051] It should be noted that ratios, concentrations, amounts, and other numerical data can be expressed herein in a range format. It will be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint. It is also understood that there are a number of values disclosed herein, and that each value is also herein disclosed as “about” that particular value in addition to the value itself. For example, if the value “10” is disclosed, then “about 10” is also disclosed. Ranges can be expressed herein as from “about” one particular value, and/or to “about” another particular value. Similarly, when values are expressed as approximations, by use of the antecedent “about,” it will be understood that the particular value forms a further aspect. For example, if the value “about 10” is disclosed, then “10” is also disclosed.

[0052] When a range is expressed, a further aspect includes from the one particular value and/or to the other particular value. For example, where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included in the disclosure, e.g. the phrase “x to y” includes the range from ‘x’ to ‘y’ as well as the range greater than ‘x’ and less than ‘y’. The range can also be expressed as an upper limit, e.g. ‘about x, y, z, or less’ and should be interpreted to include the specific ranges of ‘about x’, ‘about y’, and ‘about z’ as well as the ranges of Tess than x’, less than y’, and Tess than z’. Likewise, the phrase ‘about x, y, z, or greater’ should be interpreted to include the specific ranges of ‘about x’, ‘about y’, and ‘about z’ as well as the ranges of ‘greater than x’, greater than y’, and ‘greater than z’. In addition, the phrase “about ‘x’ to ‘y’”, where ‘x’ and ‘y’ are numerical values, includes “about ‘x’ to about ‘y’”.

[0053] It is to be understood that such a range format is used for convenience and brevity, and thus, should be interpreted in a flexible manner to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited. To illustrate, a numerical range of “about 0.1% to 5%” should be interpreted to include not only the explicitly recited values of about 0.1% to about 5%, but also include individual values (e.g., about 1%, about 2%, about 3%, and about 4%) and the sub-ranges (e.g., about 0.5% to about 1.1%; about 5% to about 2.4%; about 0.5% to about 3.2%, and about 0.5% to about 4.4%, and other possible sub-ranges) within the indicated range.

[0054] As used herein, the terms “about,” “approximate,” “at or about,” and “substantially” mean that the amount or value in question can be the exact value or a value that provides equivalent results or effects as recited in the claims or taught herein. That is, it is understood that amounts, sizes, formulations, parameters, and other quantities and characteristics are not and need not be exact, but can be approximate and/or larger or smaller, as desired, reflecting tolerances, conversion factors, rounding off, measurement error and the like, and other factors known to those of skill in the art such that equivalent results or effects are obtained. In some circumstances, the value that provides equivalent results or effects cannot be reasonably determined. In such cases, it is generally understood, as used herein, that “about” and “at or about” mean the nominal value indicated ±10% variation unless otherwise indicated or inferred. In general, an amount, size, formulation, parameter or other quantity or characteristic is “about,” “approximate,” or “at or about” whether or not expressly stated to be such. It is understood that where “about,” “approximate,” or “at or about” is used before a quantitative value, the parameter also includes the specific quantitative value itself, unless specifically stated otherwise. [0055] Prior to describing the various aspects of the present disclosure, the following definitions are provided and should be used unless otherwise indicated. Additional terms can be defined elsewhere in the present disclosure.

[0056] As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.

[0057] As used in the specification and the appended claims, the singular forms “a,” “an” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a proton beam degrader,” “a degrader foil,” or “a conduit,” includes, but is not limited to, two or more such proton beam degraders, degrader foils, or conduits, and the like.

[0058] The terms “configured for” or “configured to,” as used herein with respect to a specified operation or function, refer to a device, component, circuit, structure, machine, signal, etc. that is physically constructed, programmed, formatted and/or arranged to perform the specified operation or function.

[0059] The various concepts introduced above and discussed in greater detail below can be implemented in any of numerous ways, as the described concepts are not limited to any particular manner of implementation. Examples of specific implementations and applications are provided primarily for illustrative purposes.

[0060] As used herein, the terms “optional” or “optionally” means that the subsequently described event or circumstance can or cannot occur, and that the description includes instances where said event or circumstance occurs and instances where it does not.

[0061] Unless otherwise specified, temperatures referred to herein are based on atmospheric pressure (i.e., one atmosphere).

[0062] In-memory Computing Architecture

[0063] FIG. 1 depicts a block diagram of an example in-memory computing architecture 100. The in-memory computing architecture 100 can be adapted, for example, to a scalable neural network accelerator architecture based on in-memory computing (IMC). However, the in-memory computing architecture 100 is not limited to neural network applications, and can be employed in numerous applications where high data throughput with low power consumption is desired. The in-memory computing architecture 100 includes a plurality of Compute In-Memory unit (CIMU) tiles 102. The plurality of CIMU tiles 102 are arranged in an array within the architecture. The plurality of CIMU tiles 102 can be individually enabled/disabled based on the computations to be carried out by the in-memory computing architecture 100. In examples where the in-memory computing architecture 100 can be used to implement neural networks, the neural networks can be mapped to one or more CIMU tiles of the plurality of CIMU tiles 102. The remainder of the CIMU tiles of the plurality of CIMU tiles 102 can be disabled to reduce power consumption. The in-memory computing architecture 100 can include, in part, activation buffers 104, segmented weight buffers 106, and one or more phase-locked loops (PLLs) 108. The activation buffers 104 can provide signals representative of activations from previous stages of computation, for instance previous layers in a neural network. The segmented weight buffers 106 can provide data required for computation together with the activations/data from previous stages, for instance these weight buffers could store the weights of neural network layers. The one or more PLLs 108 can provide reference clock signals to various portions of the in-memory computing architecture 100. The in-memory computing architecture 100 can also include off-chip interfaces 110 (referenced in FIG. 1 as “off-chip control” element 110) for communication with off-chip processors or software to send and receive control or data signals. The off-chip interface 110 can, by itself or in concert with other elements, provide circuits and protocols for high-speed interfaces for wired or wireless connections involving data, control signals, or both, to other processors or other arrays of CIMU tiles, for example, enabling the inmemory computing architecture 100 to scale upward as desired.

[0064] Each of the plurality of CIMU tiles 102 can include a plurality of CIMUs 112, an on-chip network 114, and a weight network 116. While FIG. 1 shows each of the plurality of CIMU tiles 102 including four CIMUs 112, this is only an example, and the CIMU tiles 102 can include fewer or more CIMUs 112. One or more of the CIMUs 112 can include a compute in-memory (CIM) array 118, compute dataflow buffers 120, programmable digital single instruction multiple data (SIMD) module(s) 122, and a programming and control module 124. The CIM array 118 can be an array of computing cells, discussed further below. The CIM array 118 can carry out computations based on data stored in the computing cells and data provided by the activation buffers 104. The computing cells can be used to perform computational operations between inputs and data stored in a memory cell within the computing cells. The operations can include logical operations (AND, NOR, etc.) or multiplication operations carried out between inputs. The CIM array 118 can carry out matrix operations between multi -bit operands, which is particularly useful in neural network computations where activations are multiplied with weights. In some such applications, the weights can be stored in the memory cells of the CIM array 118 and activations can be provided as input vectors. Each computing cell in the CIM array 118 can perform the multiplication operation between a 1 -bit weight and a portion of the input activation, which can be represented in digital or analog signal form. Some example computing cells can generate a result that is in the form of an electrical signal. For example, the computing cell can output an analog voltage that is representative of the computation result. In some other examples, the computing cell can output an electrical current that is representative of the computation result. The electrical signals of various computing cells can be accumulated and processed to generate the overall matrix multiplication result. For example, electrical signals representative of computation from all computing cells in a single column of the CIM array 118 can be accumulated to represent a portion of the computation. Accumulated electrical signals from multiple columns of computing cells of the CIM array 118 can be combined and processed to generate an overall matrix multiplication result. For instances where the electrical signal generated by the computing cells is an electrical current, the currents from various computing cells within a column can be summed to generate a representative accumulated electrical current. In instances where the electrical signal generated by the computing cell is an analog voltage, the analog voltage generated by each computing cell can be stored in capacitors within the computing cell and then accumulated as a voltage that is representative of a portion of the overall matrix multiplication result. The accumulated result, whether an electrical current or an analog voltage, can be converted into digital form using analog to digital converters (ADCs) and further processed, stored, or passed on to other CIM arrays 118 for further computations.

[0065] The programmable digital SIMD 122 can have an instruction set for flexible element-wise operation and the compute dataflow buffers 120 can support wide range of neural network dataflows. Each CIMU 112 can provide a high-level of configurability and can be abstracted into a software library of instructions for interfacing with a compiler (for allocating/mapping an application, neural network and the like to the architecture), and where instructions can thus also be added prospectively. That is, the library can include single/fused instructions such as elements mult/add, h(») activation, (N-step convolutional stride + matrix-vector-multiplication (MVM) + batch norm. +h(») activation + max. pool), (dense + MVM) and the like. In various nonlimiting examples, h(») can indicate an activation function, including without limitation the rectified linear unit ReLU(x) function, the sigmoid function (o(x)), and other such functions. Max pooling, a downsampling technique for reducing spatial dimensions to maintain computational efficiency while retaining other important features of the CIMU array or the network, can also be a subject of the computation. The N-step convolutional stride can refer to the number of pixels or other information bits that a kernel or convolutional filter moves or glides across the input image during convolution to effect operations like feature detection, pattern recognition, blurring, image sharpening, image recognition, and the like.

[0066] The on-chip network 114 (OCN) can include routing channels within Network In/Out Blocks, and a Switch Block, which provides flexibility via a disjoint architecture as shown, for example, by the disjoint buffer switch 133 in the enlarged view of OCN 114. This flexibility, among other benefits, enables modules that are independent of one another to work in parallel. The OCN 114 works with configurable CIMU input/output ports to optimize data structuring to/from an in-memory computing engine, to maximize data locality across MVM dimensionalities and tensor depth/pixel indices. The OCN 114 routing channels can include bidirectional wire pairs as shown by the duo-directional pipelined routing structure 131 in the expanded view if the OCN 114, so as to ease repeater/pipeline-FF insertion, while providing sufficient density.

[0067] The in-memory computing architecture 100 can be used to implement a neural network (NN) accelerator, wherein a plurality of compute in memory units (CIMUs 112) are arrayed and interconnected using a very flexible on-chip network (OCN 114) wherein the outputs of one CIMU can be connected to or flow to the inputs of another CIMU or to multiple other CIMUs, the outputs of many CIMUs can be connected to the inputs of one CIMU, the outputs of one CIMU can be connected to the inputs of another CIMU and so on. The OCN 114 can be implemented as a single on-chip network, as a plurality of on-chip network portions, or as a combination of on-chip and off-chip network portions.

[0068] The CIMUs 112 can be surrounded by an on-chip network for moving activations between CIMUs 112 (activation network) as well as moving weights from embedded L2 memory to CIMUs 112 (weight-loading interface). This has similarities with architectures used for coarse-grained reconfigurable arrays (CGRAs), but with cores providing high- efficiency MVM and element-wise computations targeted for neural network acceleration. Various options exist for implementing the on-chip network. The approach in FIG. 1 enables routing segments along a CIMU 112 to take outputs from that CIMU 112 and/or to provide inputs to that CIMU 112. In this manner data originating from any CIMU 112 can be routed to any CIMU 112, and any number of CIMUs 112.

[0069] Each CIMU 112 is associated with an input buffer (not shown) for receiving computational data from the on-chip network and composing the received computational data into an input vector for matrix vector multiplication (MVM) processing by the CIMU to generate thereby computed data comprising an output vector.

[0070] Each CIMU 112 is associated with a shortcut buffer (not shown), for receiving computational data from the on-chip network 114, imparting a temporal delay to the received computational data, and forwarding delayed computation data toward a next CIMU 112 or an output in accordance with a dataflow map such that dataflow alignment across multiple CIMUs 112 is maintained. At least some of the input buffers can be configured to impart a temporal delay to computational data received from the on-chip network 114 or from a shortcut buffer. The dataflow map can support pixel-level pipelining to provide pipeline latency matching.

[0071] The temporal delay imparted by shortcut or input buffers includes at least one of an absolute temporal delay, a predetermined temporal delay, a temporal delay determined with respect to a size of input computational data, a temporal delay determined with respect to an expected computational time of the CIMU 112, a control signal received from a dataflow controller, a control signal received from another CIMU 112, and a control signal generated by the CIMU 112 in response to the occurrence of an event within the CIMU. In some aspects, at least one of the input buffer and shortcut buffers of each of the plurality of CIMUs 112 in the array of CIMUs 112 can be configured in accordance with a dataflow map supporting pixel-level pipelining to provide pipeline latency matching. The array of CIMUs 112 can also include parallelized computation hardware configured for processing input data received from at least one of respective input and shortcut buffers.

[0072] A least a subset of the CIMUs 112 can be associated with on-chip network 114 portions including operand loading network portions configured in accordance with a dataflow of an application mapped onto the IMC. The application mapped onto the IMC comprises a neural network (NN) mapped onto the IMC such that parallel output computed data of configured CIMUs executing at a given layer are provided to configured CIMUs 112 executing at a next layer, said parallel output computed data forming respective NN feature-map pixels.

[0073] The input buffer can be configured for transferring input NN feature-map data to parallelized computation hardware within the CIMU in accordance with a selected stride step, such as discussed above. The NN can comprise a convolution neural network (CNN), and the input buffer can be used to buffer a number of rows of an input feature map corresponding to a size or height of the CNN kernel.

[0074] The CIM array 118 in each CIMU 112 can perform matrix vector multiplication (MVM) in accordance with a bit-parallel, bit-serial (BPB S) computing process in which single bit computations are performed using an iterative barrel shifting with column weighting process, followed by a results accumulation process.

[0075] FIG. 2 shows additional details of a portion of the in-memory computing architecture 100 shown in FIG. 1, and in particular, details of an example compute inmemory (CIM) array 200 and associated components. In one example implementation, the CIM array 200 can be used, for example, to implement, in part, the CIM array 118 discussed above in relation to the in-memory computing architecture 100 shown in FIG. 1. The CIM array 200 can include a fully row/column-parallel (1152 row><256 column) array of computing cells 202 of an in-memory-computing (IMC) macro enabling N-bit (5-bit) input processing. The number of rows (1152), the number or columns (256), and the number of bits (5-bit) of input shown in FIG. 2 are only examples, and any or all of these quantities and circuit configuration details can be varied based on desired implementations. The computing cells can be used to perform computational operations between inputs and data stored in a memory cell within the computing cells. The operations can include logical operations (AND, NOR, etc.) or multiplication operations carried out between inputs. In some examples, the operands of the computation can be 1 -bit each. In some other examples, one of the operands can be an analog signal (voltage or current) while the other a 1 -bit operand stored in the memory cell.

[0076] The in-memory computing architecture 100, in some examples, can be utilized for matrix vector multiplication (MVM) operations, which dominate compute-intensive and data-intensive Al workloads, in a manner that reduces compute energy and data movement by orders of magnitude. This is achieved through efficient analog compute in the computing cells 202, and by thus accessing a compute result (e.g., inner product), rather than individual bits, from memory. But, doing so fundamentally instates an energy/throughput-vs.-SNR tradeoff, where going to analog introduces compute noise and accessing a compute result increases dynamic range (i.e., reducing SNR for a given readout architecture). The computing cells 202, which store computational results in the form of a voltage in capacitors within the computing cells 202, can employ metal-fringing capacitors, which can achieve very low noise from analog nonidealities, and thus have the potential for extremely high dynamic range.

[0077] FIG. 2 shows a block diagram of the CIM array 200 including an 1152 (row)*256 (col.) array of 10T (“ten-transistor”) SRAM computing cells 202, which in this example are multiplying bit-cells (M-BCs) (such as, for example, a 10T M-BC 202, although the number of transistors of SRAM interface 204 and M-BCs 202 is purely implementationdependent and the circuit can use different numbers of transistors or other circuit elements without departing from the principles of the disclosure); peripheral circuits for standard writing/reading thereto (e.g., a bit line (BL) decoder 204 and 256 BL drivers 206-1 through 206-256 (collectively referred to as BL drivers 206), a word line (WL) or address decoder 208 and 1152 WL drivers 210-1 through 210-1152 (collectively referred to as WL drivers 210), and control block 212 for controlling the BL decoder such as SRAM interface 204 and the WL decoder 208); peripheral circuitry for providing 5-bit inputvector elements thereto (e.g., 1152 Dynamic-Range Doubling (DRD) DACs 214-1 through 214-1152 (collectively referred to as DRD DACs 214), and a corresponding inmemory computing (IMC) controller (“IMC control block”) controller 216); peripheral circuitry for digitizing the compute result from each column (e.g., 256 8-bit successive approximation register (SAR) ADCs 218-1 through 218-256 (collectively referred to as SAR ADCs 218), and column reset mechanisms 220-1 through 220-256 (collectively referred to as column reset mechanisms 220) (e.g., CMOS switches configured to pull the output voltage levels of column compute lines CLs to a reset voltage VRST during a reset phase of operation, and to allow the voltage levels of column compute lines CLs to reflect their respective compute results during an evaluation phase of operation). For example, the RST switches corresponding to CL1-CL256, or a subset thereof, can close to produce the desired reset voltage VRST during the reset phase. The RST switches can then open during an ensuing evaluation phase, thereby enabling the voltage values at the CLs to reflect the computed product.

[0078] In addition, the lower right portion of FIG. 2 depicts an example enlarged view of a representative one of the 256 8-bit ADCs, which includes various switch mechanisms ADCRST (Analog-to-Digital Converter Reset), ADCSMP (Analog-to-Digital Converter Sample) and voltage designations VADCRST and VCMPR, the latter voltage designation connected in this example to a positive terminal of the comparator CMPR and the former voltage designation selectively applied via the ADCRST and ADCSMP switch to reset the comparator. The negative terminal of comparator CMPR receives a compute line (CL) value when the circuit is activated. An output of comparator CMPR is coupled to SAR logic for outputting an 8-bit digital result. It will be appreciated, however, that the implementation details of the above circuits are representative in nature and that variations to the circuits are possible without departing from the scope or spirit of the present disclosure.

[0079] While writing/reading is typically performed row-by-row, MVM operations are typically performed by applying input-vector elements corresponding to neural -network input activations to all rows at once. That is, each DRD DAC 214j, in response to a respective 5-bit input-vector element Xj [4:0], generates a respective differential output signal (lAj/IAbj) which is subjected to a 1-bit multiplication with the stored weights (Aij/Abij) at each computing cell 202j in the corresponding row of computing cells 202, and accumulation through charge-redistribution across computing cell 202 capacitors (CM-BC) on the compute line (CL) to yield an inner product in each column, which is then digitized via the respective SAR ADCs 218 of each column.

[0080] FIG. 3 shows an example circuit diagram of the computing cells 202 discussed above in relation to FIG. 2. The computing cells 202 can include a highly dense structure for achieving weight storage and multiplication, thereby minimizing data-broadcast distance and control signals within the context of i-row, j -column arrays implemented using such computing cells, such as the 1152 (row)*256 (col.) CIM array 200 of 10T SRAM multiplying bit cells (M-BCs).

[0081] The exemplary computing cells 202 includes a six-transistor bit cell portion 222, a first switch SW1, a second switch SW2, a capacitor C, a word line (WL) 224, a first bit line (BLj) 227, a second bit line (BLbj) 228, and a compute line (CL) 230.

[0082] The six-transistor bit cell portion 222 (here, NMOS transistors 226a, 226b, 226e, 226f and PMOS transistors 226c and 226d) is depicted in this example as being located in a middle portion of the computing cells 202, and includes six transistors 226a-226f. The 6-transistor bit cell portion 222 can be used for storage, and to read and write data. In one example, the 6-transistor bit cell portion 222 stores the filter weight. In some examples, data is written to the computing cells 202 through the word line (WL) 224, the first bit line (BL) 227, and the second bit line (BLb) 228.

[0083] The computing cells 202 can include a first CMOS switch SW1 and a second CMOS switch SW2. The first switch SW 1 is depicted as being controlled by a first stored signal Aij such that, when closed, the first switch SW1 couples one of the received differential output signals provided by the DRD DACs 214, illustratively IA, to a first terminal of the capacitor C. The second switch SW2 is depicted as being controlled by a second stored signal Abij such that, when closed, the second switch SW2 couples the other one of the received differential output signals (lA/IAb) of the corresponding DRD DACs 214, illustratively lAb, to the first terminal of the capacitor C. The second terminal of the capacitor C is connected to a compute line (CL) 230 via an output port 232 that provides a result of the computation of the computation cell 202. It is noted that in various other examples, the input signals provided to the first and second switches SW 1 and SW2 can comprise a fixed voltage (e.g., Vaa), ground, or some other voltage level.

[0084] The computing cells 202, including the first SW1 and second SW2 switches, can implement computation on the data stored in the six-transistor bit cell portion 222. The result of a computation is sampled as charge on the capacitor C. According to various implementations, the capacitor C can be is positioned above the computing cell 202 and utilize no additional area on the circuit. In some implementations, a logic value of either Vdd or ground is stored on the capacitor C. In other implementations, the voltage stored on the capacitor C can comprise a positive or negative voltage in accordance with the operation of the first and the second switches SW 1 and SW2, and the output voltage level generated by the corresponding DRD DACs 214 shown in FIG. 2.

[0085] Thus, with continued reference to FIG. 3, the value that is stored on the capacitor C is highly stable, since the capacitor C value is either driven up to a fixed analog voltage or down to ground. In some examples, the capacitor C is a metal-oxide-metal (MOM) finger capacitor, and in some examples, the capacitor C can be about 0.1 femto-Farhads (fF) to about 10 fF or can be about 1.2 fF. MOM capacitors have very good matching temperature and process characteristics, and thus have highly linear and stable compute operations. Note that other types of logic functions can be implemented using the computing cells 202 by changing the way the transistors 226a-226f and/or the first and the second switches SW1 and SW2 are connected and/or operated during the reset and evaluation phases of operation. The six-transistor bit cell portion 222 is exemplary can in other instances be implemented using different numbers of transistors. In addition, the bit cell portion 222 can have different architectures. In some examples, the bit cell portion 222 can be a static random-access memory (SRAM), dynamic RAM (DRAM), Magnetoresistive RAM (MRAM), resistive RAM (RRAM), or the like.

[0086] Power And Noise Configurable Analog to Digital Converters

[0087] FIG. 4 depicts a block diagram of an example successive-approximation-register (SAR) analog to digital converter (ADC) architecture 400. While FIG. 4 shows a single ended implementation for example purposes, fully differential implementations are equally possible and can be used in the context of the present disclosure. FIG. 4 shows voltage inputs 402 to the SAR ADC architecture 400. Example voltage inputs 402 include a first reference voltage terminal 402-1 (“VREFP 402-1”) and a second reference voltage terminal 402-2 (“VREFN 402-2”). The first reference voltage terminal 402-1 and the second reference voltage terminal 402-2 can receive a first reference voltage VREFP and a second reference voltage VREFN, respectively. In some examples, the ADC can include only one reference voltage terminal and can receive only a single reference voltage. In the example shown in FIG. 4, the ADC can consider either one of the two reference voltages received, or can derive a reference voltage based on the two received reference voltages. In one example, the second reference voltage VREFN can be zero volts or a ground voltage and the reference voltage of the ADC can then be the value of the first reference voltage VREFP. In some examples, a difference between the first reference voltage VREFP and the second reference voltage VREFN can be used to determine the reference voltage of the ADC. The full scale range of the SAR ADC architecture 400 can be a function of the reference voltage. For example, the reference voltage can indicate the maximum input voltage that the SAR ADC architecture 400 can digitize.

[0088] SAR ADC architecture 400 has an input analog voltage 404. Input analog voltage 404 can be a compute line (CL) analog voltage input as depicted and discussed with reference to FIG. 2 and FIG. 3. SAR ADC architecture 400 shows a sampling switch 406, an ADC reset voltage (VADCRST) 408, and a reset switch 410. SAR ADC architecture 400 includes SAR logic 412, capacitive digital to analog converter (CAP DAC) 414, and SAR ADC comparator 416. SAR ADC comparator 416 has an input voltage VCMPR 418, in this example at its positive terminal. SAR ADC comparator 416 is described herein in greater detail with reference to FIG. 5. The output of SAR ADC architecture 400 is output code 420. Output code 420 is a digital output providing a digital representation of input analog voltage 404. In one example the voltages VREFP 402-1 and VREFN 402-2 can be provided to the CAP DAC 414 to adjust the full-scale input swing of the SAR ADC architecture 400. The full-scale input swing of the SAR ADC 400 architecture can be equal to (VREFP - VREFN), i.e., the difference between the two voltages. In some examples, the value of the voltage VREFN 402-2 can be set to zero volts. The full-scale swing can represent the expected swing of the input analog voltage 404 that is to be converted into a digital value by the SAR ADC architecture 400.

[0089] For in-memory computing systems, such as the in-memory computing system depicted with reference to the in-memory computing architecture 100, the ADC (such as described herein with reference to SAR ADC architecture 400) area and power accounts for a large portion of the overall area and power of the system. The ADC signal-to-noise ratio (SNR) has a significant impact on the overall system performance and should be designed to be better than the overall system accuracy. The primary limits on ADC performance are ADC quantization noise and ADC thermal noise. ADC performance is typically evaluated for a uniformly distributed input signal. With this assumption, for a given ADC full scale (FS) range, the ADC quantization noise power (s_q ²) is given by:

where N is the ADC resolution in bits and FS is the ADC full scale input range. (In some examples, the 2^N term in the above equation can be 2^N-1.) The ADC quantization noise power for a given ADC resolution (N) is directly proportional to the full scale range. The ADC thermal noise power (s_n ²) is determined by the ADC power, and the ADC SNR is given by:

For large FS values, s_q ² dominates the SNR while for small FS, s_n ² can begin to dominate. [0090] For MVM operations using in-memory computing arrays (such as, for example, the CIM array 200 described herein with reference to FIG. 2), the actual dynamic range of the signals at the input to the ADCs, is often much smaller than the potential dynamic range determined by the array dimensions. The actual dynamic range of the signals at the inputs to the ADC can be determined from the value of the weights written into the array, which is known prior to the MVM operation. As such, the ADC quantization noise can be reduced by reducing the FS range since the entire FS range may not be used. However, when reducing the FS range, the ADC SNR can be negatively impacted due to the SNR becoming dominated by the thermal noise <J_n . Accordingly, the ADC thermal noise should also be reduced. The ADC noise power and FS range can both be made configurable such that the noise can be configured to be lower for low FS values and higher for higher FS values thereby only using the requisite ADC power when required and reducing the ADC power when not required.

[0091] FIG. 5 depicts a block diagram of a SAR ADC comparator 416 example architecture. FIG. 5 shows the S AR ADC comparator 416 including a pre-amplifier stage 510 and a latch stage 520. Pre-amplifier stage 510 includes a set of programmable capacitors 515, depicted in FIG. 5 as programmable capacitors 515-1 and 515-2 positioned at internal nodes of the SAR ADC comparator 416. For example, the programmable capacitors 515 can be positioned at the output of the pre-amplifier stage 510 and the input of the latch stage 520. However, it should be noted that the programmable capacitors could potentially be positioned at other internal nodes of the comparator as well. While FIG. 5 depicts the set of programmable capacitors 515 with two programmable capacitors 515, any suitable number of programmable capacitors 515 can be used. An example configuration of programmable capacitors 515 is described in greater detail herein with reference to FIG. 6.

[0092] In a SAR ADC, the SAR ADC comparator 416 can be both a source of noise and large contributor to power dissipation. As depicted in FIG. 5, the SAR ADC comparator 416 uses a clocked pre-amplifier stage 510 followed by a latch stage 520. The overall noise performance is enhanced by the addition of capacitive loads from the set of programmable capacitors 515 to the pre-amplifier stage 510. The set of programmable capacitors 515 increases the integration time of the pre-amplifier stage 510 and reduces the overall thermal noise of the SAR ADC comparator 416, i.e., the noise performance of the SAR ADC 400 can be a function of the capacitance value of set of programmable capacitors 515 within the SAR ADC comparator 416. The set of programmable capacitors 515 allows for a flexible design where the SAR ADC comparator 416 (and accordingly the ADC) can be configured to be lower noise at a higher power or lower power with higher noise as shown in the simulated results in FIG. 7. FIG. 7 shows simulated results of SAR ADC comparator 416 noise and power in response to changes in pre-amplifier stage 510 capacitance. In particular, FIG. 7 shows normalized average power 702 and the normalized input referred noise power 704 in relation to increasing values of the load capacitor settings. As the capacitance increases (indicated on the x- axis from left to right as increasing numbers 0 to 3, where each number corresponds to an example number of unit load capacitances), the noise power decreases, but due to the increase in capacitance, the normalized average power 702 increases. The programming of the set of programmable capacitors 515 can be combined with the setting of the ADC full scale (FS) and knowledge of the weights in the array to either increase or decrease the overall power of the SAR ADC comparator 416 with a corresponding decrease or increase the thermal noise of the SAR ADC comparator 416. For example, a decrease in VREFP 402-1 would be accompanied by an increase in the capacitance value setting of the set of programmable capacitors 515.

[0093] FIG. 6 is a schematic circuit diagram of a programmable capacitor bank 600 for implementation as programmable capacitors 515. Programmable capacitor bank 600 can include a plurality of capacitors 606-1, 606-2, . . . 606-n (collectively referred to as “a plurality of capacitors 606) and a plurality of switches 604-1, 604-2, . . . 604-n (collectively referred to as “a plurality of switches 604”) where each switch of the plurality of switches 604 is positioned in series with each capacitor of the plurality of capacitors 606. One end of each of the plurality of switches 604 is coupled with the respective capacitor of the capacitors 606 and the other end of all the switches are coupled together and to the output of the pre-amplifier stage 510. The programmable capacitor bank 600 can receive control signals that are provided to the control inputs of the plurality of switches 604. For example, the programmable capacitor bank 600 can receive n control signals: Control bitfO] 602-1, Control bitfl] 602-2, . . . , Control bitfn] 602-n (collectively referred to as control bit inputs 602). These control signals can correspond to or can be derived from a capacitor configuration input. For example, the capacitor configuration input can be an n-bit value, such that each bit of the capacitor configuration input corresponds to each of the n control bit inputs 602. In some other examples, the capacitor configuration input can be an encoded value, which is decoded and provided as the control bit inputs 602. In an example, each capacitor 606 can have a different capacitance value as compared to the other capacitors 606. Alternately, each capacitor 606 can have the same capacitance value as compared to the other capacitors 606. As depicted in FIG. 6, switches 604 and capacitors 606 are positioned in parallel such that capacitances are additive based on actuated (i.e., closed) switches 604. Capacitors 606 can be binary weighted so that the most significant bit (MSB) of control bits 602 switches the largest binary weighted capacitor 606 and the least significant bit (LSB) switches the smallest binary weighted capacitor 606.

[0094] FIG. 8 is a block diagram of a programmable reference voltage generator 800. The programmable reference voltage generator 800 generates the bias voltages and currents used to generate the ADCs reference voltages 810. A plurality of programmable reference voltage generators 800 can be utilized for the plurality of ADCs associated with the compute in-memory array. The programmable reference voltage generator 800 includes a bias current generator 802 with an output current 804, and an ADC reference voltage generator 808 with one or more reference voltage configuration bits 806 and output reference voltages 810. Bias generator 802 is described in greater detail herein with reference to FIG. 9. ADC reference voltage generator 808 generates reference voltages 810 at output nodes. ADC reference voltage generator 808 is described herein in greater detail in reference to FIG. 10. As depicted in FIG. 8, ADC reference voltage generator 808 outputs reference voltages 810. Output reference voltages 810 can include VREFP 810-1, VREFN 810-2, and VCMPR 810-3. VREFP 810-1 can be provided to the VREFP 402-1, VREFN 810-2 can be provided to the VREFN 402-2, and VCMPR 810-3 can be provided as the input voltage VCMPR 418, described herein with reference to input voltages to SAR ADC architecture 400 of FIG. 4. The programmable reference voltage generator 800 can receive one or more reference voltage configuration bits shown as VREF CTRLfl :0], While two bits are shown in this example, it should be appreciated that the reference voltage configuration bits can be fewer or greater than that shown in FIG. 8. The programmable reference voltage generator 800 can generate the one or more reference voltages based on the one or more reference voltage configuration bits.

[0095] FIG. 9 is a schematic circuit diagram of bias generator 802. Reference bias generation is done by an integrated band-gap voltage 902 (VBG) reference used to generate a proportional to absolute temperature (PTAT) current through a resistor 904. The resulting current is then mirrored to created bias currents 804 for the ADC reference generation and buffering, as depicted in FIG. 8. It should be noted that the bias current generation shown in FIG. 9 is only one example, and that other approaches to generating the bias current can also be used.

[0096] FIG. 10 is a schematic circuit diagram of ADC reference voltage generator 808. Output current 804 from the bias generator 802 (IBIAS 804) is applied to a programmable resistor 1002 to produce voltage VREFP 810-1 which is buffered by buffer 1004 before being output to the respective ADC. The programmable resistors 1002 can include, in some examples, parallel connected combinations of resistors in series with switches, where the switching ON/OFF of the switches can result in the respective resistor being connected/disconnected in parallel and resulting in selectable equivalent resistance, which, based on the magnitude of the Ibias 804 can result in selectable voltage VREFP 810-1, which is buffered by the buffer 1004. A similar circuit can be utilized to generate the VREFN 810-2 voltage, albeit with a different bias current or different set of programmable resistors, or both. The value of the reference voltages 810 is controlled by the VREF_CTRL[l :0] 806 (the reference voltage configuration bits; FIG. 8). In some examples, based on the values of the programmable resistors 1002, the configuration bits VREF_CTRL[1 :O] 806 can control the output voltages 810 in such a way to adjust the ADC full scale swing to full scale (FS), half full scale (FS/2) or quarter full scale (FS/4). While FIG. 10 shows only two bits for the VREF CTRL, additional bits can also be used for increasing the levels of reference voltages.

[0097] In additional examples, the various components described herein form a circuit that functions to configure power and noise within an ADC. The circuit includes a compute-in-memory array with a plurality of ADCs and a plurality of programmable reference voltage generators. The circuit also includes a controller to receive data stored in the multiplying bit-cells, determine a full-scale range of each ADC, determine a recommended reference voltage VREFP 402-1 for each ADC, determine a recommended capacitance for each ADC, and set the one or more reference voltage configuration bits and the capacitor configuration input, based on the recommended reference voltage and the recommended capacitance. The controller can determine the recommended reference voltage based on a reference voltage look-up table and the recommended capacitance based on a capacitance look-up table. Alternately, the controller can determine the recommended reference voltage and capacitance based on a desired SNR. The circuit can also include capacitor configuration registers that store capacitor configuration inputs and reference voltage configuration registers that store reference voltage configuration bits corresponding to the programmable reference voltage generators. The referenced registers can be loaded at the time of loading data stored in the multiplying bit-cells.

[0098] FIG. 11 shows a block diagram of an example controller 1100. The controller 1100 can be utilized to implement the reference voltage configuration at output(s) 1111 and the capacitance configuration at output(s) 1110 discussed herein. In some implementations, the controller 1100 can be part of the segmented weight buffers 106 shown in FIG. 1. In some implementations, the controller 1100 can be part of the control block 212 shown in FIG. 2. In some implementations, the controller 1100 can be a standalone controller dedicated to the reference voltage configuration and the capacitance configuration. The controller 1100 can be implemented using one or more microprocessors, microcontrollers, field programmable gate arrays (FPGAs), digital signal processors, programmable array logic or other programmable devices, application specific integrated circuits, etc. In some examples, the controller 1100 can receive the data that is to be stored in the CIM array and determine the reference voltage for each of the plurality of ADCs. In particular, the controller 1100 can infer from the data stored in the multiplying cells in each column the input volage swing to be expected at the plurality of ADCs. Accordingly, the controller 1100 can select for each ADC, a reference voltage that results in a full swing range for the ADC that is greater than the input voltage swing at that ADC. The controller 1100 can generate the reference voltage control bits at output 1111 corresponding to the selected reference voltage and provide the reference voltage control bits to the programmable reference voltage generator 800 to generate the desired reference voltage. In some examples, the controller 1100 can select the appropriate reference voltage based on a reference voltage look-up table that includes various values of input voltage swings and the corresponding values of reference voltages. The controller 1100 can select the value of appropriate reference voltage and generate the corresponding reference voltage configuration bits, or if the look-up table includes the reference voltage configuration bits as well, read the configuration bits and provide an output 1111 of the bits to the programmable reference voltage generator 800. In some examples, the controller 1100 can, without the use of a look-up table, determine the full scale range to be a percentage value greater than the expected input voltage swing and then select the closest or next greatest available reference voltage and then generate the corresponding reference voltage configuration bits.

[0099] In some examples, the controller 1100 can receive from software 1102 the input swing values expected at each ADC, and the controller 1100 can use the values to either determine the reference voltage analytically, or using a look-up table, and generate the appropriate reference voltage configuration bits. In some examples, the software 1102 can generate the reference voltage configuration bits and store the configuration bits in reference voltage configuration registers 1104, which can include memory storage for configuration bits associated with each of the plurality of ADCs. The controller 1100 can read the reference voltage configuration registers 1104 and provide the programmable reference voltage generator 800 with the reference voltage configuration bits. The software 1102 can be the software that determines the values of the data to be loaded into the multiplying bit cells and can determine the expected input swing at inputs of the plurality of ADCs.

[0100] The controller 1100 also can determine the value of the set of programmable capacitors 515 for each ADC based on the selected reference voltage. For example, if the reference voltage is reduced, the controller 1100 can increase the value of the capacitance of the set of programmable capacitors 515. The controller 1100 can analytically generate the capacitance value or determine the appropriate capacitance value using a capacitance look-up table, which can include a list of reference voltage values and corresponding capacitance values. The controller 1100 can generate the capacitance configuration inputs at controller output(s) 1110 based on the determined capacitance value and provide to the plurality of ADCs. In some examples, the software 1102 can store the capacitor configuration inputs corresponding to the plurality of ADCs in a plurality of capacitor configuration registers 1106. In such examples, the software 1102 can read the plurality of capacitor configuration registers 1106 and provide the capacitor configuration inputs at output(s) 1111 to the plurality of ADCs. In some examples, the software 1102 can determine the expected signal-to-noise ratio (SNR) at each ADC based, in part, on the input voltage swing expected at the ADC. The software 1102 can then determine the appropriate values of the set of programmable capacitors 515 based on the expected SNR so as to increase the SNR. The software 1102 can then store the appropriate capacitor configuration inputs into the plurality of capacitor configuration registers 1106 for the software 1102 to read and provide to the programmable capacitor bank 600.

[0101] In some examples, the software 1102 can load the capacitor configuration inputs and the reference voltage configuration bits in the capacitor configuration registers 1106 and the reference voltage configuration registers 1104 at the time when data is loaded into the CIM array.

[0102] SAR ADC with programmable capacitors

[0103] While the SAR ADC architecture 400 shown in FIG. 4 is discussed in relation to the CIM arrays, the SAR ADC architecture 400 can be operated in any implementations that need analog to digital conversion. In such instances, the set of programmable capacitors 515 can be utilized to reduce the dominance of thermal noise in the overall noise of the ADC. For example, the values of the set of programmable capacitors 515 can be adjusted based on the reference voltage for the ADC. In some examples, the values of the set of programmable capacitors 515 can be adjusted independent of the value of the reference voltage to reduce the noise associated with the ADC. In some instances, a controller can select the values of the set of programmable capacitors 515 based on the desired noise level and the expected power consumption for the selected value of capacitance. The SAR ADC can include a reference voltage terminal to receive the reference voltage, where the full-scale range of the SAR ADC is a function of the reference voltage. The SAR ADC can include an analog voltage input that receives an input analog voltage for digital conversion. The SAR ADC also can include the set of programmable capacitors, similar to the set of programmable capacitors 515 discussed herein, where the set of programmable capacitors can have a capacitance that is based on a capacitor configuration input, where the noise performance and the power consumption of the ADC is a function of the capacitance value. Based on the input voltage, the reference voltage, and the capacitance value of the set of programmable capacitors, the ADC can generate, at a digital output, a digital representation of the input analog voltage received at the analog voltage input.

ASPECTS OF THE DISCLOSURE

[0104] The present disclosure will be better understood upon reading the following numbered aspects, which should not be confused with the claims. Each of the numbered aspects described below can, in some instances, be combined with aspects described elsewhere in the disclosure. The following listing of example aspects is supported by the disclosure provided herein.

[0105] Aspect 1. A circuit, including: a compute in-memory (CIM) array of multiplying bit-cells, the array generating a plurality of result analog voltages resulting from a multiplication of data stored in the multiplying bit-cells and input voltages; and [0106] a plurality of analog to digital converters (ADCs) coupled with the CIM array, each ADC of the plurality of ADCs including: a reference voltage terminal receiving a reference voltage, wherein a full-scale range of each ADC is a function of the reference voltage, an analog voltage input receiving a result analog voltage of the plurality of result analog voltages, a set of programmable capacitors configured to have a capacitance value based on a capacitor configuration input, wherein a noise performance of the ADC is a function of the capacitance value, and a digital output providing a digital representation of the result analog voltage received at the analog voltage input; wherein the circuit further comprises a plurality of programmable reference voltage generators coupled with a plurality of reference voltage terminals of the plurality of ADCs, each programmable reference voltage generator of the plurality of programmable reference voltage generators receiving one or more reference voltage configuration bits and generating the reference voltage for a respective ADC of the plurality of ADCs based on the one or more reference voltage configuration bits.

[0107] Aspect 2. The circuit of any one of Aspects 1-12, wherein the capacitor configuration input and the one or more reference voltage configuration bits are based on data stored in the multiplying bit-cells of the CIM array of multiplying bit-cells.

[0108] Aspect s. The circuit of any one of Aspects 1-12, wherein the capacitor configuration input and the one or more reference voltage configuration bits are configured such that for a respective ADC, a decrease in the reference voltage corresponds to an increase in the capacitance value of the set of programmable capacitors. [0109] Aspect 4. The circuit of any one of Aspects 1-12, wherein the capacitor configuration input is configured to be independent of the reference voltage.

[0110] Aspect 5. The circuit of any one of Aspects 1-12, wherein each ADC of the plurality of ADCs is a successive-approximation-register ADC including at least one comparator, wherein the at least one comparator includes: a pre-amplifier stage coupled with the input terminals of the comparator, and a latch stage coupled with the preamplifier stage, wherein the set of programmable capacitors is positioned at the output of the pre-amplifier stage.

[0111] Aspect 6. The circuit of claim 1, wherein the set of programmable capacitors is positioned at an input of each ADC.

[0112] Aspect 7. The circuit of claim 1, further including: a controller configured to: receive as input at least a portion of the data stored in the multiplying bit-cells, determine the full-scale range of each ADC of the plurality of ADCs, determine a recommended reference voltage for each ADC of the plurality of ADCs, determine a recommended capacitance for each ADC of the plurality of ADCs, and set the one or more reference voltage configuration bits and the capacitor configuration input for each ADC of the plurality of ADCs, respectively, based on the recommended reference voltage and the recommended capacitance.

[0113] Aspect 8. The circuit of any one of Aspects 1-12, wherein the controller is configured to: determine the recommended reference voltage based on a reference voltage look-up table, and determine the recommended capacitance based on a capacitance lookup table.

[0114] Aspect 9. The circuit of any one of Aspects 1-12, wherein the controller is configured to: determine the recommended reference voltage and the recommended capacitance based on a desired signal to noise ratio (SNR).

[0115] Aspect 10. The circuit of any one of Aspects 1-12, further including: a plurality of capacitor configuration registers storing capacitor configuration inputs corresponding to the plurality of ADCs; and a plurality of reference voltage configuration registers storing one or more reference voltage configuration bits corresponding to the plurality of programmable reference voltage generators.

[0116] Aspect 11. The circuit of any one of Aspects 1-12, wherein the plurality of capacitor configuration registers and the plurality of reference voltage configuration registers are loaded at a time of loading the data stored in the multiplying bit-cells. [0117] Aspect 12. The circuit of any one of Aspects 1-12, wherein each programmable capacitor of the set of programmable capacitors includes a plurality of switched capacitors, wherein states of switches of the plurality of switched capacitors are controlled based on the plurality of capacitor configuration registers.

[0118] Aspect 13. A method for configuring a plurality of analog to digital converters (ADCs) coupled with a compute in-memory (CIM) array of multiplying bit-cells, the array generating a plurality of result analog voltages resulting from a multiplication of data stored in the multiplying bit-cells and input voltages, each of the plurality of ADCs including: a reference voltage terminal receiving a reference voltage, wherein a full-scale range of each ADC is a function of the reference voltage, an analog voltage input receiving a result analog voltage of the plurality of result analog voltages, a set of programmable capacitors configured to have a capacitance value based on a capacitor configuration input, wherein a noise performance of the ADC is a function of the capacitance value, and a digital output providing a digital representation of the result analog voltage of the plurality of result analog voltages received at the analog voltage input, the method including: generating a reference voltage for each ADC of the plurality of ADCs based on respective reference voltage configuration bits.

[0119] Aspect 14. The method of any one of Aspects 13-23, including: generating the capacitor configuration input and the respective reference voltage configuration bits based on data stored in the multiplying bit-cells of the CIM array of multiplying bit-cells. [0120] Aspect 15. The method of any one of Aspects 13-23, including: responsive to a decrease in the reference voltage, generating the capacitor configuration input to increase the capacitance value of the set of programmable capacitors.

[0121] Aspect 16. The method of any one of Aspects 13-23, including: generating the capacitor configuration input to change the capacitance value of the set of programmable capacitors independently of the reference voltage.

[0122] Aspect 17. The method of any one of Aspects 13-23, wherein each ADC of the plurality of ADCs is a successive-approximation-register ADC including at least one comparator, wherein the at least one comparator includes: a pre-amplifier stage coupled with input terminals of the at least one comparator, and a latch stage coupled with the preamplifier stage, wherein the set of programmable capacitors is positioned at an output of the pre-amplifier stage.

[0123] Aspect 18. The method of any one of Aspects 13-23, wherein the set of programmable capacitors is positioned at an input of each ADC. [0124] Aspect 19. The method of any one of Aspects 13-23, including: receiving as input at least a portion of the data stored in the multiplying bit-cells; determining the full- scale range of each ADC of the plurality of ADCs; determining a recommended reference voltage for each ADC of the plurality of ADCs; determining a recommended capacitance for each ADC of the plurality of ADCs; and setting the respective reference voltage configuration bits and the capacitor configuration input for each ADC of the plurality of ADCs, respectively, based on the recommended reference voltage and the recommended capacitance.

[0125] Aspect 20. The method of any one of Aspects 13-23, including: determining the recommended reference voltage based on a reference voltage look-up table, and determining the recommended capacitance based on a capacitance look-up table.

[0126] Aspect 21. The method of any one of Aspects 13-23, including: determining the recommended reference voltage and the recommended capacitance based on a desired signal-to-noise ratio (SNR).

[0127] Aspect 22. The method of any one of Aspects 13-23, including: storing capacitor configuration inputs corresponding to the plurality of ADCs in a plurality of capacitor configuration registers; and storing the respective reference voltage configuration bits corresponding to the plurality of programmable reference voltage generators in a plurality of reference voltage configuration registers.

[0128] Aspect 23. The method of any one of Aspects 13-23, including: storing capacitor configuration inputs and the reference voltage configuration bits at a time of loading the data stored in the multiplying bit-cells.

[0129] Aspect 24. A successive-approximation-register (SAR) analog to digital converter (ADC) including: a reference voltage terminal receiving a reference voltage, wherein a full-scale range of the SAR ADC is a function of the reference voltage, an analog voltage input receiving an input analog voltage for digital conversion, a set of programmable capacitors configured to have a capacitance value based on a capacitance configuration input, wherein a noise performance of the ADC is a function of the capacitance value, and a digital output providing a digital representation of the input analog voltage received at the analog voltage input.

[0130] Aspect 25. The SAR ADC of any one of Aspects 24-30, wherein the capacitor configuration input is based, in part, on a value of the reference voltage.

[0131] Aspect 26. The SAR ADC of any one of Aspects 24-30, wherein the set of programmable capacitors includes a plurality of switched capacitors connected in parallel, and wherein an on or off state of switches of each of the plurality of switched capacitors is determined based on the capacitor configuration input.

[0132] Aspect 27. The SAR ADC of any one of Aspects 24-30, wherein the reference voltage is based on an expected input analog voltage swing.

[0133] Aspect 28. The SAR ADC of any one of Aspects 24-30, wherein the reference voltage and the capacitance configuration input are based on a desired signal-to-noise ratio (SNR).

[0134] Aspect 29. The SAR ADC of any one of Aspects 24-30, wherein the reference voltage and the capacitance configuration input are based on a desired input analog voltage swing and a desired signal-to-noise ratio (SNR).

[0135] Aspect 30. The SAR ADC of any one of Aspects 24-29, wherein the reference voltage and the capacitance configuration input are based on a desired power dissipation of the SAR ADC.

[0136] The examples disclosed herein are illustrative and not limiting in nature. Details disclosed with respect to the methods described herein included in one example or aspect can be applied to other examples and aspects. Any aspect of the present disclosure that has been described herein can be disclaimed, i.e., exclude from the claimed subject matter whether by proviso or otherwise.

[0137] Various modifications to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other implementations without departing from the spirit or scope of this disclosure. Thus, the claims are not intended to be limited to the implementations shown herein, but are to be accorded the widest scope consistent with this disclosure, the principles and the novel features disclosed herein.

Claims

CLAIMS What is claimed is:

1. A circuit, comprising: a compute in-memory (CIM) array of multiplying bit-cells, the array generating a plurality of result analog voltages resulting from a multiplication of data stored in the multiplying bit-cells and input voltages; and a plurality of analog to digital converters (ADCs) coupled with the CIM array, each ADC of the plurality of ADCs including: a reference voltage terminal receiving a reference voltage, wherein a full- scale range of each ADC is a function of the reference voltage, an analog voltage input receiving a result analog voltage of the plurality of result analog voltages, a set of programmable capacitors configured to have a capacitance value based on a capacitor configuration input, wherein a noise performance of the ADC is a function of the capacitance value, and a digital output providing a digital representation of the result analog voltage received at the analog voltage input; wherein the circuit further comprises a plurality of programmable reference voltage generators coupled with a plurality of reference voltage terminals of the plurality of ADCs, each programmable reference voltage generator of the plurality of programmable reference voltage generators receiving one or more reference voltage configuration bits and generating the reference voltage for a respective ADC of the plurality of ADCs based on the one or more reference voltage configuration bits.

2. The circuit of claim 1, wherein the capacitor configuration input and the one or more reference voltage configuration bits are based on data stored in the multiplying bitcells of the CIM array of multiplying bit-cells.

3. The circuit of claim 1, wherein the capacitor configuration input and the one or more reference voltage configuration bits are configured such that for a respective ADC, a decrease in the reference voltage corresponds to an increase in the capacitance value of the set of programmable capacitors.

4. The circuit of claim 1, wherein the capacitor configuration input is configured to be independent of the reference voltage.

5. The circuit of claim 1, wherein each ADC of the plurality of ADCs is a successive- approximation-register ADC comprising at least one comparator, wherein the at least one comparator includes: a pre-amplifier stage coupled with the input terminals of the comparator, and a latch stage coupled with the pre-amplifier stage, wherein the set of programmable capacitors is positioned at the output of the pre-amplifier stage.

6. The circuit of claim 1, wherein the set of programmable capacitors is positioned at an input of each ADC.

7. The circuit of claim 1, further comprising: a controller configured to: receive as input at least a portion of the data stored in the multiplying bitcells, determine the full-scale range of each ADC of the plurality of ADCs, determine a recommended reference voltage for each ADC of the plurality of ADCs, determine a recommended capacitance for each ADC of the plurality of ADCs, and set the one or more reference voltage configuration bits and the capacitor configuration input for each ADC of the plurality of ADCs, respectively, based on the recommended reference voltage and the recommended capacitance.

8. The circuit of claim 7, wherein the controller is configured to: determine the recommended reference voltage based on a reference voltage look-up table, and determine the recommended capacitance based on a capacitance look-up table.

9. The circuit of claim 7, wherein the controller is configured to: determine the recommended reference voltage and the recommended capacitance based on a desired signal to noise ratio (SNR).

10. The circuit of claim 1, further comprising: a plurality of capacitor configuration registers storing capacitor configuration inputs corresponding to the plurality of ADCs; and a plurality of reference voltage configuration registers storing one or more reference voltage configuration bits corresponding to the plurality of programmable reference voltage generators.

11. The circuit of claim 10, wherein the plurality of capacitor configuration registers and the plurality of reference voltage configuration registers are loaded at a time of loading the data stored in the multiplying bit-cells.

12. The circuit of claim 10, wherein each programmable capacitor of the set of programmable capacitors includes a plurality of switched capacitors, wherein states of switches of the plurality of switched capacitors are controlled based on the plurality of capacitor configuration registers.

13. A method for configuring a plurality of analog to digital converters (ADCs) coupled with a compute in-memory (CIM) array of multiplying bit-cells, the array generating a plurality of result analog voltages resulting from a multiplication of data stored in the multiplying bit-cells and input voltages, each of the plurality of ADCs including: a reference voltage terminal receiving a reference voltage, wherein a full-scale range of each ADC is a function of the reference voltage, an analog voltage input receiving a result analog voltage of the plurality of result analog voltages, a set of programmable capacitors configured to have a capacitance value based on a capacitor configuration input, wherein a noise performance of the ADC is a function of the capacitance value, and a digital output providing a digital representation of the result analog voltage of the plurality of result analog voltages received at the analog voltage input, the method comprising: generating a reference voltage for each ADC of the plurality of ADCs based on respective reference voltage configuration bits.

14. The method of claim 13, comprising: generating the capacitor configuration input and the respective reference voltage configuration bits based on data stored in the multiplying bit-cells of the CIM array of multiplying bit-cells.

15. The method of claim 13, comprising: responsive to a decrease in the reference voltage, generating the capacitor configuration input to increase the capacitance value of the set of programmable capacitors.

16. The method of claim 13, comprising: generating the capacitor configuration input to change the capacitance value of the set of programmable capacitors independently of the reference voltage.

17. The method of claim 13, wherein each ADC of the plurality of ADCs is a successive-approximation-register ADC comprising at least one comparator, wherein the at least one comparator includes: a pre-amplifier stage coupled with input terminals of the at least one comparator, and a latch stage coupled with the pre-amplifier stage, wherein the set of programmable capacitors is positioned at an output of the pre-amplifier stage.

18. The method of claim 13, wherein the set of programmable capacitors is positioned at an input of each ADC.

19. The method of claim 13, comprising: receiving as input at least a portion of the data stored in the multiplying bit-cells; determining the full-scale range of each ADC of the plurality of ADCs; determining a recommended reference voltage for each ADC of the plurality of ADCs; determining a recommended capacitance for each ADC of the plurality of ADCs; and setting the respective reference voltage configuration bits and the capacitor configuration input for each ADC of the plurality of ADCs, respectively, based on the recommended reference voltage and the recommended capacitance.

20. The method of claim 19, comprising: determining the recommended reference voltage based on a reference voltage look-up table, and determining the recommended capacitance based on a capacitance look-up table.

21. The method of claim 19, comprising: determining the recommended reference voltage and the recommended capacitance based on a desired signal-to-noise ratio (SNR).

22. The method of claim 13, comprising: storing capacitor configuration inputs corresponding to the plurality of ADCs in a plurality of capacitor configuration registers; and storing the respective reference voltage configuration bits corresponding to the plurality of programmable reference voltage generators in a plurality of reference voltage configuration registers.

23. The method of claim 22, comprising: storing capacitor configuration inputs and the reference voltage configuration bits at a time of loading the data stored in the multiplying bit-cells.

24. A successive-approximation-register (SAR) analog to digital converter (ADC) comprising: a reference voltage terminal receiving a reference voltage, wherein a full-scale range of the SAR ADC is a function of the reference voltage, an analog voltage input receiving an input analog voltage for digital conversion, a set of programmable capacitors configured to have a capacitance value based on a capacitance configuration input, wherein a noise performance of the ADC is a function of the capacitance value, and a digital output providing a digital representation of the input analog voltage received at the analog voltage input.

25. The SAR ADC of claim 24, wherein the capacitor configuration input is based, in part, on a value of the reference voltage.

26. The SAR ADC of claim 24, wherein the set of programmable capacitors includes a plurality of switched capacitors connected in parallel, and wherein an on or off state of switches of each of the plurality of switched capacitors is determined based on the capacitor configuration input.

27. The SAR ADC of claim 24, wherein the reference voltage is based on an expected input analog voltage swing.

28. The SAR ADC of claim 24, wherein the reference voltage and the capacitance configuration input are based on a desired signal -to-noise ratio (SNR).

29. The SAR ADC of claim 24, wherein the reference voltage and the capacitance configuration input are based on a desired input analog voltage swing and a desired signal - to-noise ratio (SNR).

30. The SAR ADC of claim 24, wherein the reference voltage and the capacitance configuration input are based on a desired power dissipation of the SAR ADC.