WO2025122348A1

WO2025122348A1 - Flow-through edge shield to lessen current crowding effects during wafer electroplating

Info

Publication number: WO2025122348A1
Application number: PCT/US2024/056626
Authority: WO
Inventors: Gregory J. Wilson; Paul R. Mchugh
Original assignee: Applied Materials Inc
Current assignee: Applied Materials Inc
Priority date: 2023-12-06
Filing date: 2024-11-20
Publication date: 2025-06-12
Anticipated expiration: 2026-06-06
Also published as: US20250188640A1

Abstract

An edge shield for reducing electrical current crowding of a wafer, having a first side and a second side, during jet array electroplating, including one or more rings disposed below a second side of the wafer and configured to restrict current flow to an edge of the wafer, and at least one opening configured to allow electrolyte flow to pass through. Further, a system for reducing electrical current crowding of a wafer during jet array electroplating, including a chamber where, when the wafer is placed inside the chamber, there is a first gap between a wall of the chamber and an edge of the wafer and a second gap between a jet array and the second side of the wafer, and an edge shield disposed in the second gap, wherein the edge shield includes at least one opening configured to allow electrolyte flow to escape the chamber.

Description

FLOW-THROUGH EDGE SHIELD TO LESSEN CURRENT CROWDING EFFECTS

DURING WAFER ELECTROPLATING

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of U.S. Application No. 18/530,640, filed on December 6, 2023, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

[0002] Edge uniformity is a problem for electroplating processes. Current crowding at the wafer edge may is stronger when there are larger gaps between the wafer and edge shield.

[0003] Conventionally, electroplating chambers for heterogenous applications, i.e.. heterogenous nucleation, may use paddle agitation. To protect against current crowding at an edge of the wafer, weir shields, which are above the paddle and close to the wafer, have been used. The weir shield, however, can block mass-transfer to the wafer edge. Masstransfer may be advantageous at a wafer's edge. Specifically, mass-transfer determines the availability’ of cupric (Cu++) ions and additives at the plating surface. Plating consumes Cu++ ions at the surface, which must be replenished via mass-transfer.

[0004] In contrast, a jet array may be used in an electroplating chamber. The jet array allows for high mass transfer. Current density flows from the anode through the jet array to the wafer. Because the wafer is placed into the chamber for processing, there is typically a gap between the wafer and the opposite chamber walls. This gap may be larger than 8 mm. At the edge of the wafer, current can flow beyond the wafer edge and then return to the edge of the wafer. This phenomenon again leads to current crowding at the edge of the wafer, which leads to high edge current densities and/or deposition rates. Ideally, the chamber outer walls could be aligned with the edge of the plated film to minimize current crowding effects. However, the chamber outer walls must allow for an exit for the flow delivered to the chamber through the jet array.

[0005] Accordingly, edge shields, systems, and methods are needed for use in electroplating with high agitation jet arrays. SUMMARY

[0006] This summary' is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This summary is not intended to identify key features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0007] In one aspect, disclosed herein is an edge shield for reducing electrical current crowding of a wafer during jet array electroplating, including one or more rings disposed below a second side of the wafer and configured to restrict current flow to an edge of the wafer, and at least one opening configured to allow electrolyte flow to pass through.

[0008] In some embodiments, the at least one opening is configured between an edge of the wafer and the one or more rings. In some embodiments, the one or more rings are disposed vertically away from one another (i.e., stacked). In some embodiments, the one or more rings have a radial thickness ranging from about 20 mm to about 41 mm. In some embodiments, the edge shield has a height of about 11 mm.

[0009] In some embodiments, the at least one opening is a plurality of openings. In some embodiments, the edge shield further comprises an edge block, wherein a second side of the wafer contacts the edge block.

[0010] In another aspect, disclosed herein is a system for reducing electrical current crowding of a wafer during jet array electroplating, including a chamber configured to hold the wafer, wherein, when the w afer is placed inside the chamber, there is a first gap betw een a wall of the chamber and an edge of the wafer and a second gap between a jet array and a second side of the wafer. and an edge shield disposed in the second gap, wherein the edge shield includes at least one opening configured to allows electrolyte How to escape the chamber, where, during operation, the edge shield directs current flow away from an edge of the wafer.

[0011] In some embodiments, the edge shield comprises a ring. In some embodiments, the at least one opening configured is between the ring and the edge of the w afer. In some embodiments, the ring has a radial thickness betw een about 20 mm and about 50 mm. In some embodiments, the ring is configured for filling the second gap.

[0012] In some embodiments, the ring is a first ring, and wherein the edge shield comprises a plurality of rings. In some embodiments, each ring of the plurality of rings has a radial thickness of less than about 40.5 mm. In some embodiments, the plurality' of rings is disposed below the wafer. In some embodiments, each ring of the plurality of rings has a radial thickness of about 21 mm. In some embodiments, each ring of the plurality' of rings has a height of about 1 mm to 3 mm. In some embodiments, the plurality of rings comprises three rings. In some embodiments, the at least one opening is a first opening, and the edge shield comprises a plurality of openings. In some embodiments, the edge shield further comprises an edge block, wherein a second side of the wafer contacts the edge block. In some embodiments, the wafer overlaps with the edge block by about 1 to 3 mm.

[0013] In yet another aspect, disclosed herein is a method of jet-array electroplating a wafer with an edge shield, including placing the wafer inside of an electroplating chamber, applying electrolyte flow to the wafer with a jet array, electroplating the wafer with one or more materials, restricting current flow to the edge of the wafer with one or more rings of the edge shield, and allowing electrolyte to flow out of the electroplating chamber through one or more openings in the edge shield.

DESCRIPTION OF THE DRAWINGS

[0014] The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same become better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

[0015] FIGURE 1A is a simplified illustration of an electroplating chamber including jet array, in accordance with the present technology’;

[0016] FIGURE I B is an example jet array, in accordance with the present technology⁷;

[0017] FIGURE 1 C is a top-down view of a wafer inside an electroplating chamber, in accordance with the present technology;

[0018] FIGURE ID is a two-dimensional axisymmetric electric field simulation of the wafer of FIG. 1C, in accordance with the present technology;

[0019] FIGURE IE is a graph of current density⁷ over the wafer of FIG. ID, in accordance with the present technology;

[0020] FIGURE 2A is a top-down view of a wafer inside an electroplating chamber yvith an edge shield, in accordance yvith the present technology; [0021] FIGURE 2B is a two-dimensional axisymmetric electric field simulation of the wafer of FIG. 2A, in accordance with the present technology⁷;

[0022] FIGURE 2C is a graph of current density over the wafer of FIG. 2B, in accordance with the present technology;

[0023] FIGURE 3A is a perspective view of a wafer with an edge shield, in accordance with the present technology⁷;

[0024] FIGURE 3B is a side view of a wafer with an edge shield, in accordance with the present technology;

[0025] FIGURE 3C is a closeup view of an edge shield, in accordance with the present technology⁷;

[0026] FIGURE 3D is a two-dimensional axisymmetric electric field simulation of a wafer having an edge shield of a first thickness, in accordance with the present technology;

[0027] FIGURE 3E is a graph of current density⁷ over the wafer having the edge shield of the first thickness as shown in FIG. 3D, in accordance with the present technology⁷;

[0028] FIGURE 3F is a two-dimensional axisymmetric electric field simulation of the wafer having an edge shield of a second thickness, in accordance with the present technology⁷;

[0029] FIGURE 3G is a graph of current density⁷ over a wafer having the edge shield of the second thickness as shown in FIG. 3D in accordance with the present technology;

[0030] FIGURE 3H is a two-dimensional axisymmetric electric field simulation of the wafer having an edge shield and an edge block, in accordance with the present technology;

[0031] FIGURE 31 is a graph of cunent density over a wafer having the edge shield and an edge block as shown in FIG. 3H in accordance with the present technology; and

[0032] FIGURE 4 is a method of jet-array electroplating a wafer with an edge shield, in accordance with the present technology.

DETAILED DESCRIPTION

[0033] Disclosed herein are novel edge shields, systems, and methods for reducing current density⁷ at an edge of a wafer during jet array⁷ electroplating. In some embodiments, the edge shields include one or more rings configured to prevent and/or reduce edge current crowding, however still allowing electrolyte flow to pass through and exit a chamber. In some embodiments, the edge shield may include stacked, thin rings with flow channels. In other embodiments, the edge shield may include a tall ring with radial holes or slots to allow for electrolyte flow passage. In some embodiments, the edge shields, systems, and methods described herein allow for edge shielding structures that allow electrolyte flow to pass through the chamber radially but block ionic current flow to the edge of the wafer in order to lessen current crowding. Drawings are not necessarily drawn to scale.

[0034] Turning now to the FIGURES, FIG. 1A is a simplified illustration of an electroplating chamber 150 including a jet array 105 (also referred to herein as a jet array plate), in accordance with the present technology. In some embodiments, the electroplating chamber 150 is configured to hold a wafer 100. In some embodiments, the electroplating chamber 150 is further configured to contain ajet array 105 The jet array 105 may include a plurality of tubes (as shown in FIG. IB) configured to deliver one or more jet streams of electrolyte flow 110A, HOB, HOC to the wafer 100. In some embodiments, the chamber 120 is a fountain plating chamber. The wafer 100 may have a first side SI and a second side S2. In some embodiments, the first side SI is a backside of wafer 100 and the second side S2 is a frontside of wafer 100. The wafer 1 0 may be processed face down (with the second side S2 facing the jet array 105) in the chamber 120, as shown in FIG. 1A. Electrolyte flow 110A, HOB, HOC impinges on the wafer 100 surface and then flows radially outward. Beyond the edge of the wafer 100, the electrolyte flow 110A, HOB, 110C may flow over a weir to a drain (as shown in FIG. 3 A). The system 1000 may further include a catholyte 103, a membrane 1 17, an anolyte 109, a wafer seal 107, a catholyte inlet 111, and an anolyte exit 113. It should be understood that FIG. 1A is a simplified illustration, and additional components may be omitted or optional in system 1000. Further, not all components illustrated in FIG. 1A may be included in system 1000.

[0035] In some embodiments, when the wafer 100 is placed inside the chamber 150, there is a gap G1 between the wafer edge and the chamber wall. In some embodiments, the gap G1 is greater than or equal to about 8 mm. When the gap G1 exceeds 8 mm, there may be additional current crowding at the edge of the wafer. In some embodiments, there may be a second gap G2 between the wafer 100 and the jet array 105. These two gaps (Gl, G2) define volume through which ionic current spreads beyond the wafer edge and then returns to the wafer edge. [0036] In operation, the wafer 100 is placed inside the chamber 150, and the jet array 105 delivers one or more streams of electrolyte flow 110A, HOB, 1 IOC to the surface of the wafer 100. The electrolyte flow 110A, HOB, HOC impinges the wafer 100 and radially exits the chamber 150. An anode below the jet array 105 delivers current to the wafer 100 (cathode) through the electrolyte 110A, 110B, HOC. Ionic current flows through the jet array tubes (or nozzles) and then to the wafer surface. Because of a first gap G1 between the edge of the wafer 100 and the chamber 150, at the edge of the wafer 100, current can flow beyond the wafer edge and then return to the edge of the wafer 100. Accordingly, in some embodiments, an edge shield as shown and described herein may be included. While an edge shield is not illustrated in FIG. 1A for clarity, it should be understood that any of the edge shields illustrated and described herein may be used with the system shown in FIG. 1A.

[0037] In one aspect, disclosed herein is a system for reducing electrical current crowding of the wafer 100 during jet array electroplating, including the wafer 100, the chamber (or electroplating chamber) 150 configured to hold the wafer, where when the wafer 100 is placed inside the chamber, there is a first gap G1 between a wall of the chamber and an edge of the wafer (as shown in FIGs. 1C. 2A, and 3B). and an edge shield (as shown in FIGs. 2A and 3B) disposed in the gap. In some embodiments, the edge shield includes at least one opening configured to allow electrolyte flow to escape the chamber, and during operation, the edge shield blocks current flow to the edge of the wafer.

[0038] FIG. IB is an example jet array 105. in accordance with the present technology. In some embodiments, the jet array 105 includes a plurality of jets 115A, 115B, 115C arranged in an array across the jet array 105. In some embodiments, the jet array 105 may be shaped cylindrically , such as shown in FIG. IB. In some embodiments, the jet array 105 may be shaped to substantially match the shape of the wafer (such as wafer 100). In some embodiments, the jet array 105 is the same size as the w afer.

[0039] In operation, the plurality of jets 115 A, 115B, 115C deliver electrolyte flow and ionic current to the wafer to electroplate the wafer. The electric current may be used to reduce dissolved metal cations to form a thin metal coating on the surface of the wafer.

[0040] FIG. 1C is a top-down view of a wafer 100 inside an electroplating chamber 150, in accordance with the present invention. In some embodiments, FIG. 1C is a view of the w afer 100 inside the chamber (or electroplating chamber) 150 as shown in FIG. 1A. [0041] The wafer 100 may have a radius r. In some embodiments, the radius r is about 300 mm. In other embodiments, the wafer may have another radius r.

[0042] In some embodiments, when the wafer 100 is placed inside the chamber 150, there is a gap Gl between the wafer edge WE and the chamber edge CE. In some embodiments, the gap G1 is greater than or equal to about 8 mm. When the gap G1 exceeds 8 mm, there may be additional current crowding at the edge of the wafer WE. In some embodiments, there is a second gap G2 between the wafer 100 and the jet array (as shown in FIG. 1A and ID). These two gaps (Gl, G2) define volume through which ionic current spreads beyond the wafer edge WE and then returns to the wafer edge WE.

[0043] FIG. ID is a two-dimensional axisymmetric electric field simulation of the wafer 100 of FIG. 1C, in accordance with the present technology'. As shown in FIG. 1C, the wafer (illustrated as the light grey semicircle) has a radius r. The centerline of the wafer CL is also illustrated. In some embodiments, the radius r is about 22 mm. Also illustrated is the flux radius Fr, the chamber radius Cr, and the gap Gl . On the left axis, the height H of the two-dimensional perspective modeled is show n.

[0044] FIG. ID represents a simulation of current density’ where the radius r is about 22 mm. the flux radius Fr is about 36 mm, a cunent is 6 Amps, a seed is 10 pm copper (Cu) and the electrical conductivity of the electrolyte bath is about 500 mS/cm. As shown in FIG. IE, there is a high current density' over much of the w afer, and a very' high current density at the edge of the wafer.

[0045] FIG. IE is a graph of current density over the wafer of FIG. ID, in accordance with the present technology⁷. As explained herein, the current density' on the wafer illustrated FIGs. 1C and ID is high, particularly at the edge of the wafer. As described here, the “edge” of the wafer (WE in FIG. 1C) refers to the edge around the wafer and extending about 1-4 mm into the wafer.

[0046] On the horizontal axis is the radius of the wafer (referred to as a coupon for the purpose of the simulation, or printed circuit board (PCB)) in millimeters. On the vertical axis is the current density (j) in mA/cm². The illustrated coupon has a radius of 22 mm. The current density (j) at the center of the wafer is about 200 mA/cm² but increases steadily to over 1600 mA/cm² at the edge (r > 20 mm). As explained above, this current crowding at the edge of the coupon results in high edge non-uniformity. Poor edge uniformity’ can compromise yield for die located near the wafer edge. [0047] FIG. 2A is a top-dow n view of a wafer 100 inside an electroplating chamber 150 with an edge shield 1200 formed by at least one ring 120, and at least one opening O, in accordance with the present technology. In some embodiments, the edge shield 1200 includes at least one ring 120 and at least one opening O. In some embodiments, the edge shield 1200 is configured to reducing electrical current crowding of a wafer during jet array electroplating, as shown in FIG. 1 A. In some embodiments, at least one (i.e., one or more) ring 120 is disposed around the wafer 100 and configured to restrict current flow at an edge of the wafer. In some embodiments, the at least one opening O is configured to allow the electrolyte flow to pass through the chamber 150, and out of the chamber 150.

[0048] In some embodiments, at least one opening O configured is between an edge of the wafer WE and the one or more rings 120. In some embodiments, the one or more rings 120 each have a radial thickness T ranging from about 5 mm to about 50 mm. In some embodiments, the one or more rings 120 each have a radial thickness T ranging from about 20 mm to about 41 mm. In some embodiments, the one or more rings 120 each have a thickness of 40.5 mm, depending on how much room is available within the chamber 150 geometry’. In some embodiments, the one or more rings 120 are disposed below from the wafer 100. In some embodiments, the opening O is a radial pass-through in the shield ring itself 120, 120-i, as shown in FIG. 2A. In some embodiments, the opening O is a ringshaped opening through the ring 120, which separates a portion of the ring 120-i from the ring 120. In such embodiments, the portion of the ring 120-i contacts the wafer 100.

[0049] In some embodiments, when the edge shield 1200 is placed into the chamber 150 and around the wafer 100, the gap G2 between the edge shield 1200 and the chamber edge is smaller than the gap G1 of FIG. 1C.

[0050] In some embodiments, the opening O is a channel (or radial channel). While an edge shield without an opening O may prevent current crowding at the edge of the wafer, such an edge shield also prevents the flow of electrolyte to exit the chamber. Accordingly, the opening O allow s for electrolyte fluid flow to escape the chamber 150.

[0051] FIG. 2B is a tw o-dimensional axisymmetric electric field simulation of the wafer of FIG. 2A, in accordance with the present technology. One skilled in the art should appreciate that the simulation shows electrical potential. The current density flow is normal to the potential lines. Shown in FIG. 2B are a thickness of the one or more rings T, a centerline of the wafer CL, a radius r of the coupon, a flux radius Fr, and a chamber radius Cr. On the vertical axis, the height H of the two-dimensional perspective modeled is shown. Also shown is the opening O.

[0052] The modeled simulation of current density illustrated in FIG. 2B is for a coupon having a 22 mm radius r, a 43 mm flux radius Fr, and an 82 mm chamber radius Cr. The thickness T of the wafer was simulated at 40.5 mm. The coupon was simulated in a bath of 500 mS/cm of electroplating solution.

[0053] FIG. 2C is a graph of current density over the wafer of FIG. 2B, in accordance with the present technology. On the horizontal axis is the radius of the wafer in millimeters. On the vertical axis is the cunent density in (mA/cm²). The illustrated coupon has a radius of 22 mm. The current density remains mostly uniform at slightly less than 400 (mA/cm²) extending from the center of the wafer toward its periphery, until the edge of the wafer (<20 mm). At a radius of about 20 mm, the current density increases until a radius of about 22 mm, to a current density of slightly less than 700 (mA/cm²). While the current density may still increase at the edge of the wafer, the current density is reduced from that of the wafer without the edge shield, shown in FIG. IE. Further, the current density throughout the wafer (from the center to 20 mm) remains mostly uniform throughout. In this manner, a more uniform current density over the wafer was achieved when the edge shield is present.

[0054] FIG. 3 A is a perspective view of a w afer 100 with an edge shield 1200, in accordance with the present technology. In some embodiments, FIG. 3 A is a cross-section of FIG. 2A. In some embodiments, the edge shield 1200 includes an edge block 107. a plurality of rings 12 A, 120B, and a plurality of openings (or channels) Cl, C2, C3. In some embodiments, one or more rings 120A, 120B are a plurality⁷ of rings. While two rings are illustrated, one skilled in the art should understand that any number of rings may be included in edge shield 1200. In some embodiments, the at least one opening is a plurality of channels Cl, C2, C3, C4 (as shown in FIG. 3A). As described herein, a channel is an opening between each ring in the plurality of rings 120A, 120B or between a ring of the plurality of rings 120A, 120B and the edge block 107. While three channels Cl, C2, C3 are illustrated, any number of channels may be included in the edge shield 1200. In some embodiments, each ring in the plurality of rings 120A, 120B has a radial thickness of about 40.5 mm (as described and shown in more detail in FIGs. 3D-3E below). In some embodiments, the plurality' of rings 120A, 120B is disposed below' the wafer 100. In some embodiments, each ring of the plurality of rings 120A, 120B has a radial thickness of about 21 mm (as described and shown in more detail in FIGs. 3D-3E below). In some embodiments, each ring of the plurality of rings 120A, 120B has a height ranging from about 1 mm to about 3 mm. In some embodiments, the plurality of rings 120 A, 120B comprises three rings.

[0055] In some embodiments, the one or more rings 120A, 120B are disposed vertically away from one another (i.e., stacked). In some embodiments, the one or more rings 120 A, 120B have a radial thickness ranging from about 20 mm to about 41 mm. In some embodiments, the plurality of channels Cl, C2, C3 is located between each ring of the plurality of rings 120 A, 120B as shown in FIG. 3 A. In some embodiments, each channel of the plurality of channels Cl, C2, C3 has a height of about 2 mm.

[0056] In some embodiments, the edge shield 1200 has a height of about 11 mm. In some embodiments, the edge shield 1200 further includes an edge block 107. It should be understood that in some embodiments, the edge block 107 is optional. In some embodiments, the edge block 107 is replaced with an additional ring of the plurality of rings. In operation, the edge block holds the wafer 100 at a distance from the jet array plate 105, so that a second gap G2 is formed. In some embodiments, the wafer 100 includes a first side SI and a second side S2. The first side SI may be a back side of the wafer 100, w hile the second side S2 may be a front side of the wafer 100. When the edge shield 1200 is in place, there may be a flow plenum 123 between the wafer 100 and the chamber wall. In some embodiments, a flow weir 127 may surround the wafer 100.

[0057] FIG. 3B is a side view' of a wafer 1 0 with an edge shield 1200, in accordance with the present technology. In some embodiments, the wafer has a first side SI and a second side S2. The first side S 1 may be a backside and the second side S2 may be a frontside. The wafer may be held by an edge block 107 above a jet array 105. In some embodiments, there is a second gap G2 between the wafer 100 and the jet array 105. In some embodiments, there is an edge shield 1200 disposed in the second gap G2. In some embodiments, the edge shield includes the edge block 107, but in other embodiments, the edge block 107 is not considered a part of the edge shield 1200. In some embodiments, the edge block 107 may be part of a wafer holder or wafer seal of the chamber 150. In some embodiments, the edge shield 1200 includes aplurality offings 120 A, 120B and a plurality of openings (channels) Cl, C2, C3. The edge shield 1200 may be surrounded by a flow plenum 123 and a flow weir 127.

[0058] FIG. 3C is a closeup view of an edge shield 1200, in accordance with the present technology. Also shown in FIG. 3C is a jet array 105, a wafer 100, a flow plenum 123, and a flow weir 127 surrounding the wafer 100. The wafer may have a first side SI and a second side S2 as described herein.

[0059] In some embodiments, the wafer 100 has a radius of 150 mm. In some embodiments, the edge block 107 overlaps with a portion of the wafer 100. The wafer may contact the edge block 107. In some embodiments, the wafer 100 overlaps with the edge block 107 by about 1 to 3 mm. As shown in FIG. 3C, the last 3 mm of the edge of the wafer 100 may contact the edge block 107. In some embodiments, the edge block 107 is part of the edge shield 1200. In some embodiments, the edge shield 1200 further includes a plurality of rings 120A, 120B and a plurality of channels Cl, C2, C3. In some embodiments, the channels Cl, C2, C3 are radial holes through the edge shield 1200.

[0060] FIG. 3D is a two-dimensional axisymmetric electric field simulation of a wafer having an edge shield of a first thickness Tl, in accordance with the present technology. The simulation may correspond to the wafer 100 shown in FIG. 3 A, where the thickness Tl may be the radial thickness of the one or more rings 120A, 120B. Show n in FIG. 3D is a center line CL of the wafer, a radius r of the w afer, a flux radius Fr, and a chamber radius Cr. On the vertical axis, the height H of the tw o-dimensional perspective modeled is shown. In some embodiments, the height of the edge shield is equal to the height H. Also shown is the height Hl of each channel of the plurality of channels shown in FIG. 3A, and the height H2 of each ring in the plurality of rings in FIG. 3A.

[0061] The modeled simulation of FIG. 3D corresponds to a coupon having a 22 mm radius r. a 43 mm flux radius Fr, a height H of 11 mm and an 82 mm chamber radius Cr. The thickness Tl of each ring of the edge shield w as simulated at 40.5 mm. In some embodiments, the edge shield has a height of about 11 mm, each ring in the plurality of rings has a height H2 of about 1 mm to about 3 mm, and each opening in the plurality of openings (channels) have a height Hl of about 2 mm. The coupon was simulated in a bath of 500 mS/cm.

[0062] FIG. 3E is a graph of current density over the w afer having the edge shield of the first thickness as shown in FIG. 3B, in accordance with the present technology⁷. On the horizontal axis is the radius of the wafer in millimeters. On the vertical axis is the current density (j) in mA/cm². The coupon illustrated has a radius of 22 mm.

[0063] The current density remains mostly uniform at slightly more than 400 mA/cm² extending from the center of the coupon, until the edge of the coupon (<20 mm). At about 21 mm, the current density increases until 22 mm, to a current density' of about 600 mA/cm². While the current density still increases at the edge of the wafer, it is reduced from that of the wafer without the edge shield, as shown in FIG. IE, and from that of the wafer with the edge shield shown in FIG. 2C. Further, the current density throughout the wafer (from the center to 21 mm) remained mostly uniform throughout. In this manner, more uniformity' of the current density' over the wafer was achieved with the edge shield of FIG. 3 A having a ring thickness of about 40.5 mm.

[0064] FIG. 3F is a two-dimensional axisymmetric electric field simulation of the wafer having an edge shield of a second thickness T2, in accordance with the present technology⁷. The simulation may be of the wafer 100 shown in FIG. 3 A, where the thickness T2 may be the radial thickness of the plurality of rings 120 A, 120B. Show n in FIG. 3F are a center line CL of the wafer, a radius r of the wafer, a flux radius Fr, and a chamber radius Cr. On the left axis, the height H of the two-dimensional perspective modeled is shown. In some embodiments, the height of the edge shield is equal to the height H. Also show n is the height Hl of each channel of the plurality of channels show n in FIG. 3A, and the height H2 of each ring of the plurality' of rings in FIG. 3A.

[0065] The modeled simulation of FIG. 3F is for a coupon having a 22 mm radius r, a 43 mm flux radius Fr, a height H of 11 mm and an 82 mm chamber radius Cr. The thickness T2 of the plurality' of rings was simulated at 21 mm. In some embodiments, the edge shield has a height H of about 11 mm, each ring in the plurality of rings has a height H2 of about 1 mm, and each opening in the plurality of openings (channels) has a height Hl of about 2 mm. The wafer was simulated in a bath of 500 mS/cm.

[0066] FIG. 3G is a graph of current density' over a wafer having the edge shield of the second thickness as shown in FIG. 3F in accordance with the present technology'. On the horizontal axis is the radius of the wafer in millimeters. On the vertical axis is the current density (j) in mA/cm². The illustrated wafer has a radius of 22 mm.

[0067] The current density remains mostly uniform at slightly less than 400 mA/cm² extending from the center of the wafer, until the edge of the wafer (<20 mm). At a radius of about 20 mm, the current density increases until the radius of about 22 mm, where a current density⁷ is slightly less than about 800 mA/cm². While the current density still increases at the edge of the wafer, the current density is reduced from that of the wafer without the edge shield, as shown in FIG. IE, but not in comparison of that of the wafer with the edge shield shown in FIG. 2C. Further, the current density throughout the wafer (from the center to about 21 mm radius) remained mostly uniform throughout. In this manner, more uniformity of the current density over the wafer was achieved with the edge shield of FIG. 3 A having a ring thickness of about 21 mm, in comparison to a system lacking an edge shield.

[0068] FIG. 3H is a two-dimensional axisymmetric electric field simulation of the wafer 100 having an edge shield 1200 and an edge block 107, in accordance with the present technology. In some embodiments. FIG. 3H may be a system as shown and described in FIG. 3 A. Shown is the wafer 100 having a center line CL. The edge block 1200 includes an edge block 107, a plurality of rings 120A, 120B, and a plurality of channels Cl, C2, C3.

[0069] FIG. 31 is a graph of current density over a wafer having the edge shield and an edge block as shown in FIG. 3H in accordance with the present technology. On the horizontal axis is the radius of the wafer in millimeters. On the vertical axis is the current density (j) in mA/cm². The illustrated wafer has a radius of 22 mm.

[0070] The current density remains mostly uniform at about 400 mA/cm² extending from the center of the wafer, all the way to the edge of the wafer (<22 mm). The edge shield including the edge block kept the current density uniform throughout the entire wafer better than the wafers shown in FIG. IE, FIG. 2C, and FIG. 3D. In this manner, more uniformity of the current density over the wafer was achieved with the edge shield of FIG. 3A having an edge block.

[0071] FIG. 4 is a method 400 of jet-array electroplating a wafer with an edge shield, in accordance with the present technology. The method 400 may be carried out with any of the edge shields or systems described herein. In some embodiments, the method is carried out with an electroplating chamber (such as chamber 150), a wafer (such as wafer 100), and a jet array (such as jet array 105). In some embodiments, the method is carried out with an edge shield (such as shown in FIGs. 2A-2C and 3A-3E). [0072] In block 405, a wafer is placed inside of the electroplating chamber. In some embodiments, there is a gap between the wafer and an opposing wall of the electroplating chamber when the wafer is placed inside. In some embodiments, the gap is greater than 8 mm. In some embodiments, the gap is about 11 mm.

[0073] In block 410, current flow is restricted to the edge of the wager with one or more rings of the edge shield. In some embodiments, the edge shield includes a plurality of rings (such as three rings). In some embodiments, the one or more rings are disposed below the wafer. In some embodiments, the one or more rings fill the gap between the edge of the wafer and the wall of the electroplating chamber. It should be understood that block 420 may occur simultaneously with blocks 415 and 420.

[0074] In block 415, current flow is applied to the wafer with a jet array. In some embodiments, the jet array includes a plurality of jets arranged in an array. In some embodiments, the jet array is shaped and sized to be substantially like the wafer. In some embodiments, the jet array is cylindrical.

[0075] In block 420, the wafer is electroplated. It should be understood that block 415 and 420 may be performed simultaneously. Further, in some embodiments, block 415 may occur before block 420 In some embodiments, the wafer is electroplated with copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), titanium (Ti), platinum (Pt), or the like. In some embodiments, a seed of the system by be 10 pm of Cu.

[0076] In block 425, electrolyte is allowed to flow from the electroplating chamber through one or more openings in the edge shield. In some embodiments, the one or more openings are one or more channels. In some embodiments, each channel is located between the one or more rings of the edge shield. It should be understood that block 435 may occur simultaneously with blocks 410, 415, and 420. In some embodiments, the electrolyte flows through the openings and out of the electroplating chamber (i.e., to escape the electroplating chamber). In this way, the openings allow electrolyte delivered from the jet array to exit the chamber.

[0077] It should be understood that method 400 should be interpreted as merely representative. In some embodiments, process blocks of method 400 may be performed simultaneously, sequentially, in a different order, or even omitted, without departing from the scope of this disclosure. [0078] The present application may reference quantities and numbers. Unless specifically stated, such quantities and numbers are not to be considered restrictive, but representative of the possible quantities or numbers associated with the present application. Also, in this regard, the present application may use the term ‘'plurality’⁷ to reference a quantity or number. In this regard, the term “plurality” is meant to be any number that is more than one, for example, two, three, four, five, etc. The terms “about,” “approximately,” “near,” etc., mean plus or minus 5% of the stated value. For the purposes of the present disclosure, the phrase “at least one of A, B. and C,” for example, means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C), including all further possible permutations when greater than three elements are listed.

[0079] The detailed description set forth above in connection with the appended drawings, where like numerals reference like elements, are intended as a description of various embodiments of the present disclosure and are not intended to represent the only embodiments. Each embodiment described in this disclosure is provided merely as an example or illustration and should not be construed as preferred or advantageous over other embodiments. The illustrative examples provided herein are not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Similarly, any steps described herein may be interchangeable with other steps, or combinations of steps, in order to achieve the same or substantially similar result. Generally, the embodiments disclosed herein are non-limiting, and the inventors contemplate that other embodiments within the scope of this disclosure may include structures and functionalities from more than one specific embodiment shown in the figures and described in the specification.

[0080] In the foregoing description, specific details are set forth to provide a thorough understanding of exemplary embodiments of the present disclosure. It will be apparent to one skilled in the art, however, that the embodiments disclosed herein may be practiced without embodying all the specific details. In some instances, well-known process steps have not been described in detail in order not to unnecessarily obscure various aspects of the present disclosure. Further, it will be appreciated that embodiments of the present disclosure may employ any combination of features described herein.

[0081] The present application may include references to directions, such as “vertical,” “horizontal,” “front,” “rear,” “left,” “right,” “top,” and “bottom,” etc. These references, and other similar references in the present application, are intended to assist in helping describe and understand the particular embodiment (such as when the embodiment is positioned for use) and are not intended to limit the present disclosure to these directions or locations.

[0082] The present application may also reference quantities and numbers. Unless specifically stated, such quantities and numbers are not to be considered restrictive, but exemplary of the possible quantities or numbers associated with the present application. Also, in this regard, the present application may use the term “plurality” to reference a quantity or number. In this regard, the term “plurality” is meant to be any number that is more than one, for example, two, three, four, five, etc. The term “about,” “approximately,” etc., means plus or minus 5% of the stated value. The term “based upon” means “based at least partially upon.”

[0083] The principles, representative embodiments, and modes of operation of the present disclosure have been described in the foregoing description. However, aspects of the present disclosure, which are intended to be protected, are not to be construed as limited to the particular embodiments disclosed. Further, the embodiments described herein are to be regarded as illustrative rather than restrictive. It will be appreciated that variations and changes may be made by others, and equivalents employed, without departing from the spirit of the present disclosure. Accordingly, it is expressly intended that all such variations, changes, and equivalents fall within the spirit and scope of the present disclosure as claimed.

[0084] While illustrative embodiments have been illustrated and described, it will be appreciated that various changes can be made therein without departing from the spirit and scope of the invention.

Claims

CLAIMS We claim:

1 . An edge shield for reducing electrical current crowding of a wafer, having a first side and a second side, during jet array electroplating, comprising: one or more rings disposed below the second side of the wafer and configured to restrict current flow to an edge of the wafer; and at least one opening configured to allow electrolyte flow to pass through.

2. The edge shield of Claim 1, wherein the at least one opening is configured between an edge of the wafer and the one or more rings.

3. The edge shield of Claim 1, wherein the one or more rings are disposed vertically away from one another.

4. The edge shield of any one of Claims 1-3. wherein the one or more rings have a radial thickness ranging from about 20 mm to about 50 mm.

5. The edge shield of any one of Claims 1-3, wherein the edge shield has a height of less than about 15 mm.

6. The edge shield of any one of Claims 1-3, wherein the at least one opening is a plurality of openings.

7. The edge shield of any one of Claims 1-3, wherein the edge shield further comprises an edge block, wherein the second side of the wafer contacts the edge block.

8. A system for reducing electrical current crowding of a wafer during jet array electroplating, comprising: a chamber configured to hold the wafer, wherein, when the wafer is placed inside the chamber, there is a first gap between a wall of the chamber and an edge of the wafer and a second gap between a jet array and a second side of the wafer; and an edge shield disposed in the second gap, wherein the edge shield includes at least one opening configured to allow electrolyte flow to escape the chamber, wherein, during operation, the edge shield directs current flow away from an edge of the wafer.

9. The system of Claim 8, wherein the edge shield comprises a ring.

10. The system of Claim 9, wherein the at least one opening is a radial pass- through in the ring, and wherein the ring has a radial thickness between about 5 mm and about 50 mm.

11. The system of Claim 9 or Claim 10, wherein the ring is configured for filling the second gap.

12. The system of any one of Claims 9-11, wherein the ring is a first ring, and wherein the edge shield comprises a plurality of rings, each ring of the plurality of rings has the radial thickness of less than about 40.5 mm. and wherein the plurality of rings is disposed below the wafer.

13. The system of Claim 12, wherein the at least one opening is a first opening, and the edge shield comprises a plurality of openings.

14. The system of any one of Claims 9-13, wherein the edge shield further comprises an edge block, wherein the wafer has a first side and the second side, and wherein the second side of the wafer contacts the edge block.

15. The system of any one of Claims 9-13, wherein the wafer overlaps with the edge block by about 1 to 3 mm.