WO2025119892A1

WO2025119892A1 - Optoelectronic device and method for processing the same

Info

Publication number: WO2025119892A1
Application number: PCT/EP2024/084472
Authority: WO
Inventors: Florian VOEGL
Original assignee: Ams Osram International GmbH
Current assignee: Ams Osram International GmbH
Priority date: 2023-12-05
Filing date: 2024-12-03
Publication date: 2025-06-12
Anticipated expiration: 2026-06-05

Abstract

The invention concerns a µLED comprising a semiconductor layer stack with a first and second doped semiconductor layer and an active layer arranged in between. A first region of the layer stack is characterized by inclined sidewall portions and comprises the first doped semiconductor layer. A second region of the layer stack characterized by substantially perpendicular sidewalls comprises the second doped semiconductor layer, the active layer and optionally a portion of the first semiconductor layer closest in proximity to the active layer. A first conductive layer is arranged on the inclined sidewalls of the first region of the semiconductor stack, extending laterally to form a top surface that provides electrical connectivity between the first doped layers of surrounding pixels, while simultaneously providing optical isolation between the doped layers, thus substantially eliminating crosstalk between pixels. A second conductive reflective layer provides electrical contact to the second doped layer, and is electrically isolated from the first conductive layer by means of a dielectric layer arranged between the two reflective layers.

Description

OPTOELECTRONIC DEVICE AND METHOD FOR PROCESSING THE SAME

The present application claims priority from DE application DE 10 2023 134 038 . 7 dated December 5 , 2024 , the disclosure of which is incorporated herein by reference in its entirety . The present invention concerns an optoelectronic device and a method for processing the same .

BACKGROUND pLEDs are optoelectronic semiconductor devices characterized by geometric structures and dimensions not smaller than 70pm, with typical dimensions in the range between 20pm to 50pm, and possibly down to a few pm, for example between 1pm and 10pm .

A common challenge in optoelectronic devices comprising arrays of pLEDs is optical crosstalk between adj acent pixels . This occurs when a doped layer between pixels acts as a waveguide for the light . Consequently, when emitted light from one pixel undergoes total internal reflection, the reflected light can travel within the semiconductor to neighbouring pixels , from where outcoupling occurs . The resultant decrease in such crosstalk is particularly problematic in display applications as light may bleed from bright pixels into neighbouring pixels .

Integration of inclined sidewalls through sidewall etching, as described in reference US 11 , 404 , 400 has been presented as a means of achieving higher light emission efficiency ( LEE ) and far-field properties . However, the presence of residual n-GaN and buffer layers between pixels on the n-side allows optical crosstalk between neighbouring pixels . It is therefore necessary to fully isolate neighbouring pixels through full removal of Epi between pixels on the side from which light exits the pLED pixel .

It is an obj ect of the present application to provide an optoelectronic device or pLED and a respective method for processing an optoelectronic device or pLED that eliminates crosstalk between neighbouring pixels in an array comprising a plurality of said optoelectronic devices . SUMMARY OF THE INVENTION

This and other obj ects are addressed by the subj ect matter of the independent claims . Features and further aspects of the proposed principles are outlined in the dependent claims .

The inventor proposes a special pixel design with at least two electrically isolated conductive layers in contact with the respective doped layers of the pLED semiconductor stack . The conductive mirrors serve partly to reflect emitted light within the pixel and simultaneously to provide electrical contact to the doped layers . The proposed principle allows full removal of remaining epi-layers between pixels on the side corresponding to the exit direction of light from the optoelectronic device . At least one of the conductive layers can be metal or other reflective layers if needed .

The proposed principle may be implemented on a two-step pixel structure , wherein part of the pLED is characterized by vertical sidewalls for optimal internal quantum efficiency ( IQE ) while part of the pLED closer to the emission surface is shaped to achieve inclined sidewalls for optimized light extraction . A conductive , no light transmitting layer arranged on the inclined sidewalls extends to the emission surface and extends laterally to fully isolate the doped semiconductor region from neighbouring pixels , thus substantially eliminating crosstalk between pixels .

In some aspects , the inventor proposes an optoelectronic device , in particular a pLED . The device comprises a semiconductor layer stack comprising a first doped semiconductor layer , a second doped semiconductor layer and an active layer arranged between the first and second doped semiconductor layers .

The semiconductor stack is characterized by a stepped structure , i . e . , with a first portion comprising the first doped layer , and a second portion comprising the second doped layer , the active layer, optionally a second portion of the first doped semiconductor layer and at least one layer of conductive material , comprising at least one of a transparent conductive oxide , in particular ITO and/or a third conductive reflective material and/or a DBR mirror .

In accordance with the proposed principle , the sidewalls of the first portion of the semiconductor stack are inclined such that the cross- sectional area of the first portion of the semiconductor stack decreases with decreasing distance from the active layer . The surface of the first portion of the semiconductor stack corresponding to the light emission surface of the pLED is thus characterized by a larger cross-sectional area in comparison to the surface facing the second portion of the semiconductor stack .

In accordance with the proposed principle , the sidewalls of the second portion of the semiconductor stack are substantially perpendicular to the surface of the first doped semiconductor layer . In some aspects , the conductive layer arranged between the second doped semiconductor layer and the dielectric layer may be structured to have a smaller cross-sectional area than the cross-sectional area of the second doped semiconductor layer and the active layer , whereby the sidewalls of said conductive layer are substantially perpendicular to the horizontal top surface , thereby forming a step-like structure in the second portion of the semiconductor stack . In alternative embodiments , the conductive layer between the second doped semiconductor layer and the dielectric layer may be characterized by a cross-sectional area substantially equal to the cross-sectional area of the second doped semiconductor layer and the active layer , such that the sidewalls of the second portion of the semiconductor stack are characterized by a continuous vertical profile .

The stepped structure of the semiconductor stack comprising a first portion with inclined sidewalls and a second portion with vertical sidewalls can be achieved by for example using a conventional mesa etching process and then treating a portion of the exposed sidewalls with an etching process to obtain vertical sidewalls . For nitride material systems based on GaN, InGaN, AlGaN or InAlGaN, KOH etching may be used . It has been found that KOH etching using longer etch times and high temperature provides a self-aligning and self-limiting etch, resulting in vertical sidewalls . Implementation of the approach leads to a first portion of the pLED close to the emission surface that is shaped and optimized for light extraction, and a second portion of the pLED with vertical sidewalls optimized for high IQE .

In some aspects , the stepped structure of the semiconductor stack comprises a first portion with inclined sidewalls and a second portion with vertical sidewalls . Such structure can alternatively be achieved in two steps by using a first mesa etching process and then treating the exposed sidewall with an etching process to obtain vertical sidewalls . For nitride material systems based on GaN, InGaN, AlGaN or InAlGaN, KOH etching may be used . It has been found that KOH etching using longer etch times and high temperature provides a self-aligning and self-limiting etch, resulting in vertical sidewalls . In a next step the first mesa may be covered with a photo resist or dielectric material with a rounded shape and a second mesa etch may be conducted resulting in inclined sidewalls . The sidewall angle can be controlled by the photo resist shape and choice of plasma parameters .

Optionally a ALD step can be conducted after wet etching to functionalize and passivate the vertical sidewalls of the first mesa to reduce non-radiative recombination at sidewalls . In this case this layer needs to be removed partly in the second mesa etch step .

Implementation of the approach leads to a first portion of the pLED close to the emission surface that is shaped and optimized for light extraction, and a second portion of the pLED with vertical sidewalls optimized for high IQE .

In accordance with the proposed principle , a first conductive layer is arranged on the sidewalls of the first portion of the semiconductor stack extending to the top surface of the first doped layer , and further extending laterally away from the semiconductor stack, wherein the top surface of the conductive layer is substantially flush with the top surface of the first portion of the semiconductor stack . The conductive reflective layer may be a reflective metal layer comprising, for example , Ag, Al or Au . Furthermore , a dielectric material is arranged on the surface of the first conductive reflective layer facing away from the top surface of , the dielectric material extending along the inclined surface of the first conductive layer on the surface facing away from the first doped layer, and further extending along part of the bottom surface of the first portion of the semiconductor stack to the edges of the sidewalls of the second portion of the semiconductor stack . The dielectric material is further arranged to encapsulate the second portion of the semiconductor stack, covering the vertical sidewalls , and extending along the bottom surface . The dielectric layer comprises a recess in the bottom surface with a cross-sectional area smaller than the cross- sectional area of the bottom surface of the second doped layer . The dielectric material may be a few tens of nm thick and comprises one or more dielectric sublayer . It may include 1₂O₃ or SiO₂ as material , although it is not limited thereto .

A second conductive reflective layer is arranged on the surface of the dielectric layer facing away from the first conductive layer , extending along the inclined sidewalls of the dielectric layer , encapsulating the second portion of the semiconductor stack and the surrounding dielectric layer , and extending along the bottom of the second portion of the semiconductor stack, covering both the dielectric layer and the recess within the dielectric layer . The second conductive reflective layer is electrically isolated by the dielectric layer from the first conductive layer . Furthermore , the second conductive reflective layer is in electrical contact with the second doped semiconductor layer , said electrical contact achieved via the recess in the dielectric layer, and through the at least one conductive layer arranged on the surface of the second doped semiconductor layer facing away from the active layer .

In accordance with the proposed principle , an electrical contact surface is arranged on a surface of the second conductive reflective layer facing away from the dielectric layer and corresponding to the recess in the dielectric layer to provide electrical contact with the second doped semiconductor layer . In some aspects , a second electrical contact is arranged on the bottom surface of the first conductive layer, laterally displaced from the first doped layer, and passing through the dielectric layer, extending vertically such that the bottom surface of the second electrical contact surface is substantially flush with the bottom surface of the first electrical contact surface . A non- conductive fill layer encapsulates the electrical contact surfaces and the structure comprising the semiconductor stack, the conductive layers , and the dielectric layer .

In accordance with the proposed principle , a carrier substrate is provided comprising at least one electrical contact surface corresponding to the first electrical contact surface connected to the second conductive reflective layer, and in some aspects , at least one electrical contact surface corresponding to the second contact surface connected to the first conductive layer . The carrier substrate may comprise a Si-based CMOS or display substrate but is not limited thereto .

The pLED in accordance with the proposed principle substantially enables full spatial isolation of doped layers of individual pLED pixels within an array, while simultaneously enabling electrical contact between array pixels via the laterally extended conductive reflective layer on the top surface of the device . Typical parameters relevant for adj usting and optimizing the light extraction efficiency of the device include , but are not limited to height and angle of the sidewalls of the first portion of the semiconductor stack, outcoupling structures on the emission side , i . e . the surface of the first doped layer facing away from the active layer , any anti-reflective coatings , plens , DBR or optical element , the conductive material on the surface of the second doped layer facing away from the active layer , and the like .

The proposed principle is not limited to a specific material system . Rather , nitrides , phosphides and arsenide-based material systems can be used . Examples for arsenide material systems include GaAs and AlGaAs , nitrides include GaN, and additionally ternary and quarternary systems like AlGaN, InGaN and InAlGaN . Phosphide-based systems may include GaP, InP and A1P as well as InGaP, AlGaP and InAlGaP . The above mentioned first and second doped semiconductor layers may comprise one or more sublayers . The sublayers may comprise different material composition based on the selected system, different doping concentration, doping gradients and may even be undoped in some instances . The sublayers provide a dedicated functionality such as current spreading, current inj ection, to mention a few . The active layer may comprise a multi quantum well structure including a plurality of barrier and quantum well layers . The active layer may be undoped but can also comprise a small doping concentration in some aspects . In some further aspects , the active layer may comprise two cladding layers , which are undoped . The cladding layers reduce or prevent a diffusion of dopants into the active layer , thus reducing aging effects .

In some aspects the doped layers and the active layer may be passivated . Said dielectric may be achieved, for example , through use of KOH and ALD A1₂O₃ or ALD AIN . Both conductive reflective layers may also be isolated using the same dielectric process .

In some aspects , the lateral dimensions of the first portion of the semiconductor stack may be in the range between 700nm and 25pm, particularly in the range between 1pm and 10pm . The angle of inclination of the first portion of the semiconductor stack measured from a horizontal plane may be between 30 ° and 90 ° , particularly between 30 ° and 60 ° . The depth of the first portion of the semiconductor stack may be between 200nm and 3pm, particularly between 500 nm and 1 pm. The depth of the second portion of the semiconductor stack may be in the range between 100 nm and 300 nm, and the lateral dimensions of the second portion of the semiconductor stack may be less than or substantially equal to 1pm, whereby the lateral cross-sectional area of the second portion of the semiconductor stack is smaller than the cross sectional area of the surface of the first portion of the semiconductor stack closest to the active layer .

In some aspects , the top view of the light emission surface of the optoelectronic device may take a circular, hexagonal or square form. In some aspects , the conductive reflective layer in contact with the first doped semiconductor layer may be deposited directly without an intermediate layer of TCO material , such as ITO .

In some further aspects , an additional layer of ITO is arranged on the sidewalls of the first portion of the semiconductor stack between the first doped semiconductor layer and the first conductive layer . The layer of ITO improves the adherence of the conductive reflective layer to the doped semiconductor layer, which is particularly relevant in GaN-based systems , especially in the case of larger dimensioned pLEDs .

In some further aspects , the second conductive reflective surface may be further structured, decreasing or eliminating portions in contact with the inclined surface of the dielectric layer along the sidewalls of the first portion of the semiconductor stack and/or decreasing or eliminating the coverage of the conductive reflective layer along the horizontal bottom surface of the first portion of the semiconductor stack .

In some further aspects , the second conductive reflective layer may be arranged on the surface of the second doped layer facing away from the active layer, with the cross sectional area of the second conductive reflective layer being substantially equal to the cross sectional area of the second doped layer . The dielectric layer may further be arranged to encapsulate the second portion of the semiconductor stack and the second conductive reflective layer , extending along the bottom surface and sidewalls of the second portion of the semiconductor stack, and comprising a recess within the bottom surface to provide electrical contact to the second doped layer . The first conductive layer is furthermore arranged along the vertical surfaces of the dielectric layer facing away from the second portion of the semiconductor stack and extend laterally to cover part of the bottom surface of the first portion of the semiconductor stack, in addition to the inclined sidewalls of the first doped layer of the semiconductor stack . The top surface of the first conductive layer then extends laterally away from the semiconductor stack, with the top surface of the first conductive layer arranged flush with the top surface of the first doped semiconductor layer .

Some aspects of the device in accordance with the proposed principle relate to application of an outcoupling structure to or in the surface of the first doped semiconductor layer to further improve the light extraction efficiency . The outcoupling structure may be adj usted independently of the remaining parts of the optoelectronic device , thus not affecting the internal quantum efficiency in the quantum layer , for example . In some aspects , the outcoupling structure comprises a micro lens . The micro lens can be formed directly from the first doped semiconductor layer . In some aspects , the first doped semiconductor layer may comprise a dedicated sublayer configured to be structured to form the micro lens . In some alternative aspects , the micro lens may be separately formed of a different material and attached to the emission surface of the first doped semiconductor layer . In some aspects , a micro lens is bonded to material of the first doped semiconductor layer . This may, for instance , be achieved by arranging an adhesive layer on the surface of the first doped semiconductor layer, to which a micro lens may be attached . Various forms of micro lens may be applied as outcoupling structures , including but not limited to hemispherical and frustum-based profiles .

Other outcoupling structures may be applied to or on the surface of the first doped semiconductor layer . In some aspects , a periodic structure is etched into the first doped semiconductor layer, the periodic structure optionally forming a photonic crystal . In some other aspects , a grating is applied on the surface of the first doped semiconductor layer, such a grating comprising periodic liner or concentric structures . In some other aspects , the first doped semiconductor layer comprises a roughened surface facing away from the active layer .

In some aspects , the first doped semiconductor layer and the top surface of the first conductive layer may be covered by a protective coating on a surface facing away from the active layer . In some aspects , such a protective coating may comprise an anti-reflective material . In some other aspects , a DBR layer may be applied on the surface of the first doped semiconductor layer facing away from the active layer and optionally on the top surface of the first conductive layer arranged flush with the top surface of the first doped semiconductor layer .

In some aspects , the second portion of the semiconductor stack is characterized by sidewalls inclined at an angle substantially equal to the angle of inclination of the sidewalls of the first portion of the semiconductor stack, such that the sidewalls of the pLED pixel are smooth and continuous , rather than forming a step-like profile .

Some further aspects relate to different schemes for achieving electrical contact with the doped layers , and these will be described hereafter .

In some aspects , a global electrical contact is arranged on the top surface of the first conductive layer , providing electrical contact to the first doped layer, while electrical contact to the second doped layer of individual pixels is achieved via individual metal contacts arranged on the side of the second conductive reflective layer facing away from the second doped layer . Corresponding electrical contacts for each individual pixel are provided within the carrier substrate .

In some further aspects , individual electrical contacts on the lower surface of the first conductive layer , i . e . the surface facing towards the fill layer, are arranged to form electrical contact to the first doped layer of individual pixels . In this aspect , the first conductive layer of each individual pixel is electrically isolated from neighbouring pixels by the dielectric layer . Contact to the second doped semiconductor layer is achieved through individual metal contact surfaces arranged on the surface of the second conductive reflective layer facing away from the active layer .

Some other aspects concern a method of processing an optoelectronic device . The method comprises the steps of providing a semiconductor layer stack on a growth substrate , the semiconductor layer stack comprising a first doped semiconductor layer , a second doped semiconductor layer and an active layer arranged between the first and second doped semiconductor layers . The base material systems of the layer stack can be one of the abovementioned systems based on nitrides , arsenide and phosphides , and combinations thereof . At least one conductive layer is arranged on the surface of the second doped semiconductor layer facing away from the active layer . Said conductive layer may comprise at least one of a transparent conductive oxide , particularly ITO, and/or a third conductive reflective layer, and/or a DBR mirror .

In a subsequent step, a mesa etch is conducted to form and expose sidewalls of the first doped semiconductor layer , the active layer and the second doped semiconductor layer . Portions of the first doped semiconductor layer are covered with a photo resist material , and a second mesa etch is conducted to form the sidewalls of a second portion of the semiconductor layer stack extending from a surface of the second doped semiconductor layer facing away from the active layer to the active layer . In some aspects , the sidewalls of the second portion of the semiconductor stack may extend to a portion of the first doped semiconductor layer adj acent to the active layer .

The second mesa etch provides the sidewalls of the second portion of the semiconductor stack with a straight and substantially perpendicular surface with regard to the surface of the second doped semiconductor layer . The portions of the first doped semiconductor layer that are still covered by a photo resist material are inclined, having an increasing cross-sectional area with increasing distance from the active layer . Hence , the first doped semiconductor layer is characterized by a cross sectional area that generally becomes larger with increasing distance from the active layer .

In accordance with the proposed method, the photo resist material is removed from the surface of the first doped semiconductor layer, and a layer of dielectric material is applied to encapsulate the second portion of the semiconductor stack comprising the second doped layer , the active layer and optionally a portion of the first doped layer . The top surface of the first portion of the semiconductor stack closest to the active layer is also covered by the dielectric material , with a recess provided thereupon to achieve electrical contact with the second doped semiconductor layer . The dielectric material may comprise one of A1₂O₃ and SiO₂ and may be deposited in particular using an atomic layer deposition process .

In an alternative approach a two-step method is utilised . In a first step a first mesa etching process is conducted , the exposed sidewalls are subsequently treated with an etching process to obtain vertical sidewalls . This etching process may depend on the material of the semiconductor layer stack . For nitride material systems based on GaN, InGaN, AlGaN or InAlGaN, KOH etching process can be conducted as such process is highly selective . It has been found that a combination longer etch times and high temperature during the KOH etching process provides a self-aligning and self-limiting etch, resulting in vertical sidewalls .

Optionally a ALD with A12O3 or AIN can be conducted after wet etching to functionalize and passivate the sidewalls of the first etched mesa

In a next step the first mesa may be covered with a photo resist or dielectric material with a rounded shape and a second mesa etch may be conducted resulting in inclined sidewalls . The sidewall angle can be controlled by the photo resist shape and choice of plasma parameters .

In a subsequent step, a first conductive material layer is deposited on the inclined sidewalls of the first doped semiconductor layer , extending laterally to cover the surface of the first doped semiconductor layer around the mesa structure , and facing away from the growth substrate . Then an additional deposition of dielectric material is conducted, extending to cover the conductive reflective material on the inclined sidewalls of the first doped semiconductor layer, and laterally extending to cover the conductive reflective material layer deposited on the surface of the first doped semiconductor layer around the mesa structure .

In accordance with the proposed method, a second conductive reflective material layer is then deposited on the surface of the dielectric layer encapsulating the mesa structure , such that the conductive reflective layer extends on the top surface and vertical sidewalls of the second portion of the semiconductor stack, and further extends along the inclined sidewalls of the first portion of the semiconductor stack .

In a subsequent step according to the proposed method, metal contacts are fabricated for interface to a carrier substrate . One such metal contact is arranged on the top surface of the second conductive reflective material , corresponding to the recess in the dielectric made for achieving electrical contact to the second doped semiconductor layer . A second metal contact is arranged on a surface of the first conductive reflective surface laterally displaced from the semiconductor mesa structure via a recess in the dielectric layer . In this way the second metal contact achieves electrical contact with the first doped semiconductor layer . A non-conductive fill material is thereafter deposited to encapsulate the mesa structure and the metal contacts .

A carrier substrate is prepared for bonding with the layer stack by provision of metal contacts corresponding to the metal contacts arranged on the conductive reflective layers . The carrier substrate may for instance comprise a CMOS substrate or Si-based display substrate . In a subsequent step the layer stack is then bonded to the carrier substrate .

In accordance with the proposed method, the growth substrate is removed, and additionally, portions of the first doped semiconductor layer are removed until a surface of the first conductive reflective layer flush with the first doped semiconductor layer is exposed, in effect ensuring complete isolation of the first doped semiconductor layer in adj acent pixels . This step is crucial in ensuring elimination of crosstalk between adj acent pixels . In some aspects , an additional coating is deposited on the top surfaces of the first doped semiconductor layer and the conductive reflective layer extending laterally from the emission surface of the first doped layer . Such a coating may comprise a protective layer, an anti- reflective layer or a DBR layer .

Some aspects concern the step of providing a semiconductor layer . This step may also comprise depositing a transparent conductive layer and/or a third conductive reflective layer and/or a DBR layer on the surface of the second doped semiconductor layer facing away from the active layer . In some aspects , the transparent conductive layer and/or conductive reflective layer and/or DBR may act as a hard mask for the first and/or second mesa etch . This layer supports current inj ection into the second doped layer but can also be used to somehow restrict the current to a central region . For this purpose , the conductive transparent layer is structured after the first and/or second etch have been conducted . The cross-sectional area of the conductive transparent layer and/or conductive reflective layer and/or DBR layer may be smaller than the cross-sectional area of the second doped layer and the active layer after the structuring process . In some aspects , the cross-sectional area of the conductive transparent layer and/or conductive reflective layer and/or DBR layer may be substantially equal to the cross-sectional area of the second doped layer and the active layer .

In some further aspects , conducting the first mesa etch comprises the steps of depositing and structuring a hard mask layer on the second doped semiconductor layer , whereas surface portions of the second doped semiconductor layer are exposed . Then, an etching process is conducted to remove material of the exposed surface portions . The etching process may be a dry etching process , a wet etching process , or a combination thereof . The type and parameters of the etching process depend on the material systems , design choices and other parameters . In particular , the type and parameters of the etching process are selected to achieve inclined sidewalls in a first step, and to achieve vertical sidewalls substantially perpendicular to the top surface of the second doped layer in a subsequent step . A self-limiting process that stops once a vertical sidewall is reached may be achieved by selection of appropriate etching parameters based on the base system used, the etchant and possibly the crystal plane .

Different materials and several sublayers may be used for the deposited conductive reflective material layers . This may be necessary to ensure formation of a good and low-ohmic resistant interface to the semiconductor layers . Hence , deposition of the conductive reflective layers may comprise a conductive transparent oxide as a sublayer on which the reflective material is deposited . In some other aspects , alloy layers or a plurality of metal sublayers may be used . In some aspects , the deposited conductive material layer comprises one of Ag , Al or Au to form a reflective layer .

Some other aspects concern the step of structuring a light-emitting surface of the first doped semiconductor layer . This step may comprise for instance , forming an outcoupling structure on or in a surface of the first doped semiconductor layer facing away from the active layer . To ensure prevention of crosstalk between adj acent pixels where such outcoupling structures extend vertically from the sidewalls of the first doped semiconductor layer and are thus no longer flush with the top surface of the metal semiconductor layer , any such outcoupling structures of adj acent pLED pixels should be arranged such that they are spatially isolated from each other .

In some aspects , the surface of the first semiconductor layer facing away from the active layer is roughened . In alternative aspects , the surface of the first doped semiconductor layer facing away from the active layer is structured to form a micro lens thereupon . In this aspect , the micro lens may comprise the same base material system as the first doped semiconductor layer . In some other aspects , a specific sublayer may be integrated in the first doped semiconductor layer for the purpose of formation of outcoupling structures , such as a micro lens . In some aspects , the micro lens material is undoped . In some other aspects , the micro lens is separately processed and subsequently deposited on the surface of the first doped semiconductor layer facing away from the active layer . The material of the micro lens may comprise the same base material as the material of the layer stack but may also comprise a different base material . To avoid reflection, it should however have a refractive index that is only slightly different from the refractive index of the material of the surface on which the micro lens is arranged .

In some other aspects , in which the micro lens is processed separately, an adhesive layer is applied on the surface of the first doped semiconductor layer facing away from the active layer . The micro lens is then positioned and attached to the surface of the first doped semiconductor layer . The adhesive should be index-matched to reduce reflections of light generated in the layer stack .

Other than micro lenses , other outcoupling structures are possible . In some aspects , a periodic structure is formed on or in the first doped semiconductor layer , the periodic structure optionally forming a photonic crystal . The periodic structure may be implemented directly into the first doped semiconductor layer, or optionally bonded thereto , or applied using an adhesive .

Several of the above-mentioned structures and surface treatment processes , such as different forms of coatings , may be combined to implement an optimized outcoupling structure . This allows optimization of efficiency of the pLED device .

SHORT DESCRIPTION OF THE DRAWINGS

Further aspects and embodiments in accordance with the proposed principle will become apparent in relation to the various embodiments and examples described in detail in connection with the accompanying drawings in which :

Figure 1 shows an exemplary embodiment of an optoelectronic device in accordance with some aspects of the proposed principle ;

Figures 2 to 4 illustrate some exemplary embodiments of an optoelectronic device in accordance with some aspects of the proposed principle ; Figures 5 to 7 show additional exemplary embodiments of an optoelectronic device in accordance with some aspects of the proposed principle ;

Figures 8A to 8D illustrate exemplary embodiments of an optoelectronic device with various outcoupling structures in accordance with some aspects of the proposed principle ;

Figures 9A to 9C illustrate top view variations of outcoupling structures in accordance with some aspects shown in Figures 8C and 8D;

Figure 10 illustrates additional coating layer options accordance with some aspects of the proposed principle ;

Figures 11A to 11C illustrate some possible electrical contact layout options in accordance with some aspects of the proposed principle ;

Figures 12A to 12 F illustrate steps of a method of processing an optoelectronic device in accordance with some aspects of the proposed principle ;

Figures 13A to 13E illustrate further steps in producing an optoelectronic device in certain aspects according to the proposed principle .

Figures 14A to 14E show an alternative embodiment for a method of processing an optoelectronic device in accordance with some aspects of the proposed principle .

DETAILED DESCRIPTION

The following embodiments and examples disclose various aspects and their combinations according to the proposed principle . The embodiments and examples are not always to scale . Likewise , different elements can be displayed enlarged or reduced in size to emphasize individual aspects . It goes without saying that the individual aspects of the embodiments and examples shown in the figures can be combined with each other without further ado , without this contradicting the principle according to the invention . Some aspects show a regular structure or form . It should be noted that in practice slight differences and deviations from the ideal form may occur without , however , contradicting the inventive idea .

In addition, the individual figures and aspects are not necessarily shown in the correct size , nor do the proportions between individual elements have to be essentially correct . Some aspects are highlighted by showing them enlarged . However , terms such as "above" , "over" , "below" , "under" "larger" , "smaller" and the like are correctly represented with regard to the elements in the figures . So it is possible to deduce such relations between the elements based on the figures .

Figure 1 illustrates an exemplary embodiment of an optoelectronic device with reflective conductive layers deposited along the pixel sidewalls in accordance with the proposed principle .

The optoelectronic device comprises a semiconductor stack 10 , made up of two regions 101 and 102 . The first region of the semiconductor stack 101 comprises a first doped layer 11 and is characterized by inclined sidewalls . The second region of the semiconductor stack 102 comprises part of the first doped layer 11 , an active layer 12 comprising a plurality of quantum wells and quantum barriers , a second doped layer 13 , and a conductive layer, in this aspect comprising a transparent conductive oxide layer 14 . The sidewalls of the second doped region are arranged perpendicular to the top surface of the optoelectronic device . In this aspect of the invention, the TCO layer 14 is structured such that the cross-sectional area of the TCO layer is smaller than the cross-sectional area of the second doped layer 13 and the active layer 12 .

A first conductive layer 151 is arranged along the inclined sidewalls of the first region of the semiconductor stack 101 , further extending laterally beyond the area occupied by the first doped layer 11 . The top surface of the first conductive layer 151 is substantially flush with the top surface of the first doped layer 11 . A dielectric layer 16 is arranged to encapsulate the second portion of the semiconductor stack 102 , part of the surface of the second portion of the semiconductor stack closest to the active layer, and the inclined sidewalls and extended lateral surface of the first conductive layer 151 . A recess in the dielectric layer on a surface adj acent to the bottom surface of the second portion of the dielectric stack 102 allows electrical contact to the second doped layer 13 .

A second conductive reflective layer 152 is arranged on a surface of the dielectric layer 16 such that it is electrically isolated from the first conductive layer 151 by the dielectric layer 16 . The second conductive reflective layer extends along the inclined sidewalls of the first region of the semiconductor stack 101 , arranged on a surface of the dielectric layer facing away from the first conductive layer 151 . The second conductive reflective layer 152 further encapsulates the first region of the semiconductor stack 102 , covering the vertical sidewalls and the bottom surface , and filling in the recess formed in the bottom surface of the dielectric layer .

Metal contacts 18a and 18b are respectively arranged on surfaces of the first and second conductive layers 151 and 152 , providing electrical contact to the first and second doped semiconductor layers respectively . A non-conductive fill material layer 17 is deposited to encapsulate the semiconductor mesa stack and the metal contacts .

A carrier substrate 19 comprising a CMOS substrate or a Si-based display substrate is provided, comprising metal contact surfaces 19a and 19b , corresponding respectively to the metal contact surfaces 18a and 18b connected to the semiconductor stack .

Figure 2 shows an aspect of the proposed device wherein a layer of ITO is deposited on the inclined sidewalls of the first region of the semiconductor stack, arranged between the first doped semiconductor layer 11 and the first conductive layer 151 . The ITO layer serves to enhance adherence of the metal reflective layer to the material of the first doped semiconductor layer during the metal deposition process . Figure 3 shows a further aspect of the proposed device in which the second conductive reflective layer 152 is structured along the inclined sidewalls corresponding to the first region of the semiconductor stack 101 , and optionally along the horizontal bottom surface of the first region of the semiconductor stack . Such structuring may reduce material requirements , and in the case of simultaneous structuring along the diagonal sidewalls and along the bottom surface of the first region of the semiconductor stack, the combination of the dielectric layer 16 and the second conductive reflective layer 152 encapsulating the second region of the semiconductor stack 102 may serve as a resistant mas k during the deposition of the first conductive layer 151 on the sidewalls of the first doped semiconductor layer , which may simplify the production process associated with the optoelectronic device .

Figure 4 shows an alternative aspect of the proposed device , in which the second conductive reflective layer 152 is arranged on the surface of the second doped semiconductor layer 13 facing away from the active layer 12 . In this embodiment , the cross-sectional area of the second conductive reflective layer 152 is substantially equal to the cross- sectional area of the second doped semiconductor layer 13 and the active layer 12 . The first conductive layer 151 is arranged to partially or fully encapsulate the vertical sidewalls of the second region of the semiconductor stack 102 , and extend along part of the bottom surface of the first portion of the semiconductor stack 101 , further extending along the inclined sidewalls of the first doped semiconductor layer 13 , and outwards from the light emitting surface of the semiconductor stack, such that the top surface of the first conductive reflective layer is substantially flush with the surface of the first doped semiconductor layer facing away from the active layer .

Figure 5 illustrates an aspect of the proposed device wherein the ITO layer 14 is not additionally structured subsequent to the formation of the second region of the semiconductor stack, and as such is characterized by a cross sectional area substantially equal to the cross-sectional area of the second doped layer and the active layer . Figure 6 illustrates an alternative aspect of the proposed device wherein the cavity formed in the dielectric layer on the bottom surface of the second region 102 of the semiconductor stack is characterized by a cross-sectional area that is substantially equal to the cross- sectional area of the second doped semiconductor layer and the active layer . In this embodiment , the layer 153 arranged between the second conductive reflective layer and the second doped layer may comprise a transparent conductive oxide , particularly ITO and/or a third conductive reflective layer and/or a DBR mirror .

Figure 7 illustrates a further aspect of the proposed device wherein the sidewalls of the second region 102 of the semiconductor stack are characterized by sidewalls inclined at an angle that is substantially equal to the angle of inclination of the first region 101 of the semiconductor stack, such that the sidewalls form a continuous , smooth, inclined profile rather than a stepped profile . The dielectric layer 16 is structured with a stepped profile along the inclined sidewalls , providing electrical insulation between the first conductive reflective layer 151 and the second conductive reflective layer 152 .

Figures 8A to 8D illustrate aspects of the proposed device comprising optical outcoupling structures for improvement of the light extraction efficiency of the optoelectronic device .

In Figures 8A and 8B , the outcoupling device comprises a micro lens , whereby the profile of the micro lens may take different forms including but not limited to the right frustum-shaped structure 110 illustrated in Figure 8A, or the convex-shaped structure 111 illustrated in Figure 8B .

In some aspects , the micro lens may be an extension of the first doped semiconductor layer, whereby the process of removal of the growth substrate and material forming the first doped layer includes a structuring of the surface of the first doped semiconductor layer facing away from the active layer to form a lens shape extending vertically beyond the top surface of the first conductive reflective layer, rather than forming a flush horizontal top surface . In some embodiments , the micro lens may be formed in a separate process , comprising in some aspects of such embodiments the same material as the first doped layer . In other aspects the micro lens may be formed of different material , and/or may be undoped . In such embodiments whereby the micro lens is formed in a separate process , the outcoupling structure may be attached to the surface of the first doped semiconductor layer facing away from the active layer by means of an adhesive layer arranged between the micro lens and the first doped semiconductor layer .

Figures 8C and 8D show further aspects of the proposed optoelectronic device comprising periodic outcoupling structures on or in the surface of the first doped semiconductor layer, whereby such outcoupling structures may take the form of gratings and/or optionally form photonic crystals .

Figures 9A and 9B illustrate the top view of aspects comprising periodic gratings arranged on the surface of the first doped semiconductor layer, whereby the periodicity may be linear or in the form of concentric structures radiating from a central point respectively . The periodic structures illustrated in such embodiments may be formed via a structuring process during the removal of the growth substrate and excess material from the first doped semiconductor layer or may be separately formed and subsequently bonded to the surface of the first doped semiconductor layer facing away from the active layer . In embodiments involving separate formation of the periodic gratings , the outcoupling structure may comprise the material identical in composition and doping concentration to the first doped semiconductor layer in some aspects , and in alternative aspects , the outcoupling structure may comprise material of different composition and/or different doping concentration, and in some aspects the material comprising the outcoupling structure may be undoped .

Figure 9C illustrates the top view of aspects comprising periodic structures arranged within the top surface of the first doped semiconductor layer . The periodic structures may comprise photonic crystals , and may be produced by structuring of the first doped semiconductor layer during the removal process of the growth substrate and excess material from the first doped semiconductor layer , or may be produced by a combination of material removal and bonding processes , whereby the periodic structures may take the form of cylindrical holes/cavities structured into the first doped semiconductor layer, or alternatively may take the form of cylindrical pillars protruding from a planar surface parallel to the top surface of the first doped semiconductor layer ( not illustrated ) .

Figure 10 illustrates a further aspect according to the proposed principle comprising an additional top layer 20 arranged on the top surface of the first doped semiconductor layer 11 and the first conductive layer 151 . The additional top layer may comprise at least one of a protective coating , an anti-reflective coating and/or a DBR layer .

Figures 11A to 11C illustrate alternative electrical contact schemes in accordance with certain aspects of the proposed optoelectronic device .

Figure 11A illustrates some aspects of the proposed device , wherein one global metal contact is arranged on the top surface of the first conductive reflective layer . In this embodiment the top surface of the first conductive reflective layer forms a common contact surface for a plurality of pLED pixels deposited on a common substrate . An alternative implementation of this embodiment is achieved by direct use of an exposed part of the top surface of the first conductive reflective layer as a common global contact to the first doped semiconductor layers of the plurality of pixels deposited on the substrate , thereby not necessitating a separate metal contact . Furthermore , in this embodiment the connection to the second doped semiconductor layer is achieved by means of individual metal contacts 18b arranged on the second conductive reflective layer of each pLED pixel and bonded to corresponding metal contacts 19b arranged on the surface of the carrier substrate layer 19 . Figure 11B illustrates further aspects of the proposed device , whereby at least one global metal contact 18a is arranged in contact with a surface of the first conductive reflective layer facing the non- conductive fill layer 17 , and laterally displaced from the semiconductor stacks . The at least one global metal contact is connected to a corresponding global electrical contact 19a in the carrier substrate , penetrating through the dielectric layer 16 and the non-conductive fill layer 17 . Furthermore , in this embodiment each individual pLED pixel comprises an individual metal contact 18b arranged in contact with the second conductive reflective layer thereof , with the individual metal contacts bonded to corresponding individual metal contacts 19b within the carrier substrate 19 .

Figure 11C illustrates alternative aspects of the proposed device , whereby the first conductive reflective layers of individual pLED pixels are electrically isolated from each other by the structured dielectric layer 16 and the non-conductive fill layer 17 . In this embodiment , each individual pLED pixel comprises two metal contacts . A first metal contact 18a is arranged on a surface of the first conductive reflective layer facing the fill layer 17 via an opening in the dielectric layer 16 , further penetrating the non-conductive fill layer to make electrical contact with a corresponding individual metal contact 19a arranged on the surface of the carrier substrate 19 . The first metal contact is laterally displaced from the semiconductor stack . A second metal contact is arranged on a surface of the second conductive reflective layer facing away from the active layer , corresponding to the bottom surface of the second region of the semiconductor stack . This second metal contact 18b is similarly bonded to a corresponding individual contact 19b arranged on the surface of the carrier substrate 19 .

Figures 12A to 12 F illustrate initial steps in a method for producing the proposed optoelectronic device in accordance with certain aspects of the proposed principle .

In Figure 12A, a growth substrate 30 is provided, on which a first doped semiconductor layer 11 and a second doped semiconductor layer 13 are deposited, with an active layer 12 arranged between the two doped semiconductor layers . The growth substrate may comprise different materials depending on the material system used for the semiconductor layer stack . In the illustrated aspect , the growth substrate 30 comprises sapphire or silicon, for growing a nitride-based semiconductor stack . The growth substrate may additionally include different circuitry to connect and supply the pLED attached thereto . Furthermore , an undoped buffer layer ( not illustrated) may be deposited on the surface of the growth substrate for provision of a smooth and defect-free surface on which the subsequent semiconductor layers may be epitaxially grown .

The semiconductor layers may comprise a material system based on nitrides , phosphides , or arsenide . In the illustrated example , the semiconductor layer material is based on the nitride system, in particular GaN . In this regard the doped semiconductor layers 11 and 13 may comprise a plurality of sublayers , not illustrated herein . The various sublayers may comprise identical or various different doping concentrations , dopant gradients or even undoped layers based on intended functionality .

The active region 12 is deposited on the top surface of the first doped layer 11 and comprises a multi quantum well structure , comprising a plurality of alternating quantum well layers and barrier layers . The barrier layers and quantum well layers are often undoped . The active layer 12 may further comprise two cladding layers , arranged between the active layer 12 and the doped semiconductor layers 11 and 13 respectively . The cladding layers serve to prevent dopant diffusion from the doped layers 11 and 13 into the multi quantum well structure forming the active layer 12 .

An optional transparent conductive oxide layer 14 may be deposited on the surface of the second doped semiconductor layer facing away from the active layer .

Figure 12B illustrates a subsequent step whereby a structured photo resist layer 40 is arranged on the top surface of the deposited semiconductor layer stack and optional transparent conductive oxide layer . The resist material is shaped with a goal of achieving a specific resist shape , which when used in combination with specific etching processes , in particular a plasma etching process , results in inclined sidewalls with a desired angle .

Figure 12C illustrates a subsequent step in a method according to the proposed principle , whereby material is removed from layers 11 , 12 , 13 and 14 by means of an etching process . The inclined sidewalls comprise an adj ustable angle a which is adj ustable and dependent on the shaping of the photo resist layer 40 as previously described in a prior step . The height of the etch may be adj usted based on etching time , etching concentration as well as other parameters . The width of the etched cone comprises a diameter substantially corresponding to the surface covered by the photoresist layer 40 .

In a subsequent step, a second photo-resist layer 50 is deposited to cover the etched semiconductor layer stack . Due to the conical structure of the semiconductor layer stack, subsequent smoothing , and planarization processes such as mechanical grinding may be required to form an ideal flat planar surface , as illustrated in Figure 12D .

The photo-resist layer is removed in the next step via an etching process to expose the optional transparent conductive oxide layer 14 , the second doped semiconductor layer 13 and the active layer 12 , with the results illustrated in Figure 12E . The etch depth of the resist is crucial in defining the shape of the pixel and is therefore an important design parameter . The etching process is designed to ensure that the active quantum well region is exposed during the etching of the second photo resist layer 50 . A portion of the first doped semiconductor layer 11 may be exposed during this etching step . The etching process may be achieved by any plasma etching or plasma processing which is characterized by an etch rate of the resist layer significantly greater than the etch rate of the transparent conductive oxide layer 14 and the material forming the doped semiconductor layers and the active layer, for example 0₂-plasma, which stops on ITO and GaN, but achieves etch rates in the range of 100 ' s nm/min in photo resist . A second mesa etching process is performed for structuring of the exposed semiconductor stack layers corresponding to the second region 102 of the semiconductor stack, resulting in substantially vertical sidewalls as illustrated in Figure 12 F .

For nitride-based systems , KOH etching is typically performed for defect removal and surface dielectric . Use of KOH etching on GaN systems is self-limiting in the lateral direction, resulting in vertical sidewalls . In some aspects , a concentration of KOH in the range between 10% and 40% in combination with a high temperature in the range between 40 ° C and 90 ° C may be used . Due to lateral self-limitation, the material on the sidewalls is removed until substantially vertical sidewalls are achieved . Etching in the vertical direction stops at the surface of the photo-resist material . Other suitable etchant materials like H3PO4 , H2 SO5 , NH3 , either alone or combined in a sequence of etching steps may be used . The photo resist material 50 must in any case be resistant to the selected chemical etchants . The photo resist material is removed in a subsequent step in preparation for further processing steps in accordance with aspects of the proposed principle .

In some aspects of the proposed method, a dielectric layer is deposited to encapsulate the second region of the semiconductor stack comprising an optional TOO layer 14 , the second doped semiconductor layer 13 , the active layer 12 and optionally a portion of the first doped semiconductor layer 11 closest in proximity to the active layer . The dielectric layer may be laterally extended along the top surface of the first region 101 of the semiconductor stack to cover a horizontal surface of the first doped layer 11 parallel to and facing away from the growth layer 30 . A first conductive reflective layer 151 is deposited on the exposed surfaces , comprising the inclined sidewalls of the first doped layer 11 and extending laterally to cover portions of doped material adj acent to the pixel mesa structures . In some aspects a layer of transparent conductive oxide may be deposited on the first doped semiconductor layer prior to deposition of the conductive reflective metal layer to promote adherence and electrical conductivity between the metal and semiconductor layers . In a subsequent step , additional dielectric material is deposited on the surface of the first conductive reflective layer, resulting in a continuous dielectric layer 16 encapsulating the first and second regions of the semiconductor stack, and laterally covering the first conductive reflective layer in the surface extending beyond the pixel mesa structures . A recess is made in the dielectric material on a horizontal surface of the second region 102 of the semiconductor stack facing away from the active region 12 . A second conductive reflective layer 152 is deposited in a subsequent step , encapsulating the first region 102 of the semiconductor stack, and extending along a horizontal surface of the first region of the semiconductor stack closest to the active layer 12 , and additionally along the inclined sidewalls of the first region 101 of the semiconductor stack . The second conductive reflective layer fills and covers the recess in the dielectric layer , allowing electrical contact with the second doped semiconductor layer 13 . The first and second conductive reflective layers are electrically isolated by the dielectric layer 16 . Figure 13A shows the resultant pixel structure .

A further processing step in accordance with the proposed principle involves provision of metal contacts 18a and 18b electrically connected to the first and second doped layers 11 and 13 respectively via the first and second conductive layers 151 and 152 . In some aspects of the proposed method, a first metal contact 18a is deposited on a surface of the first conductive layer 151 facing away from the growth substrate 30 , and laterally displaced from the pixel mesa structure . The first metal contact 18a is arranged to penetrate through the dielectric layer 16 . A second metal contact 18b is deposited on a horizontal surface of the second conductive reflective metal corresponding to the recess in the dielectric material created to provide electrical contact to the second doped semiconductor layer 13 . A non-conductive fill material 17 is deposited to encapsulate the pixel mesa structure and the metal contacts , leaving surfaces of the metal contacts 18a and 18b exposed to provide electrical contact to the pLED pixel . Figure 13B shows the result of this process step . In a subsequent processing step illustrated in Figure 13C, a carrier substrate comprising metal contact surfaces 19a and 19b , corresponding to the metal contact surfaces 18a and 18b of the pLED pixel is provided, and the pLED structure is bonded to the carrier substrate . The bonded pixel complete with electrical contact to the carrier substrate is illustrated in Figure 13D .

Figure 13E shows some aspects of the proposed methods , wherein a surface coating layer is deposited in a final processing step . The surface coating layer may comprise a protective layer whose material is dependent on required functionality and/or an anti-reflective layer and/or a DBR layer . In further aspects , not illustrated herein, the surface of the first doped semiconductor layer may be subj ected to additional processing to achieve optical coupling structures in the form of gratings , photonic crystals , micro lenses , or surface roughening . Such optical coupling structures may alternatively be processed separately and bonded to the surface of the first doped semiconductor layer by means of appropriate bonding processes or suitable adhesive materials .

Another aspect related to a processing method for an optoelectronic device according to the proposed principle is shown in Figures 14A to 14E . A first mesa etch is conducted on a semiconductor stack comprising two doped semiconductor layers , an active layer arranged between the two doped semiconductor layers and an optional transparent conductive layer to produce a portion 102 of the semiconductor stack comprising vertical sidewalls . The etch comprises the steps of depositing a patterned photoresist layer on the semiconductor stack, after which a dry etching process is conducted on the patterned semiconductor stack . The depth of the first etch is controlled to produce a first portion of the semiconductor stack comprising the second doped layer, the active layer , the optional transparent conductive layer and optionally, part of the first doped layer adj acent to the active layer . Then the first photoresist layer ( not shown ) is removed and a wet etching step is conducted on the first portion of the semiconductor stack resulting in substantially vertical sidewalls . For nitride systems , the etchant may comprise KOH, which allows a highly selective etch only laterally and self-limiting in vertical sidewalls given by the ITO size and by proper choice of etching parameters .

Optionally ( not shown ) a ALD with A12O3 or AIN can be conducted after wet etching to functionalize and passivate the sidewalls of the portion 102 of the semiconductor layer stack .

In a subsequent step, shown in Figure 14B a second photoresist layer 50 is deposited to encapsulate the previously etched portion 102 of the semiconductor stack . It has a cross section larger than the previously portion 102 of the semiconductor layer stack . A subsequent etching process is conducted, said etching process selected to produce inclined sidewalls in a portion 101 of the semiconductor stack ( and optional a dielectric layer on top if deposited ) . Etching depth and sidewall angle of inclination are dependent on selected etching parameters . At the end of the etching process the portion 102 of the semiconductor layer stack is still encapsulated .

Figure 14C shows a further step in the processing of an electronic device in accordance with the proposed principle . In this step, the first conductive layer 151 is deposited using the previously deposited photoresist mask 50 . The conductive layer 151 is arranged so as to cover at least the inclined sidewalls of the portion 101 of the semiconductor stack and further extends laterally at a substantially horizontal surface of the first doped layer substantially parallel to and facing away from the growth substrate 30 , said horizontal surface vertically displaced from the portion 101 of the semiconductor stack at a distance corresponding to the depth of the second mesa etch .

The photoresist layer is removed in a further step, shown in Figure 14D . In some aspects of the proposed method, the conductive layer 14 may be further etched to achieve a lateral cross-sectional area smaller than the lateral cross-sectional area of the second doped layer 13 and the active layer 12 .

A subsequent step shown in Figure 14E comprises depositing of a dielectric layer 16 encapsulating the semiconductor stack and the first conductive layer 151 . The dielectric layer extends laterally away from the mesa stack to cover portions of the first doped layer surrounding the mesa stack . A recess is provided within the dielectric layer to allow electrical contact to the second doped layer 13 and the optional transparent conductive layer 14 . A second conductive layer 152 is then deposited on a surface of the dielectric layer facing away from the deposited semiconductor stack to encapsulate the semiconductor stack portions 101 and 102 , and to occupy the recess produced in the dielectric layer for provision of electrical contact to the second doped layer 13 .

In subsequent processing steps , not illustrated herein, the growth substrate 30 and part of the first doped layer 11 are removed, whereby the removal of the first doped layer is such that a surface of the previously deposited first conductive layer 151 facing away from the dielectric layer is exposed . Provision of metal contact surfaces and bonding to a carrier substrate may then be conducted-

Additional processing steps not illustrated may comprise deposition of additional layers on the lateral surface of the processed stack facing away from the active layer, depending on desired characteristics . Such layers may include , but are not limited to protective coatings , antiref lective layers , DBR layers , and so on . In other aspects , the light emitting surface of the first doped layer may be subj ected to further processes to achieve desired optical output characteristics . Such processes may include , but are not limited to roughening of the emission surface , and integration of coupling structures such as lenses , photonic crystals and gratings .

LIST OF REFERENCES semiconductor device semiconductor stack 1 first region of semiconductor stack2 second region of semiconductor stack first doped layer active layer (multi-quantum well ) second doped layer transparent conductive oxide layer1 first conductive layer 2 second reflective conductive layer3 third conductive layer dielectric layer fill layer a , 18b metal contact on device a , 19b metal contact in substrate surface coating layer epitaxial growth substrate first photo resist layer second photo resist layer

Claims

1 . Optoelectronic device , in particular a pLED comprising : a semiconductor stack comprising : o a first region comprising a first doped layer ; and o a second region comprising a second doped layer, an active layer arranged between the first and second doped layers , and optionally part of the first doped layer; a first conductive layer in contact with sidewalls of the first region of the semiconductor stack, and extending laterally beyond the sidewalls of the first doped layer, wherein the top surface of the first conductive layer lies substantially flush with the top surface of the first doped layer; a structured dielectric layer arranged to encapsulate the first region of the semiconductor stack and extending laterally to cover a bottom surface of the second region of the semiconductor stack, further extending to cover an outer surface of the first conductive layer; wherein the outer surface refers to a surface facing away from the sidewalls of the first region of the semiconductor stack; a second conductive reflective layer in contact with the structured dielectric layer , arranged to encapsulate the second region of the semiconductor stack thereby contacting the second doped layer, and optionally extending along a portion of the structured dielectric layer over the outer surface of the first conductive layer; a carrier substrate comprising at least one electrical contact surface at a position corresponding to at least one electrical contact arranged on the surface of the second conductive reflective layer, wherein the first and second conductive layers are electrically isolated from each other by the dielectric layer .

2 . Device according to claim 1 , wherein the sidewalls of the first region of the semiconductor stack are inclined such that the surface of the first doped layer facing away from the active layer is characterized by a larger cross-sectional area than the surface of the first doped layer in contact with the active region, and wherein the sidewalls of the second region of the semiconductor stack are perpendicular .

3 . Device according to any of the preceding claims , wherein the first conductive layer comprises a reflective metal or a reflective metal layer stack; and/or wherein the second conductive reflective layer comprise a reflective metal layer or a reflective metal layer stack .

4 . Device according to any of the preceding claims , comprising a layer between the second doped layer and the second conductive reflective layer , wherein the layer between the second doped layer and the second reflective layer comprises a transparent conductive layer , in particular ITO , and/or a third conductive reflective layer , and/or a distributed Bragg reflector ( DBR) layer .

5 . Device according to any of the preceding claims , wherein the cross- sectional area of the second region of the semiconductor stack is smaller than the cross-sectional area of the first region of the semiconductor stack .

6 . Device according to any of the preceding claims , wherein the cross- sectional area of the first region of the semiconductor stack taken at the surface of the first region in closest proximity to the active layer is substantially equal to the cross-sectional area of the second region of the semiconductor stack, taken at the surface of the second region in closest proximity to the active layer .

7 . Device according to claim 4 , wherein the lateral cross-sectional area of a layer between the second doped layer and the second conductive reflective layer is smaller than the lateral cross- sectional area of the second doped layer .

8 . Device according to claim 4 , wherein the lateral cross-sectional area of a layer between the second doped layer and the second conductive reflective layer is substantially equal to the lateral cross-sectional area of the second doped layer .

9 . Device according to any of the preceding claims , wherein the carrier substrate comprises one or more complementary metal oxide semiconductor ( CMOS ) devices .

10 . Device according to any of the preceding claims , comprising an electrical contact connecting the first conductive layer and an n- contact on the carrier substrate .

11 . Device according to any of the preceding claims , further comprising a global n-contact being in contact with the first conductive layer , wherein the global contact is arranged on at least one of :

- the top surface of the first conductive layer, corresponding to the surface of the first conductive layer facing away from the dielectric layer; and/or

- the lower surface of the first conductive layer, corresponding to the surface of the first conductive layer closest to the dielectric layer , with the global contact penetrating through the dielectric layer and the fill material , and making electrical contact with at least one electrical contact surface arranged within the carrier substrate .

12 . Device according to any of the preceding claims , wherein the at least one electrical contact in the carrier substrate is a p-contact surface .

13 . Device according to claim 12 , wherein the carrier substrate further comprises at least one of : a global n-contact ; and/or a plurality of n-contacts corresponding in number to a plurality of optoelectronic devices arranged in an array .

14 . Device according to any of the preceding claims , wherein the top surface of the first doped layer comprises an outcoupling structure , wherein the outcoupling structure comprises the shape and/or form of at least one of : a right frustum; a spherical dome , in particular , a hemisphere ; a grating with horizontal grooves ; and a grating with concentric circular groves or cylindrical cavitations / indentations a periodic surface structure , in particular a photonic crystal .

15 . Device according to any of the preceding claims , wherein an outcoupling structure arranged on the top surface of the first doped layer comprises a micro lens , said micro lens bonded to the light emitting surface of the first doped layer or structured in the first doped layer .

16 . Device according to any of the preceding claims , wherein the top surface of the device is covered by a layer comprising at least one of a protective coating or an antiref lective coating or a distributed Bragg reflector ( DBR) .

17 . Device according to any of the preceding claims , comprising a transparent conductive layer on portions of the first reflective layer covering the sidewalls of the first doped layer .

18 . Method of processing an optoelectronic device , comprising

- Providing a functional pLED stack in a series of steps comprising : o providing a growth substrate comprising sapphire or silicon, o depositing a first doped layer on the growth substrate , o depositing an active region along the growth direction, o depositing a second doped layer on the active region along the growth direction, and o depositing at least one conductive layer on the second doped layer;

- Structuring of the functional LED stack and conductive layer to form sidewalls ;

- Depositing a photo resist covering the conductive layer , the second doped layer, the active region and the top surface of the first doped layer; - Depositing a first conductive layer on the exposed side walls of the first doped layer;

- Removal of the photo resist and depositing a dielectric layer on the first conductive layer, the exposed sidewalls of the active region, the second doped layer and the at least one conductive layer on the second doped layer , and on the surface of the at least one conductive layer facing away from the second doped layer;

- Creating an opening in the dielectric layer to expose the top surface of the pLED stack;

- Depositing a second reflective layer on the dielectric layer ;

- Fabrication of electrical n- and p-contacts connected respectively to the first and second conductive layers ;

- Depositing a fill layer encapsulating the pLED stack and the electrical contacts ;

- Bonding the pLED device to a Si-carrier ;

- Removal of growth substrate and first doped layer such that the sidewalls of the first doped layer do not extend laterally beyond the first conductive layer .

19 . Method according to claim 18 , wherein the step of Structuring of the functional LED stack and conductive layer to form sidewalls comprises the steps of :

Providing a structured hard mas k on the conductive layer ;

Conducting a first mesa etch to form sidewalls of functional LED stack and conductive layer;

Treating the conductive layer , the second doped layer and the active region such as to comprise vertical sidewalls , in particular using a KOH process .

20 . Method according to claim 18 or 19 , wherein the doped layers comprise one of GaN, InGaN, AlGaN and AlInGaN .

21 . Method according to claims 18 to 20 , wherein the n-contact connected to the first reflective layer is positioned on a top surface of the first reflective layer .

22 . Method according to claims 18 to 21 , wherein the n-contact connected to the first reflective layer is positioned on a bottom surface of the first reflective layer , passing through the dielectric layer and the fill layer .

23 . Method according to any of the preceding claims , wherein at least one of a protective coating or an anti-reflective coating or a DBR layer is deposited on the top surfaces of the first doped layer and the first conductive layer .