WO2025119434A2 - Method for inspecting a semiconductor sample using a secondary-ion mass spectrometer with a focused ion beam, and analysis device for this purpose - Google Patents

Abstract

The invention relates to a method for inspecting a semiconductor sample (30) using a secondary-ion mass spectrometer (SIMS) with a material-removing focused ion beam (13), having the following steps: - positioning the semiconductor sample (30) on a sample stage (20); - carrying out an analysis scan by irradiating a region-of-interest (ROI) (31) in a semiconductor structure (36) on the semiconductor sample (30) with the ion beam (13); - registering the secondary ions in a mass spectrometer unit (17) in order to generate an electronic image (41) and/or other data set for characterizing the semiconductor structure (36) in the region of the irradiated ROI (31); - using a semiconductor sample (30), with a semiconductor structure (36) and at least one positioning marking (33, 34, 35), and a sample stage (20) which can be moved in at least two dimensions relative to the ion beam (13); - providing navigation data for the semiconductor sample (30) with the semiconductor structure (36) and the positioning marking (33, 34, 35); - carrying out a preliminary scan by means of a data-based navigation to a position marking (33, 34, 35) and irradiating the region of the semiconductor sample (30) with the ion beam (13) using a large scanning region; - adjusting an internal coordinate system for the sample stage (20) by comparing the position of the position marking (33, 34, 35) on the sample stage (20), said position being derived from the navigation data, with the position ascertained by the preliminary scan; - positioning the ion beam (13) over the ROI (31) to be analyzed by means of a data-based navigation of the sample stage (20) and/or laterally deflecting the ion beam (13) using the navigation data; and - carrying out a SIMS analysis scan using a scanning region which is reduced in comparison to the preliminary scan.

Description

Method for analyzing a semiconductor sample using a secondary ion mass spectrometer with a focused ion beam and analysis device therefor

Technical field

The invention relates to an examination method for a semiconductor sample by means of a secondary ion mass spectrometer with a focused ion beam having the features of the preamble of claim 1 and to an analysis device therefor having the features of the preamble of claim 13.

State of the art

Manufacturing multiple devices at wafer scale presents several significant challenges, many of which are related to the delicate and precise nature of quantum devices and targeted technologies. These challenges include:

- Uniformity and consistency: Devices require precise control of materials and manufacturing processes. Achieving uniformity and consistency across all devices on a wafer is critical to their reliable operation. Variations in materials, dimensions, or processing steps can lead to chip-to-chip variations.

- Manufacturing tolerances: Components often require manufacturing at the nanoscale with extremely tight tolerances. Achieving these tolerances across a large wafer can be technically challenging and require special manufacturing techniques.

- Cost: Scaling up production to the wafer level can be expensive due to the need for specialized equipment and cleanroom facilities. Cost-effective device manufacturing methods are a constant challenge.

The research and fabrication of quantum devices is a promising field in which both academic groups and industrial companies are already active. Some specific challenges for this new application include:

- Error correction: Quantum error correction is a critical aspect of quantum computing. With multiple devices on a wafer, error correction becomes more complex, as errors in one device can affect neighboring devices. Developing error correction strategies that are both effective and scalable is an important task.

- Integration of components: Quantum devices can consist of multiple components, such as qubits, control electronics, and readout systems. Seamlessly integrating these components on a single wafer while maintaining their functionality is challenging.

- Testing and calibration: Each quantum device must be individually tested, calibrated, and characterized to ensure it meets performance specifications. This becomes increasingly time- and resource-intensive the larger the number of devices on a wafer.

- Noise: Quantum devices are sensitive to noise, including temperature fluctuations and electromagnetic radiation. Controlling and shielding these sources of interference is challenging when multiple devices are densely packed on a wafer. - Qubit crosstalk: In quantum computing, qubits (quantum bits) should ideally not interact with each other unless they are intentionally coupled. On a wafer with multiple qubits, preventing unintentional interactions, or crosstalk, between neighboring qubits is a major challenge.

- Scalability: As the number of quantum devices on a wafer increases, so does the complexity of the control and readout systems. Scaling quantum technologies to accommodate many devices on a single wafer without compromising performance represents a major technical challenge.

Addressing these challenges requires a combination of advanced materials science, manufacturing techniques, error correction strategies, and system integration approaches.

Secondary ion mass spectrometry (SIMS) is a powerful analytical technique for investigating semiconductor structures, especially during failure analysis during the manufacturing process. SIMS provides detailed information about the composition, structure, and distribution of elements and isotopes on the surface and, in this context, within semiconductor materials. The most important applications for SIMS in the semiconductor industry are:

- Process control and quality assurance: SIMS is used for process control in semiconductor manufacturing. It helps ensure the consistency and quality of thin-film deposition, ion implantation, etching, and other processes by analyzing the elemental composition of materials at various process steps. This helps identify deviations or impurities that could affect the performance of the final product.

- Defect analysis: SIMS is very useful for identifying and characterizing defects in semiconductor materials and devices. It can detect tiny traces of contaminants or foreign materials that can cause defects in integrated circuits (ICs). This is critical for improving yield and reliability.

- Depth Profiling: SIMS is particularly well-suited for depth profiling, which allows semiconductor manufacturers to determine the distribution of dopants, impurities, and other materials within the various layers of semiconductor devices. This information is essential for optimizing chip performance and reliability.

- Elemental mapping: SIMS can create elemental maps that show the spatial distribution of different elements on a semiconductor surface. This is valuable for identifying patterns, variations, and material interactions that are critical for process optimization and device performance.

- Materials research and development: SIMS is used in research and development to develop new materials and processes for semiconductor manufacturing. Researchers can use SIMS to understand the behavior of materials at the atomic and molecular level, which is essential for the development and improvement of semiconductor technologies.

- Thin-film characterization: SIMS is widely used to characterize the composition of thin films and multilayer structures in semiconductor devices. This is important for optimizing the properties of these materials for specific applications.

- Ion implantation monitoring: SIMS can be used to monitor the success and accuracy of ion implantation processes, which are essential for creating specific doping profiles in semiconductor materials.

- Trace element analysis: SIMS can detect trace elements and impurities in semiconductor materials. Even small amounts of impurities can affect the performance of components, which is why accurate detection with high sensitivity is crucial.

Typically, the area to be analyzed on the semiconductor sample is first located while using the SIMS and the actual examination is then carried out by remaining in this area.

A disadvantage of using SIMS to examine thin-film semiconductor topographies is that each irradiation process reduces the semiconductor structure to an extent that is relevant in relation to the original structure thickness. While conventional semiconductor structures with a typical layer thickness of >1 00nm retain electrical functionality despite structural loss caused by one or more SIMS analysis processes, this is not the case with modern thin-film structures with a thickness of 25nm and less. With each SIMS analysis process, structural loss and primary ion implantation occur in an irradiated area. These losses are so significant that - depending on the grid density - electrical functionality is no longer guaranteed after just a few passes, or fault detection cannot be continued using the same wafer.

Even if the semiconductor structure's functionality is no longer required after analysis, material removal is detrimental, for example, in an analysis for three-dimensional structural elucidation, which is becoming increasingly important for modern semiconductor structures with multiple layers. In this case, it may no longer be possible to determine whether a surface defect was already present during manufacturing or was only introduced by preliminary scans with the focused ion beam.

Further disadvantages of this approach may be that modern dense semiconductor structures cannot be analyzed precisely enough, that approaching the desired target region requires manual intervention and is therefore hardly reproducible by machine, and that no reliable Data correlation with other data sources, such as optical or electron microscopic images, is possible.

Task

The object of the invention is therefore in particular to improve an examination method for a semiconductor sample by means of a secondary ion mass spectrometer (SIMS) with a focused ion beam (FIB) in such a way that the structural loss or the primary ion implantation on the semiconductor sample is reduced, so that a larger number of examination runs for testing several ROI on the same semiconductor sample is possible, wherein the electrical functionality of the semiconductor structure is preferably maintained, and largely automatic and well reproducible analyses are made possible.

Solution

These objects are achieved by an examination method for a semiconductor sample having the features of claim 1.

The basic idea of the invention is to first specifically approach the target region in the semiconductor structure that is of interest for the examination (so-called region of interest, ROI) using navigation data obtained in advance that relate to the semiconductor structure, and to expose the semiconductor structure to the focused ion beam only in the approached ROI.

Whenever reference is made to an "ion beam," this always refers to a "focused ion beam" (FIB), which is known as a means of surface analysis using emitted ions, usually gallium or helium. The ion beam is focused to a point using electrostatic and magnetic lenses and scanned line by line across the surface. Secondary electrons emerge from the surface, which are detected and create an image of the surface. However, this always involves ablation of the structure to be analyzed. According to the invention, this unavoidable ablation is shifted to regions located outside the semiconductor structure to be analyzed.

Put simply, according to the invention, the sample stage is initially moved using only navigation data so that the focused ion beam can initially be applied to a region of the sample that does not require precise analysis. There, an existing or specially added, clearly visible mark is irradiated with the focused ion beam in order to make a correction using the target position derived from the navigation data and the actual position determined during material removal. The mark can be a characteristic structural feature within the semiconductor structure to be analyzed, for example, an angle or an intersection point.

The testing method presented here is particularly suitable for samples from semiconductor production (e.g. CMOS, compound semiconductors, etc.).

The term “semiconductor” in the sense of the present invention also includes structures made of materials which are not semiconducting in the physical-electrical sense, but which are applied to similar substrates using similar manufacturing methods as in semiconductor production and with similar layer thicknesses and structure sizes.

However, the method also applies to other samples for which precise navigation data are available, such as rock samples that have been previously examined using an SEM or light microscope. In the following, the term "semiconductor sample" will be used only for generalization purposes.

"Semiconductor samples" in the sense of the invention refer to complete wafers containing multiple dies, to a sequence of multiple dies, or to a single die on a substrate. The method thus relates to the examination of semiconductor structures regardless of their Size and arrangement. Preferably, only one wafer or other substrate is placed in the sample chamber.

If several semiconductor samples on several wafers or on other separate substrates are to be introduced into the sample chamber together and examined, the examination method of the invention can be applied several times, for each substrate individually.

At the end of the process, an electronic image comparable to an SEM image and/or another data set should be obtained that is suitable for characterizing the semiconductor structure in the area of the irradiated ROI. This can, for example, also include measurement results that detect contamination with foreign atoms.

The image can be an image obtained from the secondary electron emissions, visible to the human eye, which is comparable to an image taken by a scanning electron microscope.

Other data sets that can be acquired include point spectra, line spectra, or image spectra. If point, line, or image spectra are recorded, a complete spectrum is available for each pixel. The data formats used for this are usually proprietary to the manufacturer, and the data volume is large. Alternatively, one can choose to record only scalar values, such as the sum of a copper signal, per pixel. This can produce an image with a false color representation in .bmp or .tif format. In this case, the data volume is significantly smaller, yet, in the example mentioned, a measure of the copper distribution can still be obtained.

While spectra are usually recorded in OD, 1D, and 2D on the X,Y surface—that is, as a point, line, or image spectrum—one can alternatively focus the ion beam on a single point for a longer period of time. The sputtering effect causes the beam to "burrow" into the depth of the sample. A depth profile in the Z direction is then obtained for this X,Y point. Such ablation with the aim of obtaining a depth profile can be achieved according to the invention not only selectively, but also by tracing a path in the plane, in that by repeatedly executing the analysis scan with the same navigation data at least one upper semiconductor layer is partially ablated and an examination is made possible in a further semiconductor layer located below the partially ablated semiconductor layer.

Accordingly, an “other data set” within the meaning of the present invention includes point spectra, line spectra and/or image spectra and/or images showing the distribution of a single element and/or a depth profile reflecting the distribution of an element in the Z direction.

Navigation data for the semiconductor sample can be obtained from:

- CAD data, such as GDS II files,

- Position lists, e.g. KLARF files to indicate previously detected defects of the semiconductor structure or

- other image data previously acquired using non-destructive analysis methods, such as light microscopy, which are suitable for orientation and precise localization of the ROI on the sample.

In the context of the present invention, “data-based navigation” means that reproducible data relating to geometric features of the semiconductor structure on the semiconductor sample are obtained before the region of interest is approached and the ion beam directed at any location on the semiconductor structure is switched on.

The targeted approach to the target region is made possible, on the one hand, by placing the semiconductor sample with the semiconductor structure to be examined on a very precisely movable sample stage, such as a so-called laser interferometer stage. On the other hand, the invention provides for the semiconductor sample to be positioned with one or more separately mounted on the substrate formed positioning marks outside the semiconductor structure to be examined or to select characteristic geometric points within the semiconductor structure at which multiple irradiation with the ion beam is possible.

“Positioning marks” within the meaning of the present invention are therefore all reliably detectable points on the substrate of the semiconductor sample which are formed in addition to the semiconductor structure or which are selected within the semiconductor structure and for which multiple irradiation is possible without disadvantages.

If there are more than two positioning marks, they are arranged in such a way that they do not all lie on a straight line and are therefore suitable as reference points in a 2D coordinate system.

It is also possible that no dedicated marks outside the semiconductor structure are used as positioning marks, but that characteristic structures within the semiconductor structure, or for example the lower left corner of a chip that is repeated several times on a wafer, are selected for this purpose.

At the beginning of the analysis process, the area on the semiconductor sample containing at least one positioning mark is positioned under the ion beam based on a target value. The target value is calculated from the navigation data used to prepare the semiconductor sample and a fixed, known position on the sample stage.

An initial pre-scan is then performed to analyze the area of the semiconductor sample with at least one positioning mark. This pre-scan can be performed using known SIMS or SE detection methods. By determining the difference between the theoretical target position of the positioning mark and the actual position, the sample-internal coordinate system can be aligned with the coordinate system of the sample stage. By repeating the step for further positioning marks, errors in the positioning of the semiconductor sample can be detected not only in the XY plane of the sample stage, but also a rotation of the semiconductor sample relative to the sample stage and an error in the zoom factor, which arises, for example, from a different distance between the sample surface and the radiation source.

After alignment, the sample stage is moved relative to the stationary ion beam source and, using the distances known from the navigation data, is moved in the sample stage plane to precisely target the ROI to be examined in the semiconductor structure. Only then is a SIMS analysis of the ROI performed under ion irradiation.

The combination of CAD/blank sample navigation and SIMS offers several significant advantages, especially in terms of precision, efficiency, and accuracy of sample analysis. These include:

- Increased precision: Data-driven navigation enables precise and accurate sample positioning. It ensures that the SIMS instrument precisely targets the location of interest on the sample surface or within a complex structure. This precision is critical for analyzing specific features, layers, or structures in semiconductor devices or other materials.

- Efficient data acquisition: Data-driven navigation streamlines the data acquisition process. By precisely specifying the areas of interest or features, e.g., in a CAD model, the SIMS device can automatically scan and analyze these specific regions, eliminating time-consuming manual adjustments.

- Minimized sample damage: During SIMS analysis, the primary ion beam can cause sputtering and thus damage to the sample surface, as well as unwanted implantation of the primary ions. Data-based navigation minimizes this damage by ensuring that the ion beam only reaches the intended areas of the semiconductor sample. scanned and the integrity of the neighboring regions is preserved. In particular, this ensures that the ROI itself is not damaged by orientation scans that would otherwise be necessary.

- Handling complex geometries: CAD models can accurately represent complex 3D structures. This is especially valuable in semiconductor manufacturing, where modern chips feature complicated architectures. Data-driven navigation enables SIMS to analyze specific layers, trenches, and vias within these complex structures.

- Improved reproducibility: Data-driven navigation enables consistent and repeatable analyses. Researchers and developers can save and reuse data-driven navigation plans for future analyses or share them with colleagues to ensure consistent data collection and comparability.

- Data correlation: Data-based navigation facilitates the correlation of SIMS data with other data sources, such as optical or electron microscopic images. By comparing SIMS data with the CAD model, researchers can accurately correlate SIMS results with the specific characteristics of other imaging modalities.

In summary, data-driven navigation for SIMS significantly enhances the capabilities and efficiency of the technology. It is particularly valuable in industries such as semiconductor manufacturing, where precise analysis of complex structures is essential for quality control and research and development. By integrating CAD models into SIMS instruments, researchers and developers can achieve higher levels of accuracy, reproducibility, and productivity in their analysis processes.

Once the start position for the analysis scan has been reached, the analysis scan can be performed:

- at a stationary position (“spot mode”) and/or - as an X/Y scan (“raster scan mode”) and/or

- along a route predefined from navigation data or a route, which may also be a polygonal route (“shape mode”).

The above analysis scan modes can also be performed multiple times in succession to examine the depth of the sample (Z-direction) using the sputtering effect. Simply put, the examination method in this embodiment involves burrowing the ion beam into the depth of the semiconductor structure. To do this, the upper layers must be partially removed. For this purpose, the ion beam's intensity and/or irradiation time per unit area are varied so that its effect on the sample is increased beyond that required for pure SIMS analysis.

Particularly interesting is the sample examination along a section of the semiconductor structure, referred to above as shape mode. With known CAD data as navigation data and the possibility of highly precise positioning of the ion beam, for example, a section of an etched trench with a curve or trenches with a specific design width can be irradiated. This can be done for repeating substructures of the semiconductor structure, thus obtaining a statistical distribution or distribution across the entire wafer or substrate of the semiconductor sample. This distribution then provides information about the size of a process window.

The probe size should be smaller than the structure to be examined, such as the width of a trench. The analytical scan also increases the signal-to-noise ratio for very thin layers, such as those formed by impurities, because much more material is available for analysis than with a pure point analysis. Preferably, the positioning means and the diameter of the ion beam are matched to achieve a resolution of better than 20 nm in trench analysis scans.

An advantageous variant of the examination method provides for the use of a semiconductor sample that has at least three positioning marks arranged at different locations on the same substrate as the semiconductor structure to be analyzed, which are not all arranged on the same straight line. This allows for the precise measurement of a reference point in a two-dimensional plane.

Furthermore, it may be advantageous if, from the preliminary scan of the at least three positioning marks, correction data for a position correction in the reference system of the sample stage and/or for the height of the semiconductor sample on the sample stage relative to a primary ion column emitting the focused ion beam and/or a rotation error of the semiconductor sample relative to the stationary housing with the primary ion column are determined, and the alignment is performed based on this correction data. This makes the subsequent structural elucidation even more precise.

Due to alignment using SIMS, each irradiation procedure results in a loss of structure in the area of the positioning mark. Various measures are available to compensate or mitigate this.

For example, the positioning marks can preferably be formed with a thickness that is significantly greater than the layer thickness of the semiconductor structures to be determined in subsequent analysis scans, and in particular, 2 to 4 times the thickness of the semiconductor structure. This allows for a certain amount of material removal through multiple raster scans.

It is also possible to provide more than one set of positioning marks on the semiconductor sample and to perform the alignment with a second set after a first set has been compromised by previous pre-scans for alignment operations.

It is particularly advantageous if the raster speed for the preliminary scan performed for alignment purposes is increased compared to the subsequent analysis scan, for example, by a factor of 2 to 4. This means that the pixel dwell time is shorter and the irradiation intensity is lower, which leads to less destruction of the positioning marks. The increased image noise caused by a higher raster speed is not harmful because the positioning marks are large relative to the size of the ROI and are geometrically designed, e.g., as a cross, so that their center of gravity, or their center, used as the coordinate system origin or reference point, can still be reliably identified.

In this context, a preferred embodiment of the examination method of the invention provides that certain size ratios are selected and the positioning marks are made large compared to the smallest structures to be resolved, namely in particular 2 to 4 times the areal extent of the ROI, wherein the areal extent of the ROI is at least twice the size of the focused ion beam.

With a focused ion beam size (beam size/spot size) of 5 nm, the physical limit for lateral resolution for SIMS is approximately 10 nm due to the lateral extent of the "collision cascade," which describes the area from which secondary ions are emitted by the sample. Depending on the signal-to-noise ratio in the SIMS image, a lateral resolution of < 20 nm can thus routinely be expected. This makes the positioning marks robust against unwanted sputtering during the pre-scans.

An analysis device suitable for carrying out the examination method is specified in claim 13. This initially includes a secondary ion mass spectrometer, comprising

- a primary ion column containing a primary ion source that accelerates the ions and delivers them to the semiconductor sample as a focused ion beam;

- a high-vacuum sample chamber in which the semiconductor sample and an extraction unit for secondary ions are arranged, and;

- a mass spectrometer unit with a detector;

The mass spectrometer unit contains a mass analyzer that separates the secondary ions according to their mass-to-charge ratio.

The analysis device also comprises a sample stage that is laterally movable in at least two spatial coordinates, with the sample stage plane aligned perpendicular to the focused ion beam. The sample stage, in particular, has a drive system for moving the sample stage relative to the stationary sample chamber. For this purpose, spindles driven by DC motors or stepper motors can be provided.

The sample stage also includes a feedback measuring system to determine the position of the sample stage within the sample chamber and, if necessary, its travel speed. The feedback measuring system can be an encoder connected to the spindle, or encoders mounted on glass measuring rods positioned off the spindle.

A laser interferometer is particularly preferred to achieve the highest possible accuracy in motion monitoring. With its spatial resolution in the sub-nanometer range, this allows for the successful targeting of structures on chips with repetitive motions in the range of a few nanometers, such as memory structures. Examining critical points in repetitive structures requires a spatial precision significantly better than half the pitch of the structure. A particularly preferred embodiment provides for the use of a shift piezo actuator in the drive devices of both axes. Unlike the main drives, e.g., DC motors, the shift piezo actuators can move the sample stage continuously and smoothly. Due to the very small travel distances made possible by the use of the shift piezo actuators, the use of a laser interferometer as a feedback measurement system is required in this embodiment to fully utilize the possible precision in the nm range.

Finally, the analysis device also includes a stage control unit to control the drives of the sample stage.

The following describes the implementation of an analysis using an analysis device that has a stage control unit for the sample stage and a control PC for the secondary ion mass spectrometer, as well as an ion column in which the ion beam is deflected via electrostatic or electromagnetic fields, for which a further control unit is provided.

If separate control units are provided for the sample stage, for the control of the ion beam by deflection and for the secondary ion mass spectrometer, the invention provides a data link between the control units in order to coordinate the emission of the ion beam with the movement of the stage.

All control units for the ion beam, sample stage, and SIMS are monitored and controlled by a global control unit. These control units can be physically separate or integrated into the global control unit.

In a first step, the ion source is started so that a stable ion beam is emitted. Furthermore, the column is aligned so that the beam passes centrally through the beam aperture with the smallest possible Diameter, depending on the diameter of the beam aperture, and round shape, can impinge on the sample. This procedure is performed on a "dummy" sample or at a corner of the actual sample to prevent damage to the ROIs by sputtering or ion implantation.

Once the previously described preparations are complete, the sample stage can perform its first target movement, e.g., to move to the area of one of the positioning marks on the semiconductor sample. A travel command with an X-Y target coordinate is sent from the control PC to the stage control unit. This unit first calculates a travel profile, i.e., X-Y target values from the start time to arrival. The profile typically includes acceleration and deceleration processes.

After the profile has been created, the journey is carried out, with the stage control unit continuously controlling or checking the following actions, for example with a frequency of 10 kHz:

- It sends control variables to the actuators, e.g. voltages for the DC motors of the drive system.

- It measures the current actual position using a laser interferometer.

- It performs a target-actual comparison of the position and corrects the control variables of the actuators accordingly.

The stage control unit determines that the target position has been reached as soon as the actual position is within a preselected tolerance zone, the so-called error band. This is typically set to twice the spot size of the ion beam. For example, if the spot size is 5 nm, the error band size is set to 10 nm.

The stage control unit then switches off the actuators and sends a message to the control PC that the target position has been successfully reached.

In a preferred analysis device for carrying out the examination method according to the invention, the following typical dimensions are given: - Edge length of a semiconductor sample to be examined: 100 mm;

- Distance of positioning marks: 1 to 100 mm;

- Travel distance during a destination journey, e.g. from die to die: 5 mm;

- Number of pre-calculated TARGET X-Y values for creating a driving profile along the route: approx. 50,000;

- Travel speed: 2 mm/s (DC motors with spindles), up to 20 mm/s (piezo linear drives);

- Error tube for target arrival: 10nm.

Description of an implementation example

The invention is explained in more detail below with reference to the exemplary embodiment of an analysis device shown in the drawings. The figures show in detail:

Fig. 1 shows a schematic representation of an analysis device for examining a semiconductor sample;

Fig. 2 the trajectory of a primary ion beam on a semiconductor sample in a schematic, perspective view and

Fig. 3A, 3B each show a semiconductor sample on a sample stage from above.

Figure 1 shows an analysis device 100 for examining a semiconductor sample. This largely corresponds to the known design of a secondary electron mass spectrometer, with only the selection of a sample stage 20 being specifically adapted for carrying out the analysis method according to the invention.

A high-vacuum sample chamber 11 is formed in a pressure-resistant and hermetically sealable housing 10. The sample stage 20 is arranged therein. It comprises a base 21, which is firmly connected to the housing 10, and the actual sample stage 20, on which a semiconductor sample 30 can be mounted and which is movable at least two-dimensionally relative to the base, generally in a Cartesian coordinate system. The high-vacuum Sample chamber 11 can be evacuated so that a high vacuum can be created. A primary ion source 12 is arranged in a vertically aligned column at the top of the housing 20. The ion beam 13 emitted from there is aligned perpendicular to the sample stage 20.

An extraction unit 14 is arranged between the primary ion source 12 and the sample stage 20. This extraction unit serves to collect, focus, and laterally divert the secondary ions released from a semiconductor sample placed on the sample stage 20. The secondary ion beam 16 thus formed and laterally deflected is focused by transfer lenses 15 and directed to a mass spectrometer unit 17, where the secondary ions are separated according to their mass-to-charge ratio and guided to a detector.

The movable part of the sample stage 20 is moved relative to the base by a stage control unit 22. The stage control unit 22 is connected to a control PC 18, which also controls the primary ion source 12 and on which the signals generated in the detector of the mass spectrometer unit 17 are visualized.

Figure 2 shows a schematic, perspective view of a semiconductor sample 30 placed on the sample stage. It comprises several semiconductor structures to be examined, each forming a region of interest (ROI) 31, and a total of three positioning marks 33, 34, 35 in two edge strips. By moving the sample stage, the semiconductor sample 30 can be moved relative to the stationary and vertically aligned primary ion beam 13 using a movement path 32 specified by the control unit of the sample stage. This allows a line scan 42 to be performed or an image 31 of the semiconductor sample 30, or of individual ROIs 31 thereon, to be generated. Furthermore, the areas with the cross-shaped positioning marks 33, 34, 35 can be targeted. Figure 3A shows a top view of the semiconductor sample 30 mounted on the sample stage 20. As indicated by the block arrows, the sample stage 20 can be moved in the X and Y directions. At the beginning of the examination process, the sample stage 20 is positioned so that the ion beam is above a positioning mark 35. A target position 35' for the positioning mark 35 is derived from the manufacturing data of the semiconductor sample 30. The target position 35' is indicated in Figure 3A by the dashed crosses. Due to the manual placement of the semiconductor sample 30 on the sample stage 20, a deviation between the theoretical target position 35' determined from CAD data of the semiconductor sample 30 and the actual position is to be expected. Therefore, the primary ion beam 13 is switched on at the target position 35' to perform an imaging pre-scan, which is represented by the dashed circle. The positioning mark 35 is detected in the edge area of the detection range around the target position 35'.

The preliminary scan is repeated by moving to the target positions 33', 34' for the positioning marks 33, 34 to also detect possible rotation and zoom errors. Using the deviations determined in the preliminary scans, the coordinate system derived from the CAD data of the semiconductor sample 30 and the actual coordinate system on the sample stage are aligned so that all target positions match the actual positions, as shown in Figure 3B.

From the position mark 34 last approached for a preliminary scan, a movement path 32 can be generated by means of the control unit in order to place the primary ion beam 13 exactly on an ROI 31 in order to perform an analysis scan there. List of reference symbols

100 analysis device

10 housings

11 Sample chamber

12 Primary ion source

13 focused ion beam

14 Extraction unit

16 Secondary ion beam

15 transfer lenses

17 Mass spectrometer unit

18 control PCs

20 rehearsal stage

22 Stage control unit

30 semiconductor samples

31 Region of Interest (ROI)

32 Movement path

33, 34, 35 positioning marks

33', 34' 35' Target positions

36 Semiconductor structure

41 Image

42 line scans

Claims

Patent claims: 1 . Method for examining a semiconductor sample (30) using a secondary ion mass spectrometer (SIMS) with a material-removing focused ion beam (FIB) (13), comprising at least the following steps: Positioning the semiconductor sample (30) on a sample stage (20); Carrying out an analysis scan by irradiating at least one region of interest (ROI) (31) in at least one semiconductor structure (36) on the semiconductor sample (30) with the ion beam (13) to release secondary ions from the semiconductor structure (36); Registration of the secondary ions in a mass spectrometer unit (17) to generate an electronic image (41) and/or another data set for characterizing the semiconductor structure (36) in the region of the irradiated ROI (31); characterized by at least the following steps: - using a semiconductor sample (30) having on the same substrate the semiconductor structure (36) to be analyzed and at least one positioning mark (33, 34, 35), - using a sample stage (20) which can be moved in at least two dimensions relative to the ion beam (13); Providing navigation data for the semiconductor sample (30) with the semiconductor structure (36) and the positioning mark (33, 34, 35); Performing a preliminary scan by data-based navigation to a position of a positioning mark (33, 34, 35) derived from the navigation data and irradiating the area of the semiconductor sample (30) with the ion beam (13) with a large scan area; Readjustment (alignment) of an internal coordinate system for the sample stage (20) by comparing the position of the positioning mark (33, 34, 35) derived from the navigation data on the Sample stage (20) with the position of the positioning mark (33, 34, 35) determined by the preliminary scan; Positioning the ion beam (13) over the ROI (31) to be analyzed by data-based navigation of the sample stage (20) and/or lateral deflection of the ion beam (13), wherein the travel path of the sample stage (20) leading to the position and/or the amount of lateral deflection of the ion beam (13) is calculated from the navigation data of the semiconductor sample (30); Carrying out a SIMS analysis scan to generate the electronic image (41) and/or the other data set by irradiating the semiconductor structure (36) by means of the ion beam (13) with a scan area reduced compared to the preliminary scan. 2. Examination method according to claim 1, characterized in that a semiconductor sample (30) is used which has, on the same substrate as the semiconductor structure (36) to be analyzed, at least three positioning marks (33, 34, 35) arranged offset therefrom, which are not all arranged on the same straight line. 3. Examination method according to claim 2, characterized in that from the preliminary scan of at least three positioning marks (33, 34, 35) correction data for a position correction in the reference system of the sample stage (20) and/or for the height of the semiconductor sample (30) on the sample stage (20) relative to a primary ion column (12) emitting the focused ion beam (13) and/or a rotation error of the semiconductor sample (30) relative to the stationary housing (10) with the primary ion column (12) are determined and the alignment is carried out using this correction data. 4. Examination method according to claim 2 or 3, characterized in that more than one set of at least three positioning marks (33, 34, 35) is provided on the semiconductor sample (30). 5. Examination method according to one of claims 1 to 4, characterized in that the positioning marks (33, 34, 35) are arranged on the semiconductor sample (30) offset from the semiconductor structure (36). 6. Examination method according to one of the preceding claims, characterized in that the positioning marks (33, 34, 35) are formed with a thickness which is greater than the layer thickness of the ROI (31) to be clarified in later analysis scans in the semiconductor structure (36). 7. Examination method according to one of the preceding claims, characterized in that a raster speed with which the focused ion beam (13) is guided over the surface for the purpose of alignment in a preliminary scan is increased compared to a raster speed in the subsequently following analysis scan. 8. Examination method according to claim 7, characterized in that the raster speed in the preliminary scan is increased to 2 to 4 times the raster speed in the analysis scan. 9. Examination method according to one of the preceding claims, characterized in that the areal extent of the positioning marks (33, 34, 35) in the plane of the sample stage (20) is in each case large in relation to the size of the ROI (31). 10. Examination method according to claim 9, characterized in that the areal extent of the positioning marks (33, 34, 35) is 2 times to 4 times the areal extent of the ROI (31), wherein the areal extent of the ROI is at least twice the size of the focused ion beam (13). 11. Examination method according to one of the preceding claims, characterized in that the focused ion beam (13) is guided over the semiconductor sample (30) in at least one path predefined by navigation data. 12. Examination method according to one of the preceding claims, characterized in that by repeatedly performing the analysis scan with the same navigation data, at least one upper semiconductor layer is partially removed and an examination is made possible in a further semiconductor layer located below the partially removed semiconductor layer. 13. Analysis device (100) for carrying out the examination method for a semiconductor sample (30) by means of a secondary ion mass spectrometer (SIMS) with a focused ion beam (13) according to one of the preceding claims, at least comprising - a secondary ion mass spectrometer, comprising o a primary ion column (12) containing a primary ion source and accelerating the ions and delivering them to the semiconductor sample (30) as a focused ion beam (13); o a high-vacuum sample chamber (11) in which the semiconductor sample (30) and an extraction unit (14) for secondary ions are arranged, and; o a mass spectrometer unit (17) with a detector; - a sample stage (20) which is laterally movable in at least two surface coordinates via drive systems, wherein a support plane of the sample stage (20) is aligned normal to the focused ion beam (13); - a back-measuring system to determine the position of the sample stage within the high-vacuum sample chamber (11) and - a stage control unit (22) for controlling the drive systems on the sample stage (20) and/or a control unit for deflecting the focused ion beam (13) as a function of the actual position data obtained by the feedback measuring system and/or the desired position data derived from navigation data of the semiconductor sample (30). 14. Analysis device (100) according to claim 13, characterized in that the drive systems are formed by DC motors and spindles, wherein an encoder is connected to the spindle as a feedback measuring system. 15. Analysis device (100) according to claim 13 or 14, characterized in that the drive systems are each designed as a DC motor-spindle combination, which is supplemented by a sliding piezo actuator and that the laser interferometer is provided as a feedback measuring system.