WO2025111937A1

WO2025111937A1 - Display panel and display device

Info

Publication number: WO2025111937A1
Application number: PCT/CN2023/135460
Authority: WO
Inventors: 孙智磊; 伏宝泽; 钱海蛟; 欧阳欠
Original assignee: Nanjing Boe Display Technology Co Ltd; BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Current assignee: Nanjing Boe Display Technology Co Ltd; BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Priority date: 2023-11-30
Filing date: 2023-11-30
Publication date: 2025-06-05
Anticipated expiration: 2026-05-30
Also published as: CN120419314A

Abstract

The present disclosure provides a display panel and a display device. The display panel comprises a display area and a peripheral area; a plurality of first signal lines located on a substrate are provided in the peripheral area; the first signal lines each comprise a signal connecting line portion; the orthographic projections of cross-line portions on the substrate partially overlap with the orthographic projections of at least some of second sub-signal lines among a plurality of second sub-signal lines on the substrate; the cross-line portions are spaced apart from the signal connecting line portions comprised in at least some of the second sub-signal lines among the plurality of second sub-signal lines by at least two insulating layers; and/or, the signal connecting line portions comprise a plurality of signal connecting line parts extending in a first direction; the width of the signal connecting line parts in a second direction is smaller than a width threshold; the signal connecting line portions extend in the first direction; and the second direction intersects with the first direction. The present disclosure alleviates the problem of short-circuit of the first signal lines.

Description

Display panel and display device

Technical Field

本公开涉及显示技术领域，尤其涉及一种显示面板和显示装置。The present disclosure relates to the field of display technology, and in particular to a display panel and a display device.

Background Art

在相关技术中，时钟信号线的AD(Abnormal Dislay，非正常显示)不良和DGS(Data-Gate Short，数据线与栅线之间的短路)不良，指Cu(铜)扩散引起的源漏金属层与栅金属层之间的短路，继而引起的严重不良。多数情况下，Cu的扩散被认为是由水汽渗入导致Cu腐蚀生成Cu+、Cu2+离子引起，继而在电压作用下发生Cu的电迁移和热迁移。其他可能的原因还有异物和ESD(静电释放)导致时钟信号线AD。在时钟信号线区，位于源漏金属层的子线和位于栅金属层的母线之间压差较大，且源漏金属层和栅金属层的交叠面积较大，因此短路常发生在时钟信号区。在源漏金属层的栅金属层的交叠区域呈爬坡状，薄膜形变引起的结构不均匀会导致电荷分布不均匀。通常减少所述母线和所述子线之间的压差，或者，增加栅金属层与源漏金属层之间的绝缘层的厚度，都会该不良具有改善效果，但是如上方法会直接影响MOS(金属-氧化物-半导体)结构，或者引起膜层应力失配等问题。In the related art, the AD (Abnormal Dislay) and DGS (Data-Gate Short) defects of the clock signal line refer to the short circuit between the source-drain metal layer and the gate metal layer caused by the diffusion of Cu (copper), which in turn causes serious defects. In most cases, the diffusion of Cu is believed to be caused by the corrosion of Cu due to the infiltration of water vapor, which generates Cu+ and Cu2+ ions, and then the electromigration and thermal migration of Cu occur under the action of voltage. Other possible reasons include foreign matter and ESD (electrostatic discharge) causing the AD of the clock signal line. In the clock signal line area, the voltage difference between the sub-line located in the source-drain metal layer and the busbar located in the gate metal layer is large, and the overlapping area of the source-drain metal layer and the gate metal layer is large, so short circuits often occur in the clock signal area. The overlapping area of the gate metal layer in the source-drain metal layer is in a climbing shape, and the structural unevenness caused by the film deformation will lead to uneven charge distribution. Generally, reducing the voltage difference between the busbar and the sub-line, or increasing the thickness of the insulating layer between the gate metal layer and the source/drain metal layer, will improve the problem. However, the above method will directly affect the MOS (metal-oxide-semiconductor) structure, or cause problems such as film stress mismatch.

发明内容Summary of the invention

在一个方面中，本公开实施例提供一种显示面板，包括显示区域和环绕所述显示区域的周边区域，在所述周边区域内，设置有位于基底上的多条第一信号线；所述第一信号线包括信号连接线部；In one aspect, an embodiment of the present disclosure provides a display panel, comprising a display area and a peripheral area surrounding the display area, wherein a plurality of first signal lines located on a substrate are disposed in the peripheral area; the first signal lines include a signal connection line portion;

所述多条第一信号线分为包括跨线部的第一子信号线和不包含跨线部的第二子信号线；The plurality of first signal lines are divided into first sub-signal lines including a crossover portion and second sub-signal lines not including a crossover portion;

所述跨线部在所述基底上的正投影与多条所述第二子信号线中的至少部分第二子信号线在所述基底上的正投影部分重叠；The orthographic projection of the cross-line portion on the substrate partially overlaps with the orthographic projection of at least part of the second sub-signal lines among the plurality of second sub-signal lines on the substrate;

所述跨线部和多条所述第二子信号线中的至少部分第二子信号线包括的信号连接线部之间间隔至少两层绝缘层；和/或，所述信号连接线部包括多条沿第一方向延伸的信号连接线部分，所述信号连接线部分沿第二方向的宽度小于宽度阈值；At least two insulating layers are spaced between the cross-line portion and a signal connection line portion included in at least part of the second sub-signal lines of the plurality of second sub-signal lines; and/or, the signal connection line portion includes a plurality of signal connection line portions extending along the first direction, and the width of the signal connection line portion along the second direction is less than a width threshold;

所述信号连接线部沿所述第一方向延伸，所述第二方向与所述第一方向相交。The signal connection line portion extends along the first direction, and the second direction intersects with the first direction.

可选的，所述宽度阈值大于或等于5μm而小于或等于8μm。Optionally, the width threshold is greater than or equal to 5 μm and less than or equal to 8 μm.

可选的，所述显示面板包括沿着远离所述基底依次排列的第一导电层、第二导电层和第三导电层；相邻的导电层之间设置有至少一层绝缘层；Optionally, the display panel comprises a first conductive layer, a second conductive layer and a third conductive layer which are sequentially arranged away from the substrate; at least one insulating layer is provided between adjacent conductive layers;

所述跨线部位于所述第三导电层，所述信号连接线部位于所述第一导电层。The cross-line portion is located in the third conductive layer, and the signal connection line portion is located in the first conductive layer.

可选的，所述第一导电层包括设置于所述显示区域的遮光图形，所述第二导电层包括设置于所述显示区域的栅线，所述第三导电层包括设置于所述显示区域的数据线。Optionally, the first conductive layer includes a light shielding pattern arranged in the display area, and the second conductive layer includes The gate line is arranged in the display area, and the third conductive layer includes a data line arranged in the display area.

可选的，所述第一信号线还包括信号主体线部；Optionally, the first signal line further includes a signal main line portion;

所述信号主体线部包括第一主体线部分、第二主体线部分和第三主体线部分；所述第一主体线部分、第二主体线部分和第三主体线部分位于不同的导电层；The signal main line portion includes a first main line portion, a second main line portion and a third main line portion; the first main line portion, the second main line portion and the third main line portion are located in different conductive layers;

所述第三主体线部分通过第一过孔与所述第二主体线部分电连接；The third main body line portion is electrically connected to the second main body line portion through a first via;

所述第一主体线部分在所述基底上的正投影、所述第二主体线部分在所述基底上的正投影和所述第三主体线部分在所述基底上的正投影至少部分重叠。An orthographic projection of the first body line portion on the substrate, an orthographic projection of the second body line portion on the substrate, and an orthographic projection of the third body line portion on the substrate at least partially overlap.

可选的，所述第一信号线还包括信号导接线部；Optionally, the first signal line further includes a signal conducting line portion;

所述信号导接线部设置于所述信号主体线部与所述信号连接线部之间；The signal conducting wire portion is arranged between the signal main wire portion and the signal connecting wire portion;

所述信号导接线部包括位于不同导电层的第一导接线部分和第二导接线部分；The signal conductive line portion includes a first conductive line portion and a second conductive line portion located in different conductive layers;

所述第一导接线部分通过第二过孔与所述第二导接线部分电连接；The first conductive line portion is electrically connected to the second conductive line portion through a second via hole;

所述第一导接线部分在所述基底上的正投影与所述第二导接线部分在所述基底上的正投影至少部分重叠。An orthographic projection of the first conductive line portion on the substrate at least partially overlaps with an orthographic projection of the second conductive line portion on the substrate.

可选的，所述信号连接线部、所述第一主体线部分和所述第一导接线部分电连接，所述第三主体线部分和所述第二导接线部分电连接。Optionally, the signal connection line portion, the first main body line portion and the first conductive line portion are electrically connected, and the third main body line portion and the second conductive line portion are electrically connected.

所述信号主体线部包括位于不同导电层的第一主体线部分和第二主体线部分；The signal main body line portion includes a first main body line portion and a second main body line portion located in different conductive layers;

所述第一主体线部分通过第三过孔与所述第二主体线部分电连接；The first main body line portion is electrically connected to the second main body line portion through a third via;

所述第一主体线部分在所述基底上的正投影和所述第二主体线部分在所述基底上的正投影至少部分重叠。An orthographic projection of the first body line portion on the substrate and an orthographic projection of the second body line portion on the substrate at least partially overlap.

可选的，所述信号连接线部与所述第一主体线部分电连接。Optionally, the signal connection line portion is electrically connected to the first main body line portion.

可选的，所述跨线部在所述基底上的正投影与所述跨线部所属的第一信号线包括的信号连接线部在所述基底上的正投影部分重叠；Optionally, an orthographic projection of the line-jumping portion on the substrate partially overlaps with an orthographic projection of a signal connection line portion included in a first signal line to which the line-jumping portion belongs on the substrate;

所述跨线部通过第四过孔与所述跨线部所属的第一信号线包括的信号连接线部电连接。The cross-line portion is electrically connected to a signal connection line portion included in a first signal line to which the cross-line portion belongs through a fourth via hole.

可选的，所述显示面板还包括设置于所述第三导电层远离所述基底一侧的第四导电层；Optionally, the display panel further includes a fourth conductive layer disposed on a side of the third conductive layer away from the substrate;

所述第一信号线还包括信号主体线部；The first signal line also includes a signal main line portion;

所述第三主体线部分在所述基底上的正投影与所述第一主体线部分在所述基底上的正投影至少部分重叠，所述第三主体线部分在所述基底上的正投影与所述第二主体线部分在所述基底上的正投影至少部分重叠；The orthographic projection of the third main body line portion on the substrate at least partially overlaps with the orthographic projection of the first main body line portion on the substrate, and the orthographic projection of the third main body line portion on the substrate at least partially overlaps with the orthographic projection of the second main body line portion on the substrate;

所述第三主体线部分通过第五过孔与所述第二主体线部分电连接，所述第三主体线部分通过第六过孔与所述第一主体线部分电连接。The third main body line portion is electrically connected to the second main body line portion through a fifth via hole, and the third main body line portion is electrically connected to the first main body line portion through a sixth via hole.

可选的，所述第四导电层包括设置于所述显示区域的像素电极。 Optionally, the fourth conductive layer includes a pixel electrode arranged in the display area.

可选的，所述第一信号线还包括第一转接部；所述第一转接部在所述基底上的正投影与所述跨线部所属的第一信号线包括的信号连接线部在所述基底上的正投影至少部分重叠；所述第一转接部在所述基底上的正投影与所述跨线部在所述基底上的正投影至少部分重叠；Optionally, the first signal line further includes a first adapter portion; the orthographic projection of the first adapter portion on the substrate at least partially overlaps with the orthographic projection of the signal connection line portion included in the first signal line to which the cross-line portion belongs on the substrate; the orthographic projection of the first adapter portion on the substrate at least partially overlaps with the orthographic projection of the cross-line portion on the substrate;

所述第一转接部通过第七过孔与该信号连接线部电连接，所述第一转接部通过第八过孔与所述跨线部电连接；The first adapter portion is electrically connected to the signal connection line portion through a seventh via hole, and the first adapter portion is electrically connected to the cross-line portion through an eighth via hole;

所述第一转接部与所述信号连接线位于不同层，所述第一转接部与所述跨线部位于不同的导电层。The first transfer portion and the signal connection line are located in different layers, and the first transfer portion and the cross-line portion are located in different conductive layers.

可选的，所述显示面板包括沿着远离所述基底依次排列的第二导电层、第三导电层、第五导电层、第六导电层和第四导电层；所述第五导电层与所述第六导电层搭接；所述第二导电层与所述第三导电层之间设置有至少一层绝缘层，所述第三导电层与所述第五导电层之间设置有至少一层绝缘层，所述第六导电层与所述第四导电层之间设置有至少一层绝缘层；Optionally, the display panel includes a second conductive layer, a third conductive layer, a fifth conductive layer, a sixth conductive layer and a fourth conductive layer arranged in sequence away from the substrate; the fifth conductive layer is overlapped with the sixth conductive layer; at least one insulating layer is provided between the second conductive layer and the third conductive layer, at least one insulating layer is provided between the third conductive layer and the fifth conductive layer, and at least one insulating layer is provided between the sixth conductive layer and the fourth conductive layer;

所述跨线部的至少部分位于所述第六导电层，所述信号连接线部位于所述第二导电层。At least a portion of the cross-line portion is located in the sixth conductive layer, and the signal connection line portion is located in the second conductive layer.

可选的，所述第二导电层包括设置于所述显示区域的栅线，所述第三导电层包括设置于所述显示区域的数据线，所述第五导电层包括设置于所述显示区域的公共电极，所述第六导电层包括设置于所述显示区域的辅助金属图形。Optionally, the second conductive layer includes gate lines arranged in the display area, the third conductive layer includes data lines arranged in the display area, the fifth conductive layer includes common electrodes arranged in the display area, and the sixth conductive layer includes auxiliary metal patterns arranged in the display area.

可选的，所述第一信号线还包括第一转接部；Optionally, the first signal line further includes a first adapter;

所述第一转接部通过第九过孔与所述信号连接线部电连接，所述第一转接部通过第十过孔与所述跨线部电连接；The first adapter portion is electrically connected to the signal connection line portion through a ninth via hole, and the first adapter portion is electrically connected to the cross-line portion through a tenth via hole;

所述第一转接部与所述信号连接线部位于不同层，所述第一转接部与所述跨线部位于不同的导电层。The first transfer portion and the signal connection line portion are located in different layers, and the first transfer portion and the cross-line portion are located in different conductive layers.

可选的，所述第一信号线还包括第一转接部和第二转接部；所述第二转接部与所述跨线部搭接；Optionally, the first signal line further includes a first transfer portion and a second transfer portion; the second transfer portion is overlapped with the crossover portion;

所述第一转接部通过第十三过孔与所述信号连接线部电连接，所述第一转接部通过第十四过孔与所述第二转接部电连接；The first transfer portion is electrically connected to the signal connection line portion through a thirteenth via hole, and the first transfer portion is electrically connected to the second transfer portion through a fourteenth via hole;

所述第一转接部与所述信号连接线部位于不同层，所述第一转接部与所述第二转接部位于不同的导电层。The first transfer portion and the signal connection line portion are located in different layers, and the first transfer portion and the second transfer portion are located in different conductive layers.

可选的，所述第一信号线还包括第三转接部和连接线；Optionally, the first signal line further includes a third adapter and a connecting line;

所述第三转接部通过第十一过孔与所述跨线部电连接，所述第三转接部通过第十二过孔与所述连接线电连接；The third adapter portion is electrically connected to the cross-line portion through an eleventh via hole, and the third adapter portion is electrically connected to the connection line through a twelfth via hole;

所述第三转接部与所述跨线部位于不同的导电层，所述第三转接部与所述连接线位于不同的导电层。The third transfer portion and the cross-line portion are located in different conductive layers, and the third transfer portion and the connecting line are located in different conductive layers.

可选的，所述第一信号线还包括位于所述第五导电层的第一连接部；所述第一连接部与所述跨线部搭接； Optionally, the first signal line further includes a first connecting portion located in the fifth conductive layer; the first connecting portion is overlapped with the cross-line portion;

所述第一连接部在所述基底上的正投影覆盖跨线区域在所述基底上的正投影；The orthographic projection of the first connecting portion on the substrate covers the orthographic projection of the cross-line area on the substrate;

所述跨线区域为所述跨线部与多条所述第二子信号线中的至少部分第二子信号线包括的信号连接线部之间的交叠区域。The cross-line region is an overlapping region between the cross-line portion and a signal connection line portion included in at least some of the second sub-signal lines in the plurality of second sub-signal lines.

可选的，所述跨线部包括第一跨线部分和第二跨线部分；Optionally, the cross-line portion includes a first cross-line portion and a second cross-line portion;

所述第一跨线部分在所述基底上的正投影覆盖所述第二跨线部分在所述基底上的正投影；The orthographic projection of the first cross-line portion on the substrate covers the orthographic projection of the second cross-line portion on the substrate;

所述第一跨线部分与所述第二跨线部分直接搭接。The first jumper portion is directly overlapped with the second jumper portion.

可选的，所述第一信号线还包括第一转接部和第二转接部；所述第二转接部与所述第一跨线部分电连接；Optionally, the first signal line further includes a first transfer portion and a second transfer portion; the second transfer portion is electrically connected to the first cross-line portion;

所述第一转接部通过第十三过孔与时钟信号连接线部电连接，所述第一转接部通过第十四过孔与所述第二转接部电连接；The first transfer portion is electrically connected to the clock signal connection line portion through a thirteenth via hole, and the first transfer portion is electrically connected to the second transfer portion through a fourteenth via hole;

所述第一转接部与所述信号连接线部位于不同的导电层，所述第一转接部与所述第二转接部位于不同的导电层。The first transfer portion and the signal connection line portion are located in different conductive layers, and the first transfer portion and the second transfer portion are located in different conductive layers.

可选的，所述第一信号线还包括第三转接部、第四转接部和连接线；Optionally, the first signal line further includes a third adapter, a fourth adapter and a connecting line;

所述第四转接部与所述第一跨线部分电连接；所述第四转接部与所述第一跨线部分位于同一导电层；The fourth transfer portion is electrically connected to the first cross-line portion; the fourth transfer portion and the first cross-line portion are located in the same conductive layer;

所述第三转接部通过第十五过孔与所述第四转接部电连接，所述第三转接部通过第十六过孔与所述连接线电连接；The third adapter is electrically connected to the fourth adapter through a fifteenth via hole, and the third adapter is electrically connected to the connection line through a sixteenth via hole;

所述第三转接部与所述第四转接部位于不同的导电层，所述第三转接部与所述连接线位于不同的导电层。The third transfer portion and the fourth transfer portion are located in different conductive layers, and the third transfer portion and the connecting line are located in different conductive layers.

在第二个方面中，本公开实施例提供一种显示装置，包括上述的显示面板。In a second aspect, an embodiment of the present disclosure provides a display device, comprising the above-mentioned display panel.

BRIEF DESCRIPTION OF THE DRAWINGS

图1是本公开至少一实施例所述的显示面板中的第一信号线的平面布局图；FIG1 is a plan layout diagram of a first signal line in a display panel according to at least one embodiment of the present disclosure;

图2是图1中的遮光金属层的平面布局图；FIG2 is a plan layout diagram of the light-shielding metal layer in FIG1 ;

图3是图1中的栅金属层的平面布局图，；FIG3 is a planar layout diagram of the gate metal layer in FIG1 ;

图4是图1中的源漏金属层的平面布局图；FIG4 is a planar layout diagram of the source/drain metal layer in FIG1 ;

图5是图4中的A-A’截面图；Fig. 5 is a cross-sectional view of A-A' in Fig. 4;

图6是图4中的B-B’截面图；Fig. 6 is a cross-sectional view of B-B' in Fig. 4;

图7A是图4中的C-C’截面图；Fig. 7A is a cross-sectional view of C-C' in Fig. 4;

图7B是显示面板的周边区域ZY和显示区域AA中的部件的示意图；FIG7B is a schematic diagram of components in the peripheral area ZY and the display area AA of the display panel;

图7C是是图7B中的K-K’截面图；Fig. 7C is a cross-sectional view K-K' in Fig. 7B;

图8是在制作图1-图7A所示的至少一实施例中的第一信号线时，遮光金属层成膜并刻蚀，得到的图形；FIG8 is a graph obtained by forming a light shielding metal layer and etching it when manufacturing the first signal line in at least one embodiment shown in FIG1 to FIG7A;

图9是在制作图1-图7A所示的至少一实施例中的第一信号线时，缓冲层成膜，栅绝缘层成膜，栅金属层成膜并刻蚀，以栅金属层为掩膜版刻蚀栅绝缘层，得到的图形；FIG. 9 is a diagram showing the formation of a buffer layer, a gate insulation layer, and a first signal line in at least one embodiment of the manufacturing process shown in FIG. 1 to FIG. 7A. The insulating layer is formed into a film, the gate metal layer is formed into a film and then etched, and the gate insulating layer is etched using the gate metal layer as a mask to obtain a pattern;

图10是在制作图1-图7A所示的至少一实施例中的第一信号线时，层间介质层成膜后，作出遮光金属层与栅金属层以及源漏金属层搭接孔的示意图；FIG10 is a schematic diagram showing a method of making overlapping holes between a light shielding metal layer and a gate metal layer and a source-drain metal layer after forming an interlayer dielectric layer when manufacturing the first signal line in at least one embodiment shown in FIG1 to FIG7A;

图11是在制作图1-图7A所示的至少一实施例中的第一信号线时，源漏金属层成膜并刻蚀，得到的图形；FIG11 is a diagram obtained by forming a source-drain metal layer and etching it when manufacturing the first signal line in at least one embodiment shown in FIG1 to FIG7A;

图12A、图12B、图12C、图12D、图12E、图12F和图12G为以上可步骤的断面图；12A, 12B, 12C, 12D, 12E, 12F and 12G are cross-sectional views of the above steps;

图13是本公开至少一实施例所述的显示面板中的第一信号线的平面布局图；13 is a plan layout diagram of a first signal line in a display panel according to at least one embodiment of the present disclosure;

图14是图13中的遮光金属层的平面布局图；FIG14 is a plan layout diagram of the light-shielding metal layer in FIG13;

图15是图13中的源漏金属层的平面布局图；FIG15 is a plan layout diagram of the source/drain metal layer in FIG13 ;

图16是图13中的D-D’截面图；Fig. 16 is a cross-sectional view of D-D' in Fig. 13;

图17是本公开至少一实施例所述的显示面板中的第一信号线的布局图；17 is a layout diagram of a first signal line in a display panel according to at least one embodiment of the present disclosure;

图18是图17中的遮光金属层的平面布局图；FIG18 is a plan layout diagram of the light-shielding metal layer in FIG17;

图19是图17中的源漏金属层的平面布局图；FIG19 is a planar layout diagram of the source/drain metal layer in FIG17 ;

图20是图17中的像素电极层的平面布局图；FIG20 is a plan layout diagram of the pixel electrode layer in FIG17;

图21是图17中的E-E’截面图；Fig. 21 is a cross-sectional view of E-E' in Fig. 17;

图22是本公开至少一实施例所述的显示面板中的第一信号线的平面布局图；FIG22 is a plan layout diagram of a first signal line in a display panel according to at least one embodiment of the present disclosure;

图23是图22中的栅金属层的平面布局图；FIG23 is a plan layout diagram of the gate metal layer in FIG22;

图24是图22中的源漏金属层的平面布局图；FIG24 is a planar layout diagram of the source/drain metal layer in FIG22 ;

图25是本公开至少一实施例所述的显示面板中的第一信号线的平面布局图；FIG25 is a plan layout diagram of a first signal line in a display panel according to at least one embodiment of the present disclosure;

图26是图25中的栅金属层的平面布局图；FIG26 is a plan layout diagram of the gate metal layer in FIG25;

图27是图25中的源金属层的平面布局图；FIG27 is a plan layout diagram of the source metal layer in FIG25;

图28是图25中的金属辅助层的平面布局图；FIG28 is a plan layout diagram of the metal auxiliary layer in FIG25;

图29A是图25中的像素电极层的平面布局图；FIG29A is a plan layout diagram of the pixel electrode layer in FIG25;

图29B是显示面板的周边区域ZY和显示区域AA中的部件的示意图；FIG29B is a schematic diagram of components in the peripheral area ZY and the display area AA of the display panel;

图29C是是图29B中的L-L’截面图；Fig. 29C is a cross-sectional view of L-L' in Fig. 29B;

图30是图25中的F-F’截面图；Fig. 30 is a cross-sectional view of F-F' in Fig. 25;

图31是图25中的G-G’截面图；Fig. 31 is a cross-sectional view of G-G' in Fig. 25;

图32是图25中的H-H’截面图；Fig. 32 is a cross-sectional view of H-H' in Fig. 25;

图33和图34是本公开至少一实施例所述的显示面板中的第一信号线的平面布局图；33 and 34 are plan layout diagrams of first signal lines in a display panel according to at least one embodiment of the present disclosure;

图35是图33中的I-I’截面图；Fig. 35 is a cross-sectional view I-I' in Fig. 33;

图36是本公开至少一实施例所述的显示面板中的第一信号线的平面布局图；36 is a plan layout diagram of a first signal line in a display panel according to at least one embodiment of the present disclosure;

图37是图36中的栅金属层的平面布局图；FIG37 is a plan layout diagram of the gate metal layer in FIG36;

图38是图36中的源漏金属层的平面布局图；FIG38 is a planar layout diagram of the source/drain metal layer in FIG36 ;

图39是图36中的公共电极层的平面布局图；FIG39 is a plan layout diagram of the common electrode layer in FIG36;

图40是图36中的金属辅助层的平面布局图； FIG40 is a plan layout diagram of the metal auxiliary layer in FIG36;

图41是图36中的像素电极层的平面布局图；FIG41 is a plan layout diagram of the pixel electrode layer in FIG36;

图42是图36中的J-J’截面图；Fig. 42 is a J-J' cross-sectional view in Fig. 36;

图43是本公开至少一实施例所述的显示面板中的第一信号线的平面布局图；FIG43 is a plan layout diagram of a first signal line in a display panel according to at least one embodiment of the present disclosure;

图44是图43中的栅金属层的平面布局图；FIG44 is a plan layout diagram of the gate metal layer in FIG43;

图45是图43中的源漏金属层的平面布局图；FIG45 is a plan layout diagram of the source/drain metal layer in FIG43 ;

图46是图43中的公共电极层的平面布局图；FIG46 is a plan layout diagram of the common electrode layer in FIG43;

图47是图43中的金属辅助层的平面布局图；FIG47 is a plan layout diagram of the metal auxiliary layer in FIG43;

图48是图43中的像素电极层的平面布局图；FIG48 is a plan layout diagram of the pixel electrode layer in FIG43;

图49是在制作如图33所示的第一信号线时，栅金属层成膜后得到的图形；FIG49 is a graph obtained after the gate metal layer is formed when manufacturing the first signal line shown in FIG33;

图50是在制作如图33所示的第一信号线时，栅绝缘层成膜，半导体层成膜、刻蚀，源漏金属层成膜、刻蚀，得到的图形；FIG50 is a graph obtained by forming a gate insulating layer, forming a semiconductor layer, etching, and forming a source-drain metal layer, and etching when manufacturing the first signal line shown in FIG33;

图51是在制作如图33所示的第一信号线时，第一钝化层成膜，有机层涂布、曝光并显影，公共电极层成膜、刻蚀，得到的图形；FIG51 is a diagram obtained by forming a first passivation layer, coating, exposing and developing an organic layer, and forming and etching a common electrode layer when manufacturing the first signal line shown in FIG33;

图52是在制作如图33所示的第一信号线时，金属辅助层成膜、刻蚀，得到的图形；FIG52 is a diagram showing a pattern obtained by forming a metal auxiliary layer and etching the metal auxiliary layer when manufacturing the first signal line shown in FIG33;

图53是在制作如图33所示的第一信号线时，在金属辅助层、栅金属层和源漏金属层上留出搭孔区域的示意图；FIG53 is a schematic diagram of leaving overlapping hole areas on the metal auxiliary layer, the gate metal layer and the source-drain metal layer when manufacturing the first signal line shown in FIG33;

图54是在制作如图33所示的第一信号线时，像素电极层成膜、刻蚀，得到的图形；FIG54 is a graph obtained by forming and etching a pixel electrode layer when manufacturing the first signal line shown in FIG33;

图55是在制作如图43所示的第一信号线时，栅金属层成膜、刻蚀，得到的图形；FIG55 is a graph obtained by forming a gate metal layer and etching the gate metal layer when manufacturing the first signal line shown in FIG43;

图56是在制作如图43所示的第一信号线时，栅绝缘层成膜、半导体层成膜、刻蚀，源漏金属层成膜、刻蚀，得到的图形；FIG56 is a graph obtained by forming a gate insulating layer, forming a semiconductor layer, etching, and forming a source-drain metal layer, and etching when manufacturing the first signal line shown in FIG43;

图57是在制作如图43所示的第一信号线时，第一钝化层成膜，有机层涂布、曝光并显影，公共电极层成膜、刻蚀，得到的图形；FIG57 is a diagram showing a pattern obtained by forming a first passivation layer, coating, exposing and developing an organic layer, and forming and etching a common electrode layer when manufacturing the first signal line shown in FIG43;

图58是在制作如图43所示的第一信号线时，金属辅助层成膜、刻蚀，得到的图形；FIG58 is a graph obtained by forming a metal auxiliary layer and etching the metal auxiliary layer when manufacturing the first signal line shown in FIG43;

图59是在制作如图43所示的第一信号线时，在公共电极层、栅金属层和源漏金属层上留出搭孔区域的示意图；FIG59 is a schematic diagram of leaving overlapping hole areas on the common electrode layer, the gate metal layer and the source-drain metal layer when manufacturing the first signal line shown in FIG43;

图60是在制作如图43所示的第一信号线时，像素电极层成膜、刻蚀，得到的图形。FIG60 is a graph obtained by forming a pixel electrode layer and etching the pixel electrode layer when manufacturing the first signal line shown in FIG43.

DETAILED DESCRIPTION

下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。 The transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, in order to distinguish the two electrodes of the transistor except the gate, one of the electrodes is called the first electrode and the other is called the second electrode.

在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

本公开实施例所述的显示面板包括显示区域和环绕所述显示区域的周边区域，在所述周边区域内，设置有位于基底上的多条第一信号线；所述第一信号线包括信号连接线部；The display panel of the embodiment of the present disclosure includes a display area and a peripheral area surrounding the display area, wherein a plurality of first signal lines located on a substrate are arranged in the peripheral area; the first signal lines include a signal connection line portion;

所述多条第一信号线分为多条包括跨线部的第一子信号线和多条不包含跨线部的第二子信号线；The plurality of first signal lines are divided into a plurality of first sub-signal lines including cross-line portions and a plurality of second sub-signal lines not including cross-line portions;

所述跨线部在所述基底上的正投影与多条所述第二子信号线中的至少部分第二子信号线包括的信号连接线部在所述基底上的正投影部分重叠；The orthographic projection of the cross-line portion on the substrate partially overlaps with the orthographic projection of the signal connection line portion included in at least some of the second sub-signal lines among the plurality of second sub-signal lines on the substrate;

所述跨线部和多条所述第二子信号线中的至少部分第二子信号线之间间隔至少两层绝缘层；和/或，信号连接线部包括多条沿第一方向延伸的信号连接线部分，所述信号连接线部分沿第二方向的宽度小于宽度阈值；At least two insulating layers are spaced between the cross-line portion and at least part of the second sub-signal lines of the plurality of second sub-signal lines; and/or the signal connection line portion comprises a plurality of signal connection line portions extending along the first direction, and the width of the signal connection line portions along the second direction is less than a width threshold;

可选的，所述第一方向可以为竖直方向，所述第二方向可以为水平方向；或者，所述第一方向可以为水平方向，所述第二方向可以为竖直方向；但不以此为限。Optionally, the first direction may be a vertical direction, and the second direction may be a horizontal direction; or, the first direction may be a horizontal direction, and the second direction may be a vertical direction; but the present invention is not limited thereto.

在本公开的各平面布局图中，绘制了X-Y坐标系，其中，Y方向可以为第一方向，X方向可以为第二方向；例如，X方向可以为水平方向，Y方向可以为竖直方向。In each plan layout diagram of the present disclosure, an X-Y coordinate system is drawn, wherein the Y direction may be a first direction and the X direction may be a second direction; for example, the X direction may be a horizontal direction and the Y direction may be a vertical direction.

在本公开至少一实施例中，将所述跨线部和多条所述第二子信号线中的至少部分第二子信号线包括的信号连接线部之间设置为间隔至少两层绝缘层；和/或，将所述信号连接线部设置为包括多条沿第一方向延伸的信号连接线部分，并将所述信号连接线部分沿第二方向的宽度设置为小于宽度阈值，以在不影响MOS结构，或者引起膜层应力失配等问题的前提下，改善第一信号线短路不良问题。In at least one embodiment of the present disclosure, the signal connection line portion included in the cross-line portion and at least part of the second sub-signal lines among the plurality of second sub-signal lines is arranged to be separated by at least two insulating layers; and/or the signal connection line portion is arranged to include a plurality of signal connection line portions extending along the first direction, and the width of the signal connection line portion along the second direction is set to be less than a width threshold, so as to improve the short circuit problem of the first signal line without affecting the MOS structure or causing problems such as film layer stress mismatch.

在本公开至少一实施例中，所述宽度阈值大于或等于5μm而小于或等于8μm。In at least one embodiment of the present disclosure, the width threshold is greater than or equal to 5 μm and less than or equal to 8 μm.

在具体实施时，所述宽度阈值可以大于或等于5μm而小于或等于8μm，例如，所述宽度阈值可以为6μm；但不以此为限。In a specific implementation, the width threshold may be greater than or equal to 5 μm and less than or equal to 8 μm. For example, the width threshold may be 6 μm; but the present invention is not limited thereto.

在本公开至少一实施例中，所述第一信号线可以分为两类：In at least one embodiment of the present disclosure, the first signal lines can be divided into two categories:

第一类是包括跨线部的第一子信号线；The first type is a first sub-signal line including a cross-line portion;

第二类是不包括跨线部的第二子信号线。The second type is a second sub-signal line that does not include a cross-line portion.

可选的，所述第一信号线可以为时钟信号线，但不以此为限。Optionally, the first signal line may be a clock signal line, but is not limited thereto.

在具体实施时，所述第一信号线也可以为其他类型的信号线，本公开至少一实施例也可适用于显示面板中的其他过孔搭接的场景。In a specific implementation, the first signal line may also be a signal line of other types, and at least one embodiment of the present disclosure may also be applicable to other via-hole overlapping scenarios in a display panel.

在本公开至少一实施例中，所述第一导电层可以为遮光金属层，所述第二导电层可以为栅金属层，所述第三导电层可以为源漏金属层； In at least one embodiment of the present disclosure, the first conductive layer may be a light shielding metal layer, the second conductive layer may be a gate metal layer, and the third conductive layer may be a source-drain metal layer;

所述遮光金属层和所述栅金属层之间可以设置有缓冲层和栅绝缘层，所述缓冲层设置于所述栅绝缘层和所述遮光金属层之间，在所述栅金属层和所述源漏金属层之间可以设置有层间介质层；A buffer layer and a gate insulating layer may be provided between the light-shielding metal layer and the gate metal layer, the buffer layer is provided between the gate insulating layer and the light-shielding metal layer, and an interlayer dielectric layer may be provided between the gate metal layer and the source-drain metal layer;

所述跨线部可以位于所述第三导电层，所述信号连接线可以位于第一导电层，在所述跨线部和所述信号连接线之间可以设置有缓冲层和层间介质层。The line-jumping portion may be located in the third conductive layer, the signal connection line may be located in the first conductive layer, and a buffer layer and an interlayer dielectric layer may be provided between the line-jumping portion and the signal connection line.

在本公开至少一实施例中，所述第一导电层可以包括设置于所述显示区域的遮光图形，所述第二导电层可以包括设置于所述显示区域的栅线，所述第三导电层可以包括设置于所述显示区域的数据线。In at least one embodiment of the present disclosure, the first conductive layer may include a light shielding pattern disposed in the display area, the second conductive layer may include a gate line disposed in the display area, and the third conductive layer may include a data line disposed in the display area.

如图1所示，第一条第一信号线包括跨线部LK1和第一信号连接线部LX1；As shown in FIG1 , the first first signal line includes a cross-line portion LK1 and a first signal connection line portion LX1 ;

第二条第一信号线包括第二信号连接线部LX2；The second first signal line includes a second signal connection line portion LX2;

所述跨线部LK1在基底上的正投影与所述第二信号连接线部LX2在所述基底上的正投影部分重叠；The orthographic projection of the cross-line portion LK1 on the substrate partially overlaps with the orthographic projection of the second signal connection line portion LX2 on the substrate;

所述跨线部LK1形成于源漏金属层，所述第一信号连接线部LX1和所述第二信号连接线部LX2形成于遮光金属层；The cross-line portion LK1 is formed in a source-drain metal layer, and the first signal connection line portion LX1 and the second signal connection line portion LX2 are formed in a light shielding metal layer;

所述第一信号连接线部LX1和所述第二信号连接线部LX2沿竖直方向延伸。The first signal connection line portion LX1 and the second signal connection line portion LX2 extend in a vertical direction.

在具体实施时，第一信号线可以设置于显示面板的周边区域，例如，所述第一信号线可以设置于所述显示面板的显示区域的左侧边和/或右侧边，所述第一信号线可以沿竖直方向延伸，但不以此为限。In a specific implementation, the first signal line can be set in the peripheral area of the display panel. For example, the first signal line can be set at the left side and/or right side of the display area of the display panel. The first signal line can extend in the vertical direction, but is not limited to this.

图1是显示面板中的两条第一信号线的至少一实施例的平面布局图，图2是图1中的遮光金属层的平面布局图，图3是图1中的栅金属层的平面布局图，图4是图1中的源漏金属层的平面布局图。Figure 1 is a plan layout diagram of at least one embodiment of two first signal lines in a display panel, Figure 2 is a plan layout diagram of a light-shielding metal layer in Figure 1, Figure 3 is a plan layout diagram of a gate metal layer in Figure 1, and Figure 4 is a plan layout diagram of a source-drain metal layer in Figure 1.

在本公开至少一实施例中，所述第一信号线还包括信号主体线部；In at least one embodiment of the present disclosure, the first signal line further includes a signal main line portion;

在具体实施时，所述第一信号线还可以包括信号主体线部；In a specific implementation, the first signal line may further include a signal main line portion;

所述信号主体线部可以包括第一主体线部分、第二主体线部分和第三主体线部分，所述第一主体线部分可以位于第一导电层，所述第二主体线部分可以位于第二导电层，所述第三主体线部分可以位于第三导电层；所述第三主体线部分可以通过第一过孔与第二主体线部分电连接。The signal main line portion may include a first main line portion, a second main line portion and a third main line portion, the first main line portion may be located in a first conductive layer, the second main line portion may be located in a second conductive layer, and the third main line portion may be located in a third conductive layer; the third main line portion may be electrically connected to the second main line portion through a first via.

如图1-4所示，所述第一条第一信号线还包括第一信号主体线部ZX1，所述第二条第一信号线还包括第二信号主体线部ZX2；As shown in FIG. 1-4 , the first first signal line further includes a first signal main line portion ZX1 , and the second first signal line further includes a second signal main line portion ZX2 ;

所述第一信号主体线部可以包括第一主体线部分ZXB1、第二主体线部分ZXB2和第三主体线部分ZXB3；The first signal main line portion may include a first main line portion ZXB1, a second main line portion ZXB2, and a The third main line part is ZXB3;

ZXB1位于遮光金属层，ZXB2位于栅金属层，ZXB3位于源漏金属层；ZXB1 is located in the light shielding metal layer, ZXB2 is located in the gate metal layer, and ZXB3 is located in the source and drain metal layer;

所述第三主体线部分ZXB3通过第一过孔H1与所述第二主体线部分ZXB2电连接。The third body line portion ZXB3 is electrically connected to the second body line portion ZXB2 through a first via hole H1.

在本公开至少一实施例中，所述第一信号线还包括信号导接线部；In at least one embodiment of the present disclosure, the first signal line further includes a signal conducting line portion;

在具体实施时，所述第一信号线还可以包括信号导接线部；所述信号导接线部可以设置于信号主体线部与信号连接线部之间；所述信号导接线部可以包括第一导接线部分和第二导接线部分，所述第一导接线部分可以位于所述第一导电层，所述第二导接线部分可以位于第三导电层；所述第一导接线部分可以通过第二过孔与所述第二导接线部分电连接。In a specific implementation, the first signal line may also include a signal conducting wire portion; the signal conducting wire portion may be arranged between the signal main line portion and the signal connecting line portion; the signal conducting wire portion may include a first conducting wire portion and a second conducting wire portion, the first conducting wire portion may be located in the first conductive layer, and the second conducting wire portion may be located in the third conductive layer; the first conducting wire portion may be electrically connected to the second conducting wire portion through a second via.

在本公开至少一实施例中，所述信号连接线部、所述第一主体线部分和所述第一导接线部分电连接，所述第三主体线部分和所述第二导接线部分电连接。In at least one embodiment of the present disclosure, the signal connection line portion, the first main body line portion, and the first conductive line portion are electrically connected, and the third main body line portion and the second conductive line portion are electrically connected.

在具体实施时，所述信号连接线部、所述第一主体线部分和所述第一导接线部分可以相互电连接，所述第三主体线部分和所述第二导接线部分可以相互电连接。In a specific implementation, the signal connection line portion, the first main body line portion and the first conductive line portion may be electrically connected to each other, and the third main body line portion and the second conductive line portion may be electrically connected to each other.

如图1-图4所示，所述第一条第一信号线可以包括第一信号导接线部DX1；所述第二条第一信号线可以包括第二信号导接线部DX2；As shown in FIG. 1 to FIG. 4 , the first first signal line may include a first signal conducting line portion DX1; the second first signal line may include a second signal conducting line portion DX2;

DX1设置于ZX1和LX1之间；DX1 is set between ZX1 and LX1;

第一信号导接线部DX1包括第一导接线部分DXB1和第二导接线部分DXB2；DXB1可以位于遮光金属层，DXB2可以位于源漏金属层；DXB1可以通过第二过孔H2与DXB2电连接；The first signal conductive line portion DX1 includes a first conductive line portion DXB1 and a second conductive line portion DXB2; DXB1 may be located in the light shielding metal layer, and DXB2 may be located in the source-drain metal layer; DXB1 may be electrically connected to DXB2 through a second via H2;

所述第一导接线部分DXB1在所述基底上的正投影与所述第二导接线部分DXB2在所述基底上的正投影至少部分重叠；The orthographic projection of the first conductive line portion DXB1 on the substrate at least partially overlaps with the orthographic projection of the second conductive line portion DXB2 on the substrate;

所述信号连接线部LX1、所述第一主体线部分ZXB1和所述第一导接线部分DXB1电连接，所述第三主体线部分ZXB3和所述第二导接线部分DXB2电连接。The signal connection line portion LX1, the first main line portion ZXB1, and the first conductive line portion DXB1 are electrically connected, and the third main line portion ZXB3 and the second conductive line portion DXB2 are electrically connected.

在本公开至少一实施例中，所述跨线部在所述基底上的正投影与所述跨线部所属的第一信号线包括的信号连接线部在所述基底上的正投影部分重叠；In at least one embodiment of the present disclosure, an orthographic projection of the line-jumping portion on the substrate partially overlaps with an orthographic projection of a signal connection line portion included in a first signal line to which the line-jumping portion belongs on the substrate;

如图1-图4所示，所述跨线部LK1在所述基底上的正投影与所述第一信号连接线部LX1在所述基底上的正投影部分重叠；As shown in FIGS. 1 to 4 , the orthographic projection of the cross-line portion LK1 on the substrate partially overlaps with the orthographic projection of the first signal connection line portion LX1 on the substrate;

所述跨线部LK1通过第四过孔H4与所述第一信号连接线部LX1电连接。The cross-line portion LK1 is electrically connected to the first signal connection line portion LX1 through a fourth via hole H4.

图5是图4中的A-A’截面图，图6是图4中的B-B’截面图，图7A是图4中的C-C’ 截面图。FIG. 5 is a cross-sectional view of AA' in FIG. 4, FIG. 6 is a cross-sectional view of BB' in FIG. 4, and FIG. 7A is a cross-sectional view of CC' in FIG. 4 Cross-sectional view.

在图5-图7A中，标号为10的为基底，标号为11的为遮光金属层，标号为12的为缓冲层，标号为13的为栅绝缘层，标号为14的为栅金属层，标号为15的为层间介质层，标号为16的为源漏金属层，标号为17的为第一钝化层，标号为18的为第二钝化层。In Figures 5-7A, number 10 is the substrate, number 11 is the shading metal layer, number 12 is the buffer layer, number 13 is the gate insulating layer, number 14 is the gate metal layer, number 15 is the interlayer dielectric layer, number 16 is the source and drain metal layer, number 17 is the first passivation layer, and number 18 is the second passivation layer.

在图1-图7A所示的至少一实施例中，所述跨线部LK1跨过第二条第一信号线，以引入GOA(Gate On Array，设置于阵列基板上的栅极驱动电路)区域，在原有的层间介质层刻蚀过程中，适当增大刻蚀时间，保证缓冲层连同层间介质层一起被刻蚀掉，即可实现源漏金属层成膜时直接与遮光金属层相连接，完成信号传输。In at least one embodiment shown in FIGS. 1-7A , the cross-line portion LK1 crosses over the second first signal line to introduce a GOA (Gate On Array, a gate driving circuit arranged on an array substrate) area. During the original interlayer dielectric layer etching process, the etching time is appropriately increased to ensure that the buffer layer is etched together with the interlayer dielectric layer, so that the source and drain metal layers can be directly connected to the light-shielding metal layer during film formation to complete signal transmission.

在图1-图7A所示的至少一实施例中，第一条第一信号线与第二条第一信号线之间间距约为7μm，所述第一主体线部分ZXB1的沿水平方向的宽度可以约为17μm，所述第二主体线部分ZXB2沿水平方向的宽度可以约为14.6μm，所述第三主体线部分ZXB3沿水平方向的宽度可以约为11.2μm；基于三层结构的信号主体线部的阻抗降低，可以适当减小各主体线部分的沿水平方向的宽度，从而减小边框宽度；例如，各主体线部分的沿水平方向的宽度可以与相关技术相比减小3.5μm左右，一定程度上有利于减小边框宽度。In at least one embodiment shown in FIGS. 1-7A , a spacing between the first first signal line and the second first signal line is about 7 μm, a width of the first main line portion ZXB1 along the horizontal direction may be about 17 μm, a width of the second main line portion ZXB2 along the horizontal direction may be about 14.6 μm, and a width of the third main line portion ZXB3 along the horizontal direction may be about 11.2 μm; based on the impedance reduction of the signal main line portion of the three-layer structure, the width of each main line portion along the horizontal direction may be appropriately reduced, thereby reducing the border width; for example, the width of each main line portion along the horizontal direction may be reduced by about 3.5 μm compared with the related art, which is beneficial to reducing the border width to a certain extent.

在图1-图7A所示的至少一实施例中，所述跨线部LK1与所述第一信号连接线部LX1之间间隔的绝缘层为缓冲层和层间介质层，LK1与LX1之间的绝缘层的总厚度约为8000埃米，相较于相关技术，该绝缘层的总厚度增加了一倍，可以有效改善第一信号线AD问题；同时，第一信号线的三层金属结构也可以减小第一信号线的电阻，减小信号负载。In at least one embodiment shown in Figures 1-7A, the insulating layer between the cross-line portion LK1 and the first signal connection line portion LX1 is a buffer layer and an interlayer dielectric layer. The total thickness of the insulating layer between LK1 and LX1 is about 8000 angstroms. Compared with the related art, the total thickness of the insulating layer is doubled, which can effectively improve the AD problem of the first signal line; at the same time, the three-layer metal structure of the first signal line can also reduce the resistance of the first signal line and reduce the signal load.

在图1-图7A所示的至少一实施例中，尽管源漏金属层爬坡高度增加，但是Taper角(坡度角)可以通过工艺参数控制，不会发生源漏金属层爬坡断线。在具体实施时，缓冲层的厚度、第一钝化层的厚度、第二钝化层的厚度可以分别为4500埃米、3000埃米、2000埃米，源漏金属层的厚度在3300埃米至3500埃米之间，不会发生源漏金属层爬坡断线的问题。In at least one embodiment shown in FIG. 1 to FIG. 7A , although the source-drain metal layer climbing height increases, the Taper angle (slope angle) can be controlled by process parameters, and the source-drain metal layer climbing disconnection will not occur. In a specific implementation, the thickness of the buffer layer, the thickness of the first passivation layer, and the thickness of the second passivation layer can be 4500 angstroms, 3000 angstroms, and 2000 angstroms, respectively, and the thickness of the source-drain metal layer is between 3300 angstroms and 3500 angstroms, and the source-drain metal layer climbing disconnection problem will not occur.

当采用图1-图7A所示的至少一实施例时，改变了显示面板的左边框和右边框的厚度，增加的厚度为遮光金属层的厚度，该厚度为3300埃米，因此为了保证显示面板的整体盒厚一致，可以在显示面板的上边框和下边框都增加遮光金属层，在显示面板的上边框和下边框，可以将原本的单层布线改为双层布线，将原本的双层布线改为三层布线，或者在端子侧和底侧的封框区做dummy(伪)三层结构(dummy伪三层结构包括形成于遮光金属层的导电图形、形成于栅金属层的导电图形，以及，形成于源漏金属层的导电图形)，以保证整体盒厚。When at least one embodiment shown in Figures 1-7A is adopted, the thickness of the left and right frames of the display panel is changed. The increased thickness is the thickness of the light-shielding metal layer, which is 3300 angstroms. Therefore, in order to ensure the consistency of the overall box thickness of the display panel, a light-shielding metal layer can be added to the upper and lower frames of the display panel. In the upper and lower frames of the display panel, the original single-layer wiring can be changed to double-layer wiring, and the original double-layer wiring can be changed to triple-layer wiring, or a dummy three-layer structure can be made in the sealing area on the terminal side and the bottom side (the dummy pseudo three-layer structure includes a conductive pattern formed on the light-shielding metal layer, a conductive pattern formed on the gate metal layer, and a conductive pattern formed on the source and drain metal layer) to ensure the overall box thickness.

在制作图1-图7A所示的至少一实施例中的第一信号线时，具体改善工艺如下：When manufacturing the first signal line in at least one embodiment shown in FIG. 1 to FIG. 7A , the specific improvement process is as follows:

1、遮光金属层成膜并刻蚀，得到图8所示pattern(图形)；1. The light-shielding metal layer is formed into a film and etched to obtain the pattern shown in FIG8 ;

2、缓冲层成膜，栅绝缘层成膜，栅金属层成膜并刻蚀，以栅金属层为掩膜版刻蚀栅绝缘层，得到图9所示pattern；2. Forming a buffer layer, forming a gate insulating layer, forming a gate metal layer and etching the gate insulating layer, and using the gate metal layer as a mask to etch the gate insulating layer to obtain the pattern shown in FIG. 9;

3、层间介质层成膜，并在图10所示位置增大刻蚀时间开孔，作出遮光金属层与栅金属层以及源漏金属层搭接孔；3. Form the interlayer dielectric layer, increase the etching time and open holes at the position shown in Figure 10 to make the light shielding metal layer and the gate gold Metal layer and source and drain metal layer overlapping holes;

4、源漏金属层成膜并刻蚀，得到图11所示pattern；4. Form the source and drain metal layer and etch it to obtain the pattern shown in FIG11;

后续步骤为第一钝化层成膜、第二钝化层成膜，与相关技术中的工序没有差异。The subsequent steps are forming a first passivation layer and forming a second passivation layer, which are no different from the processes in the related art.

以上各步骤的断面图如图12A、图12B、图12C、图12D、图12E、图12F和图12G所示。The cross-sectional views of the above steps are shown in FIG. 12A , FIG. 12B , FIG. 12C , FIG. 12D , FIG. 12E , FIG. 12F , and FIG. 12G .

如图12A所示，在基底10上进行遮光金属层成膜、刻蚀，以及缓冲层成膜；As shown in FIG. 12A , a light shielding metal layer is formed and etched, and a buffer layer is formed on the substrate 10 ;

如图12B所示，进行栅绝缘层成膜、栅金属层成膜；As shown in FIG. 12B , a gate insulating layer and a gate metal layer are formed;

如图12C所示，对栅金属层进行刻蚀，并以栅金属层为掩膜版刻蚀栅绝缘层；As shown in FIG. 12C , the gate metal layer is etched, and the gate insulating layer is etched using the gate metal layer as a mask;

如图12D所示，进行层间介质层成膜；As shown in FIG. 12D , the interlayer dielectric layer is formed;

如图12E所示，对所述层间介质层进行刻蚀；As shown in FIG. 12E , the interlayer dielectric layer is etched;

如图12F所示，进行源漏金属层成膜并刻蚀；As shown in FIG. 12F , the source and drain metal layers are formed and etched;

如图12G所示，进行第一钝化层成膜和第二钝化层成膜。As shown in FIG. 12G , the first passivation layer and the second passivation layer are formed.

如图7B所示，在周边区域ZY，设置有图1所示的两条第一信号线，在显示区域AA，设置有栅线GL、数据线DL和子像素中的晶体管；As shown in FIG. 7B , the two first signal lines shown in FIG. 1 are disposed in the peripheral area ZY, and the gate line GL, the data line DL and the transistors in the sub-pixel are disposed in the display area AA;

在图7B中，标号为ZX的为遮光图形，标号为A1的为所述晶体管的有源图形，标号为VCOM的为公共电极，标号为PX的为像素电极。In FIG. 7B , the light shielding pattern denoted by ZX, the active pattern denoted by A1 is the transistor, the common electrode denoted by VCOM, and the pixel electrode denoted by PX.

在图7B对应的至少一实施例中，遮光图形ZX位于遮光金属层，所述晶体管的有源图形A1位于半导体层，像素电极PX位于像素电极层，公共电极VCOM位于公共电极层，栅线GL位于栅金属层，数据线DL位于源漏金属层。In at least one embodiment corresponding to FIG. 7B , the shading pattern ZX is located in the shading metal layer, the active pattern A1 of the transistor is located in the semiconductor layer, the pixel electrode PX is located in the pixel electrode layer, the common electrode VCOM is located in the common electrode layer, the gate line GL is located in the gate metal layer, and the data line DL is located in the source and drain metal layer.

图7C是图7B中的K-K’截面图。Fig. 7C is a cross-sectional view taken along line K-K' in Fig. 7B.

在图7C中，标号为10的为基底，标号为11的为遮光金属层，标号为12的为缓冲层，标号为21的为半导体层，标号为13的为栅绝缘层，标号为14的为栅金属层，标号为15的为层间介质层，标号为16的为源漏金属层，标号为17的为第一钝化层，标号为22的为有机层，标号为111的为公共电极层，标号为18的为第二钝化层，标号为19的为像素电极层。在相关技术中，玻璃大板整面的栅绝缘层干刻可能导致栅绝缘层的Taper角不良甚至过刻，从而导致后续的层间介质层发生断裂，导致源漏金属层成膜时深入层间介质层断裂处，进而使得源漏金属层和栅金属层局部间距缩短，从而使得源漏金属层-层间介质层-栅金属层的电容结构容易被击穿，增大Cu互连发生的几率。为了避免栅绝缘层干刻引起的栅绝缘层taper角不佳和栅绝缘层干刻的问题，在本公开至少一实施例中，第一信号线可以采用双层金属结构，可以将信号主体线部设置为包括第一主体线部分和第二主体线部分，所述第一主体线部分可以位于第一导电层，所述第二主体线部分可以位于第三导电层。In Figure 7C, number 10 is the substrate, number 11 is the shading metal layer, number 12 is the buffer layer, number 21 is the semiconductor layer, number 13 is the gate insulating layer, number 14 is the gate metal layer, number 15 is the interlayer dielectric layer, number 16 is the source and drain metal layer, number 17 is the first passivation layer, number 22 is the organic layer, number 111 is the common electrode layer, number 18 is the second passivation layer, and number 19 is the pixel electrode layer. In the related art, dry etching of the gate insulating layer on the entire surface of a large glass plate may result in a poor taper angle of the gate insulating layer or even over-etching, thereby causing the subsequent interlayer dielectric layer to break, causing the source and drain metal layers to penetrate into the interlayer dielectric layer break when forming a film, thereby shortening the local spacing between the source and drain metal layers and the gate metal layer, making the capacitor structure of the source and drain metal layer-interlayer dielectric layer-gate metal layer easily broken down, increasing the probability of Cu interconnection. In order to avoid the problems of poor taper angle of the gate insulating layer and dry etching of the gate insulating layer caused by dry etching of the gate insulating layer, in at least one embodiment of the present disclosure, the first signal line can adopt a double-layer metal structure, and the signal main line portion can be set to include a first main line portion and a second main line portion, the first main line portion can be located in the first conductive layer, and the second main line portion can be located in the third conductive layer.

在本公开至少一实施例中，所述多信号线还包括信号主体线部；In at least one embodiment of the present disclosure, the multi-signal line further includes a signal main body line portion;

所述第一主体线部分通过第三过孔与所述第二主体线部分电连接； The first main body line portion is electrically connected to the second main body line portion through a third via;

在具体实施时，所述第一信号线还可以包括信号主体线部，所述信号主体线部可以包括第一主体线部分和第二主体线部分；In a specific implementation, the first signal line may further include a signal main line portion, and the signal main line portion may include a first main line portion and a second main line portion;

可选的，所述第一主体线部分位于所述第一导电层，所述第二主体线部分形成所述第三导电层。Optionally, the first main line portion is located in the first conductive layer, and the second main line portion forms the third conductive layer.

在本公开至少一实施例中，所述信号连接线部与所述第一主体线部分电连接。In at least one embodiment of the present disclosure, the signal connection line portion is electrically connected to the first main body line portion.

如图13所示，第一条第一信号线包括跨线部LK1和第一信号连接线部LX1；As shown in FIG13 , the first first signal line includes a cross-line portion LK1 and a first signal connection line portion LX1 ;

图13是显示面板中的两条第一信号线的至少一实施例的平面布局图，图14是图13中的遮光金属层的平面布局图，图15是图13中的源漏金属层的平面布局图。13 is a plan layout diagram of at least one embodiment of two first signal lines in a display panel, FIG. 14 is a plan layout diagram of a light shielding metal layer in FIG. 13 , and FIG. 15 is a plan layout diagram of a source-drain metal layer in FIG. 13 .

如图13-15所示，所述第一条第一信号线还包括第一信号主体线部ZX1，所述第二条第一信号线还包括第二信号主体线部ZX2；As shown in FIGS. 13-15 , the first first signal line further includes a first signal main line portion ZX1 , and the second first signal line further includes a second signal main line portion ZX2 ;

所述第一信号主体线部可以包括第一主体线部分ZXB1和第二主体线部分ZXB2；The first signal main body line portion may include a first main body line portion ZXB1 and a second main body line portion ZXB2;

ZXB1位于遮光金属层，ZXB2位于源漏金属层；ZXB1 is located in the light shielding metal layer, and ZXB2 is located in the source and drain metal layer;

所述第一主体线部分ZXB1通过第三过孔H3与所述第二主体线部分ZXB2电连接；The first main body line portion ZXB1 is electrically connected to the second main body line portion ZXB2 through a third via H3;

所述第一主体线部分ZXB1在所述基底上的正投影和所述第二主体线部分ZXB2在所述基底上的正投影至少部分重叠。An orthographic projection of the first body line portion ZXB1 on the substrate and an orthographic projection of the second body line portion ZXB2 on the substrate at least partially overlap.

图16是图13中的D-D’截面图。Fig. 16 is a cross-sectional view taken along line D-D' in Fig. 13 .

在图16中，标号为10的为基底，标号为11的为遮光金属层，标号为12的为缓冲层，标号为15的为层间介质层，标号为16的为源漏金属层，标号为17的为第一钝化层，标号为18的为第二钝化层。In Figure 16, the number 10 is the substrate, the number 11 is the shading metal layer, the number 12 is the buffer layer, the number 15 is the interlayer dielectric layer, the number 16 is the source and drain metal layer, the number 17 is the first passivation layer, and the number 18 is the second passivation layer.

在具体实施时，除了源漏金属层与遮光金属层直接相连的方案，也可以采用像素电极层搭接源漏金属层和遮光金属层的方案。In specific implementation, in addition to the solution of directly connecting the source-drain metal layer to the light-shielding metal layer, a solution of overlapping the source-drain metal layer and the light-shielding metal layer with the pixel electrode layer may also be adopted.

在本公开至少一实施例中，所述显示面板还包括设置于所述第三导电层远离所述基底一侧的第四导电层；In at least one embodiment of the present disclosure, the display panel further includes a fourth conductive layer disposed on a side of the third conductive layer away from the substrate;

所述第一信号线还包括信号主体线部； The first signal line also includes a signal main line portion;

所述第三主体线部分通过第五过孔与所述第二主体线部分电连接，所述第三主体线部分通过第六过孔与所述第一主体线部分电连接。The third body line portion is electrically connected to the second body line portion through a fifth via hole, and the third body line portion is electrically connected to the first body line portion through a sixth via hole.

在本公开至少一实施例中，所述第四导电层可以包括设置于所述显示区域的像素电极。In at least one embodiment of the present disclosure, the fourth conductive layer may include a pixel electrode disposed in the display area.

可选的，所述第一主体线部分位于所述第一导电层，所述第二主体线部分形成所述第三导电层，所述第三主体线部分位于所述第四导电层。Optionally, the first main line portion is located in the first conductive layer, the second main line portion forms the third conductive layer, and the third main line portion is located in the fourth conductive layer.

在本公开至少一实施例中，所述第四导电层可以为像素电极层，所述像素电极层例如可以由ITO(氧化铟锡)制成，所述像素电极层可以设置于第二钝化层远离源漏金属层的一侧。In at least one embodiment of the present disclosure, the fourth conductive layer may be a pixel electrode layer, which may be made of, for example, ITO (indium tin oxide), and may be disposed on a side of the second passivation layer away from the source-drain metal layer.

图17是显示面板中的两条第一信号线的至少一实施例的平面布局图，图18是图17中的遮光金属层的平面布局图，图19是图17中的源漏金属层的平面布局图，图20是图17中的像素电极层的平面布局图。Figure 17 is a plan layout diagram of at least one embodiment of two first signal lines in the display panel, Figure 18 is a plan layout diagram of the light-shielding metal layer in Figure 17, Figure 19 is a plan layout diagram of the source and drain metal layer in Figure 17, and Figure 20 is a plan layout diagram of the pixel electrode layer in Figure 17.

如图17-图20所示，第一条第一信号线包括第一信号主体线部ZX1，所述第二条第一信号线包括第二信号主体线部ZX2；As shown in FIGS. 17 to 20 , the first first signal line includes a first signal main line portion ZX1 , and the second first signal line includes a second signal main line portion ZX2 ;

所述第一信号主体线部可以包括第一主体线部分ZXB1、第二主体线部分ZXB2和第三主体线部分ZXB3；The first signal main body line portion may include a first main body line portion ZXB1, a second main body line portion ZXB2, and a third main body line portion ZXB3;

ZXB1可以位于遮光金属层，ZXB2可以位于源漏金属层，ZXB3可以位于像素电极层；ZXB1 may be located at the light shielding metal layer, ZXB2 may be located at the source and drain metal layer, and ZXB3 may be located at the pixel electrode layer;

所述第三主体线部分ZXB3在所述基底上的正投影与所述第一主体线部分ZXB1在所述基底上的正投影至少部分重叠，所述第三主体线部分ZXB3在所述基底上的正投影与所述第二主体线部分ZXB2在所述基底上的正投影至少部分重叠；The orthographic projection of the third main body line portion ZXB3 on the substrate at least partially overlaps with the orthographic projection of the first main body line portion ZXB1 on the substrate, and the orthographic projection of the third main body line portion ZXB3 on the substrate at least partially overlaps with the orthographic projection of the second main body line portion ZXB2 on the substrate;

所述第三主体线部分ZXB3通过第五过孔H5与所述第二主体线部分ZXB2电连接，所述第三主体线部分ZXB3通过第六过孔H6与所述第一主体线部分ZXB1电连接。The third body line portion ZXB3 is electrically connected to the second body line portion ZXB2 through a fifth via hole H5 , and the third body line portion ZXB3 is electrically connected to the first body line portion ZXB1 through a sixth via hole H6 .

在本公开至少一实施例中，所述第一信号线还包括第一转接部；所述第一转接部在所述基底上的正投影与所述跨线部所属的第一信号线包括的信号连接线部在所述基底上的正投影至少部分重叠；所述第一转接部在所述基底上的正投影与所述跨线部在所述基底上的正投影至少部分重叠；In at least one embodiment of the present disclosure, the first signal line further includes a first transition portion; the orthographic projection of the first transition portion on the substrate at least partially overlaps with the orthographic projection of the signal connection line portion included in the first signal line to which the cross-line portion belongs on the substrate; the orthographic projection of the first transition portion on the substrate at least partially overlaps with the orthographic projection of the cross-line portion on the substrate;

所述第一转接部与所述信号连接线位于不同层，所述第一转接部与所述跨线部位于不同的导电层。 The first transfer portion and the signal connection line are located in different layers, and the first transfer portion and the cross-line portion are located in different conductive layers.

在具体实施时，所述第一信号线还可以包括第一转接部，所述第一转接部可以通过第七过孔与该信号连接线部电连接，所述第一转接部可以通过第八过孔与所述跨线部电连接。In a specific implementation, the first signal line may further include a first transfer portion, the first transfer portion may be electrically connected to the signal connection line portion through a seventh via hole, and the first transfer portion may be electrically connected to the cross-line portion through an eighth via hole.

可选的，所述第一转接部位于所述第四导电层。Optionally, the first transfer portion is located in the fourth conductive layer.

如图17-图20所示，第一条第一信号线包括跨线部LK1和第一信号连接线部LX1；As shown in FIGS. 17 to 20 , the first first signal line includes a cross-line portion LK1 and a first signal connection line portion LX1 ;

所述第一信号连接线部LX1和所述第二信号连接线部LX2沿竖直方向延伸；The first signal connection line portion LX1 and the second signal connection line portion LX2 extend in a vertical direction;

所述第一条第一信号线还包括第一转接部ZJ1；The first first signal line also includes a first switching portion ZJ1;

所述第一转接部ZJ1位于像素电极层；The first connecting portion ZJ1 is located at the pixel electrode layer;

所述第一转接部ZJ1在所述基底上的正投影与所述第一信号连接线部LX1在所述基底上的正投影至少部分重叠；所述第一转接部ZJ1在所述基底上的正投影与所述跨线部LX1在所述基底上的正投影至少部分重叠；The orthographic projection of the first transition portion ZJ1 on the substrate at least partially overlaps with the orthographic projection of the first signal connection line portion LX1 on the substrate; the orthographic projection of the first transition portion ZJ1 on the substrate at least partially overlaps with the orthographic projection of the cross-line portion LX1 on the substrate;

所述第一转接部ZJ1通过第七过孔H7与所述第一信号连接线部LX1电连接，所述第一转接部ZJ1通过第八过孔H8与所述跨线部LK1电连接。The first adapter portion ZJ1 is electrically connected to the first signal connection line portion LX1 through the seventh via hole H7 , and the first adapter portion ZJ1 is electrically connected to the cross-line portion LK1 through the eighth via hole H8 .

图21是图17中的E-E’截面图。FIG21 is a cross-sectional view taken along line E-E’ in FIG17 .

如图17-图21所示，制作图17所示的第一信号线的具体流程与相关的流程基本一致，即层间介质层刻蚀时间不做改变，采用套孔(层间介质层孔+钝化层孔)的形式在遮光金属层上方作出搭孔的区域，在源漏金属层上方开钝化层孔，从而使得像素电极层成膜时，将遮光金属层和源漏金属层搭接在一起，并像素电极层爬坡完好。As shown in Figures 17 to 21, the specific process of making the first signal line shown in Figure 17 is basically consistent with the relevant process, that is, the etching time of the interlayer dielectric layer does not change, and a overlapping hole area is made above the light-shielding metal layer in the form of a sleeve hole (interlayer dielectric layer hole + passivation layer hole), and a passivation layer hole is opened above the source and drain metal layer, so that when the pixel electrode layer is formed, the light-shielding metal layer and the source and drain metal layer are overlapped together, and the pixel electrode layer is well climbed.

在图21中，标号为10的为基底，标号为11的为遮光金属层，标号为12的为缓冲层，标号为15的为层间介质层，标号为16的为源漏金属层，标号为17的为第一钝化层，标号为18的为第二钝化层，标号为19的为像素电极层。In Figure 21, labeled 10 is the substrate, labeled 11 is the shading metal layer, labeled 12 is the buffer layer, labeled 15 is the interlayer dielectric layer, labeled 16 is the source and drain metal layer, labeled 17 is the first passivation layer, labeled 18 is the second passivation layer, and labeled 19 is the pixel electrode layer.

在实际操作时，测量了不同线宽的栅金属层对应的栅绝缘层干刻后的栅绝缘层taper角和过刻情况，发现只有当形成于栅金属层的信号连接线部的线宽较大时，才会出现栅绝缘层taper角不佳和栅绝缘层过刻的情况。因此，在本公开至少一实施例中，可以将所述信号连接线部设置为包括多条沿第一方向延伸的信号连接线部分，并将所述信号连接线部分沿第二方向的宽度小于宽度阈值；例如，所述信号连接线部分的线宽可以大于或等于4μm而小于或等于6μm，以保证第一信号线总体的方阻处于原本水平。In actual operation, the gate insulating layer taper angle and over-etching of the gate insulating layer after dry etching of the gate metal layer corresponding to different line widths were measured, and it was found that only when the line width of the signal connection line portion formed in the gate metal layer is large, the gate insulating layer taper angle is poor and the gate insulating layer is over-etched. Therefore, in at least one embodiment of the present disclosure, the signal connection line portion can be set to include a plurality of signal connection line portions extending along the first direction, and the width of the signal connection line portion along the second direction is less than the width threshold; for example, the line width of the signal connection line portion can be greater than or equal to 4μm and less than or equal to 6μm, so as to ensure that the overall square resistance of the first signal line is at the original level.

图22是显示面板中的两条第一信号线的至少一实施例的平面布局图，图23是图22中的栅金属层的平面布局图，图24是图22中的源漏金属层的平面布局图。22 is a plan layout diagram of at least one embodiment of two first signal lines in a display panel, FIG. 23 is a plan layout diagram of a gate metal layer in FIG. 22 , and FIG. 24 is a plan layout diagram of a source/drain metal layer in FIG. 22 .

如图22-图24所示，第一条第一信号线包括跨线部LK1和第一信号连接线部LX1；As shown in FIGS. 22 to 24 , the first first signal line includes a cross-line portion LK1 and a first signal connection line portion LX1 ;

第二条第一信号线包括第二信号连接线部LX2； The second first signal line includes a second signal connection line portion LX2;

LK1位于源漏金属层，LX1和LX2形成于栅金属层；LK1 is located in the source and drain metal layer, and LX1 and LX2 are formed in the gate metal layer;

所述第二信号连接线部包括第一信号连接线部分LXB1、第二信号连接线部分LXB2和第三信号连接线部分LXB3；The second signal connection line portion includes a first signal connection line portion LXB1, a second signal connection line portion LXB2 and a third signal connection line portion LXB3;

LXB1、LXB2和LXB3都沿竖直方向延伸，LXB1、LXB2和LXB3都位于栅金属层；LXB1, LXB2 and LXB3 all extend in the vertical direction, and LXB1, LXB2 and LXB3 are all located in the gate metal layer;

LXB1沿水平方向的宽度、LXB2沿水平方向的宽度和LXB3沿水平方向的宽度可以大于或等于4μm而小于或等于6μm；The width of LXB1 along the horizontal direction, the width of LXB2 along the horizontal direction, and the width of LXB3 along the horizontal direction may be greater than or equal to 4 μm and less than or equal to 6 μm;

LK1在基底上的正投影与LXB1在基底上的正投影部分重叠，LK1在基底上的正投影与LXB2在基底上的正投影部分重叠，LK1在基底上的正投影与LXB3在基底上的正投影部分重叠。The orthographic projection of LK1 on the substrate partially overlaps with the orthographic projection of LXB1 on the substrate, the orthographic projection of LK1 on the substrate partially overlaps with the orthographic projection of LXB2 on the substrate, and the orthographic projection of LK1 on the substrate partially overlaps with the orthographic projection of LXB3 on the substrate.

如图22-图24所示，第一条第一信号线包括第一信号主体线部ZX1，所述第二条第一信号线包括第二信号主体线部ZX2；As shown in FIGS. 22 to 24 , the first first signal line includes a first signal main line portion ZX1 , and the second first signal line includes a second signal main line portion ZX2 ;

ZXB1位于栅金属层，ZXB2位于源漏金属层；ZXB1 is located at the gate metal layer, and ZXB2 is located at the source and drain metal layer;

ZXB1通过过孔与ZXB2电连接，跨线部LK1通过过孔与LX1电连接，LK1在基底上的正投影与LX1在基底上的正投影部分重叠。ZXB1 is electrically connected to ZXB2 through a via hole, and the cross-line portion LK1 is electrically connected to LX1 through a via hole. The orthographic projection of LK1 on the substrate partially overlaps with the orthographic projection of LX1 on the substrate.

在如上实施例中，第一信号线可以为应用于显示面板，所述显示面板中的GOA电路包括Top-gate(顶栅)self-alignment(自对齐)TFT(薄膜晶体管)。In the above embodiment, the first signal line may be applied to a display panel, and the GOA circuit in the display panel includes a Top-gate self-alignment TFT (thin film transistor).

在本公开至少一实施例中，第一信号线的结构可以应用于显示面板，所述显示面板中的GOA电路可以包括具有金属辅助层的BCE(背沟道刻蚀型)TFT。In at least one embodiment of the present disclosure, the structure of the first signal line may be applied to a display panel, and a GOA circuit in the display panel may include a BCE (back channel etched) TFT having a metal auxiliary layer.

在具有金属辅助层的BCE(背沟道刻蚀型)TFT中，可以在BCE TFT中新增金属辅助层，成为M3层，M3层直接堵在公共电极层上，所述公共电极层例如可以由ITO制成，以减小公共电极层方阻，从而减少crosstalk(串扰)不良，提升显示产品良率。本公开至少一实施例可以利用M3工艺改善第一信号线AD不良的方案，即在第一信号线区域，可以将跨线部设置为位于金属辅助层，以使得跨线部与信号连接线部之间间隔至少一层绝缘层，增加跨线部与信号连接线部之间的绝缘层厚度，减小第一信号线AD发生率。In a BCE (back channel etched) TFT with a metal auxiliary layer, a metal auxiliary layer can be added to the BCE TFT to become an M3 layer. The M3 layer is directly blocked on the common electrode layer. The common electrode layer can be made of ITO, for example, to reduce the square resistance of the common electrode layer, thereby reducing crosstalk defects and improving the yield of display products. At least one embodiment of the present disclosure can use the M3 process to improve the solution of the first signal line AD defect, that is, in the first signal line area, the cross-line portion can be set to be located in the metal auxiliary layer, so that at least one insulating layer is separated between the cross-line portion and the signal connection line portion, and the thickness of the insulating layer between the cross-line portion and the signal connection line portion is increased, and the first signal line AD occurrence rate is reduced.

在本公开至少一实施例中，所述显示面板包括沿着远离所述基底依次排列的第二导电层、第三导电层、第五导电层、第六导电层和第四导电层；所述第五导电层与所述第六导电层搭接；所述第二导电层与所述第三导电层之间设置有至少一层绝缘层，所述第三导电层与所述第五导电层之间设置有至少一层绝缘层，所述第六导电层与所述第四导电层之间设置有至少一层绝缘层；In at least one embodiment of the present disclosure, the display panel includes a second conductive layer, a third conductive layer, a fifth conductive layer, a sixth conductive layer and a fourth conductive layer arranged in sequence away from the substrate; the fifth conductive layer is overlapped with the sixth conductive layer; at least one insulating layer is provided between the second conductive layer and the third conductive layer, at least one insulating layer is provided between the third conductive layer and the fifth conductive layer, and at least one insulating layer is provided between the sixth conductive layer and the fourth conductive layer;

在本公开至少一实施例中，所述第二导电层包括设置于所述显示区域的栅线，所述第三导电层包括设置于所述显示区域的数据线，所述第五导电层包括设置于所述显示区域的公共电极，所述第六导电层包括设置于所述显示区域的辅助金属图形。In at least one embodiment of the present disclosure, the second conductive layer includes gate lines arranged in the display area, the third conductive layer includes data lines arranged in the display area, the fifth conductive layer includes common electrodes arranged in the display area, and the sixth conductive layer includes auxiliary metal patterns arranged in the display area.

可选的，所述第二导电层可以为栅金属层，所述第三导电层可以为源漏金属层，所述第五导电层可以为公共电极层，所述第六导电层可以为金属辅助层，所述第四导电层可以为像素电极层；Optionally, the second conductive layer may be a gate metal layer, the third conductive layer may be a source/drain metal layer, The fifth conductive layer may be a common electrode layer, the sixth conductive layer may be a metal auxiliary layer, and the fourth conductive layer may be a pixel electrode layer;

所述公共电极层可以与所述金属辅助层直接搭接；The common electrode layer may be directly overlapped with the metal auxiliary layer;

所述跨线部的至少部分可以位于所述金属辅助层，所述信号连接线部可以为与所述栅金属层，但不以此为限。At least a portion of the cross-line portion may be located in the metal auxiliary layer, and the signal connection line portion may be located in the gate metal layer, but the present invention is not limited thereto.

在本公开至少一实施例中，所述金属辅助层可以由铜制成，所述栅金属层和所述源漏金属层也可以由铜制成，但不以此为限。In at least one embodiment of the present disclosure, the metal auxiliary layer may be made of copper, and the gate metal layer and the source-drain metal layer may also be made of copper, but the present invention is not limited thereto.

如图25-图29A所示，所述第一条第一信号线包括第一信号连接线部LX1和跨线部LK1；As shown in FIG. 25 to FIG. 29A , the first first signal line includes a first signal connection line portion LX1 and a cross-line portion LK1 ;

所述第二条第一信号线包括第二信号连接线部LX2；The second first signal line includes a second signal connection line portion LX2;

LX1和LX2位于栅金属层，LK1位于金属辅助层。LX1 and LX2 are located in the gate metal layer, and LK1 is located in the metal auxiliary layer.

图25所示的至少一实施例简单可行，不会增加Mask(掩膜)数量，可以明显减少第一信号线AD发生率。在图25所示的至少一实施例中，在第一信号跨线区，跨线部LK1与第一信号连接线部LX1之间的绝缘层包括栅绝缘层和第一钝化层，栅绝缘层的厚度、第一钝化层的厚度分别约为4000埃米、5000埃米。本公开至少一实施例将第一信号跨线区的绝缘层厚度增加了一倍以上，可以明显减少铜互连导致的第一信号线AD问题。At least one embodiment shown in FIG25 is simple and feasible, does not increase the number of masks, and can significantly reduce the AD incidence of the first signal line. In at least one embodiment shown in FIG25, in the first signal cross-line area, the insulating layer between the cross-line portion LK1 and the first signal connection line portion LX1 includes a gate insulating layer and a first passivation layer, and the thickness of the gate insulating layer and the thickness of the first passivation layer are approximately 4000 angstroms and 5000 angstroms, respectively. At least one embodiment of the present disclosure increases the thickness of the insulating layer in the first signal cross-line area by more than one time, which can significantly reduce the AD problem of the first signal line caused by copper interconnection.

图26是图25中的栅金属层的平面布局图，图27是图25中的源金属层的平面布局图，图28是图25中的金属辅助层的平面布局图，图29A是图25中的像素电极层的平面布局图。Figure 26 is a plan layout diagram of the gate metal layer in Figure 25, Figure 27 is a plan layout diagram of the source metal layer in Figure 25, Figure 28 is a plan layout diagram of the metal auxiliary layer in Figure 25, and Figure 29A is a plan layout diagram of the pixel electrode layer in Figure 25.

在本公开至少一实施例中，所述金属辅助层的厚度可以约为3000埃米，但不以此为限。In at least one embodiment of the present disclosure, the thickness of the metal auxiliary layer may be approximately 3000 angstroms, but is not limited thereto.

在本公开至少一实施例中，所述第一信号线还包括第一转接部；In at least one embodiment of the present disclosure, the first signal line further includes a first transfer portion;

可选的，第一转接部位于所述第四导电层。Optionally, the first transfer portion is located in the fourth conductive layer.

如图25-图29A所示，所述第一条第一信号线还可以包括第一转接部ZJ1；As shown in FIG. 25 to FIG. 29A , the first first signal line may further include a first transfer portion ZJ1;

所述第一转接部ZJ1可以位于像素电极层；The first transition portion ZJ1 may be located at the pixel electrode layer;

ZJ1通过第九过孔H9与第一信号连接线部LX1电连接，ZJ1通过第十过孔H10与跨线部LK1电连接；ZJ1 is electrically connected to the first signal connection line portion LX1 through the ninth via hole H9, and ZJ1 is electrically connected to the cross-line portion LK1 through the tenth via hole H10;

ZJ1在基底上的正投影与LX1在基底上的正投影部分重叠，ZJ1在基底上的正投影与跨线部LK1在基底上的正投影部分重叠。The orthographic projection of ZJ1 on the substrate partially overlaps with the orthographic projection of LX1 on the substrate, and the orthographic projection of ZJ1 on the substrate partially overlaps with the orthographic projection of the cross-line portion LK1 on the substrate.

在本公开至少一实施例中，所述第一信号线还包括第三转接部和连接线；In at least one embodiment of the present disclosure, the first signal line further includes a third transfer portion and a connecting line;

所述第三转接部通过第十一过孔与所述跨线部电连接，所述第三转接部通过第十二过孔与所述连接线电连接；The third transfer portion is electrically connected to the cross-line portion through the eleventh via hole, and the third transfer portion is electrically connected to the cross-line portion through the twelfth via hole. The hole is electrically connected to the connecting wire;

可选的，所述第三转接部位于所述第四导电层，所述连接线位于所述第三导电层。Optionally, the third transfer portion is located in the fourth conductive layer, and the connecting line is located in the third conductive layer.

在具体实施时，所述第一信号线还可以包括第三转接部和连接线，所述第三转接部可以位于像素电极层，所述连接线可以位于源漏金属层；In a specific implementation, the first signal line may further include a third transfer portion and a connection line, the third transfer portion may be located in the pixel electrode layer, and the connection line may be located in the source-drain metal layer;

所述第三转接部可以通过第十一过孔与所述跨线部电连接，所述第三转接部可以通过第十二过孔与所述连接线电连接；The third adapter portion may be electrically connected to the cross-line portion through an eleventh via hole, and the third adapter portion may be electrically connected to the connection line through a twelfth via hole;

所述连接线可以与GOA电路中的至少一TFT电连接；The connecting line may be electrically connected to at least one TFT in the GOA circuit;

所述第三转接部、第十一过孔和第十二过孔可以设置于第一信号线布线区和GOA TFT(GOA TFT可以为GOA电路中的TFT)分布区之间。The third transfer portion, the eleventh via hole and the twelfth via hole can be arranged between the first signal line wiring area and the GOA TFT (GOA TFT can be a TFT in a GOA circuit) distribution area.

如图25-图29A所示，所述第一条第一信号线还可以包括第三转接部ZJ3和连接线L1；As shown in FIG. 25 to FIG. 29A , the first first signal line may further include a third transition portion ZJ3 and a connection line L1;

所述第三转接部ZJ3位于像素电极层，所述连接线L1位于源漏金属层；The third connecting portion ZJ3 is located at the pixel electrode layer, and the connecting line L1 is located at the source-drain metal layer;

所述第三转接部ZJ3通过第十一过孔H11与所述跨线部LK1电连接，所述第三转接部ZJ3通过第十二过孔H12与所述连接线L1电连接。The third adapter ZJ3 is electrically connected to the cross-line portion LK1 through the eleventh via hole H11 , and the third adapter ZJ3 is electrically connected to the connection line L1 through the twelfth via hole H12 .

图30是图25中的F-F’截面图。Figure 30 is a cross-sectional view taken along line F-F’ in Figure 25 .

在图30中，标号为10的为基底，标号为14的为栅金属层，标号为13的为栅绝缘层，标号为17的为第一钝化层，标号为110的为金属辅助层。In FIG. 30 , reference numeral 10 is a substrate, reference numeral 14 is a gate metal layer, reference numeral 13 is a gate insulating layer, reference numeral 17 is a first passivation layer, and reference numeral 110 is a metal auxiliary layer.

图31是图25中的G-G’截面图，图32是图25中的H-H’截面图。Figure 31 is a G-G’ cross-sectional view in Figure 25, and Figure 32 is a H-H’ cross-sectional view in Figure 25.

在图31和图32中，标号为10的为基底，标号为13的为栅绝缘层，标号为14的为栅金属层，标号为16的为源漏金属层，标号为17的为第一钝化层，标号为18的为第二钝化层，标号为19的为像素电极层，标号为110的为金属辅助层。In Figures 31 and 32, numbered 10 is a substrate, numbered 13 is a gate insulating layer, numbered 14 is a gate metal layer, numbered 16 is a source/drain metal layer, numbered 17 is a first passivation layer, numbered 18 is a second passivation layer, numbered 19 is a pixel electrode layer, and numbered 110 is a metal auxiliary layer.

如图29B所示，在周边区域ZY，设置有图25所示的两条第一信号线，在显示区域AA，设置有栅线GL、数据线DL和子像素中的晶体管；As shown in FIG. 29B , the two first signal lines shown in FIG. 25 are disposed in the peripheral area ZY, and the gate line GL, the data line DL and the transistors in the sub-pixel are disposed in the display area AA;

在图29B中，标号为A1的为所述晶体管的有源图形，标号为VCOM的为公共电极，标号为FX的为辅助金属图形，标号为PX的为像素电极。In FIG. 29B , A1 is an active pattern of the transistor, VCOM is a common electrode, FX is an auxiliary metal pattern, and PX is a pixel electrode.

在图29B对应的至少一实施例中，所述晶体管的有源图形A1位于半导体层，像素电极PX位于像素电极层，公共电极VCOM位于公共电极层，辅助金属图形FX位于金属辅助层；栅线GL位于栅金属层，数据线DL位于源漏金属层。In at least one embodiment corresponding to Figure 29B, the active pattern A1 of the transistor is located in the semiconductor layer, the pixel electrode PX is located in the pixel electrode layer, the common electrode VCOM is located in the common electrode layer, and the auxiliary metal pattern FX is located in the metal auxiliary layer; the gate line GL is located in the gate metal layer, and the data line DL is located in the source and drain metal layer.

图29C是图29B中的L-L’截面图。Fig. 29C is a cross-sectional view taken along the line L-L' in Fig. 29B.

在图29C中，标号为10的为基底，标号为21的为半导体层，标号为13的为栅绝缘层，标号为14的为栅金属层，标号为16的为源漏金属层，标号为17的为第一钝化层，标号为22的为有机层，标号为110的为金属辅助层，标号为111的为公共电极层，标号为18的为第二钝化层，标号为19的为像素电极层。In Figure 29C, number 10 is the substrate, number 21 is the semiconductor layer, number 13 is the gate insulating layer, number 14 is the gate metal layer, number 16 is the source and drain metal layer, number 17 is the first passivation layer, number 22 is the organic layer, number 110 is the metal auxiliary layer, number 111 is the common electrode layer, number 18 is the second passivation layer, and number 19 is the pixel electrode layer.

在本公开至少一实施例中，所述第一信号线还包括位于所述第五导电层的第一连接部；所述第一连接部与所述跨线部搭接；In at least one embodiment of the present disclosure, the first signal line further includes a first connecting portion located in the fifth conductive layer; The first connecting portion overlaps the cross-line portion;

在具体实施时，所述第一信号线还可以包括第一连接部，所述第一连接部可以位于公共电极层，所述第一连接部与所述跨线部直接搭接，所述第一连接部在所述基底上的正投影可以覆盖所述跨线区域在所述基底上的正投影。In a specific implementation, the first signal line may further include a first connection portion, the first connection portion may be located in the common electrode layer, the first connection portion is directly overlapped with the cross-line portion, and the orthographic projection of the first connection portion on the substrate may cover the orthographic projection of the cross-line area on the substrate.

如图33所示，在图25所示的至少一实施例的基础上，所述第一条第一信号线还可以包括第一连接部LJ1；As shown in FIG. 33 , based on at least one embodiment shown in FIG. 25 , the first first signal line may further include a first connection portion LJ1 ;

第一连接部LJ1可以位于公共电极层；The first connection portion LJ1 may be located at the common electrode layer;

在图34中，标号为JY的为跨线部LK1与第二信号连接线部LX2之间的交叠区域。In FIG. 34 , the reference numeral JY indicates an overlapping region between the cross-line portion LK1 and the second signal connection line portion LX2 .

如图33和图34所示，第一连接部LJ1在基底上的正投影覆盖交叠区域JY在所述基底上的正投影，以能进一步增强阻值铜扩散的能力，减小第一信号AD发生的几率。本公开至少一实施例没有额外增加额外工序，仅需变更公共电极层的mask pattern，且第一信号线AD改善效果会更佳。As shown in Figures 33 and 34, the orthographic projection of the first connection portion LJ1 on the substrate covers the orthographic projection of the overlapping area JY on the substrate, so as to further enhance the ability of the resistance copper to diffuse and reduce the probability of the first signal AD occurring. At least one embodiment of the present disclosure does not require additional steps, only the mask pattern of the common electrode layer needs to be changed, and the improvement effect of the first signal line AD will be better.

如图33和图34所示，在跨线区域，所述第一连接部LJ1的线宽可以比跨线部LK1的线宽多出1μm-1.5μm，以使得第一连接部LJ1在基底上的正投影能够覆盖交叠区域JY在所述基底上的正投影。As shown in FIGS. 33 and 34 , in the cross-line region, the line width of the first connection portion LJ1 may be 1 μm-1.5 μm greater than the line width of the cross-line portion LK1 , so that the orthographic projection of the first connection portion LJ1 on the substrate can cover the orthographic projection of the overlapping region JY on the substrate.

图35是图33中的I-I’截面图。Figure 35 is a cross-sectional view taken along line I-I’ in Figure 33 .

在图35中，标号为10的为基底，标号为14的为栅金属层，标号为13的为栅绝缘层，标号为17的为第一钝化层，标号为110的为金属辅助层，标号为111的为公共电极层。In FIG35 , reference numeral 10 is a substrate, reference numeral 14 is a gate metal layer, reference numeral 13 is a gate insulating layer, reference numeral 17 is a first passivation layer, reference numeral 110 is a metal auxiliary layer, and reference numeral 111 is a common electrode layer.

在本公开至少一实施例中，所述第一信号线还包括第一转接部和第二转接部；所述第二转接部与所述跨线部搭接；In at least one embodiment of the present disclosure, the first signal line further includes a first transfer portion and a second transfer portion; the second transfer portion is overlapped with the crossover portion;

在具体实施时，所述第一信号线还可以包括第一转接部和第二转接部，所述第一转接部可以位于像素电极层，所述第二转接部可以位于公共电极层，所述第二转接部可以与所述跨线部直接搭接；第一转接部可以通过第十三过孔与信号连接线部电连接，第一转接部可以通过第十四过孔与第二转接部电连接，以使得所述信号连接线部与所述跨线部电连接。In a specific implementation, the first signal line may further include a first transition portion and a second transition portion, the first transition portion may be located at the pixel electrode layer, the second transition portion may be located at the common electrode layer, and the second transition portion may be directly overlapped with the jumper portion; the first transition portion may be electrically connected to the signal connection line portion through a thirteenth via hole, and the first transition portion may be electrically connected to the second transition portion through a fourteenth via hole, so that the signal connection line portion is electrically connected to the jumper portion.

图37是图36中的栅金属层的平面布局图，图38是图36中的源漏金属层的平面布局图，图39是图36中的公共电极层的平面布局图，图40是图36中的金属辅助层的平面布局图，图41是图36中的像素电极层的平面布局图。Figure 37 is a plan layout diagram of the gate metal layer in Figure 36, Figure 38 is a plan layout diagram of the source and drain metal layer in Figure 36, Figure 39 is a plan layout diagram of the common electrode layer in Figure 36, Figure 40 is a plan layout diagram of the metal auxiliary layer in Figure 36, and Figure 41 is a plan layout diagram of the pixel electrode layer in Figure 36.

如图36-图41所示，第一条第一信号线包括跨线部LK1、第一信号连接线部LX1、第一转接部ZJ1和第二转接部ZJ2；第二条第一信号线包括第二信号连接线部LX2；As shown in FIG. 36 to FIG. 41 , the first first signal line includes a cross-line portion LK1, a first signal connection line portion LX1, The first transfer portion ZJ1 and the second transfer portion ZJ2; the second first signal line includes a second signal connection line portion LX2;

LX1位于栅金属层，ZJ1位于像素电极层，ZJ2位于公共电极层，LK1位于金属辅助层；LX1 is located at the gate metal layer, ZJ1 is located at the pixel electrode layer, ZJ2 is located at the common electrode layer, and LK1 is located at the metal auxiliary layer;

第二转接部ZJ2与跨线部LK1直接搭接；The second transition part ZJ2 is directly connected with the cross-line part LK1;

第一转接部ZJ1通过第十三过孔H13与第一信号连接线部LX1电连接，第一转接部ZJ1通过第十四过孔H14与第二转接部ZJ2电连接；The first transfer portion ZJ1 is electrically connected to the first signal connection line portion LX1 through the thirteenth via hole H13, and the first transfer portion ZJ1 is electrically connected to the second transfer portion ZJ2 through the fourteenth via hole H14;

ZJ1在所述基底上的正投影与第一信号连接线部LX1在所述基底上的正投影部分重叠，ZJ1在基底上的正投影与ZJ2在基底上的正投影部分重叠；The orthographic projection of ZJ1 on the substrate partially overlaps with the orthographic projection of the first signal connection line portion LX1 on the substrate, and the orthographic projection of ZJ1 on the substrate partially overlaps with the orthographic projection of ZJ2 on the substrate;

第二条第一信号线可以包括第二信号连接线部LX2；The second first signal line may include a second signal connection line portion LX2;

LX2可以位于栅金属层。LX2 may be located at the gate metal layer.

如图36-图41所示，所述第一条第一信号线还可以包括第三转接部ZJ3和连接线L1；As shown in FIGS. 36 to 41 , the first first signal line may further include a third transition portion ZJ3 and a connection line L1;

如图36-图41所示，ZJ3可以位于像素电极层，L1可以位于源漏金属层。As shown in FIGS. 36 to 41 , ZJ3 may be located in the pixel electrode layer, and L1 may be located in the source and drain metal layer.

图42是图36中的J-J’截面图。Figure 42 is a J-J’ cross-sectional view in Figure 36.

在本公开至少一实施例中，所述跨线部包括第一跨线部分和第二跨线部分；In at least one embodiment of the present disclosure, the crossover portion includes a first crossover portion and a second crossover portion;

可选的，所述第一跨线部分位于所述第五导电层，所述第二跨线部分位于所述第六导电层。Optionally, the first cross-line portion is located in the fifth conductive layer, and the second cross-line portion is located in the sixth conductive layer.

在具体实施时，所述跨线部可以包括位于公共电极层的第一跨线部分和位于金属辅助层的第二跨线部分，所述第一跨线部分可以与第二跨线部分直接搭接。In a specific implementation, the cross-line portion may include a first cross-line portion located at the common electrode layer and a second cross-line portion located at the metal auxiliary layer, and the first cross-line portion may be directly overlapped with the second cross-line portion.

图44是图43中的栅金属层的平面布局图，图45是图43中的源漏金属层的平面布局图，图46是图43中的公共电极层的平面布局图，图47是图43中的金属辅助层的平面布局图，图48是图43中的像素电极层的平面布局图。Figure 44 is a plan layout diagram of the gate metal layer in Figure 43, Figure 45 is a plan layout diagram of the source and drain metal layer in Figure 43, Figure 46 is a plan layout diagram of the common electrode layer in Figure 43, Figure 47 is a plan layout diagram of the metal auxiliary layer in Figure 43, and Figure 48 is a plan layout diagram of the pixel electrode layer in Figure 43.

如图43-图48所示，所述第一条第一信号线可以包括第一信号连接线部LX1和跨线部；As shown in FIGS. 43 to 48 , the first first signal line may include a first signal connection line portion LX1 and a cross-line portion;

所述第二条第一信号线可以包括第二信号连接线部LX2；The second first signal line may include a second signal connection line portion LX2;

所述第一跨线部包括第一跨线部分LKB1和第二跨线部分LKB2；The first crossover portion includes a first crossover portion LKB1 and a second crossover portion LKB2;

LKB1可以位于公共电极层，LKB2可以位于金属辅助层；LKB1 may be located at the common electrode layer, and LKB2 may be located at the metal auxiliary layer;

LKB1在基底上的正投影覆盖第二跨线部分LKB2在基底上的正投影，以保证LKB1在基底上的正投影覆盖LKB2与LX2的交叠区域。The orthographic projection of LKB1 on the substrate covers the orthographic projection of the second cross-line portion LKB2 on the substrate, so as to ensure that the orthographic projection of LKB1 on the substrate covers the overlapping area of LKB2 and LX2.

在图43-图48所示的至少一实施例中，在跨线区域，LKB1的线宽可以比LKB2的线宽多出1μm-1.5μm。In at least one embodiment shown in FIGS. 43 to 48 , in the cross-line region, the line width of LKB1 may be greater than that of LKB2. The width is 1μm-1.5μm wider.

在本公开至少一实施例中，所述第一信号线还包括第一转接部和第二转接部；所述第二转接部与所述第一跨线部分电连接；In at least one embodiment of the present disclosure, the first signal line further includes a first transfer portion and a second transfer portion; the second transfer portion is electrically connected to the first cross-line portion;

如图43-图48所示，所述第一条第一信号线还可以包括第一转接部ZJ1和第二转接部ZJ2，ZJ1可以位于像素电极层，ZJ2可以位于公共电极层；As shown in FIGS. 43 to 48 , the first first signal line may further include a first transfer portion ZJ1 and a second transfer portion ZJ2, ZJ1 may be located at the pixel electrode layer, and ZJ2 may be located at the common electrode layer;

所述第二转接部ZJ2可以与第一跨线部分LKB1电连接；The second transfer portion ZJ2 may be electrically connected to the first cross-line portion LKB1;

第一转接部ZJ1通过第十三过孔H13与所述第一信号连接线部LX1电连接，第一转接部ZJ1通过第十四过孔H14与第二转接部ZJ2电连接；The first transfer portion ZJ1 is electrically connected to the first signal connection line portion LX1 through the thirteenth via hole H13, and the first transfer portion ZJ1 is electrically connected to the second transfer portion ZJ2 through the fourteenth via hole H14;

ZJ1在基底上的正投影与LX1在基底上的正投影部分重叠，ZJ1在基底上的正投影与ZJ2在基底上的正投影部分重叠。The orthographic projection of ZJ1 on the substrate partially overlaps with the orthographic projection of LX1 on the substrate, and the orthographic projection of ZJ1 on the substrate partially overlaps with the orthographic projection of ZJ2 on the substrate.

在本公开至少一实施例中，所述第一信号线还包括第三转接部、第四转接部和连接线；In at least one embodiment of the present disclosure, the first signal line further includes a third transfer portion, a fourth transfer portion and a connecting line;

可选的，所述第三转接部位于所述第四导电层，所述第四转接部位于第五导电层；所述连接线位于所述第三导电层。Optionally, the third transition portion is located in the fourth conductive layer, the fourth transition portion is located in the fifth conductive layer; and the connecting line is located in the third conductive layer.

如图43-图48所示，所述第一条第一信号线还可以包括第三转接部ZJ3、第四转接部ZJ4和连接线L1；As shown in FIGS. 43 to 48 , the first first signal line may further include a third transition portion ZJ3 , a fourth transition portion ZJ4 and a connection line L1 ;

ZJ3可以位于像素电极层，ZJ4可以位于公共电极层；ZJ3 may be located at the pixel electrode layer, and ZJ4 may be located at the common electrode layer;

ZJ4可以与LKB1电连接；ZJ4 can be electrically connected to LKB1;

ZJ3通过第十五过孔H15与第四转接部ZJ4电连接，ZJ3通过第十六过孔H16与连接线L1电连接；ZJ3 is electrically connected to the fourth adapter ZJ4 through the fifteenth via hole H15, and ZJ3 is electrically connected to the connection line L1 through the sixteenth via hole H16;

L1可以位于源漏金属层。L1 may be located at a source/drain metal layer.

ZJ3、ZJ4、H15和H16可以设置于第一信号线布线区和GOA TFT(GOA TFT可以为GOA电路中的TFT)分布区之间。ZJ3, ZJ4, H15 and H16 can be arranged between the first signal line wiring area and the GOA TFT (GOA TFT can be a TFT in the GOA circuit) distribution area.

在制作如图33所示的第一信号线时，具体流程为如下：When manufacturing the first signal line shown in FIG. 33 , the specific process is as follows:

1、栅金属层成膜，得到图49所示的pattern；1. Forming a gate metal layer to obtain the pattern shown in FIG. 49 ;

2、栅绝缘层成膜，半导体层成膜、刻蚀，源漏金属层成膜、刻蚀，得到图50所示的 pattern；2. Forming a gate insulating layer, forming a semiconductor layer, etching, forming a source and drain metal layer, and etching to obtain the structure shown in FIG. 50. pattern;

3、第一钝化层成膜，有机层涂布、曝光并显影，公共电极层成膜、刻蚀，得到图51所示的pattern；3. Forming the first passivation layer, coating, exposing and developing the organic layer, forming and etching the common electrode layer, and obtaining the pattern shown in FIG. 51 ;

4、金属辅助层成膜、刻蚀，得到图52所示的pattern；4. Forming and etching the metal auxiliary layer to obtain the pattern shown in FIG. 52 ;

5、第二钝化层成膜、按照图53虚线所示区域进行刻蚀，在金属辅助层、栅金属层和源漏金属层上留出搭孔区域；5. Form the second passivation layer, etch the area indicated by the dotted line in FIG. 53 , and leave overlapping areas on the metal auxiliary layer, the gate metal layer, and the source and drain metal layer;

6、像素电极层成膜、刻蚀，得到图54所示的pattern。6. The pixel electrode layer is formed and etched to obtain the pattern shown in FIG. 54 .

在制作如图43所示的第一信号线时，具体流程为如下：When manufacturing the first signal line shown in FIG. 43 , the specific process is as follows:

1、栅金属层成膜、刻蚀，得到图55所示的pattern；1. The gate metal layer is formed and etched to obtain the pattern shown in FIG. 55 ;

2、栅绝缘层成膜、半导体层成膜、刻蚀，源漏金属层成膜、刻蚀，得到图56所示的pattern；2. Forming a gate insulating layer, forming a semiconductor layer, etching, forming a source and drain metal layer, and etching to obtain the pattern shown in FIG. 56 ;

3、第一钝化层成膜，有机层涂布、曝光并显影，公共电极层成膜、刻蚀，得到图57所示的pattern；3. Forming the first passivation layer, coating, exposing and developing the organic layer, forming and etching the common electrode layer, and obtaining the pattern shown in FIG. 57 ;

4、金属辅助层成膜、刻蚀，得到图58所示的pattern；4. Forming and etching the metal auxiliary layer to obtain the pattern shown in FIG. 58;

5、第二钝化层成膜、按照图59虚线所示区域进行刻蚀，在公共电极层、栅金属层和源漏金属层上留出搭孔区域；5. Form the second passivation layer, etch the area indicated by the dotted line in FIG. 59 , and leave overlapping areas on the common electrode layer, the gate metal layer, and the source and drain metal layer;

6、像素电极层成膜、刻蚀，得到图60所示的pattern。6. The pixel electrode layer is formed and etched to obtain the pattern shown in FIG. 60 .

本公开实施例所述的显示装置包括上述的显示面板。The display device described in the embodiment of the present disclosure includes the above-mentioned display panel.

以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。 The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

A display panel comprises a display area and a peripheral area surrounding the display area, wherein a plurality of first signal lines located on a substrate are arranged in the peripheral area; the first signal lines comprise a signal connection line portion;

The plurality of first signal lines are divided into first sub-signal lines including a crossover portion and second sub-signal lines not including a crossover portion;

The orthographic projection of the cross-line portion on the substrate partially overlaps with the orthographic projection of at least part of the second sub-signal lines among the plurality of second sub-signal lines on the substrate;

At least two insulating layers are spaced between the cross-line portion and a signal connection line portion included in at least part of the second sub-signal lines of the plurality of second sub-signal lines; and/or, the signal connection line portion includes a plurality of signal connection line portions extending along the first direction, and the width of the signal connection line portion along the second direction is less than a width threshold;

The signal connection line portion extends along the first direction, and the second direction intersects with the first direction.

The display panel according to claim 1, wherein the width threshold is greater than or equal to 5 μm and less than or equal to 8 μm.

The display panel according to claim 1, wherein the display panel comprises a first conductive layer, a second conductive layer and a third conductive layer arranged in sequence away from the substrate; at least one insulating layer is provided between adjacent conductive layers;

The cross-line portion is located in the third conductive layer, and the signal connection line portion is located in the first conductive layer.

The display panel as claimed in claim 3, wherein the first conductive layer includes a shading pattern arranged in the display area, the second conductive layer includes a gate line arranged in the display area, and the third conductive layer includes a data line arranged in the display area.

The display panel according to claim 3, wherein the first signal line further comprises a signal main line portion;

The signal main line portion includes a first main line portion, a second main line portion and a third main line portion; the first main line portion, the second main line portion and the third main line portion are located in different conductive layers;

The third main body line portion is electrically connected to the second main body line portion through a first via;

An orthographic projection of the first body line portion on the substrate, an orthographic projection of the second body line portion on the substrate, and an orthographic projection of the third body line portion on the substrate at least partially overlap.

The display panel according to claim 5, wherein the first signal line further comprises a signal conducting line portion;

The signal conducting wire portion is arranged between the signal main wire portion and the signal connecting wire portion;

The signal conductive line portion includes a first conductive line portion and a second conductive line portion located in different conductive layers;

The first conductive line portion is electrically connected to the second conductive line portion through a second via hole;

An orthographic projection of the first conductive line portion on the substrate at least partially overlaps with an orthographic projection of the second conductive line portion on the substrate.

The display panel as claimed in claim 6, wherein the signal connection line portion, the first main line portion and the first conductive line portion are electrically connected, and the third main line portion and the second conductive line portion are electrically connected.

The signal main body line portion includes a first main body line portion and a second main body line portion located in different conductive layers;

The first main body line portion is electrically connected to the second main body line portion through a third via;

An orthographic projection of the first body line portion on the substrate and an orthographic projection of the second body line portion on the substrate at least partially overlap.

The display panel as claimed in claim 8, wherein the signal connection line portion is electrically connected to the first main line portion.

The display panel according to claim 5 or 8, wherein the orthographic projection of the cross-line portion on the substrate partially overlaps with the orthographic projection of the signal connection line portion included in the first signal line to which the cross-line portion belongs on the substrate;

The cross-line portion is electrically connected to a signal connection line portion included in a first signal line to which the cross-line portion belongs through a fourth via hole.

The display panel according to claim 3, wherein the display panel further comprises a fourth conductive layer disposed on a side of the third conductive layer away from the substrate;

The first signal line also includes a signal main line portion;

The orthographic projection of the third main body line portion on the substrate at least partially overlaps with the orthographic projection of the first main body line portion on the substrate, and the orthographic projection of the third main body line portion on the substrate at least partially overlaps with the orthographic projection of the second main body line portion on the substrate;

The third body line portion is electrically connected to the second body line portion through a fifth via hole, and the third body line portion is electrically connected to the first body line portion through a sixth via hole.

The display panel as claimed in claim 11, wherein the fourth conductive layer includes a pixel electrode arranged in the display area.

The display panel according to claim 11, wherein the first signal line further comprises a first transition portion; the orthographic projection of the first transition portion on the substrate at least partially overlaps with the orthographic projection of the signal connection line portion included in the first signal line to which the cross-line portion belongs on the substrate; the orthographic projection of the first transition portion on the substrate at least partially overlaps with the orthographic projection of the cross-line portion on the substrate;

The first adapter portion is electrically connected to the signal connection line portion through a seventh via hole, and the first adapter portion is electrically connected to the cross-line portion through an eighth via hole;

The first transfer portion and the signal connection line are located in different layers, and the first transfer portion and the cross-line portion are located in different conductive layers.

The display panel according to claim 1, wherein the display panel comprises a second conductive layer, a third conductive layer, a fifth conductive layer, a sixth conductive layer and a fourth conductive layer arranged in sequence away from the substrate; the fifth conductive layer overlaps the sixth conductive layer; at least one insulating layer is provided between the second conductive layer and the third conductive layer, at least one insulating layer is provided between the third conductive layer and the fifth conductive layer, and at least one insulating layer is provided between the sixth conductive layer and the fourth conductive layer;

At least a portion of the cross-line portion is located in the sixth conductive layer, and the signal connection line portion is located in the second conductive layer.

The display panel as described in claim 14, wherein the second conductive layer includes gate lines arranged in the display area, the third conductive layer includes data lines arranged in the display area, the fifth conductive layer includes common electrodes arranged in the display area, and the sixth conductive layer includes auxiliary metal patterns arranged in the display area.

The display panel according to claim 14, wherein the first signal line further comprises a first transfer portion;

The first adapter portion is electrically connected to the signal connection line portion through a ninth via hole, and the first adapter portion is electrically connected to the cross-line portion through a tenth via hole;

The first transfer portion and the signal connection line portion are located in different layers, and the first transfer portion and the cross-line portion are located in different conductive layers.

The display panel according to claim 14, wherein the first signal line further comprises a first transition portion and a second transition portion; the second transition portion is overlapped with the crossover portion;

The first transfer portion is electrically connected to the signal connection line portion through a thirteenth via hole, and the first transfer portion is electrically connected to the second transfer portion through a fourteenth via hole;

The first transfer portion and the signal connection line portion are located in different layers, and the first transfer portion and the second transfer portion are located in different conductive layers.

The display panel according to any one of claims 14 to 17, wherein the first signal line further comprises a third transition portion and a connecting line;

The third adapter portion is electrically connected to the cross-line portion through an eleventh via hole, and the third adapter portion is electrically connected to the connection line through a twelfth via hole;

The third transfer portion and the cross-line portion are located in different conductive layers, and the third transfer portion and the connecting line are located in different conductive layers.

The display panel according to any one of claims 14 to 17, wherein the first signal line further comprises a first connecting portion located in the fifth conductive layer; the first connecting portion is overlapped with the cross-line portion;

The orthographic projection of the first connecting portion on the substrate covers the orthographic projection of the cross-line area on the substrate;

The cross-line region is an overlapping region between the cross-line portion and a signal connection line portion included in at least some of the second sub-signal lines in the plurality of second sub-signal lines.

The display panel according to claim 14, wherein the cross-line portion comprises a first cross-line portion and a second cross-line portion;

The orthographic projection of the first cross-line portion on the substrate covers the orthographic projection of the second cross-line portion on the substrate;

The first jumper portion is directly overlapped with the second jumper portion.

The display panel according to claim 20, wherein the first signal line further comprises a first transition portion and a second transition portion; the second transition portion is electrically connected to the first cross-line portion;

The first transfer portion is electrically connected to the clock signal connection line portion through a thirteenth via hole, and the first transfer portion is electrically connected to the second transfer portion through a fourteenth via hole;

The first transfer portion and the signal connection line portion are located in different conductive layers, and the first transfer portion and the second transfer portion are located in different conductive layers.

The display panel according to claim 20, wherein the first signal line further comprises a third adapter, a fourth adapter and a connecting line;

The fourth transfer portion is electrically connected to the first cross-line portion; the fourth transfer portion and the first cross-line portion are located in the same conductive layer;

The third adapter is electrically connected to the fourth adapter through a fifteenth via hole, and the third adapter is electrically connected to the connection line through a sixteenth via hole;

The third transfer portion and the fourth transfer portion are located in different conductive layers, and the third transfer portion and the connecting line are located in different conductive layers.

A display device comprises the display panel according to any one of claims 1 to 22.