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WO2025108793A1 - Method for producing a soi structure, in particular suitable for photonic applications, and carrier substrate for the structure - Google Patents

Method for producing a soi structure, in particular suitable for photonic applications, and carrier substrate for the structure Download PDF

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Publication number
WO2025108793A1
WO2025108793A1 PCT/EP2024/082138 EP2024082138W WO2025108793A1 WO 2025108793 A1 WO2025108793 A1 WO 2025108793A1 EP 2024082138 W EP2024082138 W EP 2024082138W WO 2025108793 A1 WO2025108793 A1 WO 2025108793A1
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WIPO (PCT)
Prior art keywords
layer
support substrate
heat treatment
temperature
soi structure
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French (fr)
Inventor
Carine Duret
Isabelle Bertrand
Aurélien MAK
Alexandre COUVRAT
Djamel MESSAOUDENE
Ludovic Ecarnot
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Soitec SA
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Soitec SA
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Publication of WO2025108793A1 publication Critical patent/WO2025108793A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Definitions

  • the present invention relates to the field of semiconductors and microelectronics. It relates to a method for manufacturing an SOI (Silicon on Insulator) structure, particularly suitable for photonic applications.
  • SOI Silicon on Insulator
  • the invention also relates to a support substrate for said structure.
  • TSVs through-silicon vias
  • BMDs bulk micro-defects
  • the manufacturing of SOI structures requires very high temperature thermal budgets. It can notably implement the Smart Cut TM process for the transfer of the useful layer in monocrystalline silicon (c-Si) onto the support substrate, via a dielectric intermediate layer.
  • the well-known Smart Cut process is based on the implantation of light ions into a c-Si donor substrate to form a buried fragile plane which defines, with the front face of the donor substrate, the useful layer to be transferred.
  • the implanted donor substrate is then assembled on the support substrate.
  • a dielectric layer is formed on the donor substrate, on the support substrate or on both substrates, prior to assembly: this dielectric layer is intended to form the buried insulating layer of the SOI structure.
  • the next step consists of a separation along the buried fragile plane, giving rise, on the one hand, to an intermediate structure comprising the useful layer transferred onto the support substrate via the dielectric layer, and on the other hand, the rest of the donor substrate.
  • the support substrate of the SOI structure is resistant to failure modes such as slip lines, marks or other deformations likely to be generated during the heat treatment, due to temperature gradients or contact points between the substrate and holding elements in the furnace.
  • failure modes such as slip lines, marks or other deformations likely to be generated during the heat treatment, due to temperature gradients or contact points between the substrate and holding elements in the furnace.
  • BMD micro-defects allow the trapping of species (in particular metallic contamination) in the support substrate, limiting the diffusion of contaminants to the useful layer during the manufacturing of the components.
  • the present invention relates to a method of manufacturing an SOI structure, comprising the following steps:
  • a first heat treatment defined by a plateau at a temperature above 1200°C and below 1280°C and lasting between 1 second and 60 seconds, by a temperature reduction ramp between 10°C/s and 70°C/s, and by an argon or argon-hydrogen type atmosphere, followed by
  • a support substrate comprising:
  • the invention also relates to a monocrystalline silicon support substrate, having:
  • the support substrate may comprise a silicon oxide dielectric layer at least on its front face.
  • the invention finally relates to an SOI structure comprising a useful layer arranged on the dielectric layer, itself arranged on a support substrate as mentioned above.
  • the dielectric layer advantageously has a thickness of between 500nm and 2000nm.
  • Figures 1a, 1b and 1c show the steps of the method for manufacturing a support substrate for an SOI structure, in accordance with the invention
  • Some figures are schematic representations which, for readability purposes, are not to scale.
  • the layer thicknesses along the z axis are not to scale with the lateral dimensions along the x and y axes.
  • the invention relates to a method for manufacturing an SOI 100 structure particularly suitable for photonic applications, which require in particular the formation of V-shaped trenches and conductive vias in the support substrate 10 of said structure 100.
  • the SOI 100 structure comprises a thick buried dielectric layer, typically between 500nm and 2000nm.
  • the method comprises, firstly, a step a) corresponding to the provision of an initial substrate 10' in monocrystalline silicon CZ (Czochralski growth process).
  • the initial substrate 10' has a front face 10a and a rear face 10b, substantially parallel to a main plane (x,y) ( ). It advantageously takes the form of a circular plate, with a diameter typically between 200mm and 450mm. Its total thickness, along the z axis normal to the main plane (x,y), can vary between a few hundred microns (for example 300 ⁇ m) and 1000 ⁇ m.
  • the initial substrate 10’ has an interstitial oxygen content of between 15 and 27 ppma according to the ASTM’79 standard. Its resistivity is less than 200 ohms.cm, typically between 1 ohm.cm and 100 ohms.cm.
  • the initial substrate 10’ is intended to form a support substrate 10 for the SOI structure 100 after having undergone the subsequent step b).
  • Step b) corresponds to the application of a sequence of heat treatments to the initial bare substrate 10', i.e. devoid, at least on its front face 10a, of any layer of silicon oxide other than possibly a layer of native oxide.
  • the sequence consists of two successive heat treatments, without any other intervening thermal cycle.
  • the first heat treatment is carried out in a rapid thermal annealing (RTA) equipment and is defined by a temperature plateau, temperature ramps and a gas atmosphere.
  • the temperature of the plateau is above 1200°C and below 1280°C.
  • the duration of the plateau can be from 1 second to 60 seconds.
  • the ramp down is between 10°C/s and 70°C/s.
  • the ramp up is also fast, but can be chosen in a wider range than the ramp down, in particular between 10°C/s and 100°C/s.
  • the atmosphere during this first heat treatment is of the argon or argon-hydrogen type (typically Ar > 70%).
  • a nitrogen atmosphere is not possible because too many vacancies are injected into the substrate, particularly through the front face 10a, which does not promote the depletion of vacancies in a very thick surface layer.
  • An oxidizing atmosphere is also to be avoided because it helps to compensate for the injection of vacancies, particularly in a deep layer of the substrate that we wish to enrich in vacancies.
  • This first heat treatment applied to the initial bare substrate 10’ makes it possible to generate a profile of vacancies in its depth, namely a low concentration of vacancies in a surface layer 11’,13’ and a high concentration of vacancies in a deep layer 12’.
  • surface layer 11', 13' is meant a layer whose thickness starts at a free face 10a, 10b of the initial substrate 10' (in particular, its front face 10a, but potentially also its rear face 10b) and extends over a depth greater than or equal to 40 ⁇ m in the volume of said substrate 10' ( ).
  • a surface layer 13' with a low concentration of vacancies can be formed on the side of the rear face 10b of the initial substrate 10', if said rear face 10b is – like the front face 10a – bare, during the first heat treatment.
  • deep layer 12 we mean a layer which is located under the surface layer 11’, 13’ (starting from the free face of the surface layer considered), and which extends into the volume of the initial substrate 10’.
  • This deep layer with a high concentration of vacancies can for example extend between the surface layer 11’ on the front face 10a and that 13’ on the rear face 10b of the initial substrate 10’. Later in the thermal sequence applied to the initial substrate 10’, the vacancies will help to fix oxygen precipitates where they are present, by constituting preferential nucleation sites.
  • vacancies can be generated everywhere in the initial substrate 10’, on the surface as well as in depth, with a density depending on the thermal budget applied.
  • these vacancies diffuse very quickly, the probability that they recombine at the surface is greater if we are close to the surface, we therefore have a gradient of vacancies at the surface, which can be modulated in particular by the temperature decrease speed: the faster we decrease, the more we will freeze the vacancies in place and recombine at the surface, which gives rise to a surface layer depleted in vacancies of thin thickness; the slower we decrease, the more pronounced the vacancy concentration gradient will be, which results in a surface layer of greater thickness.
  • an argon-hydrogen atmosphere adds a participation of hydrogen (which diffuses quickly in the initial substrate 10') to the passivation of the vacancies, on the surface but also deeper down, which can increase the thickness of the surface layer.
  • an Ar/H atmosphere can reduce the vacancy concentration of the deep layer, which is not desirable.
  • the above-mentioned first heat treatment conditions provide the right compromise to generate a surface layer thickness 11’, 13’ depleted in vacancies, typically between 40 ⁇ m and 100 ⁇ m, and a deep layer 12’ very rich in vacancies.
  • these conditions avoid, or at least limit, the creation of defects such as SL slip lines or PM pinmarks in or on the initial substrate 10’, which are detrimental to the future SOI structure.
  • the first heat treatment is followed by a second heat treatment, defined by a plateau at a temperature between 900°C and 1100°C, without a plateau before this temperature.
  • the temperature of the plateau is between 950°C and 1000°C.
  • the duration of the plateau is typically between 2 hours and several tens of hours, for example 40 hours.
  • the temperature rise and fall ramps are advantageously between 0.5°C/min and 10°C/min and may possibly be different from each other.
  • the atmosphere of the second heat treatment may be neutral or oxidizing. This second heat treatment is advantageously carried out in a conventional furnace (with vertical or horizontal tube).
  • the second heat treatment promotes the precipitation of oxygen on the vacancies distributed in the substrate 10’ according to the profile frozen during the first heat treatment.
  • the precipitation is made possible by the presence of interstitial oxygen, which recalls the importance of the choice of the range of interstitial oxygen contents of the initial substrate 10’ provided in step a) of the process.
  • the second heat treatment is also defined so as not to passivate or recombine the vacancies before they have helped create BMD micro-defects.
  • This sequence of heat treatments is essential to form the target support substrate 10, of which a stripped surface layer 11, 13 (from the surface layer 11', 13'), with a thickness greater than or equal to 40 ⁇ m, has a concentration of BMD micro-defects less than 10 8 /cm 3 , and of which an enriched deep layer 12 (from the deep layer 12'), under the stripped surface layer 11, 13, has a concentration of BMD micro-defects of between 2.10 8 /cm 3 and 5.10 10 /cm 3 .
  • the density and potentially the size of the BMD micro-defects are conventionally measured by light scattering tomography (LST for "Light Scattering Tomography"), at the level of the edge (in the plane (y, z) in the figures) of the support substrate 10.
  • LST Light Scattering Tomography
  • the support substrate 10 obtained also has excellent mechanical quality, with a very low density of SL or PM type defects, or even none of these defects, at the end of the heat treatment sequence.
  • the absence (or very low density) of these defects, and the concentration of BMD micro-defects greater than or equal to 2x10 8 /cm 3 will give the support substrate 10 great mechanical robustness during subsequent heat treatments at high temperatures, and avoid SL slip line type failures in the future SOI structure (both during its preparation and during that of the components).
  • the stripped surface layer 11, 13, which can extend over a thickness of between 40 ⁇ m and 100 ⁇ m, is particularly suitable for the formation of V-shaped trenches or vias, during the manufacture of components on and/or in the SOI structure 100.
  • the atmosphere of the second heat treatment is oxidizing, at least during the plateau, to form, on the support substrate 10, all or part of a dielectric layer of silicon oxide, said dielectric layer 20 being intended to be arranged between a useful layer 30 and the support substrate 10 in the SOI structure 100.
  • This embodiment is advantageous in that it makes it possible to combine two functions of the second heat treatment and to rationalize the thermal steps applied to the support substrate 10.
  • the second heat treatment may be defined by temperature rise ramps of a few degrees per minute, up to 1000°C, under an argon atmosphere with low oxygen supply, a plateau at a temperature of 1000°C under an oxidizing atmosphere, and a descent ramp of a few degrees per minute.
  • the manufacturing method comprises, after step b) of applying the sequence of heat treatments, a step c) of oxidation of the support substrate 10 to form, on said support substrate, all or part of a dielectric layer of silicon oxide; the dielectric layer 20 is intended to be arranged between a useful layer 30 and the support substrate 10 in the SOI structure 100.
  • the oxidation step c) has no negative influence on the stripped surface layer 11, 13 and the enriched deep layer 12, because the precipitation of oxygen on the vacancies took place during the second heat treatment. Step c) can then induce an increase in the size of the BMD micro-defects.
  • the dielectric layer 20 is preferably (or at least in the vast majority) grown on the support substrate 10, because a high thickness of dielectric layer on the front face of the donor substrate (in reference to the Smart Cut process) makes it difficult to form the buried fragile plane by ion implantation.
  • step b) There shows two examples of support substrate 10 produced according to a method in accordance with the invention.
  • the sequence of step b) consisted of a first heat treatment defined by a plateau at a temperature between 1220°C and 1260°C, lasting between 1 second and 60 seconds, and by a temperature reduction ramp between 10°C/s and 70°C/s, followed by a second heat treatment defined by a plateau at a temperature between 950°C and 1000°C, without a plateau before this temperature, under an oxidizing atmosphere.
  • the images were obtained by LST.
  • the thickness of the stripped surface layer 11 can be greater thanks to the implementation of an Ar/H atmosphere during the first heat treatment: in the left image of the , the thickness of the stripped surface layer 11 is approximately 70 ⁇ m for an Ar atmosphere, whereas in the right image, the thickness of the stripped layer 11 is approximately 90 ⁇ m for an Ar/H atmosphere, with a hydrogen concentration of less than 30%.
  • the support substrate 10, in both examples, has good mechanical quality with no or very few SL and PM defects.
  • a plateau temperature at the first heat treatment of 1200°C (or lower), even under an Ar/H atmosphere and using a temperature reduction ramp of between 10°C/s and 70°C/s, does not allow the expected gap profile to be generated: at the end of the heat treatment sequence, the support substrate (outside the invention) does not have a stripped surface layer (example on the left in the ).
  • a temperature reduction ramp that is too slow during the first heat treatment is detrimental to the preservation of a marked vacancy profile: for example, with a reduction ramp of 5°C/s, the support substrate at the end of the heat treatment sequence does not present an enriched deep layer (example on the right in the ).
  • the manufacturing method according to the invention further comprises a step d) corresponding to the formation of an intermediate structure comprising the useful layer 30 of monocrystalline silicon arranged on the dielectric layer 20, itself arranged on a front face 10a of said support substrate 10, by a thin layer transfer technique such as the Smart Cut TM process.
  • a monocrystalline silicon donor substrate is implanted from its front face, so as to define a buried fragile plane substantially parallel to said front face and delimiting, with the latter, the thin layer to be transferred.
  • the implantation is usually carried out with light species such as hydrogen ions, helium or a combination of these two species.
  • the fragile plane is so named because it includes nano-cracks in lenticular form generated by the implanted light species.
  • a dielectric layer 20 is formed at least on the front face 10a of the support substrate 10. It is not excluded, however, that a part of the buried dielectric layer of the future SOI structure is produced on the donor substrate.
  • the donor substrate and the support substrate 10 are then assembled, by direct bonding between the front faces of said substrates, to form a bonded assembly.
  • Surface cleaning and/or activation well known in the field of molecular adhesion bonding, may be applied to the substrates prior to assembly, to obtain excellent bonding quality. Assembly in a controlled atmosphere is also possible.
  • Separation at the buried fragile plane is preferably achieved by applying a heat treatment at medium temperature, typically between 350°C and 500°C, due to the growth of microcracks by coalescence and pressurization of gaseous species.
  • separation can be caused by applying mechanical stress to the bonded assembly.
  • an intermediate structure of the SOI type is obtained, on the one hand, and the rest of the donor substrate, on the other hand. Finishing sequences, including cleaning, surface treatments (etching, polishing, etc.) and/or heat treatments, are usually applied to the intermediate SOI structure, and aim to remove a superficial part of the transferred useful layer 30. This makes it possible to restore a good surface condition (defectivity and roughness) and a good crystalline quality to the useful silicon layer 30.
  • the useful layer 30 typically has a thickness of between 50 nm and 500 nm.
  • the manufacturing method then comprises a step e) of applying a third heat treatment to the intermediate structure, at a temperature between 900°C and 1250°C, under a neutral or reducing atmosphere, to form the SOI structure.
  • a third heat treatment does not affect the stripped surface layer 11, 13 and the deep layer enriched in BMD 12, induced by the sequence of the first and second heat treatments. It can advantageously induce an increase in the size of the BMD micro-defects.
  • the invention also relates to a support substrate 10 made of monocrystalline silicon, particularly suitable for SOI structures aimed in particular at photonic applications, the support substrate 10 having:
  • bare surface layer 11,13 with a thickness greater than 40 ⁇ m, having a micro-defect concentration (BMD) less than 10 8 /cm 3 ,
  • BMD micro-defects
  • the support substrate 10 may further comprise a silicon oxide dielectric layer on its front face 10a and/or on its rear face 10b.
  • said dielectric layer has a thickness of between 500nm and 2000nm.
  • the invention relates to an SOI structure comprising a useful layer 30 in c-Si arranged on the dielectric layer 20, itself arranged on the aforementioned support substrate 10.
  • This SOI structure is particularly suitable for the manufacture of photonic components on and/or in the useful layer 30 as well as in the support substrate 10 (in particular, V-shaped trenches and conductive vias).

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Abstract

The invention relates to a method for producing a SOI structure, comprising the following steps: a) providing an initial substrate made of monocrystalline silicon, having an interstitial oxygen content of between 15 and 27 ppma according to standard ASTM'79 and a resistivity of less than 200 ohms.cm, the initial substrate being intended to form a carrier substrate for the SOI structure after having undergone the subsequent step b); b) applying a sequence of heat treatments to the initial substrate while it is devoid, at least on a front face, of a silicon oxide layer other than optionally a native oxide layer, the sequence consisting of: - a first heat treatment defined by a plateau at a temperature higher than 1200°C and lower than 1280°C and with a duration of between 1 second and 60 seconds, by a temperature decrease ramp of between 10°C/s and 70°C/s, and by an argon or argon-hydrogen atmosphere; followed by - a second heat treatment defined by a plateau at a temperature of between 900°C and 1100°C, without an intermediate step before this temperature, under a neutral or oxidising atmosphere, in order to form a carrier substrate comprising: - a stripped surface layer, with a thickness greater than 40 μm and having a micro-defect concentration (BMD) of less than 108/cm3, and - an enriched deep layer, under the stripped surface layer, having a micro-defect concentration (BMD) of between 2.108/cm3 and 5.1010/cm3. The invention also relates to a carrier substrate and a SOI structure including the carrier substrate.

Description

Procédé de fabrication d’une structure SOI notamment adaptée pour les applications photoniques, et substrat support pour ladite structureMethod for manufacturing an SOI structure particularly suitable for photonic applications, and support substrate for said structure

La présente invention vise le domaine des semi-conducteurs et de la microélectronique. Elle concerne un procédé de fabrication d’une structure SOI (Silicium sur Isolant), notamment adaptée pour les applications photoniques. L’invention concerne également un substrat support pour ladite structure.The present invention relates to the field of semiconductors and microelectronics. It relates to a method for manufacturing an SOI (Silicon on Insulator) structure, particularly suitable for photonic applications. The invention also relates to a support substrate for said structure.

ARRIERE PLAN TECHNOLOGIQUE DE L’INVENTION :TECHNOLOGICAL BACKGROUND OF THE INVENTION:

Dans le domaine de la photonique sur SOI, certaines techniques de couplage des fibres optiques avec les composants nécessitent de réaliser des tranchées en V (« V-groove » selon la terminologie anglo-saxonne) par gravure chimique anisotrope dans le substrat support de la structure SOI, à une profondeur de l’ordre de 50 à 80µm. En outre, il est de plus en plus recherché de co-intégrer des composants, en permettant de connecter électriquement la face avant et la face arrière de la structure SOI. Une telle connexion se fait classiquement à l’aide de vias conducteurs traversants (TSV pour « Through Silicon Via ») élaborés par gravure sèche du substrat support de la structure SOI, typiquement sur une profondeur de 50 à 100µm. Notons que le substrat support est plus épais que 100µm tout au long des procédés de fabrication de la structure SOI et d’élaboration des composants, mais il est habituellement aminci en face arrière dans ces gammes d’épaisseur, ce qui permet de récupérer le contact électrique par le ou les via(s) débouchants.In the field of SOI photonics, some techniques for coupling optical fibers with components require the creation of V-grooves by anisotropic chemical etching in the substrate supporting the SOI structure, to a depth of around 50 to 80µm. In addition, it is increasingly sought to co-integrate components, allowing the front and back faces of the SOI structure to be electrically connected. Such a connection is traditionally made using through-silicon vias (TSVs) produced by dry etching the substrate supporting the SOI structure, typically to a depth of 50 to 100µm. Note that the support substrate is thicker than 100µm throughout the SOI structure manufacturing and component development processes, but it is usually thinned on the back face in these thickness ranges, which allows the electrical contact to be recovered through the through via(s).

La présence de défauts dans le substrat support, tels que notamment des micro-défauts (BMD pour « bulk micro-defect ») bien connus dans l’industrie du silicium monocristallin, peut perturber les gravures de tranchées en V ou de vias, et provoquer des défaillances ultérieures au niveau des composants. Ces micro-défauts BMD sont issus de la précipitation d’oxygène interstitiel sur des sites de nucléation préférentiels (par exemple, des lacunes), et ne sont pas favorables lorsque des gravures profondes telles que précitées sont prévues dans le substrat support.The presence of defects in the support substrate, such as bulk micro-defects (BMDs) well known in the monocrystalline silicon industry, can disrupt V-trench or via etchings and cause subsequent component failures. These BMDs arise from the precipitation of interstitial oxygen at preferential nucleation sites (e.g., vacancies) and are not favorable when deep etchings such as those described above are planned in the support substrate.

Par ailleurs, la fabrication des structures SOI nécessite des budgets thermiques à très hautes températures. Elle peut notamment mettre en œuvre le procédé Smart CutTM pour le transfert de la couche utile en silicium monocristallin (c-Si) sur le substrat support, via une couche intermédiaire diélectrique. Le procédé Smart Cut, bien connu, est basé sur l’implantation d’ions légers dans un substrat donneur en c-Si pour former un plan fragile enterré qui définit, avec la face avant du substrat donneur, la couche utile à transférer. Le substrat donneur implanté est ensuite assemblé sur le substrat support. En général, une couche diélectrique est formée sur le substrat donneur, sur le substrat support ou sur les deux substrats, préalablement à l’assemblage : cette couche diélectrique est destinée à former la couche isolante enterrée de la structure SOI. L’étape suivante consiste en une séparation le long du plan fragile enterré, donnant lieu, d’une part à une structure intermédiaire comprenant la couche utile transférée sur la substrat support via la couche diélectrique, et d’autre part, le reste du substrat donneur. Furthermore, the manufacturing of SOI structures requires very high temperature thermal budgets. It can notably implement the Smart Cut TM process for the transfer of the useful layer in monocrystalline silicon (c-Si) onto the support substrate, via a dielectric intermediate layer. The well-known Smart Cut process is based on the implantation of light ions into a c-Si donor substrate to form a buried fragile plane which defines, with the front face of the donor substrate, the useful layer to be transferred. The implanted donor substrate is then assembled on the support substrate. In general, a dielectric layer is formed on the donor substrate, on the support substrate or on both substrates, prior to assembly: this dielectric layer is intended to form the buried insulating layer of the SOI structure. The next step consists of a separation along the buried fragile plane, giving rise, on the one hand, to an intermediate structure comprising the useful layer transferred onto the support substrate via the dielectric layer, and on the other hand, the rest of the donor substrate.

Après la séparation de la couche utile et son report sur le substrat support, des traitements thermiques sont requis pour lisser la surface libre de la couche utile et guérir des défauts cristallins présents dans cette dernière. Cela implique que le substrat support de la structure SOI soit résistant aux modes de défaillance de type lignes de glissement (« slip lines »), marques ou autres déformations susceptibles d’être générées au cours du traitement thermique, du fait de gradients de température ou de points de contact entre le substrat et des éléments de maintien dans le four. Pour protéger le substrat support contre ces défaillances, il est avantageux qu’il présente une densité de micro-défauts BMD suffisante et homogène tant radialement qu’en profondeur, lesquels micro-défauts le rendent robuste à la déformation mécanique. En outre, les micro-défauts BMD permettent le piégeage d’espèces (notamment contamination métallique) dans le substrat support, limitant la diffusion de contaminants jusqu’à la couche utile lors de la fabrication des composants. After the separation of the useful layer and its transfer to the support substrate, heat treatments are required to smooth the free surface of the useful layer and heal the crystal defects present in the latter. This implies that the support substrate of the SOI structure is resistant to failure modes such as slip lines, marks or other deformations likely to be generated during the heat treatment, due to temperature gradients or contact points between the substrate and holding elements in the furnace. To protect the support substrate against these failures, it is advantageous for it to have a sufficient and homogeneous density of BMD micro-defects both radially and in depth, which micro-defects make it robust to mechanical deformation. In addition, BMD micro-defects allow the trapping of species (in particular metallic contamination) in the support substrate, limiting the diffusion of contaminants to the useful layer during the manufacturing of the components.

OBJET DE L’INVENTION :SUBJECT OF THE INVENTION:

Pour réconcilier les différentes contraintes liées à la présence de micro-défauts BMD dans le substrat support d’une structure SOI, la présente invention propose un procédé de fabrication d’une structure SOI, notamment adaptée pour applications photoniques, dont le substrat support comprend :

  • une couche de surface appauvrie en micro-défauts BMD, présentant une épaisseur supérieure à 40µm, typiquement comprise entre 40µm et 100µm, et
  • une couche profonde riche en micro-défauts BMD, pour garantir un comportement mécanique stable du substrat support, et donc de la structure SOI, au cours de sa fabrication et au cours de l’élaboration des composants.
To reconcile the various constraints linked to the presence of BMD micro-defects in the support substrate of an SOI structure, the present invention proposes a method for manufacturing an SOI structure, particularly suitable for photonic applications, the support substrate of which comprises:
  • a surface layer depleted in BMD micro-defects, having a thickness greater than 40µm, typically between 40µm and 100µm, and
  • a deep layer rich in BMD micro-defects, to guarantee stable mechanical behavior of the support substrate, and therefore of the SOI structure, during its manufacturing and during the development of the components.

BREVE DESCRIPTION DE L’INVENTION :BRIEF DESCRIPTION OF THE INVENTION:

La présente invention concerne un procédé de fabrication d’une structure SOI, comprenant les étapes suivantes :The present invention relates to a method of manufacturing an SOI structure, comprising the following steps:

a) la fourniture d’un substrat initial en silicium monocristallin, présentant une teneur en oxygène interstitiel comprise entre 15 et 27 ppma selon la norme ASTM’79 et une résistivité inférieure à 200 ohms.cm, le substrat initial étant destiné à former un substrat support pour la structure SOI après avoir subi l’étape b) subséquente :a) the provision of an initial substrate made of monocrystalline silicon, having an interstitial oxygen content of between 15 and 27 ppma according to the ASTM’79 standard and a resistivity of less than 200 ohms.cm, the initial substrate being intended to form a support substrate for the SOI structure after having undergone the subsequent step b):

b) l’application d’une séquence de traitements thermiques au substrat initial alors qu’il est dépourvu, au moins sur une face avant, d’une couche d’oxyde de silicium autre qu’éventuellement une couche d’oxyde natif, ladite séquence consistant en :b) the application of a sequence of heat treatments to the initial substrate while it is devoid, at least on one front face, of a layer of silicon oxide other than possibly a layer of native oxide, said sequence consisting of:

- un premier traitement thermique défini par un plateau à une température supérieure à 1200°C et inférieure à 1280°C et d’une durée comprise entre 1 seconde et 60 secondes, par une rampe de descente en température comprise entre 10°C/s et 70°C/s, et par une atmosphère de type argon ou argon-hydrogène, suivi par- a first heat treatment defined by a plateau at a temperature above 1200°C and below 1280°C and lasting between 1 second and 60 seconds, by a temperature reduction ramp between 10°C/s and 70°C/s, and by an argon or argon-hydrogen type atmosphere, followed by

- un deuxième traitement thermique défini par un plateau à une température comprise entre 900°C et 1100°C, sans palier avant cette température, sous atmosphère neutre ou oxydante, pour former un substrat support comprenant :- a second heat treatment defined by a plateau at a temperature between 900°C and 1100°C, without a plateau before this temperature, under a neutral or oxidizing atmosphere, to form a support substrate comprising:

- une couche de surface dénudée, d’épaisseur supérieure à 40 μm et présentant une concentration en micro-défauts BMD inférieure à 108/cm3, et- a bare surface layer, with a thickness greater than 40 μm and having a concentration of BMD micro-defects less than 10 8 /cm 3 , and

- une couche profonde enrichie, sous la couche de surface dénudée, présentant une concentration en micro-défauts comprise entre 2.108/cm3 et 5.1010/cm3.- a deep enriched layer, under the bare surface layer, presenting a concentration of micro-defects between 2.10 8 /cm 3 and 5.10 10 /cm 3 .

Selon des caractéristiques avantageuses de l’invention, prises seules ou selon toute combinaison réalisable :

  • la température du plateau du premier traitement thermique est comprise entre 1220°C et 1260°C ;
  • le deuxième traitement thermique est défini par des rampes de montée et de descente en température comprises entre 0,5°C/min et 10°C/min ;
  • la température du plateau du deuxième traitement thermique est comprise entre 950°C et 1000°C ;
  • l’atmosphère du deuxième traitement thermique est oxydante, au moins au cours du plateau, pour former, sur le substrat support, tout ou partie d’une couche diélectrique en oxyde de silicium, ladite couche diélectrique étant destinée à être disposée entre une couche utile et le substrat support dans la structure SOI ;
  • le procédé de fabrication comprend, après l’étape b) d’application de la séquence de traitements thermiques, une étape c) d’oxydation du substrat support pour former, sur le substrat support, tout ou partie d’une couche diélectrique en oxyde de silicium, ladite couche diélectrique étant destinée à être disposée entre une couche utile et le substrat support dans la structure SOI ;
  • le procédé de fabrication comprend en outre les étapes suivantes :
    d) la formation d’une structure intermédiaire comprenant la couche utile en silicium monocristallin disposée sur la couche diélectrique, elle-même disposée sur une face avant du substrat support, par une technique de transfert de couche mince,
    e) l’application d’un troisième traitement thermique à la structure intermédiaire, à une température comprise entre 900°C et 1250°C, sous atmosphère neutre ou réductrice, pour former la structure SOI.
According to advantageous characteristics of the invention, taken alone or in any feasible combination:
  • the temperature of the first heat treatment plate is between 1220°C and 1260°C;
  • the second heat treatment is defined by temperature rise and fall ramps between 0.5°C/min and 10°C/min;
  • the temperature of the second heat treatment plate is between 950°C and 1000°C;
  • the atmosphere of the second heat treatment is oxidizing, at least during the plateau, to form, on the support substrate, all or part of a dielectric layer of silicon oxide, said dielectric layer being intended to be arranged between a useful layer and the support substrate in the SOI structure;
  • the manufacturing method comprises, after step b) of applying the sequence of heat treatments, a step c) of oxidation of the support substrate to form, on the support substrate, all or part of a dielectric layer of silicon oxide, said dielectric layer being intended to be arranged between a useful layer and the support substrate in the SOI structure;
  • the manufacturing process further comprises the following steps:
    d) the formation of an intermediate structure comprising the useful layer of monocrystalline silicon arranged on the dielectric layer, itself arranged on a front face of the support substrate, by a thin layer transfer technique,
    e) applying a third heat treatment to the intermediate structure, at a temperature between 900°C and 1250°C, under a neutral or reducing atmosphere, to form the SOI structure.

L’invention concerne également un substrat support en silicium monocristallin, présentant :The invention also relates to a monocrystalline silicon support substrate, having:

- une résistivité inférieure à 200 ohm.cm,- a resistivity lower than 200 ohm.cm,

- une couche de surface dénudée, d’épaisseur supérieure à 40 μm, présentant une concentration en micro-défauts BMD inférieure à 108/cm3, - a bare surface layer, with a thickness greater than 40 μm, presenting a concentration of BMD micro-defects less than 10 8 /cm 3 ,

- une couche profonde enrichie, sous la couche de surface dénudée, présentant une concentration en micro-défauts BMD comprise entre 2.108/cm3 et 5.1010/cm3.- an enriched deep layer, under the bare surface layer, presenting a concentration of BMD micro-defects between 2.10 8 /cm 3 and 5.10 10 /cm 3 .

Le substrat support peut comprendre une couche diélectrique en oxyde de silicium au moins sur sa face avant.The support substrate may comprise a silicon oxide dielectric layer at least on its front face.

L’invention concerne enfin une structure SOI comprenant une couche utile disposée sur la couche diélectrique, elle-même disposée sur un substrat support tel que précité.The invention finally relates to an SOI structure comprising a useful layer arranged on the dielectric layer, itself arranged on a support substrate as mentioned above.

La couche diélectrique présente avantageusement une épaisseur comprise entre 500nm et 2000nm.The dielectric layer advantageously has a thickness of between 500nm and 2000nm.

D’autres caractéristiques et avantages de l’invention ressortiront de la description détaillée qui va suivre en référence aux figures annexées sur lesquelles :Other characteristics and advantages of the invention will emerge from the detailed description which follows with reference to the appended figures in which:

Les figures 1a, 1b et 1c présentent les étapes du procédé de fabrication d’un substrat support pour une structure SOI, conformément à l’invention ; Figures 1a, 1b and 1c show the steps of the method for manufacturing a support substrate for an SOI structure, in accordance with the invention;

La présente une structure SOI comprenant un substrat support conforme à l’invention ; There has an SOI structure comprising a support substrate according to the invention;

La présente des images en coupe de substrats supports conformes à l’invention, obtenues par tomographie par diffusion de la lumière (LST pour « Light Scattering Tomography ») ; la mesure, faite sur chaque substrat support clivé, est basée sur la collecte de la lumière diffusée par les micro-défauts BMD au niveau de la tranche dudit substrat support ; There presents cross-sectional images of support substrates in accordance with the invention, obtained by light scattering tomography (LST); the measurement, made on each cleaved support substrate, is based on the collection of light scattered by the BMD micro-defects at the edge of said support substrate;

La présente des images en coupe de substrats supports non conformes à l’invention, images également obtenues par LST. There presents cross-sectional images of support substrates not in accordance with the invention, images also obtained by LST.

Certaines figures sont des représentations schématiques qui, dans un objectif de lisibilité, ne sont pas à l’échelle. En particulier, les épaisseurs des couches selon l’axe z ne sont pas à l’échelle par rapport aux dimensions latérales selon les axes x et y.Some figures are schematic representations which, for readability purposes, are not to scale. In particular, the layer thicknesses along the z axis are not to scale with the lateral dimensions along the x and y axes.

L’invention concerne un procédé de fabrication d’une structure SOI 100 particulièrement adaptée pour des applications photoniques, lesquelles nécessitent en particulier la formation de tranchées en V et de vias conducteurs dans le substrat support 10 de ladite structure 100. La structure SOI 100 comporte une couche diélectrique enterrée épaisse, typiquement comprise entre 500nm et 2000nm. The invention relates to a method for manufacturing an SOI 100 structure particularly suitable for photonic applications, which require in particular the formation of V-shaped trenches and conductive vias in the support substrate 10 of said structure 100. The SOI 100 structure comprises a thick buried dielectric layer, typically between 500nm and 2000nm.

Le procédé comprend, en premier lieu, une étape a) correspondant à la fourniture d’un substrat initial 10’ en silicium monocristallin CZ (processus de croissance de Czochralski). Le substrat initial 10’ présente une face avant 10a et une face arrière 10b, sensiblement parallèles à un plan principal (x,y) ( ). Il prend avantageusement la forme d’une plaquette de forme circulaire, de diamètre typiquement compris entre 200mm et 450mm. Son épaisseur totale, selon l’axe z normal au plan principal (x,y), peut varier entre quelques centaines de microns (par exemple 300 μm) et 1000 μm.The method comprises, firstly, a step a) corresponding to the provision of an initial substrate 10' in monocrystalline silicon CZ (Czochralski growth process). The initial substrate 10' has a front face 10a and a rear face 10b, substantially parallel to a main plane (x,y) ( ). It advantageously takes the form of a circular plate, with a diameter typically between 200mm and 450mm. Its total thickness, along the z axis normal to the main plane (x,y), can vary between a few hundred microns (for example 300 μm) and 1000 μm.

Le substrat initial 10’ présente une teneur en oxygène interstitiel comprise entre 15 et 27 ppma selon la norme ASTM’79. Sa résistivité est inférieure à 200 ohms.cm, typiquement comprise entre 1 ohm.cm et 100 ohms.cm. Le substrat initial 10’ est destiné à former un substrat support 10 pour la structure SOI 100 après avoir subi l’étape b) subséquente.The initial substrate 10’ has an interstitial oxygen content of between 15 and 27 ppma according to the ASTM’79 standard. Its resistivity is less than 200 ohms.cm, typically between 1 ohm.cm and 100 ohms.cm. The initial substrate 10’ is intended to form a support substrate 10 for the SOI structure 100 after having undergone the subsequent step b).

L’étape b) correspond à l’application d’une séquence de traitements thermiques au substrat initial 10’ nu, c’est-à-dire dépourvu, au moins sur sa face avant 10a, de toute couche d’oxyde de silicium autre qu’éventuellement une couche d’oxyde natif. La séquence consiste en deux traitements thermiques successifs, sans autre cycle thermique intercalé.Step b) corresponds to the application of a sequence of heat treatments to the initial bare substrate 10', i.e. devoid, at least on its front face 10a, of any layer of silicon oxide other than possibly a layer of native oxide. The sequence consists of two successive heat treatments, without any other intervening thermal cycle.

Le premier traitement thermique est effectué dans un équipement de recuit rapide RTA (« rapid thermal anneal ») et est défini par un plateau en température, des rampes de montée et descente en température et une atmosphère gazeuse. La température du plateau est supérieure à 1200°C et inférieure à 1280°C. Avantageusement, elle est comprise entre 1220°C et 1260°C, voire entre 1220°C et 1250°C. La durée du plateau peut être de 1 seconde à 60 secondes. La rampe de descente est comprise entre 10°C/s et 70°C/s. La rampe de montée est également rapide, mais peut être choisie dans une gamme plus large que la rampe de descente, en particulier entre 10°C/s et 100°C/s. L’atmosphère au cours de ce premier traitement thermique est de type argon ou argon-hydrogène (typiquement Ar > 70%). Une atmosphère azote n’est pas envisageable car un trop grand nombre de lacunes est injecté dans le substrat, notamment par la face avant 10a, ce qui ne favorise pas l’appauvrissement en lacunes d’une couche de surface de grande épaisseur. Une atmosphère oxydante est également à proscrire car elle participe à compenser l’injection de lacunes, notamment dans une couche profonde du substrat que l’on souhaite au contraire enrichir en lacunes.The first heat treatment is carried out in a rapid thermal annealing (RTA) equipment and is defined by a temperature plateau, temperature ramps and a gas atmosphere. The temperature of the plateau is above 1200°C and below 1280°C. Advantageously, it is between 1220°C and 1260°C, or even between 1220°C and 1250°C. The duration of the plateau can be from 1 second to 60 seconds. The ramp down is between 10°C/s and 70°C/s. The ramp up is also fast, but can be chosen in a wider range than the ramp down, in particular between 10°C/s and 100°C/s. The atmosphere during this first heat treatment is of the argon or argon-hydrogen type (typically Ar > 70%). A nitrogen atmosphere is not possible because too many vacancies are injected into the substrate, particularly through the front face 10a, which does not promote the depletion of vacancies in a very thick surface layer. An oxidizing atmosphere is also to be avoided because it helps to compensate for the injection of vacancies, particularly in a deep layer of the substrate that we wish to enrich in vacancies.

Ce premier traitement thermique appliqué au substrat initial 10’ nu permet de générer un profil de lacunes dans sa profondeur, à savoir une faible concentration de lacunes dans une couche de surface 11’,13’ et une forte concentration de lacunes dans une couche profonde 12’.This first heat treatment applied to the initial bare substrate 10’ makes it possible to generate a profile of vacancies in its depth, namely a low concentration of vacancies in a surface layer 11’,13’ and a high concentration of vacancies in a deep layer 12’.

Par couche de surface 11’,13’, on entend une couche dont l’épaisseur démarre au niveau d’une face libre 10a,10b du substrat initial 10’ (en particulier, sa face avant 10a, mais potentiellement également sa face arrière 10b) et s’étend sur une profondeur supérieure ou égale à 40μm dans le volume dudit substrat 10’ ( ). Notons qu’une couche de surface 13’ à faible concentration de lacunes peut être formée du côté de la face arrière 10b du substrat initial 10’, si ladite face arrière 10b est – comme la face avant 10a – à nu, durant le premier traitement thermique.By surface layer 11', 13' is meant a layer whose thickness starts at a free face 10a, 10b of the initial substrate 10' (in particular, its front face 10a, but potentially also its rear face 10b) and extends over a depth greater than or equal to 40μm in the volume of said substrate 10' ( ). Note that a surface layer 13' with a low concentration of vacancies can be formed on the side of the rear face 10b of the initial substrate 10', if said rear face 10b is – like the front face 10a – bare, during the first heat treatment.

Par couche profonde 12’, on entend une couche qui est située sous la couche de surface 11’,13’ (en partant de la face libre de la couche de surface considérée), et qui s’étend dans le volume du substrat initial 10’. Cette couche profonde à forte concentration de lacunes peut par exemple s’étendre entre la couche de surface 11’ en face avant 10a et celle 13’ en face arrière 10b du substrat initial 10’. Plus tard dans la séquence thermique appliquée au substrat initial 10’, les lacunes vont aider à fixer des précipités d’oxygène là où elles sont présentes, en constituant des sites préférentiels de nucléation.By deep layer 12’, we mean a layer which is located under the surface layer 11’, 13’ (starting from the free face of the surface layer considered), and which extends into the volume of the initial substrate 10’. This deep layer with a high concentration of vacancies can for example extend between the surface layer 11’ on the front face 10a and that 13’ on the rear face 10b of the initial substrate 10’. Later in the thermal sequence applied to the initial substrate 10’, the vacancies will help to fix oxygen precipitates where they are present, by constituting preferential nucleation sites.

Pendant le plateau du premier traitement thermique, des lacunes peuvent être générées partout dans le substrat initial 10’, en surface comme en profondeur, avec une densité dépendant du budget thermique appliqué. Lors de la descente en température, ces lacunes diffusant très vite, la probabilité qu'elles se recombinent à la surface est plus grande si on est proche de la surface, on a donc un gradient de lacunes à la surface, qui peut être modulé notamment par la vitesse de descente en température : plus on descend vite, plus on va figer les lacunes sur place et peu recombiner à la surface, ce qui donne lieu à une couche de surface appauvrie en lacunes de faible épaisseur ; plus on descend lentement, plus le gradient de concentration de lacunes sera prononcé, ce qui se traduit par une couche de surface de plus forte épaisseur. Cela étant, en dessous d'une certaine vitesse de descente en température, même les lacunes situées en profondeur tendent à diffuser et à se recombiner en surface, ce qui impacte négativement la couche profonde attendue riche en lacunes. L’atmosphère de recuit a également un impact : comparée à une atmosphère argon, une ambiance argon-hydrogène ajoute une participation de l’hydrogène (qui diffuse vite dans le substrat initial 10’) à la passivation des lacunes, en surface mais également plus en profondeur, ce qui peut permettre d’augmenter l’épaisseur de la couche de surface. A contrario, dans certaines conditions d’application, une atmosphère Ar/H peut amoindrir la concentration en lacunes de la couche profonde, ce qui n’est pas souhaitable.During the plateau of the first heat treatment, vacancies can be generated everywhere in the initial substrate 10’, on the surface as well as in depth, with a density depending on the thermal budget applied. During the temperature decrease, these vacancies diffuse very quickly, the probability that they recombine at the surface is greater if we are close to the surface, we therefore have a gradient of vacancies at the surface, which can be modulated in particular by the temperature decrease speed: the faster we decrease, the more we will freeze the vacancies in place and recombine at the surface, which gives rise to a surface layer depleted in vacancies of thin thickness; the slower we decrease, the more pronounced the vacancy concentration gradient will be, which results in a surface layer of greater thickness. However, below a certain temperature decrease speed, even the vacancies located at depth tend to diffuse and recombine at the surface, which negatively impacts the expected deep layer rich in vacancies. The annealing atmosphere also has an impact: compared to an argon atmosphere, an argon-hydrogen atmosphere adds a participation of hydrogen (which diffuses quickly in the initial substrate 10') to the passivation of the vacancies, on the surface but also deeper down, which can increase the thickness of the surface layer. Conversely, in certain application conditions, an Ar/H atmosphere can reduce the vacancy concentration of the deep layer, which is not desirable.

Les conditions du premier traitement thermique précitées (températures du plateau, rampes, durées, atmosphères) apportent le bon compromis pour générer une épaisseur de couche de surface 11’,13’ appauvrie en lacunes, comprise typiquement entre 40 μm et 100 μm, et une couche profonde 12’ très riche en lacunes. En outre, ces conditions évitent, ou tout au moins limitent, la création de défauts tels que des lignes de glissement SL (« slip lines ») ou des marques PM (« pinmarks ») dans ou sur le substrat initial 10’, préjudiciables à la future structure SOI.The above-mentioned first heat treatment conditions (plate temperatures, ramps, durations, atmospheres) provide the right compromise to generate a surface layer thickness 11’, 13’ depleted in vacancies, typically between 40 μm and 100 μm, and a deep layer 12’ very rich in vacancies. In addition, these conditions avoid, or at least limit, the creation of defects such as SL slip lines or PM pinmarks in or on the initial substrate 10’, which are detrimental to the future SOI structure.

Dans la séquence selon l’invention, le premier traitement thermique est suivi par un deuxième traitement thermique, défini par un plateau à une température comprise entre 900°C et 1100°C, sans palier avant cette température. Préférentiellement, la température du plateau est comprise entre 950°C et 1000°C. La durée du plateau est typiquement comprise entre 2h et plusieurs dizaines d’heures, par exemple 40h. Les rampes de montée et de descente en température sont avantageusement comprises entre 0,5°C/min et 10°C/min et peuvent éventuellement être différentes entre elles. L’atmosphère du deuxième traitement thermique peut être neutre ou oxydante. Ce deuxième traitement thermique est avantageusement opéré dans un four classique (avec tube vertical ou horizontal).In the sequence according to the invention, the first heat treatment is followed by a second heat treatment, defined by a plateau at a temperature between 900°C and 1100°C, without a plateau before this temperature. Preferably, the temperature of the plateau is between 950°C and 1000°C. The duration of the plateau is typically between 2 hours and several tens of hours, for example 40 hours. The temperature rise and fall ramps are advantageously between 0.5°C/min and 10°C/min and may possibly be different from each other. The atmosphere of the second heat treatment may be neutral or oxidizing. This second heat treatment is advantageously carried out in a conventional furnace (with vertical or horizontal tube).

Le deuxième traitement thermique favorise la précipitation d’oxygène sur les lacunes distribuées dans le substrat 10’ selon le profil figé lors du premier traitement thermique. La précipitation est rendue possible par la présence d’oxygène interstitiel, ce qui rappelle l’importance du choix de la gamme de teneurs en oxygène interstitiel du substrat initial 10’ fourni à l’étape a) du procédé.The second heat treatment promotes the precipitation of oxygen on the vacancies distributed in the substrate 10’ according to the profile frozen during the first heat treatment. The precipitation is made possible by the presence of interstitial oxygen, which recalls the importance of the choice of the range of interstitial oxygen contents of the initial substrate 10’ provided in step a) of the process.

Le deuxième traitement thermique est également défini de manière à ne pas passiver ou recombiner les lacunes avant qu’elles n’aient aidé à créer des micro-défauts BMD.The second heat treatment is also defined so as not to passivate or recombine the vacancies before they have helped create BMD micro-defects.

Cette séquence de traitements thermiques est essentielle pour former le substrat support 10 visé, dont une couche de surface dénudée 11,13 (issue de la couche de surface 11’,13’), d’épaisseur supérieure ou égale à 40 μm, présente une concentration en micro-défauts BMD inférieure à 108/cm3, et dont une couche profonde enrichie 12 (issue de la couche profonde 12’), sous la couche de surface dénudée 11,13, présente une concentration en micro-défauts BMD comprise entre 2.108/cm3 et 5.1010/cm3. Rappelons que la densité et potentiellement la taille des micro-défauts BMD sont classiquement mesurées par tomographie par diffusion de la lumière (LST pour « Light Scattering Tomography »), au niveau de la tranche (dans le plan (y,z) sur les figures) du substrat support 10.This sequence of heat treatments is essential to form the target support substrate 10, of which a stripped surface layer 11, 13 (from the surface layer 11', 13'), with a thickness greater than or equal to 40 μm, has a concentration of BMD micro-defects less than 10 8 /cm 3 , and of which an enriched deep layer 12 (from the deep layer 12'), under the stripped surface layer 11, 13, has a concentration of BMD micro-defects of between 2.10 8 /cm 3 and 5.10 10 /cm 3 . It should be recalled that the density and potentially the size of the BMD micro-defects are conventionally measured by light scattering tomography (LST for "Light Scattering Tomography"), at the level of the edge (in the plane (y, z) in the figures) of the support substrate 10.

Le substrat support 10 obtenu présente en outre une excellente qualité mécanique, avec une très faible densité de défauts de type SL ou PM, voire aucun de ces défauts, à l’issue de la séquence de traitements thermiques. L’absence (ou la très faible densité) de ces défauts, et la concentration en micro-défauts BMD supérieure ou égale à 2x108/cm3 vont conférer au substrat support 10 une grande robustesse mécanique lors de traitements thermiques ultérieurs à hautes températures, et éviter les défaillances de type lignes de glissement SL dans la future structure SOI (tant lors de son élaboration que lors de celle des composants). La couche de surface dénudée 11,13, qui peut s’étendre sur une épaisseur comprise entre 40 μm à 100 μm, est particulièrement adaptée à la formation de tranchées en V ou de vias, lors de la fabrication de composants sur et/ou dans la structure SOI 100.The support substrate 10 obtained also has excellent mechanical quality, with a very low density of SL or PM type defects, or even none of these defects, at the end of the heat treatment sequence. The absence (or very low density) of these defects, and the concentration of BMD micro-defects greater than or equal to 2x10 8 /cm 3 will give the support substrate 10 great mechanical robustness during subsequent heat treatments at high temperatures, and avoid SL slip line type failures in the future SOI structure (both during its preparation and during that of the components). The stripped surface layer 11, 13, which can extend over a thickness of between 40 μm and 100 μm, is particularly suitable for the formation of V-shaped trenches or vias, during the manufacture of components on and/or in the SOI structure 100.

Selon un mode particulier de réalisation du procédé, l’atmosphère du deuxième traitement thermique est oxydante, au moins au cours du plateau, pour former, sur le substrat support 10, tout ou partie d’une couche diélectrique en oxyde de silicium, ladite couche diélectrique 20 étant destinée à être disposée entre une couche utile 30 et le substrat support 10 dans la structure SOI 100. Ce mode de réalisation est avantageux en ce qu’il permet de combiner deux fonctions du deuxième traitement thermique et de rationaliser les étapes thermiques appliquées au substrat support 10.According to a particular embodiment of the method, the atmosphere of the second heat treatment is oxidizing, at least during the plateau, to form, on the support substrate 10, all or part of a dielectric layer of silicon oxide, said dielectric layer 20 being intended to be arranged between a useful layer 30 and the support substrate 10 in the SOI structure 100. This embodiment is advantageous in that it makes it possible to combine two functions of the second heat treatment and to rationalize the thermal steps applied to the support substrate 10.

A titre d’exemple, pour former une couche diélectrique de 2 μm sur le substrat support 10, le deuxième traitement thermique pourra être défini par des rampes de montée en température de quelques degrés par minute, jusqu’à 1000°C, sous atmosphère argon avec faible apport d’oxygène, un plateau à une température de 1000°C sous atmosphère oxydante, et une rampe de descente de quelques degrés par minute.For example, to form a 2 μm dielectric layer on the support substrate 10, the second heat treatment may be defined by temperature rise ramps of a few degrees per minute, up to 1000°C, under an argon atmosphere with low oxygen supply, a plateau at a temperature of 1000°C under an oxidizing atmosphere, and a descent ramp of a few degrees per minute.

Selon un autre mode de réalisation, le procédé de fabrication comprend, après l’étape b) d’application de la séquence de traitements thermiques, une étape c) d’oxydation du substrat support 10 pour former, sur ledit substrat support, tout ou partie d’une couche diélectrique en oxyde de silicium ; la couche diélectrique 20 est destinée à être disposée entre une couche utile 30 et le substrat support 10 dans la structure SOI 100. L’étape c) d’oxydation n’a pas d’influence négative sur la couche de surface dénudée 11,13 et la couche profonde enrichie 12, car la précipitation d’oxygène sur les lacunes s’est opérée lors du deuxième traitement thermique. L’étape c) peut alors induire une augmentation de la taille des micro-défauts BMD.According to another embodiment, the manufacturing method comprises, after step b) of applying the sequence of heat treatments, a step c) of oxidation of the support substrate 10 to form, on said support substrate, all or part of a dielectric layer of silicon oxide; the dielectric layer 20 is intended to be arranged between a useful layer 30 and the support substrate 10 in the SOI structure 100. The oxidation step c) has no negative influence on the stripped surface layer 11, 13 and the enriched deep layer 12, because the precipitation of oxygen on the vacancies took place during the second heat treatment. Step c) can then induce an increase in the size of the BMD micro-defects.

Rappelons que les applications photoniques sur silicium requièrent en général des structures SOI comportant une couche diélectrique enterrée épaisse, typiquement comprise entre 500nm et 2000nm. Cette épaisseur étant significative, la couche diélectrique 20 est crue préférentiellement (ou tout au moins en grande majorité) sur le substrat support 10, car une forte épaisseur de couche diélectrique sur la face avant du substrat donneur (en référence au procédé Smart Cut) rend difficile la formation du plan fragile enterré par implantation ionique.Let us recall that photonic applications on silicon generally require SOI structures comprising a thick buried dielectric layer, typically between 500nm and 2000nm. This thickness being significant, the dielectric layer 20 is preferably (or at least in the vast majority) grown on the support substrate 10, because a high thickness of dielectric layer on the front face of the donor substrate (in reference to the Smart Cut process) makes it difficult to form the buried fragile plane by ion implantation.

La montre deux exemples de substrat support 10 élaborés selon un procédé conforme à l’invention. En particulier, la séquence de l’étape b) a consisté en un premier traitement thermique défini par un plateau à une température comprise entre 1220°C et 1260°C, d’une durée comprise entre 1 seconde et 60 secondes, et par une rampe de descente en température comprise entre 10°C/s et 70°C/s, suivi par un deuxième traitement thermique défini par un plateau à une température comprise entre 950°C et 1000°C, sans palier avant cette température, sous atmosphère oxydante. Les images ont été obtenues par LST. On observe dans les deux cas, une couche de surface dénudée 11 et une couche profonde enrichie en BMD 12 ; l’épaisseur de la couche de surface dénudée 11 peut être supérieure grâce à l’implémentation d’une atmosphère Ar/H lors du premier traitement thermique : sur l’image de gauche de la , l’épaisseur de la couche de surface dénudée 11 est de 70 μm environ pour une atmosphère Ar, alors que sur l’image de droite, l’épaisseur de la couche dénudée 11 est de 90 μm environ pour une atmosphère Ar/H, avec une concentration d’hydrogène inférieure à 30%. Le substrat support 10, dans les deux exemples, présente une bonne qualité mécanique avec pas ou très peu de défauts SL et PM.There shows two examples of support substrate 10 produced according to a method in accordance with the invention. In particular, the sequence of step b) consisted of a first heat treatment defined by a plateau at a temperature between 1220°C and 1260°C, lasting between 1 second and 60 seconds, and by a temperature reduction ramp between 10°C/s and 70°C/s, followed by a second heat treatment defined by a plateau at a temperature between 950°C and 1000°C, without a plateau before this temperature, under an oxidizing atmosphere. The images were obtained by LST. In both cases, a stripped surface layer 11 and a deep layer enriched in BMD 12 are observed; the thickness of the stripped surface layer 11 can be greater thanks to the implementation of an Ar/H atmosphere during the first heat treatment: in the left image of the , the thickness of the stripped surface layer 11 is approximately 70 μm for an Ar atmosphere, whereas in the right image, the thickness of the stripped layer 11 is approximately 90 μm for an Ar/H atmosphere, with a hydrogen concentration of less than 30%. The support substrate 10, in both examples, has good mechanical quality with no or very few SL and PM defects.

La présente deux exemples de substrat support dont le procédé de fabrication n’est pas conforme à la présente invention. Une température de plateau au premier traitement thermique de 1200°C (ou inférieure), même sous atmosphère Ar/H et en utilisant une rampe de descente en température comprise entre 10°C/s et 70°C/s, ne permet pas de générer le profil de lacunes attendu : à l’issue de la séquence de traitements thermiques, le substrat support (hors de l’invention) ne présente pas de couche de surface dénudée (exemple à gauche sur la ). En outre, en utilisant un premier traitement thermique défini par un plateau à une température comprise entre 1220°C et 1280°C, d’une durée comprise entre 1 seconde et 60 secondes, même sous atmosphère Ar/H, il s’avère qu’une rampe de descente en température trop lente au cours du premier traitement thermique est préjudiciable à la conservation d’un profil de lacunes marqué : par exemple, avec une rampe de descente de 5°C/s, le substrat support à l’issue de la séquence de traitements thermiques ne présente pas de couche profonde enrichie (exemple à droite sur la ).There presents two examples of support substrates whose manufacturing process is not in accordance with the present invention. A plateau temperature at the first heat treatment of 1200°C (or lower), even under an Ar/H atmosphere and using a temperature reduction ramp of between 10°C/s and 70°C/s, does not allow the expected gap profile to be generated: at the end of the heat treatment sequence, the support substrate (outside the invention) does not have a stripped surface layer (example on the left in the ). Furthermore, using a first heat treatment defined by a plateau at a temperature between 1220°C and 1280°C, lasting between 1 second and 60 seconds, even under an Ar/H atmosphere, it turns out that a temperature reduction ramp that is too slow during the first heat treatment is detrimental to the preservation of a marked vacancy profile: for example, with a reduction ramp of 5°C/s, the support substrate at the end of the heat treatment sequence does not present an enriched deep layer (example on the right in the ).

Après l’obtention du substrat support 10, le procédé de fabrication selon l’invention comprend en outre une étape d) correspondant à la formation d’une structure intermédiaire comprenant la couche utile 30 en silicium monocristallin disposée sur la couche diélectrique 20, elle-même disposée sur une face avant 10a dudit substrat support 10, par une technique de transfert de couche mince telle que le procédé Smart CutTM.After obtaining the support substrate 10, the manufacturing method according to the invention further comprises a step d) corresponding to the formation of an intermediate structure comprising the useful layer 30 of monocrystalline silicon arranged on the dielectric layer 20, itself arranged on a front face 10a of said support substrate 10, by a thin layer transfer technique such as the Smart Cut TM process.

Un substrat donneur en silicium monocristallin est implanté par sa face avant, de manière à définir un plan fragile enterré sensiblement parallèle à ladite face avant et délimitant, avec cette dernière, la couche mince à reporter. L’implantation est habituellement faite avec des espèces légères telles que des ions d’hydrogène, d’hélium ou une combinaison de ces deux espèces. Le plan fragile est ainsi nommé car il comprend des nano-fissures sous forme lenticulaire générées par les espèces légères implantées.A monocrystalline silicon donor substrate is implanted from its front face, so as to define a buried fragile plane substantially parallel to said front face and delimiting, with the latter, the thin layer to be transferred. The implantation is usually carried out with light species such as hydrogen ions, helium or a combination of these two species. The fragile plane is so named because it includes nano-cracks in lenticular form generated by the implanted light species.

Selon une option préférentielle, évoquée précédemment, une couche diélectrique 20 est formée au moins sur la face avant 10a du substrat support 10. Il n’est pour autant pas exclu qu’une partie de la couche diélectrique enterrée de la future structure SOI soit élaborée sur le substrat donneur.According to a preferred option, mentioned previously, a dielectric layer 20 is formed at least on the front face 10a of the support substrate 10. It is not excluded, however, that a part of the buried dielectric layer of the future SOI structure is produced on the donor substrate.

Le substrat donneur et le substrat support 10 sont ensuite assemblés, par collage direct entre les faces avant desdits substrats, pour former un ensemble collé. Des nettoyages et/ou activations de surface, bien connus dans le domaine du collage par adhésion moléculaire, pourront être appliqués aux substrats préalablement à l’assemblage, pour obtenir une excellente qualité de collage. Un assemblage en atmosphère contrôlée est également possible.The donor substrate and the support substrate 10 are then assembled, by direct bonding between the front faces of said substrates, to form a bonded assembly. Surface cleaning and/or activation, well known in the field of molecular adhesion bonding, may be applied to the substrates prior to assembly, to obtain excellent bonding quality. Assembly in a controlled atmosphere is also possible.

La séparation au niveau du plan fragile enterré s’effectue préférentiellement par application d’un traitement thermique à température moyenne, typiquement entre 350°C et 500°C, du fait de la croissance de microfissures par coalescence et mise sous pression des espèces gazeuses. Alternativement ou conjointement, la séparation peut être provoquée par l’application d’une contrainte mécanique à l’ensemble collé.Separation at the buried fragile plane is preferably achieved by applying a heat treatment at medium temperature, typically between 350°C and 500°C, due to the growth of microcracks by coalescence and pressurization of gaseous species. Alternatively or jointly, separation can be caused by applying mechanical stress to the bonded assembly.

A l’issue de cette séparation, on obtient une structure intermédiaire de type SOI, d’une part, et le reste du substrat donneur, d’autre part. Des séquences de finition, comprenant des nettoyages, des traitements de surface (gravure, polissage, etc.) et/ou des traitements thermiques, sont habituellement appliquées à la structure SOI intermédiaire, et visent à retirer une partie superficielle de la couche utile 30 reportée. Cela permet de restaurer un bon état de surface (défectivité et rugosité) et une bonne qualité cristalline à la couche utile 30 en silicium. La couche utile 30 présente typiquement une épaisseur comprise entre 50 nm et 500 nm.At the end of this separation, an intermediate structure of the SOI type is obtained, on the one hand, and the rest of the donor substrate, on the other hand. Finishing sequences, including cleaning, surface treatments (etching, polishing, etc.) and/or heat treatments, are usually applied to the intermediate SOI structure, and aim to remove a superficial part of the transferred useful layer 30. This makes it possible to restore a good surface condition (defectivity and roughness) and a good crystalline quality to the useful silicon layer 30. The useful layer 30 typically has a thickness of between 50 nm and 500 nm.

Le procédé de fabrication comprend ensuite une étape e) d’application d’un troisième traitement thermique à la structure intermédiaire, à une température comprise entre 900°C et 1250°C, sous atmosphère neutre ou réductrice, pour former la structure SOI. Un tel traitement thermique n’affecte pas la couche de surface dénudée 11, 13 et la couche profonde enrichie en BMD 12, induites par la séquence des premier et deuxième traitements thermiques. Il peut avantageusement induire une augmentation de la taille des micro-défauts BMD.The manufacturing method then comprises a step e) of applying a third heat treatment to the intermediate structure, at a temperature between 900°C and 1250°C, under a neutral or reducing atmosphere, to form the SOI structure. Such a heat treatment does not affect the stripped surface layer 11, 13 and the deep layer enriched in BMD 12, induced by the sequence of the first and second heat treatments. It can advantageously induce an increase in the size of the BMD micro-defects.

A la suite de quoi, la structure SOI 100 est disponible. As a result, the SOI 100 structure is available.

L’invention concerne également un substrat support 10 en silicium monocristallin, particulièrement adapté aux structures SOI visant notamment des applications photoniques, le substrat support 10 présentant :The invention also relates to a support substrate 10 made of monocrystalline silicon, particularly suitable for SOI structures aimed in particular at photonic applications, the support substrate 10 having:

- une résistivité inférieure à 200 ohm.cm,- a resistivity lower than 200 ohm.cm,

- une couche de surface dénudée 11,13, d’épaisseur supérieure à 40 μm, présentant une concentration en micro-défauts (BMD) inférieure à 108/cm3,- a bare surface layer 11,13, with a thickness greater than 40 μm, having a micro-defect concentration (BMD) less than 10 8 /cm 3 ,

- une couche profonde enrichie 12, sous la couche de surface, présentant une concentration en micro-défauts (BMD) comprise entre 2.108/cm3 et 5.1010/cm3.- an enriched deep layer 12, under the surface layer, presenting a concentration of micro-defects (BMD) between 2.10 8 /cm 3 and 5.10 10 /cm 3 .

Le substrat support 10 peut en outre comporter une couche diélectrique en oxyde de silicium sur sa face avant 10a et/ou sur sa face arrière 10b. Préférentiellement, ladite couche diélectrique présente une épaisseur comprise entre 500nm et 2000nm.The support substrate 10 may further comprise a silicon oxide dielectric layer on its front face 10a and/or on its rear face 10b. Preferably, said dielectric layer has a thickness of between 500nm and 2000nm.

Enfin, l’invention concerne une structure SOI comprenant une couche utile 30 en c-Si disposée sur la couche diélectrique 20, elle-même disposée sur le substrat support 10 précité. Cette structure SOI est particulièrement adaptée à la fabrication de composants photoniques sur et/ou dans la couche utile 30 ainsi que dans le substrat support 10 (en particulier, tranchées en V et vias conducteurs).Finally, the invention relates to an SOI structure comprising a useful layer 30 in c-Si arranged on the dielectric layer 20, itself arranged on the aforementioned support substrate 10. This SOI structure is particularly suitable for the manufacture of photonic components on and/or in the useful layer 30 as well as in the support substrate 10 (in particular, V-shaped trenches and conductive vias).

Bien sûr, l’invention n’est pas limitée aux modes de réalisation décrits ni au domaine des applications photoniques, et on peut y apporter des variantes de réalisation ou d’utilisation, sans sortir du cadre de l’invention. Of course, the invention is not limited to the embodiments described or to the field of photonic applications, and variants of embodiment or use can be made thereto, without departing from the scope of the invention.

Claims (11)

Procédé de fabrication d’une structure SOI (100), comprenant les étapes suivantes :
a) la fourniture d’un substrat initial (10’) en silicium monocristallin, présentant une teneur en oxygène interstitiel comprise entre 15 et 27 ppma selon la norme ASTM’79 et une résistivité inférieure à 200 ohms.cm, le substrat initial (10’) étant destiné à former un substrat support (10) pour la structure SOI (100) après avoir subi l’étape b) subséquente :
b) l’application d’une séquence de traitements thermiques au substrat initial (10’) alors qu’il est dépourvu, au moins sur une face avant (10a), d’une couche d’oxyde de silicium autre qu’éventuellement une couche d’oxyde natif, ladite séquence consistant en :
- un premier traitement thermique défini par un plateau à une température supérieure à 1200°C et inférieure à 1280°C et d’une durée comprise entre 1 seconde et 60 secondes, par une rampe de descente en température comprise entre 10°C/s et 70°C/s, et par une atmosphère de type argon ou argon-hydrogène, suivi par
- un deuxième traitement thermique défini par un plateau à une température comprise entre 900°C et 1100°C, sans palier avant cette température, sous atmosphère neutre ou oxydante, pour former un substrat support (10) comprenant :
- une couche de surface dénudée (11), d’épaisseur supérieure à 40 μm et présentant une concentration en micro-défauts (BMD) inférieure à 108/cm3, et
- une couche profonde enrichie (12), sous la couche de surface dénudée (11), présentant une concentration en micro-défauts (BMD) comprise entre 2.108/cm3 et 5.1010/cm3.A method of manufacturing an SOI structure (100), comprising the following steps:
a) providing an initial substrate (10') made of monocrystalline silicon, having an interstitial oxygen content of between 15 and 27 ppma according to the ASTM'79 standard and a resistivity of less than 200 ohms.cm, the initial substrate (10') being intended to form a support substrate (10) for the SOI structure (100) after having undergone the subsequent step b):
b) applying a sequence of heat treatments to the initial substrate (10') while it is devoid, at least on one front face (10a), of a layer of silicon oxide other than possibly a layer of native oxide, said sequence consisting of:
- a first heat treatment defined by a plateau at a temperature above 1200°C and below 1280°C and lasting between 1 second and 60 seconds, by a temperature reduction ramp between 10°C/s and 70°C/s, and by an argon or argon-hydrogen type atmosphere, followed by
- a second heat treatment defined by a plateau at a temperature between 900°C and 1100°C, without a plateau before this temperature, under a neutral or oxidizing atmosphere, to form a support substrate (10) comprising:
- a bare surface layer (11), with a thickness greater than 40 μm and having a micro-defect concentration (BMD) less than 10 8 /cm 3 , and
- an enriched deep layer (12), under the bare surface layer (11), having a concentration of micro-defects (BMD) between 2.10 8 /cm 3 and 5.10 10 /cm 3 . Procédé de fabrication selon la revendication 1, dans lequel la température du plateau du premier traitement thermique est comprise entre 1220°C et 1260°C.Manufacturing method according to claim 1, wherein the temperature of the plateau of the first heat treatment is between 1220°C and 1260°C. Procédé de fabrication selon l’une des revendications 1 et 2, dans lequel le deuxième traitement thermique est défini par des rampes de montée et de descente en température comprises entre 0,5°C/min et 10°C/min.Manufacturing method according to one of claims 1 and 2, in which the second heat treatment is defined by temperature rise and fall ramps of between 0.5°C/min and 10°C/min. Procédé de fabrication selon l’une des revendications 1 à 3, dans lequel la température du plateau du deuxième traitement thermique est comprise entre 950°C et 1000°C.Manufacturing method according to one of claims 1 to 3, in which the temperature of the plate of the second heat treatment is between 950°C and 1000°C. Procédé de fabrication selon l’une des revendications 1 à 4, dans lequel l’atmosphère du deuxième traitement thermique est oxydante, au moins au cours du plateau, pour former, sur le substrat support (10), tout ou partie d’une couche diélectrique en oxyde de silicium, ladite couche diélectrique (20) étant destinée à être disposée entre une couche utile (30) et le substrat support (10) dans la structure SOI (100).Manufacturing method according to one of claims 1 to 4, in which the atmosphere of the second heat treatment is oxidizing, at least during the plateau, to form, on the support substrate (10), all or part of a dielectric layer of silicon oxide, said dielectric layer (20) being intended to be arranged between a useful layer (30) and the support substrate (10) in the SOI structure (100). Procédé de fabrication selon l’une des revendications 1 à 5, comprenant, après l’étape b) d’application de la séquence de traitements thermiques, une étape c) d’oxydation du substrat support (10) pour former, sur le substrat support (10), tout ou partie d’une couche diélectrique en oxyde de silicium, ladite couche diélectrique (20) étant destinée à être disposée entre une couche utile (30) et le substrat support (10) dans la structure SOI (100).Manufacturing method according to one of claims 1 to 5, comprising, after step b) of applying the sequence of heat treatments, a step c) of oxidation of the support substrate (10) to form, on the support substrate (10), all or part of a dielectric layer of silicon oxide, said dielectric layer (20) being intended to be arranged between a useful layer (30) and the support substrate (10) in the SOI structure (100). Procédé de fabrication selon l’une des revendications 5 et 6, comprenant en outre les étapes suivantes :
d) la formation d’une structure intermédiaire comprenant la couche utile (30) en silicium monocristallin disposée sur la couche diélectrique (20), elle-même disposée sur une face avant (10a) du substrat support (10), par une technique de transfert de couche mince,
e) l’application d’un troisième traitement thermique à la structure intermédiaire, à une température comprise entre 900°C et 1250°C, sous atmosphère neutre ou réductrice, pour former la structure SOI (100).Manufacturing method according to one of claims 5 and 6, further comprising the following steps:
d) the formation of an intermediate structure comprising the useful layer (30) of monocrystalline silicon arranged on the dielectric layer (20), itself arranged on a front face (10a) of the support substrate (10), by a thin layer transfer technique,
e) applying a third heat treatment to the intermediate structure, at a temperature between 900°C and 1250°C, under a neutral or reducing atmosphere, to form the SOI structure (100). Substrat support (10) en silicium monocristallin, présentant :
- une résistivité inférieure à 200 ohm.cm,
- une couche de surface dénudée (11,13), d’épaisseur supérieure à 40 μm, présentant une concentration en micro-défauts (BMD) inférieure à 108/cm3,
- une couche profonde enrichie (12), sous la couche de surface dénudée (11,13), présentant une concentration en micro-défauts (BMD) comprise entre 2.108/cm3 et 5.1010/cm3.Support substrate (10) made of monocrystalline silicon, having:
- a resistivity lower than 200 ohm.cm,
- a bare surface layer (11,13), with a thickness greater than 40 μm, having a micro-defect concentration (BMD) less than 10 8 /cm 3 ,
- an enriched deep layer (12), under the bare surface layer (11,13), having a concentration of micro-defects (BMD) between 2.10 8 /cm 3 and 5.10 10 /cm 3 . Substrat support (10) selon la revendication 8, comprenant une couche diélectrique (20) en oxyde de silicium au moins sur sa face avant (10a).Support substrate (10) according to claim 8, comprising a dielectric layer (20) of silicon oxide at least on its front face (10a). Structure SOI (100) comprenant une couche utile (30) disposée sur la couche diélectrique (20), elle-même disposée sur un substrat support (10) selon la revendication 9.SOI structure (100) comprising a useful layer (30) arranged on the dielectric layer (20), itself arranged on a support substrate (10) according to claim 9. Structure (100) selon la revendication précédente, dans laquelle la couche diélectrique (20) présente une épaisseur comprise entre 500nm et 2000nm.Structure (100) according to the preceding claim, in which the dielectric layer (20) has a thickness of between 500nm and 2000nm.
PCT/EP2024/082138 2023-11-24 2024-11-13 Method for producing a soi structure, in particular suitable for photonic applications, and carrier substrate for the structure Pending WO2025108793A1 (en)

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FR3119929A1 (en) * 2021-02-15 2022-08-19 Soitec METHOD FOR MANUFACTURING A STRUCTURE SUITABLE FOR RADIO FREQUENCY APPLICATIONS, AND SUPPORT SUBSTRATE FOR SAID STRUCTURE

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* Cited by examiner, † Cited by third party
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FR3119929A1 (en) * 2021-02-15 2022-08-19 Soitec METHOD FOR MANUFACTURING A STRUCTURE SUITABLE FOR RADIO FREQUENCY APPLICATIONS, AND SUPPORT SUBSTRATE FOR SAID STRUCTURE

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